Info: constraining clock net 'clk_50m_fpga_refclk' to 50.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 27489/43848 62% Info: logic LUTs: 25573/43848 58% Info: carry LUTs: 1916/43848 4% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 15019/43848 34% Info: Packing IOs.. Info: $rsw_s9_aux_dc_p$iobuf_i: rsw_s9_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s9_aux_dc_p$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: $rsw_s8_aux_dc_p$iobuf_i: rsw_s8_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s8_aux_dc_p$tr_io' constrained to Bel 'X90/Y44/PIOA'. Info: $rsw_s7_aux_dc_p$iobuf_i: rsw_s7_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s7_aux_dc_p$tr_io' constrained to Bel 'X90/Y50/PIOA'. Info: $rsw_s6_aux_dc_p$iobuf_i: rsw_s6_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s6_aux_dc_p$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: $rsw_s5_aux_dc_p$iobuf_i: rsw_s5_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s5_aux_dc_p$tr_io' constrained to Bel 'X90/Y62/PIOA'. Info: $rsw_s4_aux_dc_p$iobuf_i: rsw_s4_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s4_aux_dc_p$tr_io' constrained to Bel 'X90/Y47/PIOA'. Info: $rsw_s3_aux_dc_p$iobuf_i: rsw_s3_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s3_aux_dc_p$tr_io' constrained to Bel 'X90/Y65/PIOA'. Info: $rsw_s31_aux_dc_p$iobuf_i: rsw_s31_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s31_aux_dc_p$tr_io' constrained to Bel 'X0/Y56/PIOA'. Info: $rsw_s30_aux_dc_p$iobuf_i: rsw_s30_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s30_aux_dc_p$tr_io' constrained to Bel 'X0/Y53/PIOA'. Info: $rsw_s2_aux_dc_p$iobuf_i: rsw_s2_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s2_aux_dc_p$tr_io' constrained to Bel 'X90/Y68/PIOA'. Info: $rsw_s29_aux_dc_p$iobuf_i: rsw_s29_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s29_aux_dc_p$tr_io' constrained to Bel 'X0/Y68/PIOA'. Info: $rsw_s28_aux_dc_p$iobuf_i: rsw_s28_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s28_aux_dc_p$tr_io' constrained to Bel 'X0/Y65/PIOA'. Info: $rsw_s27_aux_dc_p$iobuf_i: rsw_s27_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s27_aux_dc_p$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: $rsw_s26_aux_dc_p$iobuf_i: rsw_s26_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s26_aux_dc_p$tr_io' constrained to Bel 'X0/Y62/PIOA'. Info: $rsw_s25_aux_dc_p$iobuf_i: rsw_s25_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s25_aux_dc_p$tr_io' constrained to Bel 'X0/Y50/PIOA'. Info: $rsw_s24_aux_dc_p$iobuf_i: rsw_s24_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s24_aux_dc_p$tr_io' constrained to Bel 'X0/Y47/PIOA'. Info: $rsw_s23_aux_dc_p$iobuf_i: rsw_s23_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s23_aux_dc_p$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $rsw_s22_aux_dc_p$iobuf_i: rsw_s22_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s22_aux_dc_p$tr_io' constrained to Bel 'X0/Y41/PIOA'. Info: $rsw_s21_aux_dc_p$iobuf_i: rsw_s21_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s21_aux_dc_p$tr_io' constrained to Bel 'X0/Y38/PIOA'. Info: $rsw_s20_aux_dc_p$iobuf_i: rsw_s20_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s20_aux_dc_p$tr_io' constrained to Bel 'X0/Y35/PIOA'. Info: $rsw_s1_aux_dc_p$iobuf_i: rsw_s1_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s1_aux_dc_p$tr_io' constrained to Bel 'X90/Y53/PIOA'. Info: $rsw_s19_aux_dc_p$iobuf_i: rsw_s19_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s19_aux_dc_p$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: $rsw_s18_aux_dc_p$iobuf_i: rsw_s18_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s18_aux_dc_p$tr_io' constrained to Bel 'X90/Y35/PIOA'. Info: $rsw_s17_aux_dc_p$iobuf_i: rsw_s17_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s17_aux_dc_p$tr_io' constrained to Bel 'X90/Y38/PIOA'. Info: $rsw_s16_aux_dc_p$iobuf_i: rsw_s16_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s16_aux_dc_p$tr_io' constrained to Bel 'X90/Y41/PIOA'. Info: $rsw_s15_aux_dc_p$iobuf_i: rsw_s15_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s15_aux_dc_p$tr_io' constrained to Bel 'X90/Y11/PIOA'. Info: $rsw_s14_aux_dc_p$iobuf_i: rsw_s14_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s14_aux_dc_p$tr_io' constrained to Bel 'X90/Y14/PIOA'. Info: $rsw_s13_aux_dc_p$iobuf_i: rsw_s13_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s13_aux_dc_p$tr_io' constrained to Bel 'X90/Y17/PIOA'. Info: $rsw_s12_aux_dc_p$iobuf_i: rsw_s12_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s12_aux_dc_p$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: $rsw_s11_aux_dc_p$iobuf_i: rsw_s11_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s11_aux_dc_p$tr_io' constrained to Bel 'X90/Y23/PIOA'. Info: $rsw_s10_aux_dc_p$iobuf_i: rsw_s10_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s10_aux_dc_p$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: $rsw_s0_aux_dc_p$iobuf_i: rsw_s0_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s0_aux_dc_p$tr_io' constrained to Bel 'X90/Y56/PIOA'. Info: $ignition_ctrl_to_rsw_b_dc_p$iobuf_i: ignition_ctrl_to_rsw_b_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_rsw_b_dc_p$tr_io' constrained to Bel 'X0/Y17/PIOA'. Info: $ignition_ctrl_to_psc1_dc_p$iobuf_i: ignition_ctrl_to_psc1_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc1_dc_p$tr_io' constrained to Bel 'X0/Y14/PIOA'. Info: $ignition_ctrl_to_psc0_dc_p$iobuf_i: ignition_ctrl_to_psc0_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc0_dc_p$tr_io' constrained to Bel 'X0/Y11/PIOA'. Info: $i2c_fpga_to_tf_sda$iobuf_i: i2c_fpga_to_tf_sda_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_sda$tr_io' constrained to Bel 'X69/Y0/PIOA'. Info: $i2c_fpga_to_tf_scl$iobuf_i: i2c_fpga_to_tf_scl_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_scl$tr_io' constrained to Bel 'X51/Y0/PIOB'. Info: pin 'vr_v1p0_mgmt_to_fpga_pg$tr_io' constrained to Bel 'X85/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_vrhot_l$tr_io' constrained to Bel 'X53/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vddt_pg$tr_io' constrained to Bel 'X47/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vdda15_pg$tr_io' constrained to Bel 'X47/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_fault$tr_io' constrained to Bel 'X27/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_vrhot_l$tr_io' constrained to Bel 'X58/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_pg$tr_io' constrained to Bel 'X58/Y0/PIOB'. Info: pin 'vr_tf_vddcore_to_fpga_fault$tr_io' constrained to Bel 'X31/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vr_hot_l$tr_io' constrained to Bel 'X53/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdda1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdd1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOA'. Info: pin 'vr_tf_v1p8_to_fpga_fault$tr_io' constrained to Bel 'X13/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[2]$tr_io' constrained to Bel 'X83/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[1]$tr_io' constrained to Bel 'X83/Y0/PIOA'. Info: pin 'tf_to_fpga_vid[0]$tr_io' constrained to Bel 'X80/Y0/PIOB'. Info: pin 'tf_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOB'. Info: pin 'tf_pg_led$tr_io' constrained to Bel 'X38/Y0/PIOB'. Info: pin 'spi_sp_to_fpga_sck$tr_io' constrained to Bel 'X18/Y71/PIOA'. Info: pin 'spi_sp_to_fpga_mosi$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_miso_r$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_cs1_l$tr_io' constrained to Bel 'X13/Y71/PIOB'. Info: pin 'sp_to_fpga_design_reset_l$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 's9_rsw_aux_p$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 's8_rsw_aux_p$tr_io' constrained to Bel 'X90/Y44/PIOC'. Info: pin 's7_rsw_aux_p$tr_io' constrained to Bel 'X90/Y50/PIOC'. Info: pin 's6_rsw_aux_p$tr_io' constrained to Bel 'X90/Y59/PIOC'. Info: pin 's5_rsw_aux_p$tr_io' constrained to Bel 'X90/Y62/PIOC'. Info: pin 's4_rsw_aux_p$tr_io' constrained to Bel 'X90/Y47/PIOC'. Info: pin 's3_rsw_aux_p$tr_io' constrained to Bel 'X90/Y65/PIOC'. Info: pin 's31_rsw_aux_p$tr_io' constrained to Bel 'X0/Y56/PIOC'. Info: pin 's30_rsw_aux_p$tr_io' constrained to Bel 'X0/Y53/PIOC'. Info: pin 's2_rsw_aux_p$tr_io' constrained to Bel 'X90/Y68/PIOC'. Info: pin 's29_rsw_aux_p$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: pin 's28_rsw_aux_p$tr_io' constrained to Bel 'X0/Y65/PIOC'. Info: pin 's27_rsw_aux_p$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 's26_rsw_aux_p$tr_io' constrained to Bel 'X0/Y62/PIOC'. Info: pin 's25_rsw_aux_p$tr_io' constrained to Bel 'X0/Y50/PIOC'. Info: pin 's24_rsw_aux_p$tr_io' constrained to Bel 'X0/Y47/PIOC'. Info: pin 's23_rsw_aux_p$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 's22_rsw_aux_p$tr_io' constrained to Bel 'X0/Y41/PIOC'. Info: pin 's21_rsw_aux_p$tr_io' constrained to Bel 'X0/Y38/PIOC'. Info: pin 's20_rsw_aux_p$tr_io' constrained to Bel 'X0/Y35/PIOC'. Info: pin 's1_rsw_aux_p$tr_io' constrained to Bel 'X90/Y53/PIOC'. Info: pin 's19_rsw_aux_p$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: pin 's18_rsw_aux_p$tr_io' constrained to Bel 'X90/Y35/PIOC'. Info: pin 's17_rsw_aux_p$tr_io' constrained to Bel 'X90/Y38/PIOC'. Info: pin 's16_rsw_aux_p$tr_io' constrained to Bel 'X90/Y41/PIOC'. Info: pin 's15_rsw_aux_p$tr_io' constrained to Bel 'X90/Y11/PIOC'. Info: pin 's14_rsw_aux_p$tr_io' constrained to Bel 'X90/Y14/PIOC'. Info: pin 's13_rsw_aux_p$tr_io' constrained to Bel 'X90/Y17/PIOC'. Info: pin 's12_rsw_aux_p$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 's11_rsw_aux_p$tr_io' constrained to Bel 'X90/Y23/PIOC'. Info: pin 's10_rsw_aux_p$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 's0_rsw_aux_p$tr_io' constrained to Bel 'X90/Y56/PIOC'. Info: pin 'pcie_host_to_fpga_perst$tr_io' constrained to Bel 'X9/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_pwrflt$tr_io' constrained to Bel 'X4/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_prsnt_l$tr_io' constrained to Bel 'X4/Y0/PIOA'. Info: pin 'mgmt_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_mgmt_pg$tr_io' constrained to Bel 'X44/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p2_mgmt_pg$tr_io' constrained to Bel 'X49/Y0/PIOB'. Info: pin 'ldo_to_fpga_v0p75_tf_pcie_pg$tr_io' constrained to Bel 'X42/Y0/PIOB'. Info: pin 'ldo_to_fpga_smu_pg$tr_io' constrained to Bel 'X15/Y0/PIOA'. Info: pin 'ignition_rsw_b_to_ctrl_p$tr_io' constrained to Bel 'X0/Y17/PIOC'. Info: pin 'ignition_psc1_to_ctrl_p$tr_io' constrained to Bel 'X0/Y14/PIOC'. Info: pin 'ignition_psc0_to_ctrl_p$tr_io' constrained to Bel 'X0/Y11/PIOC'. Info: pin 'front_io_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y26/PIOD'. Info: pin 'fpga_to_vr_v1p0_mgmt_en$tr_io' constrained to Bel 'X85/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vddx_en$tr_io' constrained to Bel 'X27/Y0/PIOB'. Info: pin 'fpga_to_vr_tf_vddcore_en$tr_io' constrained to Bel 'X33/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdda1p8_en$tr_io' constrained to Bel 'X20/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdd1p8_en$tr_io' constrained to Bel 'X18/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[3]$tr_io' constrained to Bel 'X76/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[2]$tr_io' constrained to Bel 'X78/Y0/PIOA'. Info: pin 'fpga_to_tf_test_jtsel[1]$tr_io' constrained to Bel 'X78/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[0]$tr_io' constrained to Bel 'X80/Y0/PIOA'. Info: pin 'fpga_to_tf_test_core_tap_l$tr_io' constrained to Bel 'X76/Y0/PIOA'. Info: pin 'fpga_to_tf_pwron_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOB'. Info: pin 'fpga_to_tf_pcie_rst_l$tr_io' constrained to Bel 'X71/Y0/PIOB'. Info: pin 'fpga_to_tf_core_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOA'. Info: pin 'fpga_to_smu_tf_clk_en_l$tr_io' constrained to Bel 'X20/Y0/PIOB'. Info: pin 'fpga_to_smu_reset_l$tr_io' constrained to Bel 'X31/Y0/PIOA'. Info: pin 'fpga_to_smu_mgmt_clk_en_l$tr_io' constrained to Bel 'X38/Y0/PIOA'. Info: pin 'fpga_to_phy4_reset_l$tr_io' constrained to Bel 'X0/Y29/PIOB'. Info: pin 'fpga_to_mgmt_reset_l$tr_io' constrained to Bel 'X29/Y0/PIOB'. Info: pin 'fpga_to_ldo_v2p5_mgmt_en$tr_io' constrained to Bel 'X44/Y0/PIOA'. Info: pin 'fpga_to_ldo_v1p2_mgmt_en$tr_io' constrained to Bel 'X49/Y0/PIOA'. Info: pin 'fpga_to_ldo_v0p75_tf_pcie_en$tr_io' constrained to Bel 'X42/Y0/PIOA'. Info: pin 'fpga_to_ldo_smu_en$tr_io' constrained to Bel 'X15/Y0/PIOB'. Info: pin 'fpga_to_front_io_hsc_en$tr_io' constrained to Bel 'X0/Y26/PIOC'. Info: pin 'fpga_to_fan3_led_l$tr_io' constrained to Bel 'X29/Y0/PIOA'. Info: pin 'fpga_to_fan3_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: pin 'fpga_to_fan2_led_l$tr_io' constrained to Bel 'X22/Y0/PIOA'. Info: pin 'fpga_to_fan2_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: pin 'fpga_to_fan1_led_l$tr_io' constrained to Bel 'X18/Y0/PIOA'. Info: pin 'fpga_to_fan1_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOA'. Info: pin 'fpga_to_fan0_led_l$tr_io' constrained to Bel 'X13/Y0/PIOA'. Info: pin 'fpga_to_fan0_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOC'. Info: pin 'fpga_led0$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'fpga_debug1$tr_io' constrained to Bel 'X33/Y0/PIOB'. Info: pin 'fpga_debug0$tr_io' constrained to Bel 'X36/Y0/PIOB'. Info: pin 'fan3_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOB'. Info: pin 'fan3_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOB'. Info: pin 'fan2_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOA'. Info: pin 'fan2_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOD'. Info: pin 'fan1_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOD'. Info: pin 'fan1_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOB'. Info: pin 'fan0_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOC'. Info: pin 'fan0_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOD'. Info: pin 'clk_50m_fpga_refclk$tr_io' constrained to Bel 'X36/Y0/PIOA'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 7262 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk_50m_fpga_refclk$TRELLIS_IO_IN to global network Info: Checksum: 0xea3fb19d Info: Annotating ports with timing budgets for target frequency 50.00 MHz Info: Checksum: 0x284164af Info: Device utilisation: Info: TRELLIS_IO: 146/ 245 59% Info: DCCA: 1/ 56 1% Info: DP16KD: 2/ 108 1% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 15019/43848 34% Info: TRELLIS_COMB: 28536/43848 65% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 146 cells based on constraints. Info: Creating initial analytic placement for 30563 cells, random placement wirelen = 2401955. Info: at initial placer iter 0, wirelen = 26521 Info: at initial placer iter 1, wirelen = 18359 Info: at initial placer iter 2, wirelen = 15228 Info: at initial placer iter 3, wirelen = 15048 Info: Running main analytical placer, max placement attempts per cell = 238754952. Info: at iteration #1, type ALL: wirelen solved = 14146, spread = 274157, legal = 393425; time = 3.51s Info: at iteration #2, type ALL: wirelen solved = 55038, spread = 144491, legal = 254800; time = 3.01s Info: at iteration #3, type ALL: wirelen solved = 66977, spread = 123604, legal = 237778; time = 3.02s Info: at iteration #4, type ALL: wirelen solved = 71289, spread = 116352, legal = 217413; time = 2.79s Info: at iteration #5, type ALL: wirelen solved = 75732, spread = 112870, legal = 205042; time = 2.64s Info: at iteration #6, type ALL: wirelen solved = 78904, spread = 111228, legal = 196589; time = 2.46s Info: at iteration #7, type ALL: wirelen solved = 81691, spread = 114494, legal = 177697; time = 3.35s Info: at iteration #8, type ALL: wirelen solved = 86592, spread = 112276, legal = 165951; time = 1.96s Info: at iteration #9, type ALL: wirelen solved = 87324, spread = 111987, legal = 168936; time = 2.01s Info: at iteration #10, type ALL: wirelen solved = 89591, spread = 111203, legal = 168208; time = 2.03s Info: at iteration #11, type ALL: wirelen solved = 90890, spread = 110669, legal = 167717; time = 1.93s Info: at iteration #12, type ALL: wirelen solved = 91834, spread = 110991, legal = 179548; time = 2.13s Info: at iteration #13, type ALL: wirelen solved = 94407, spread = 111755, legal = 178012; time = 2.07s Info: HeAP Placer Time: 40.56s Info: of which solving equations: 11.88s Info: of which spreading cells: 3.30s Info: of which strict legalisation: 20.64s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 712, wirelen = 165951 Info: at iteration #5: temp = 0.000000, timing cost = 284, wirelen = 141972 Info: at iteration #10: temp = 0.000000, timing cost = 301, wirelen = 133829 Info: at iteration #15: temp = 0.000000, timing cost = 343, wirelen = 129646 Info: at iteration #20: temp = 0.000000, timing cost = 358, wirelen = 126434 Info: at iteration #25: temp = 0.000000, timing cost = 352, wirelen = 125477 Info: at iteration #30: temp = 0.000000, timing cost = 349, wirelen = 125020 Info: at iteration #33: temp = 0.000000, timing cost = 349, wirelen = 124879 Info: SA placement time 92.69s Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 40.60 MHz (FAIL at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 6.18 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 12.28 ns Info: Slack histogram: Info: legend: * represents 75 endpoint(s) Info: + represents [1,75) endpoint(s) Info: [ -4629, -3435) |+ Info: [ -3435, -2241) | Info: [ -2241, -1047) | Info: [ -1047, 147) |+ Info: [ 147, 1341) |+ Info: [ 1341, 2535) |+ Info: [ 2535, 3729) |*+ Info: [ 3729, 4923) |****+ Info: [ 4923, 6117) |*********+ Info: [ 6117, 7311) |**********+ Info: [ 7311, 8505) |*********************+ Info: [ 8505, 9699) |**************************+ Info: [ 9699, 10893) |****************************+ Info: [ 10893, 12087) |***************************************+ Info: [ 12087, 13281) |*************************************************+ Info: [ 13281, 14475) |*******************************************************+ Info: [ 14475, 15669) |*****************************************************+ Info: [ 15669, 16863) |**************************************+ Info: [ 16863, 18057) |************************+ Info: [ 18057, 19251) |************************************************************ Info: Checksum: 0xc3433835 Info: Routing globals... Info: routing clock net $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 111084 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 2 997 | 2 997 | 110088| 1.68 1.68| Info: 2000 | 33 1966 | 31 969 | 109133| 0.19 1.88| Info: 3000 | 130 2869 | 97 903 | 108672| 0.21 2.09| Info: 4000 | 226 3773 | 96 904 | 107880| 0.19 2.28| Info: 5000 | 318 4681 | 92 908 | 107309| 0.17 2.45| Info: 6000 | 417 5582 | 99 901 | 106444| 0.17 2.62| Info: 7000 | 527 6472 | 110 890 | 105627| 0.18 2.80| Info: 8000 | 634 7365 | 107 893 | 105085| 0.24 3.04| Info: 9000 | 723 8276 | 89 911 | 104911| 0.22 3.26| Info: 10000 | 812 9187 | 89 911 | 104094| 0.19 3.45| Info: 11000 | 924 10075 | 112 888 | 103332| 0.19 3.64| Info: 12000 | 1037 10962 | 113 887 | 102510| 0.20 3.84| Info: 13000 | 1147 11852 | 110 890 | 101660| 0.19 4.03| Info: 14000 | 1259 12740 | 112 888 | 100821| 0.20 4.23| Info: 15000 | 1374 13625 | 115 885 | 99975| 0.20 4.43| Info: 16000 | 1473 14526 | 99 901 | 99259| 0.24 4.67| Info: 17000 | 1583 15416 | 110 890 | 98444| 0.21 4.88| Info: 18000 | 1688 16311 | 105 895 | 97625| 0.20 5.08| Info: 19000 | 1797 17202 | 109 891 | 96779| 0.21 5.28| Info: 20000 | 1934 18065 | 137 863 | 95956| 0.21 5.50| Info: 21000 | 2050 18949 | 116 884 | 95122| 0.20 5.69| Info: 22000 | 2144 19855 | 94 906 | 94274| 0.21 5.90| Info: 23000 | 2279 20720 | 135 865 | 93462| 0.21 6.12| Info: 24000 | 2386 21613 | 107 893 | 92590| 0.20 6.32| Info: 25000 | 2493 22506 | 107 893 | 91941| 0.24 6.56| Info: 26000 | 2635 23364 | 142 858 | 91130| 0.20 6.76| Info: 27000 | 2780 24219 | 145 855 | 90328| 0.21 6.97| Info: 28000 | 2905 25094 | 125 875 | 89489| 0.21 7.18| Info: 29000 | 3023 25975 | 118 881 | 88632| 0.22 7.40| Info: 30000 | 3142 26855 | 119 880 | 87848| 0.22 7.62| Info: 31000 | 3259 27737 | 117 882 | 87003| 0.21 7.82| Info: 32000 | 3366 28630 | 107 893 | 86167| 0.24 8.06| Info: 33000 | 3489 29495 | 123 865 | 85360| 0.22 8.28| Info: 34000 | 3585 30387 | 96 892 | 84468| 0.28 8.56| Info: 35000 | 3681 31275 | 96 888 | 83601| 0.20 8.75| Info: 36000 | 3768 32164 | 87 889 | 82706| 0.19 8.95| Info: 37000 | 3888 33030 | 120 866 | 81839| 0.21 9.16| Info: 38000 | 3975 33912 | 87 882 | 80987| 0.21 9.37| Info: 39000 | 4086 34764 | 111 852 | 80107| 0.19 9.56| Info: 40000 | 4219 35589 | 133 825 | 79251| 0.20 9.76| Info: 41000 | 4343 36433 | 124 844 | 78438| 0.21 9.97| Info: 42000 | 4462 37274 | 119 841 | 77578| 0.20 10.17| Info: 43000 | 4571 38121 | 109 847 | 76704| 0.21 10.38| Info: 44000 | 4695 38965 | 124 844 | 75855| 0.21 10.59| Info: 45000 | 4809 39818 | 114 853 | 74995| 0.22 10.81| Info: 46000 | 4939 40658 | 130 840 | 74137| 0.22 11.02| Info: 47000 | 5053 41513 | 114 855 | 73289| 0.21 11.23| Info: 48000 | 5154 42371 | 101 858 | 72404| 0.22 11.46| Info: 49000 | 5266 43222 | 112 851 | 71614| 0.24 11.70| Info: 50000 | 5377 44084 | 111 862 | 70846| 0.27 11.96| Info: 51000 | 5478 44960 | 101 876 | 69950| 0.21 12.18| Info: 52000 | 5601 45820 | 123 860 | 69090| 0.22 12.40| Info: 53000 | 5751 46647 | 150 827 | 68283| 0.21 12.61| Info: 54000 | 5881 47502 | 130 855 | 67445| 0.23 12.84| Info: 55000 | 6008 48359 | 127 857 | 66600| 0.24 13.08| Info: 56000 | 6130 49209 | 122 850 | 65730| 0.23 13.32| Info: 57000 | 6257 50066 | 127 857 | 64879| 0.23 13.54| Info: 58000 | 6385 50911 | 128 845 | 64032| 0.23 13.77| Info: 59000 | 6524 51761 | 139 850 | 63185| 0.24 14.01| Info: 60000 | 6642 52627 | 118 866 | 62340| 0.25 14.25| Info: 61000 | 6778 53461 | 136 834 | 61497| 0.24 14.49| Info: 62000 | 6926 54291 | 148 830 | 60653| 0.24 14.73| Info: 63000 | 7075 55105 | 149 814 | 59815| 0.25 14.98| Info: 64000 | 7237 55912 | 162 807 | 59004| 0.25 15.22| Info: 65000 | 7372 56755 | 135 843 | 58190| 0.26 15.49| Info: 66000 | 7527 57576 | 155 821 | 57375| 0.24 15.73| Info: 67000 | 7691 58366 | 164 790 | 56584| 0.25 15.98| Info: 68000 | 7848 59137 | 157 771 | 55769| 0.24 16.22| Info: 69000 | 8006 59939 | 158 802 | 54946| 0.25 16.47| Info: 70000 | 8170 60737 | 164 798 | 54137| 0.27 16.74| Info: 71000 | 8306 61549 | 136 812 | 53297| 0.25 16.99| Info: 72000 | 8479 62320 | 173 771 | 52498| 0.38 17.38| Info: 73000 | 8642 63093 | 163 773 | 51676| 0.25 17.62| Info: 74000 | 8830 63869 | 188 776 | 50890| 0.27 17.89| Info: 75000 | 8988 64649 | 158 780 | 50059| 0.27 18.16| Info: 76000 | 9166 65429 | 178 780 | 49260| 0.26 18.42| Info: 77000 | 9384 66183 | 218 754 | 48534| 0.28 18.70| Info: 78000 | 9543 66984 | 159 801 | 47748| 0.29 18.99| Info: 79000 | 9720 67767 | 177 783 | 46969| 0.27 19.26| Info: 80000 | 9891 68543 | 171 776 | 46230| 0.28 19.55| Info: 81000 | 10086 69307 | 195 764 | 45475| 0.29 19.83| Info: 82000 | 10260 70092 | 174 785 | 44685| 0.29 20.12| Info: 83000 | 10428 70888 | 168 796 | 43928| 0.31 20.43| Info: 84000 | 10641 71633 | 213 745 | 43168| 0.28 20.71| Info: 85000 | 10835 72395 | 194 762 | 42392| 0.30 21.01| Info: 86000 | 11032 73144 | 197 749 | 41614| 0.29 21.30| Info: 87000 | 11248 73895 | 216 751 | 40858| 0.32 21.62| Info: 88000 | 11421 74682 | 173 787 | 40051| 0.30 21.91| Info: 89000 | 11586 75480 | 165 798 | 39248| 0.29 22.20| Info: 90000 | 11811 76243 | 225 763 | 38522| 0.32 22.53| Info: 91000 | 12012 77014 | 201 771 | 37755| 0.29 22.82| Info: 92000 | 12199 77817 | 187 803 | 36959| 0.29 23.11| Info: 93000 | 12356 78630 | 157 813 | 36139| 0.28 23.39| Info: 94000 | 12550 79404 | 194 774 | 35361| 0.29 23.68| Info: 95000 | 12759 80152 | 209 748 | 34596| 0.32 24.00| Info: 96000 | 12971 80913 | 212 761 | 33838| 0.31 24.31| Info: 97000 | 13175 81663 | 204 750 | 33065| 0.33 24.64| Info: 98000 | 13357 82454 | 182 791 | 32267| 0.32 24.96| Info: 99000 | 13590 83199 | 233 745 | 31524| 0.31 25.27| Info: 100000 | 13807 83962 | 217 763 | 30788| 0.33 25.60| Info: 101000 | 14033 84719 | 226 757 | 30051| 0.31 25.91| Info: 102000 | 14266 85442 | 233 723 | 29304| 0.30 26.21| Info: 103000 | 14526 86149 | 260 707 | 28611| 0.32 26.53| Info: 104000 | 14770 86859 | 244 710 | 27872| 0.31 26.84| Info: 105000 | 15030 87557 | 260 698 | 27187| 0.30 27.14| Info: 106000 | 15297 88271 | 267 714 | 26469| 0.30 27.44| Info: 107000 | 15529 88997 | 232 726 | 25726| 0.28 27.72| Info: 108000 | 15783 89690 | 254 693 | 25005| 0.30 28.03| Info: 109000 | 16010 90434 | 227 744 | 24276| 0.31 28.33| Info: 110000 | 16217 91169 | 207 735 | 23508| 0.35 28.69| Info: 111000 | 16512 91812 | 295 643 | 22842| 0.33 29.02| Info: 112000 | 16757 92529 | 245 717 | 22121| 0.29 29.31| Info: 113000 | 16971 93208 | 214 679 | 21360| 0.29 29.60| Info: 114000 | 17207 93942 | 236 734 | 20634| 0.31 29.91| Info: 115000 | 17443 94677 | 236 735 | 19893| 0.33 30.24| Info: 116000 | 17657 95448 | 214 771 | 19154| 0.30 30.54| Info: 117000 | 17980 96110 | 323 662 | 18525| 0.32 30.86| Info: 118000 | 18239 96762 | 259 652 | 17859| 0.30 31.16| Info: 119000 | 18608 97393 | 369 631 | 17278| 0.34 31.50| Info: 120000 | 18876 98125 | 268 732 | 16602| 0.36 31.86| Info: 121000 | 19115 98856 | 239 731 | 15871| 0.37 32.23| Info: 122000 | 19428 99539 | 313 683 | 15233| 0.33 32.55| Info: 123000 | 19687 100254 | 259 715 | 14505| 0.31 32.86| Info: 124000 | 19959 100966 | 272 712 | 13800| 0.31 33.17| Info: 125000 | 20219 101706 | 260 740 | 13088| 0.32 33.49| Info: 126000 | 20497 102426 | 278 720 | 12401| 0.32 33.81| Info: 127000 | 20811 103112 | 314 686 | 11789| 0.35 34.16| Info: 128000 | 21062 103861 | 251 749 | 11284| 0.43 34.60| Info: 129000 | 21411 104511 | 349 650 | 10684| 0.35 34.94| Info: 130000 | 21811 105111 | 400 600 | 10145| 0.36 35.31| Info: 131000 | 22203 105719 | 392 608 | 9600| 0.38 35.69| Info: 132000 | 22531 106391 | 328 672 | 9025| 0.35 36.04| Info: 133000 | 22838 107084 | 307 693 | 8372| 0.37 36.41| Info: 134000 | 23163 107735 | 325 651 | 7747| 0.40 36.81| Info: 135000 | 23528 108370 | 365 635 | 7207| 0.58 37.39| Info: 136000 | 23858 109040 | 330 670 | 6665| 0.48 37.88| Info: 137000 | 24070 109828 | 212 788 | 5915| 0.35 38.22| Info: 138000 | 24366 110532 | 296 704 | 5254| 0.41 38.63| Info: 139000 | 24738 111160 | 372 628 | 4748| 0.50 39.13| Info: 140000 | 25090 111808 | 352 648 | 4197| 0.49 39.61| Info: 141000 | 25479 112419 | 389 611 | 3730| 0.47 40.08| Info: 142000 | 25831 113067 | 352 648 | 3098| 0.37 40.45| Info: 143000 | 26096 113676 | 265 609 | 2403| 0.34 40.79| Info: 144000 | 26182 114268 | 86 592 | 1581| 0.33 41.12| Info: 145000 | 26281 114867 | 99 599 | 986| 0.35 41.47| Info: 146000 | 26344 115483 | 63 616 | 104| 0.33 41.80| Info: 146123 | 26353 115558 | 9 75 | 0| 0.25 42.05| Info: Routing complete. Info: Router1 time 42.05s Info: Checksum: 0x7593a5c3 Info: Critical path report for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source ignition_io_bank3_0_txrs_rx_decode_result.empty_reg_TRELLIS_FF_Q.Q Info: 1.0 1.5 Net ignition_io_bank3_0_txrs_rx_decode_result.EMPTY_N budget 0.682000 ns (71,42) -> (72,42) Info: Sink ignition_io_bank3_0_txrs_rx_channels_3_phase$D_IN_LUT4_Z_2_A_LUT4_Z_1.D Info: Defined in: Info: ./env/f7b056cc316596691506e7583ebbce34fdde671f/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:40453.28-40461.74 Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2056.27-2056.36 Info: 0.2 1.7 Source ignition_io_bank3_0_txrs_rx_channels_3_phase$D_IN_LUT4_Z_2_A_LUT4_Z_1.F Info: 1.2 2.9 Net ignition_io_bank3_0_txrs_rx_channels_3_phase$D_IN_LUT4_Z_2_A[3] budget 0.681000 ns (72,42) -> (70,45) Info: Sink WILL_FIRE_RL_ignition_io_bank3_0_txrs_rx_do_channel_receive_3_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 3.2 Source WILL_FIRE_RL_ignition_io_bank3_0_txrs_rx_do_channel_receive_3_LUT4_Z.F Info: 1.0 4.2 Net WILL_FIRE_RL_ignition_io_bank3_0_txrs_rx_do_channel_receive_3 budget 0.681000 ns (70,45) -> (71,43) Info: Sink ignition_io_bank3_0_txrs_rx_channels_4_phase$D_IN_LUT4_Z_2_B_LUT4_C_Z_LUT4_Z.C Info: Defined in: Info: ./env/f7b056cc316596691506e7583ebbce34fdde671f/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:16164.8-16164.66 Info: 0.2 4.4 Source ignition_io_bank3_0_txrs_rx_channels_4_phase$D_IN_LUT4_Z_2_B_LUT4_C_Z_LUT4_Z.F Info: 1.1 5.5 Net ignition_io_bank3_0_txrs_rx_channels_0_phase$D_IN_LUT4_Z_2_B_LUT4_C_Z[2] budget 0.681000 ns (71,43) -> (71,44) Info: Sink ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.C Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.7 Source ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.F Info: 0.0 5.7 Net ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT budget 0.545000 ns (71,44) -> (71,44) Info: Sink ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.F1 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.46-157.48 Info: 0.2 5.9 Source ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 5.9 Net ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1 budget 0.000000 ns (71,44) -> (71,44) Info: Sink ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.62-157.64 Info: 0.2 6.1 Source ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 6.1 Net ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1 budget 0.000000 ns (71,44) -> (71,44) Info: Sink ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 6.3 Source ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_2_B_LUT4_D_Z_L6MUX21_SD_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.6 8.0 Net ignition_io_bank3_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_B[2] budget 1.089000 ns (71,44) -> (74,40) Info: Sink ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.B Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 8.4 Source ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 8.4 Net ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0 budget 0.000000 ns (74,40) -> (74,40) Info: Sink ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.58-157.60 Info: 0.2 8.6 Source ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 8.6 Net ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1 budget 0.000000 ns (74,40) -> (74,40) Info: Sink ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXB Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 8.9 Source ignition_io_bank3_0_txrs_deserializers_3_out.empty_reg_LUT4_D_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.1 10.0 Net ignition_io_bank3_0_txrs_deserializers_0_out.empty_reg_LUT4_D_C[0] budget 5.234000 ns (74,40) -> (76,42) Info: Sink ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_SD_LUT4_Z_2.B Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 10.2 Source ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_SD_LUT4_Z_2.F Info: 0.9 11.1 Net ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_SD[3] budget 2.616000 ns (76,42) -> (77,41) Info: Sink ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 11.5 Source ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D0_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 11.5 Net ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D0_L6MUX21_Z_D0 budget 0.000000 ns (77,41) -> (77,41) Info: Sink ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.50-157.52 Info: 0.2 11.7 Source ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D0_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.0 11.7 Net ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D0 budget 0.000000 ns (77,41) -> (77,41) Info: Sink ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.FXA Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.66-157.68 Info: 0.2 12.0 Source ignition_io_bank3_0_txrs_rx_decode_input.D_IN_L6MUX21_Z_2_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.9 12.9 Net ignition_io_bank3_0_txrs_rx_decode_input.D_IN[8] budget 2.616000 ns (77,41) -> (75,40) Info: Sink ignition_io_bank3_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_5.M Info: Defined in: Info: ./env/f7b056cc316596691506e7583ebbce34fdde671f/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:40442.28-40450.72 Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2045.26-2045.30 Info: 0.0 12.9 Setup ignition_io_bank3_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_5.M Info: 4.1 ns logic, 8.8 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source sp_to_fpga_design_reset_l$tr_io.O Info: 1.3 1.3 Net sp_to_fpga_design_reset_l$TRELLIS_IO_IN budget 9.670000 ns (4,71) -> (6,67) Info: Sink sp_to_fpga_design_reset_l_LUT4_D.D Info: Defined in: Info: ./env/f7b056cc316596691506e7583ebbce34fdde671f/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:413.10-413.35 Info: 0.2 1.6 Source sp_to_fpga_design_reset_l_LUT4_D.F Info: 1.7 3.3 Net controller_ignition_controllers__0_tx.RST_TRELLIS_FF_Q_LSR budget 9.670000 ns (6,67) -> (14,57) Info: Sink controller_ignition_controllers__0_tx.RST_TRELLIS_FF_Q.LSR Info: 0.4 3.8 Setup controller_ignition_controllers__0_tx.RST_TRELLIS_FF_Q.LSR Info: 0.7 ns logic, 3.1 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' -> '': Info: curr total Info: 0.5 0.5 Source controller_clock_generator_sequencer_ldo_enabled_r_TRELLIS_FF_Q.Q Info: 5.4 6.0 Net fpga_to_ldo_smu_en$TRELLIS_IO_OUT budget 19.475000 ns (32,68) -> (15,0) Info: Sink fpga_to_ldo_smu_en$tr_io.I Info: Defined in: Info: ./env/f7b056cc316596691506e7583ebbce34fdde671f/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:562.10-562.28 Info: 0.5 ns logic, 5.4 ns routing Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 77.69 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 3.76 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 5.95 ns Info: Slack histogram: Info: legend: * represents 53 endpoint(s) Info: + represents [1,53) endpoint(s) Info: [ 7129, 7745) |*+ Info: [ 7745, 8361) |**+ Info: [ 8361, 8977) |*****+ Info: [ 8977, 9593) |*****+ Info: [ 9593, 10209) |*******+ Info: [ 10209, 10825) |*************+ Info: [ 10825, 11441) |*******************+ Info: [ 11441, 12057) |************************+ Info: [ 12057, 12673) |*********************************+ Info: [ 12673, 13289) |**************************************+ Info: [ 13289, 13905) |********************************************+ Info: [ 13905, 14521) |************************************************************ Info: [ 14521, 15137) |************************************************+ Info: [ 15137, 15753) |******************************************+ Info: [ 15753, 16369) |***************************************+ Info: [ 16369, 16985) |**********************************************+ Info: [ 16985, 17601) |********************************************+ Info: [ 17601, 18217) |***********************************+ Info: [ 18217, 18833) |*******************************************************+ Info: [ 18833, 19449) |**********************************+ Info: Program finished normally.