Info: constraining clock net 'CLK_12mhz' to 12.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:       113/83640     0%
Info:         logic LUTs:     61/83640     0%
Info:         carry LUTs:     52/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:        55/83640     0%

Info: Packing IOs..
Info: pin 'uart_tx$tr_io' constrained to Bel 'X0/Y92/PIOC'.
Info: pin 'uart_rx$tr_io' constrained to Bel 'X0/Y92/PIOB'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X114/Y0/PIOA'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X116/Y0/PIOA'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X114/Y0/PIOB'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X116/Y0/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X119/Y0/PIOA'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X119/Y0/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X76/Y0/PIOA'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X76/Y0/PIOB'.
Info: pin 'btn$tr_io' constrained to Bel 'X0/Y92/PIOD'.
Info: pin 'GSR_N$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'CLK_12mhz$tr_io' constrained to Bel 'X63/Y0/PIOA'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     49 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info:     Input frequency of PLL 'pll_pll.pll_i' is constrained to 12.0 MHz
Info:     Derived frequency constraint of 100.0 MHz for net pll_pll.CLKOP
Info:     Derived frequency constraint of 50.0 MHz for net pll_pll.CLKOS
Info:     Derived frequency constraint of inf MHz for net pll_pll.CLKOS2
Info:     Derived frequency constraint of inf MHz for net pll_pll.CLKOS3
Info: Promoting globals...
Info:     promoting clock net pll_pll.CLKOP to global network
Info:     promoting clock net pll_pll.CLKOS to global network
Info: Checksum: 0x4dfe34d5

Info: Device utilisation:
Info: 	          TRELLIS_IO:      13/    365     3%
Info: 	                DCCA:       2/     56     3%
Info: 	              DP16KD:       0/    208     0%
Info: 	          MULT18X18D:       0/    156     0%
Info: 	              ALU54B:       0/     78     0%
Info: 	             EHXPLLL:       1/      4    25%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    224     0%
Info: 	            SIOLOGIC:       0/    141     0%
Info: 	                 GSR:       1/      1   100%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     14     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:      55/  83640     0%
Info: 	        TRELLIS_COMB:     123/  83640     0%
Info: 	        TRELLIS_RAMW:       0/  10455     0%

Info: Placed 15 cells based on constraints.
Info: Creating initial analytic placement for 45 cells, random placement wirelen = 8957.
Info:     at initial placer iter 0, wirelen = 727
Info:     at initial placer iter 1, wirelen = 726
Info:     at initial placer iter 2, wirelen = 711
Info:     at initial placer iter 3, wirelen = 719
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ALL: wirelen solved = 711, spread = 1160, legal = 1178; time = 0.03s
Info:     at iteration #2, type ALL: wirelen solved = 727, spread = 1116, legal = 1123; time = 0.00s
Info:     at iteration #3, type ALL: wirelen solved = 724, spread = 1161, legal = 1166; time = 0.00s
Info:     at iteration #4, type ALL: wirelen solved = 724, spread = 1145, legal = 1145; time = 0.00s
Info:     at iteration #5, type ALL: wirelen solved = 721, spread = 1006, legal = 1018; time = 0.00s
Info:     at iteration #6, type ALL: wirelen solved = 723, spread = 952, legal = 968; time = 0.00s
Info:     at iteration #7, type ALL: wirelen solved = 723, spread = 964, legal = 976; time = 0.00s
Info:     at iteration #8, type ALL: wirelen solved = 726, spread = 960, legal = 978; time = 0.00s
Info:     at iteration #9, type ALL: wirelen solved = 728, spread = 950, legal = 975; time = 0.00s
Info:     at iteration #10, type ALL: wirelen solved = 727, spread = 950, legal = 987; time = 0.00s
Info:     at iteration #11, type ALL: wirelen solved = 734, spread = 955, legal = 989; time = 0.00s
Info: HeAP Placer Time: 0.24s
Info:   of which solving equations: 0.07s
Info:   of which spreading cells: 0.02s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 26, wirelen = 968
Info:   at iteration #5: temp = 0.000000, timing cost = 25, wirelen = 854
Info:   at iteration #9: temp = 0.000000, timing cost = 25, wirelen = 837 
Info: SA placement time 0.07s

Info: Max frequency for clock '$glbnet$pll_pll.CLKOS': 350.39 MHz (PASS at 50.00 MHz)
Info: Max frequency for clock '$glbnet$pll_pll.CLKOP': 350.39 MHz (PASS at 100.01 MHz)

Info: Max delay <async>                       -> <async>                      : 3.50 ns
Info: Max delay <async>                       -> posedge $glbnet$pll_pll.CLKOP: 11.61 ns
Info: Max delay <async>                       -> posedge $glbnet$pll_pll.CLKOS: 11.55 ns
Info: Max delay posedge $glbnet$pll_pll.CLKOP -> <async>                      : 1.88 ns
Info: Max delay posedge $glbnet$pll_pll.CLKOS -> <async>                      : 1.99 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  7145,   7766) |******** 
Info: [  7766,   8387) |******* 
Info: [  8387,   9008) |*********** 
Info: [  9008,   9629) |** 
Info: [  9629,  10250) | 
Info: [ 10250,  10871) | 
Info: [ 10871,  11492) | 
Info: [ 11492,  12113) | 
Info: [ 12113,  12734) | 
Info: [ 12734,  13355) | 
Info: [ 13355,  13976) | 
Info: [ 13976,  14597) | 
Info: [ 14597,  15218) | 
Info: [ 15218,  15839) | 
Info: [ 15839,  16460) | 
Info: [ 16460,  17081) | 
Info: [ 17081,  17702) |*** 
Info: [ 17702,  18323) |********** 
Info: [ 18323,  18944) |************ 
Info: [ 18944,  19565) |** 
Info: Checksum: 0x7f4cf5fb
Info: Routing globals...
Info:     routing clock net $glbnet$pll_pll.CLKOS using global 0
Info:     routing clock net $glbnet$pll_pll.CLKOP using global 1

Info: Routing..
Info: Setting up routing queue.
Info: Routing 373 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        509 |      129        332 |  129   332 |         0|       0.10       0.10|
Info: Routing complete.
Info: Router1 time 0.10s
Info: Checksum: 0xa6ed2658

Info: Critical path report for clock '$glbnet$pll_pll.CLKOS' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source blinky_50mhz_c_TRELLIS_FF_Q_24.Q
Info:  0.7  1.0    Net blinky_50mhz_c[0] (81,3) -> (82,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S1_1$CCU2_COMB0.A
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:76.16-76.30
Info:  0.3  1.3  Source blinky_50mhz_c$D_IN_CCU2C_S1_1$CCU2_COMB0.FCO
Info:  0.0  1.3    Net blinky_50mhz_c$D_IN_CCU2C_S1_1$CCU2_FCI_INT (82,3) -> (82,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S1_1$CCU2_COMB1.FCI
Info:  0.0  1.3  Source blinky_50mhz_c$D_IN_CCU2C_S1_1$CCU2_COMB1.FCO
Info:  0.0  1.3    Net blinky_50mhz_c$D_IN_CCU2C_S1_1_COUT (82,3) -> (82,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.4  Source blinky_50mhz_c$D_IN_CCU2C_S0_1$CCU2_COMB0.FCO
Info:  0.0  1.4    Net blinky_50mhz_c$D_IN_CCU2C_S0_1$CCU2_FCI_INT (82,3) -> (82,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_1$CCU2_COMB1.FCI
Info:  0.0  1.4  Source blinky_50mhz_c$D_IN_CCU2C_S0_1$CCU2_COMB1.FCO
Info:  0.0  1.4    Net blinky_50mhz_c$D_IN_CCU2C_S0_1_COUT (82,3) -> (82,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.4  Source blinky_50mhz_c$D_IN_CCU2C_S0$CCU2_COMB0.FCO
Info:  0.0  1.4    Net blinky_50mhz_c$D_IN_CCU2C_S0$CCU2_FCI_INT (82,3) -> (82,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0$CCU2_COMB1.FCI
Info:  0.0  1.4  Source blinky_50mhz_c$D_IN_CCU2C_S0$CCU2_COMB1.FCO
Info:  0.0  1.4    Net blinky_50mhz_c$D_IN_CCU2C_S0_COUT (82,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.4  Source blinky_50mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN$CCU2_COMB0.FCO
Info:  0.0  1.4    Net blinky_50mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN$CCU2_FCI_INT (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN$CCU2_COMB1.FCI
Info:  0.0  1.4  Source blinky_50mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN$CCU2_COMB1.FCO
Info:  0.0  1.4    Net blinky_50mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN_COUT (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_LUT4_Z_B_CCU2C_S1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.5  Source blinky_50mhz_c$D_IN_LUT4_Z_B_CCU2C_S1$CCU2_COMB0.FCO
Info:  0.0  1.5    Net blinky_50mhz_c$D_IN_LUT4_Z_B_CCU2C_S1$CCU2_FCI_INT (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_LUT4_Z_B_CCU2C_S1$CCU2_COMB1.FCI
Info:  0.0  1.5  Source blinky_50mhz_c$D_IN_LUT4_Z_B_CCU2C_S1$CCU2_COMB1.FCO
Info:  0.0  1.5    Net blinky_50mhz_c$D_IN_CCU2C_S1_CIN (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S1$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.5  Source blinky_50mhz_c$D_IN_CCU2C_S1$CCU2_COMB0.FCO
Info:  0.0  1.5    Net blinky_50mhz_c$D_IN_CCU2C_S1$CCU2_FCI_INT (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S1$CCU2_COMB1.FCI
Info:  0.0  1.5  Source blinky_50mhz_c$D_IN_CCU2C_S1$CCU2_COMB1.FCO
Info:  0.0  1.5    Net blinky_50mhz_c$D_IN_CCU2C_S1_COUT (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_8$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.6  Source blinky_50mhz_c$D_IN_CCU2C_S0_8$CCU2_COMB0.FCO
Info:  0.0  1.6    Net blinky_50mhz_c$D_IN_CCU2C_S0_8$CCU2_FCI_INT (83,3) -> (83,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_8$CCU2_COMB1.FCI
Info:  0.0  1.6  Source blinky_50mhz_c$D_IN_CCU2C_S0_8$CCU2_COMB1.FCO
Info:  0.0  1.6    Net blinky_50mhz_c$D_IN_CCU2C_S0_8_COUT (83,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_7$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.6  Source blinky_50mhz_c$D_IN_CCU2C_S0_7$CCU2_COMB0.FCO
Info:  0.0  1.6    Net blinky_50mhz_c$D_IN_CCU2C_S0_7$CCU2_FCI_INT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_7$CCU2_COMB1.FCI
Info:  0.0  1.6  Source blinky_50mhz_c$D_IN_CCU2C_S0_7$CCU2_COMB1.FCO
Info:  0.0  1.6    Net blinky_50mhz_c$D_IN_CCU2C_S0_7_COUT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_6$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.7  Source blinky_50mhz_c$D_IN_CCU2C_S0_6$CCU2_COMB0.FCO
Info:  0.0  1.7    Net blinky_50mhz_c$D_IN_CCU2C_S0_6$CCU2_FCI_INT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_6$CCU2_COMB1.FCI
Info:  0.0  1.7  Source blinky_50mhz_c$D_IN_CCU2C_S0_6$CCU2_COMB1.FCO
Info:  0.0  1.7    Net blinky_50mhz_c$D_IN_CCU2C_S0_6_COUT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_5$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.7  Source blinky_50mhz_c$D_IN_CCU2C_S0_5$CCU2_COMB0.FCO
Info:  0.0  1.7    Net blinky_50mhz_c$D_IN_CCU2C_S0_5$CCU2_FCI_INT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_5$CCU2_COMB1.FCI
Info:  0.0  1.7  Source blinky_50mhz_c$D_IN_CCU2C_S0_5$CCU2_COMB1.FCO
Info:  0.0  1.7    Net blinky_50mhz_c$D_IN_CCU2C_S0_5_COUT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_4$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.7  Source blinky_50mhz_c$D_IN_CCU2C_S0_4$CCU2_COMB0.FCO
Info:  0.0  1.7    Net blinky_50mhz_c$D_IN_CCU2C_S0_4$CCU2_FCI_INT (84,3) -> (84,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_4$CCU2_COMB1.FCI
Info:  0.0  1.7  Source blinky_50mhz_c$D_IN_CCU2C_S0_4$CCU2_COMB1.FCO
Info:  0.0  1.7    Net blinky_50mhz_c$D_IN_CCU2C_S0_4_COUT (84,3) -> (85,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_3$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:161.9-161.31
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  1.8  Source blinky_50mhz_c$D_IN_CCU2C_S0_3$CCU2_COMB0.FCO
Info:  0.0  1.8    Net blinky_50mhz_c$D_IN_CCU2C_S0_3$CCU2_FCI_INT (85,3) -> (85,3)
Info:                Sink blinky_50mhz_c$D_IN_CCU2C_S0_3$CCU2_COMB1.FCI
Info:  0.2  2.0  Source blinky_50mhz_c$D_IN_CCU2C_S0_3$CCU2_COMB1.F
Info:  0.5  2.5    Net blinky_50mhz_c$D_IN_CCU2C_S0_3_S1[1] (85,3) -> (85,2)
Info:                Sink blinky_50mhz_c$D_IN_LUT4_Z_3.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  2.7  Source blinky_50mhz_c$D_IN_LUT4_Z_3.F
Info:  0.1  2.8    Net blinky_50mhz_c$D_IN[23] (85,2) -> (85,2)
Info:                Sink blinky_50mhz_c_TRELLIS_FF_Q_1.DI
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:77.17-77.36
Info:  0.0  2.8  Setup blinky_50mhz_c_TRELLIS_FF_Q_1.DI
Info: 1.4 ns logic, 1.4 ns routing

Info: Critical path report for clock '$glbnet$pll_pll.CLKOP' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source blinky_100mhz_c_TRELLIS_FF_Q_25.Q
Info:  0.6  0.9    Net blinky_100mhz_c[0] (81,4) -> (81,4)
Info:                Sink blinky_100mhz_c$D_IN_CCU2C_S0_S1_L6MUX21_Z_1_SD_LUT4_Z.D
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:63.16-63.31
Info:  0.1  1.0  Source blinky_100mhz_c$D_IN_CCU2C_S0_S1_L6MUX21_Z_1_SD_LUT4_Z.F
Info:  0.5  1.5    Net blinky_100mhz_c$D_IN_CCU2C_S0_S1_L6MUX21_Z_1_SD[6] (81,4) -> (82,4)
Info:                Sink blinky_100mhz_c$D_IN_CCU2C_S0_S1_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  1.6  Source blinky_100mhz_c$D_IN_CCU2C_S0_S1_L6MUX21_Z_1_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.6  2.2    Net blinky_100mhz_c$D_IN_CCU2C_S0_COUT_CCU2C_CIN_S0[3] (82,4) -> (83,6)
Info:                Sink blinky_100mhz_d0_TRELLIS_FF_Q_CE_LUT4_Z.C
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  2.4  Source blinky_100mhz_d0_TRELLIS_FF_Q_CE_LUT4_Z.F
Info:  0.5  2.9    Net blinky_100mhz_d0_TRELLIS_FF_Q_CE (83,6) -> (82,7)
Info:                Sink blinky_100mhz_d0_TRELLIS_FF_Q.CE
Info:  0.0  2.9  Setup blinky_100mhz_d0_TRELLIS_FF_Q.CE
Info: 0.7 ns logic, 2.1 ns routing

Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info:  0.0  0.0  Source GSR_N$tr_io.O
Info:  2.6  2.6    Net GSR_N$TRELLIS_IO_IN (0,47) -> (4,94)
Info:                Sink gsr.GSR
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:44.10-44.15
Info: 0.0 ns logic, 2.6 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$pll_pll.CLKOP':
Info: curr total
Info:  0.0  0.0  Source btn$tr_io.O
Info:  8.0  8.0    Net btn$TRELLIS_IO_IN (0,92) -> (113,2)
Info:                Sink blinky_100mhz_d1_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:50.10-50.13
Info:  0.0  8.0  Setup blinky_100mhz_d1_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 8.0 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$pll_pll.CLKOS':
Info: curr total
Info:  0.0  0.0  Source btn$tr_io.O
Info:  7.8  7.8    Net btn$TRELLIS_IO_IN (0,92) -> (112,2)
Info:                Sink blinky_50mhz_d1_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:50.10-50.13
Info:  0.0  7.8  Setup blinky_50mhz_d1_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 7.8 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$pll_pll.CLKOP' -> '<async>':
Info: curr total
Info:  0.3  0.3  Source blinky_100mhz_d1_TRELLIS_FF_Q.Q
Info:  0.3  0.6    Net blinky_100mhz_d1 (113,2) -> (113,2)
Info:                Sink led2__h642_LUT4_Z.D
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:72.7-72.23
Info:  0.1  0.7  Source led2__h642_LUT4_Z.F
Info:  0.8  1.5    Net led2__h642 (113,2) -> (119,0)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:92.8-92.18
Info: 0.4 ns logic, 1.1 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$pll_pll.CLKOS' -> '<async>':
Info: curr total
Info:  0.3  0.3  Source blinky_50mhz_d1_TRELLIS_FF_Q.Q
Info:  0.5  0.8    Net blinky_50mhz_d1 (112,2) -> (113,2)
Info:                Sink led2__h642_LUT4_Z.C
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:85.7-85.22
Info:  0.1  0.9  Source led2__h642_LUT4_Z.F
Info:  0.8  1.7    Net led2__h642 (113,2) -> (119,0)
Info:                Sink led[2]$tr_io.I
Info:                Defined in:
Info:                  ./env/7f1ad267fdb144468f2f5b23546d3db1400dadd4/hdl/projects/ecp5_evn/mkClocks.v:92.8-92.18
Info: 0.4 ns logic, 1.3 ns routing

Info: Max frequency for clock '$glbnet$pll_pll.CLKOS': 358.94 MHz (PASS at 50.00 MHz)
Info: Max frequency for clock '$glbnet$pll_pll.CLKOP': 349.65 MHz (PASS at 100.01 MHz)

Info: Max delay <async>                       -> <async>                      : 2.62 ns
Info: Max delay <async>                       -> posedge $glbnet$pll_pll.CLKOP: 7.99 ns
Info: Max delay <async>                       -> posedge $glbnet$pll_pll.CLKOS: 7.82 ns
Info: Max delay posedge $glbnet$pll_pll.CLKOP -> <async>                      : 1.54 ns
Info: Max delay posedge $glbnet$pll_pll.CLKOS -> <async>                      : 1.72 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [  7139,   7740) |********* 
Info: [  7740,   8341) |**************** 
Info: [  8341,   8942) |* 
Info: [  8942,   9543) |** 
Info: [  9543,  10144) | 
Info: [ 10144,  10745) | 
Info: [ 10745,  11346) | 
Info: [ 11346,  11947) | 
Info: [ 11947,  12548) | 
Info: [ 12548,  13149) | 
Info: [ 13149,  13750) | 
Info: [ 13750,  14351) | 
Info: [ 14351,  14952) | 
Info: [ 14952,  15553) | 
Info: [ 15553,  16154) | 
Info: [ 16154,  16755) | 
Info: [ 16755,  17356) |** 
Info: [ 17356,  17957) |*********** 
Info: [ 17957,  18558) |************ 
Info: [ 18558,  19159) |** 

Info: Program finished normally.