Info: constraining clock net 'CLK_12mhz' to 12.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:        82/83640     0%
Info:         logic LUTs:     64/83640     0%
Info:         carry LUTs:     18/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:        76/83640     0%

Info: Packing IOs..
Info: pin 'uart_tx$tr_io' constrained to Bel 'X0/Y92/PIOC'.
Info: pin 'uart_rx$tr_io' constrained to Bel 'X0/Y92/PIOB'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X114/Y0/PIOA'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X116/Y0/PIOA'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X114/Y0/PIOB'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X116/Y0/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X119/Y0/PIOA'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X119/Y0/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X76/Y0/PIOA'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X76/Y0/PIOB'.
Info: pin 'btn$tr_io' constrained to Bel 'X0/Y92/PIOD'.
Info: pin 'GSR_N$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'CLK_12mhz$tr_io' constrained to Bel 'X63/Y0/PIOA'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     43 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net CLK_12mhz$TRELLIS_IO_IN to global network
Info: Checksum: 0xd7f67bc5

Info: Device utilisation:
Info: 	          TRELLIS_IO:      13/    365     3%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    208     0%
Info: 	          MULT18X18D:       0/    156     0%
Info: 	              ALU54B:       0/     78     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    224     0%
Info: 	            SIOLOGIC:       0/    141     0%
Info: 	                 GSR:       1/      1   100%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     14     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:      76/  83640     0%
Info: 	        TRELLIS_COMB:      88/  83640     0%
Info: 	        TRELLIS_RAMW:       0/  10455     0%

Info: Placed 14 cells based on constraints.
Info: Creating initial analytic placement for 85 cells, random placement wirelen = 9133.
Info:     at initial placer iter 0, wirelen = 1025
Info:     at initial placer iter 1, wirelen = 826
Info:     at initial placer iter 2, wirelen = 783
Info:     at initial placer iter 3, wirelen = 774
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ALL: wirelen solved = 755, spread = 900, legal = 915; time = 0.04s
Info: HeAP Placer Time: 0.19s
Info:   of which solving equations: 0.04s
Info:   of which spreading cells: 0.00s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 8, wirelen = 915
Info:   at iteration #5: temp = 0.000000, timing cost = 12, wirelen = 862
Info:   at iteration #6: temp = 0.000000, timing cost = 11, wirelen = 862 
Info: SA placement time 0.06s

Info: Max frequency for clock '$glbnet$CLK_12mhz$TRELLIS_IO_IN': 413.22 MHz (PASS at 12.00 MHz)

Info: Max delay <async>                                 -> <async>                                : 3.50 ns
Info: Max delay <async>                                 -> posedge $glbnet$CLK_12mhz$TRELLIS_IO_IN: 10.44 ns
Info: Max delay posedge $glbnet$CLK_12mhz$TRELLIS_IO_IN -> <async>                                : 11.55 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 80913,  81012) |* 
Info: [ 81012,  81111) |** 
Info: [ 81111,  81210) |***** 
Info: [ 81210,  81309) |** 
Info: [ 81309,  81408) |** 
Info: [ 81408,  81507) |***** 
Info: [ 81507,  81606) |***** 
Info: [ 81606,  81705) |************ 
Info: [ 81705,  81804) |******** 
Info: [ 81804,  81903) |*************** 
Info: [ 81903,  82002) |************** 
Info: [ 82002,  82101) |******* 
Info: [ 82101,  82200) |** 
Info: [ 82200,  82299) |***** 
Info: [ 82299,  82398) |********* 
Info: [ 82398,  82497) |************** 
Info: [ 82497,  82596) |***** 
Info: [ 82596,  82695) |************ 
Info: [ 82695,  82794) |*********** 
Info: [ 82794,  82893) |***** 
Info: Checksum: 0xe3a038ea
Info: Routing globals...
Info:     routing clock net $glbnet$CLK_12mhz$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 349 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        406 |       56        331 |   56   331 |         0|       0.09       0.09|
Info: Routing complete.
Info: Router1 time 0.09s
Info: Checksum: 0x89be200a

Info: Critical path report for clock '$glbnet$CLK_12mhz$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source uart_txr_deserializer_bits_remaining_TRELLIS_FF_Q_1.Q
Info:  0.6  0.9    Net uart_txr_deserializer_bits_remaining[2] (112,3) -> (112,4)
Info:                Sink uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_Z.B
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  1.1  Source uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_Z.F
Info:  0.3  1.4    Net uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D[6] (112,4) -> (112,4)
Info:                Sink uart_txr_deserializer_bits_remaining$EN_LUT4_Z.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  1.5  Source uart_txr_deserializer_bits_remaining$EN_LUT4_Z.F
Info:  0.4  1.9    Net uart_txr_deserializer_bits_remaining$EN (112,4) -> (112,4)
Info:                Sink uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_D.A
Info:                Defined in:
Info:                  ./env/fdc18e943036952ab0fc8c8b3b88a6361412fa1c/hdl/projects/ecp5_evn/mkLoopbackUART.v:85.8-85.47
Info:  0.1  2.1  Source uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_D.F
Info:  0.4  2.5    Net uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_D_Z (112,4) -> (112,3)
Info:                Sink uart_txr_deserializer_bits_remaining_TRELLIS_FF_Q_1.LSR
Info:  0.2  2.7  Setup uart_txr_deserializer_bits_remaining_TRELLIS_FF_Q_1.LSR
Info: 1.0 ns logic, 1.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info:  0.0  0.0  Source GSR_N$tr_io.O
Info:  2.6  2.6    Net GSR_N$TRELLIS_IO_IN (0,47) -> (4,94)
Info:                Sink gsr.GSR
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2043.26-2043.29
Info: 0.0 ns logic, 2.6 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$CLK_12mhz$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source GSR_N$tr_io.O
Info:  1.4  1.4    Net GSR_N$TRELLIS_IO_IN (0,47) -> (26,43)
Info:                Sink GSR_N_LUT4_D.D
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2043.26-2043.29
Info:  0.1  1.5  Source GSR_N_LUT4_D.F
Info:  5.0  6.5    Net GSR_N_LUT4_D_Z (26,43) -> (115,4)
Info:                Sink uart_txr_serializer_buffer_TRELLIS_FF_Q_6.LSR
Info:  0.2  6.7  Setup uart_txr_serializer_buffer_TRELLIS_FF_Q_6.LSR
Info: 0.4 ns logic, 6.3 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$CLK_12mhz$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.3  0.3  Source uart_txr_tx_sync_TRELLIS_FF_Q.Q
Info:  7.7  8.0    Net uart_tx$TRELLIS_IO_OUT (110,6) -> (0,92)
Info:                Sink uart_tx$tr_io.I
Info:                Defined in:
Info:                  ./env/fdc18e943036952ab0fc8c8b3b88a6361412fa1c/hdl/projects/ecp5_evn/mkLoopbackUART.v:149.7-149.23
Info: 0.3 ns logic, 7.7 ns routing

Info: Max frequency for clock '$glbnet$CLK_12mhz$TRELLIS_IO_IN': 369.41 MHz (PASS at 12.00 MHz)

Info: Max delay <async>                                 -> <async>                                : 2.62 ns
Info: Max delay <async>                                 -> posedge $glbnet$CLK_12mhz$TRELLIS_IO_IN: 6.70 ns
Info: Max delay posedge $glbnet$CLK_12mhz$TRELLIS_IO_IN -> <async>                                : 8.00 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 80626,  80733) |** 
Info: [ 80733,  80840) |** 
Info: [ 80840,  80947) | 
Info: [ 80947,  81054) | 
Info: [ 81054,  81161) |* 
Info: [ 81161,  81268) |********* 
Info: [ 81268,  81375) |****** 
Info: [ 81375,  81482) |******* 
Info: [ 81482,  81589) |*************** 
Info: [ 81589,  81696) |********************* 
Info: [ 81696,  81803) |********** 
Info: [ 81803,  81910) |* 
Info: [ 81910,  82017) |* 
Info: [ 82017,  82124) |** 
Info: [ 82124,  82231) |****** 
Info: [ 82231,  82338) |*********** 
Info: [ 82338,  82445) |********* 
Info: [ 82445,  82552) |******* 
Info: [ 82552,  82659) |******************** 
Info: [ 82659,  82766) |*********** 

Info: Program finished normally.