| ID0 |
0x0
|
|
Identification 0 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x1 |
0x1
|
| ID1 |
0x1
|
|
Identification 1 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0xde |
de
|
| VER0 |
0x2
|
|
Version 0 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
version[31..24]
|
| VER1 |
0x3
|
|
Version 1 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
version[23..16]
|
| VER2 |
0x4
|
|
Version 2 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
version[15..8]
|
| VER3 |
0x5
|
|
Version 3 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
version[7..0]
|
| SHA0 |
0x6
|
|
ShortSHA part 0 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
sha[31..24]
|
| SHA1 |
0x7
|
|
ShortSHA part 1 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
sha[23..16]
|
| SHA2 |
0x8
|
|
ShortSHA part 2 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
sha[15..8]
|
| SHA3 |
0x9
|
|
ShortSHA part 3 |
|
|
7..0 |
data |
|
|
data |
7..0 |
r |
0x0 |
sha[7..0]
|
| CS0 |
0xa
|
|
FPGA Checksum0 |
|
|
7..0 |
CS0 |
|
|
CS0 |
7..0 |
rw |
0x0 |
Scribble Register for read-write use
|
| CS1 |
0xb
|
|
FPGA Checksum1 |
|
|
7..0 |
CS1 |
|
|
CS1 |
7..0 |
rw |
0x0 |
Scribble Register for read-write use
|
| CS2 |
0xc
|
|
FPGA Checksum2 |
|
|
7..0 |
CS2 |
|
|
CS2 |
7..0 |
rw |
0x0 |
Scribble Register for read-write use
|
| CS3 |
0xd
|
|
FPGA Checksum3 |
|
|
7..0 |
CS3 |
|
|
CS3 |
7..0 |
rw |
0x0 |
Scribble Register for read-write use
|
| SCRTCHPAD |
0xe
|
|
Scratchpad |
|
|
7..0 |
TBD |
|
|
TBD |
7..0 |
rw |
0x0 |
Scribble Register for read-write use
|
| IFR |
0xf
|
|
Interrupt Flag Register |
|
|
7..0 |
RSVD |
AMD_RSTN_FEDGE |
AMD_PWROK_FEDGE |
NICMAPO |
A0MAPO |
A1MAPO |
THERMTRIP |
FANFAULT |
|
|
AMD_RSTN_FEDGE |
6 |
rw |
None |
AMD RESET fedge while in >=A0
|
|
AMD_PWROK_FEDGE |
5 |
rw |
None |
AMD PWROK fedge while in >=A0
|
|
NICMAPO |
4 |
rw |
None |
Nic MAPO
|
|
A0MAPO |
3 |
rw |
None |
A0 MAPO
|
|
A1MAPO |
2 |
rw |
None |
A1 MAPO
|
|
THERMTRIP |
1 |
rw |
None |
Thermtrip
|
|
FANFAULT |
0 |
rw |
None |
Fan Fault
|
| IER |
0x10
|
|
Interrupt Enable Register |
|
|
7..0 |
RSVD |
AMD_RSTN_FEDGE |
AMD_PWROK_FEDGE |
NICMAPO |
A0MAPO |
A1MAPO |
THERMTRIP |
FANFAULT |
|
|
AMD_RSTN_FEDGE |
6 |
rw |
None |
AMD RESET fedge while in >=A0
|
|
AMD_PWROK_FEDGE |
5 |
rw |
None |
AMD PWROK fedge while in >=A0
|
|
NICMAPO |
4 |
rw |
None |
Nic MAPO
|
|
A0MAPO |
3 |
rw |
None |
A0 MAPO
|
|
A1MAPO |
2 |
rw |
None |
A1 MAPO
|
|
THERMTRIP |
1 |
rw |
None |
Thermtrip
|
|
FANFAULT |
0 |
rw |
None |
Fan Fault
|
| STATUS |
0x11
|
|
Sequencer Status Register |
|
|
7..0 |
INT_PEND |
RSVD |
NICPWROK |
A0PWROK |
A1PWROK |
FANPWROK |
|
|
INT_PEND |
7 |
r |
0x0 |
Interrupt Pending Status
|
|
NICPWROK |
3 |
r |
0x0 |
NIC power OK
|
|
A0PWROK |
2 |
r |
0x0 |
A0 power OK
|
|
A1PWROK |
1 |
r |
0x0 |
A1 power OK
|
|
FANPWROK |
0 |
r |
0x0 |
Fan power OK
|
| EARLY_POWER_CTRL |
0x12
|
|
Early Power Control Register |
|
|
7..0 |
FANHP_RESTART |
RSVD |
EFGH_SPD_EN |
ABCD_SPD_EN |
FANPWREN |
|
|
FANHP_RESTART |
7 |
rw |
0x0 |
External pull-up give SP control of restarting.
Falling edge triggers restart function which tags 2-25sec
(default 10s) set by PMBus registers. 10us glitch filter at ADM1272.
Writing to this will cause a strobe that exceeds the glitch filter
timing and will self-clear (note actual output is inverted to meet
circuit's active low requirement
|
|
EFGH_SPD_EN |
2 |
rw |
0x0 |
Enables V2P5_DIMM_EFGH_SPD_A0 rail. (SEQ_TO_DIMM_EFGH_V2P5_EN net).
|
|
ABCD_SPD_EN |
1 |
rw |
0x0 |
Enables V2P5_DIMM_ABCD_SPD_A0 rail (SEQ_TO_DIMM_ABCD_V2P5_EN net).
|
|
FANPWREN |
0 |
rw |
0x0 |
Fan power enable
|
| PWR_CTRL |
0x13
|
|
Power Sequence Control |
|
|
7..0 |
RSVD |
A0A_EN |
A1PWREN |
|
|
A0A_EN |
1 |
rw |
0x0 |
A0 Group power enable (starts state machine)
|
|
A1PWREN |
0 |
rw |
0x0 |
A1 power enable (starts state machine)
|
| NIC_CTRL |
0x14
|
|
T6 NIC Control |
|
|
7..0 |
RSVD |
CLD_RST |
|
|
CLD_RST |
0 |
rw |
0x1 |
NIC CLD_RST control. Controls CLD_RST_N (inverted). Defaults to reset asserted to be
cleared by software when SP3 hotplug indicates enable
|
| A1SMSTATUS |
0x15
|
|
A1 SM Status |
|
|
7..0 |
A1SM |
|
|
A1SM |
7..0 |
r |
None |
State Machine enum
IDLE = 0x0
ENABLE = 0x1
WAITPG = 0x2
DELAY = 0x3
DONE = 0x5
|
| A0SMSTATUS |
0x16
|
|
A0 SM Status |
|
|
7..0 |
A0SM |
|
|
A0SM |
7..0 |
r |
None |
State Machine enum
IDLE = 0x0
PBTN = 0x1
WAITSLP = 0x2
GROUPB1_EN = 0x3
GROUPB1_PG = 0x4
GROUPB2_EN = 0x5
GROUPB2_PG = 0x6
GROUPC_PG = 0x7
DELAY_1MS = 0x8
ASSERT_PG = 0x9
WAIT_PWROK = 0xa
WAIT_RESET_L = 0xb
DONE = 0xc
SAFE_DISABLE = 0xd
|
| NICSMSTATUS |
0x17
|
|
Nic SM Status |
|
|
7..0 |
NicSM |
|
|
NicSM |
7..0 |
r |
None |
Nic SM Status
IDLE = 0x0
PS_PG = 0x1
PG_DELAY = 0x2
EARLY_RESET = 0x3
DONE = 0x4
|
| BOARD_REV |
0x18
|
|
Board Ver straps |
|
|
7..0 |
RSVD |
ID |
|
|
ID |
2..0 |
r |
None |
0x7 or 0x0 = A. 0x1 = B, 0x2 = C, 0x3 = D, 0x4 = E
|
| EARLY_RBKS |
0x19
|
|
Pre-A1 Power Readback Register |
|
|
7..0 |
RSVD |
EFGH_V2P5_SPD_PG |
ABCD_V2P5_SPD_PG |
FAN_TO_SEQ_FAN_FAIL |
FANHP_TO_SEQ_PWRGD |
FANHP_TO_SEQ_FAULT |
|
|
EFGH_V2P5_SPD_PG |
4 |
r |
0x0 |
Readback for V2P5_DIMM_EFGH_SPD_A0 rail (DIMM_TO_SEQ_EFGH_V2P5_PG net)
|
|
ABCD_V2P5_SPD_PG |
3 |
r |
0x0 |
Readback for V2P5_DIMM_ABCD_SPD_A0 rail (DIMM_TO_SEQ_ABCD_V2P5_PG net)
|
|
FAN_TO_SEQ_FAN_FAIL |
2 |
r |
0x0 |
Input from ADM1272. Rising edge enable PMBus OPERATION on
command or PMBus POWER_CYCLE required to clear, assuming all faults
are clear.
|
|
FANHP_TO_SEQ_PWRGD |
1 |
r |
0x0 |
From ADUM1272. Asserted when PWGIN > thresh, enable pin is
high and UVx and OV pins are in-range, no actuive fault conditons
and mosfet is fully enhanced (Vgs > 10V).
|
|
FANHP_TO_SEQ_FAULT |
0 |
r |
0x0 |
Input from ADM1272. Rising edge enable PMBus OPERATION on
command or PMBus POWER_CYCLE required to clear, assuming all
faults are clear. (Inverted to active high in register)
|
| A1_READBACKS |
0x1a
|
|
A1 power readbacks |
|
|
7..0 |
RSVD |
V0P9_VDD_SOC_S5_PG |
V1P8_S5_PG |
V3P3_S5_PG |
V1P5_RTC_PG |
|
|
V0P9_VDD_SOC_S5_PG |
3 |
r |
0x0 |
Readback for V0P9_SP3_VDD_SOC_S5_A1 rail
(SP3_TO_SEQ_V0P9_VDD_SOC_S5_PG)
|
|
V1P8_S5_PG |
2 |
r |
0x0 |
Readback for V1P8_SP3_VDD_18_S5_A rail
(SP3_TO_SEQ_V1P8_S5_PG)
|
|
V3P3_S5_PG |
1 |
r |
0x0 |
Readback for V3P3_SP3_VDD_33_S5_A1 rail
(SP3_TO_SEQ_V3P3_S5_PG)
|
|
V1P5_RTC_PG |
0 |
r |
0x0 |
Readback for V1P5_SP_VDD_RTC_A1 rail.
(SP3_TO_SEQ_RTC_V1P5_EN - a poor net name)
|
| AMD_A0 |
0x1b
|
|
AMD readbacks for A0-signals |
|
|
7..0 |
RSVD |
RESET |
PWROK |
SLP_S5 |
SLP_S3 |
|
|
RESET |
3 |
r |
0x0 |
Asserted (and inverted) from AMD's RESET_L pin. 10Ms minimum assertion time,
remains asserted for minimum of 1ms after PWROK assertion
(SP3_TO_SEQ_RESET_V3P3_L net)
|
|
PWROK |
2 |
r |
0x0 |
Asserted by AMD after PWR_GOOD is asserted by sequencer
should be here in: min 15ms, max of 20.4ms(SP3_TO_SEQ_PWROK_V3P3 net)
|
|
SLP_S5 |
1 |
r |
0x0 |
SP3_TO_SP_SLP_S5 inversion of signal from AMD CPU, Used
at beginning of GroupB state machine
|
|
SLP_S3 |
0 |
r |
0x0 |
SP3_TO_SP_SLP_S3 inversion of signal from AMD CPU, Used
at beginning of GroupB state machine
|
| GROUPB_PG |
0x1c
|
|
A0 Power Goods for Group B supplies |
|
|
7..0 |
V3P3_SYS_PG |
V1P8_SP3_PG |
VTT_EFGH_PG |
VTT_ABCD_PG |
VDD_MEM_EFGH_PG |
VDD_MEM_ABCD_PG |
VPP_EFGH_PG |
VPP_ABCD_PG |
|
|
V3P3_SYS_PG |
7 |
r |
0x0 |
Readback from V3P3_SYS_A0 rail (PWR_CONT_DIMM_ABCD_PG1)
PG1 from ISL68224 U352, should be configured to represent
V3P3_SYS_A0 rail status
|
|
V1P8_SP3_PG |
6 |
r |
None |
Readback for V1P8_SP3_VDD_18_A0 rail (SEQ_V1P8_SP3_VDD_PG_L) inverted
|
|
VTT_EFGH_PG |
5 |
r |
None |
Readback for VTT_EFGH_A0 rail (VTT_EFGH_A0_TO_SEQ_PG_L) inverted
|
|
VTT_ABCD_PG |
4 |
r |
None |
Readback for VTT_ABCD_A0 rail (VTT_ABCD_A0_TO_SEQ_PG_L) inverted
|
|
VDD_MEM_EFGH_PG |
3 |
r |
None |
Readback from VDD_MEM_EFGH_A0 rail (PWR_CONT2_SP3_PG1)
Power good 1 for RA229618 (U351) is configured for
VDD_MEM_EFGH_A0
|
|
VDD_MEM_ABCD_PG |
2 |
r |
None |
Readback from VDD_MEM_ABCD_A0 rail (PWR_CONT1_SP3_PG1)
Power good 1 for RA229618 (U350) is configured for
VDD_MEM_ABCD_A0
|
|
VPP_EFGH_PG |
1 |
r |
0x0 |
Readback from VPP_EFGH_A0 rail (PWR_CONT_DIMM_EFGH_PG0 net)
|
|
VPP_ABCD_PG |
0 |
r |
0x0 |
Readback from VPP_ABCD_A0 rail (PWR_CONT_DIMM_ABCD_PG0 net)
|
| GROUPB_UNUSED |
0x1d
|
|
A0 Power Goods for Un-used supplies |
|
|
7..0 |
RSVD |
EFGH_PG2 |
EFGH_PG1 |
ABCD_PG2 |
|
|
EFGH_PG2 |
2 |
r |
0x0 |
From ISL68224 U418. PWR_CONT_DIMM_EFGH_PG2 net. No defined function.
|
|
EFGH_PG1 |
1 |
r |
0x0 |
From ISL68224 U418. PWR_CONT_DIMM_EFGH_PG1 net. No defined function.
|
|
ABCD_PG2 |
0 |
r |
0x0 |
From ISL68224 U352. PWR_CONT_DIMM_ABCD_PG2 net. No defined function.
|
| GROUPBC_FLTS |
0x1e
|
|
A0 Power Faults for Group B + C supplies |
|
|
7..0 |
RSVD |
CONT2_CFP |
CONT2_NVRHOT |
CONT1_CFP |
CONT1_NVRHOT |
|
|
CONT2_CFP |
3 |
r |
0x0 |
Catastrophic fault protection output from RAA229618 U351 controlling
SP3_VDDCR_SOC_A0 and VDD_MEM_EFGH_A0 rails (PWR_CONT2_SP3_CFP net).
|
|
CONT2_NVRHOT |
2 |
r |
0x0 |
Set high (inverted from board) when rail reaches OT_WARN threshold, only valid
after configuration. From RAA229618 U351 driving rails SP3_VDDCR_SOC_A0 and
VDD_MEM_EFGH_A0 (PWR_CONT2_SP3_NVRHOT net)
|
|
CONT1_CFP |
1 |
r |
0x0 |
Catastrophic fault protection output from RAA229618 U350 controlling
SP3_VDD_VCORE_A0 and VDD_MEM_ABCD_A0 rails
|
|
CONT1_NVRHOT |
0 |
r |
0x0 |
Set high (inverted from board) when rail reaches OT_WARN threshold,
only valid after configuration (PWR_CONT1_SP3_NVRHOT net).
from RAA229618 U350 controlling SP3_VDD_VCORE_A0 and VDD_MEM_ABCD_A0 rails
|
| GROUPC_PG |
0x1f
|
|
A0 STATUS for Group C supplies |
|
|
7..0 |
RSVD |
VDD_VCORE |
VDDCR_SOC_PG |
|
|
VDD_VCORE |
1 |
r |
0x0 |
Power good 0 from RA229618 (U350) is configured for
SP3_VDD_VCORE_A0 (PWR_CONT1_SP3_PG0 net)
|
|
VDDCR_SOC_PG |
0 |
r |
0x0 |
Power good 0 for RA229618 (U351) is configured for
SP3_VDDCR_SOC_A0 (PWR_CONT2_SP3_PG0 net)
|
| NIC_STATUS |
0x20
|
|
Power Status for NIC HP supplies |
|
|
7..0 |
RSVD |
NIC_3V3_PG |
NIC_V1P5D_PG |
NIC_V1P5A_PG |
NIC_V1P2_ENET_PG |
NIC_V1P2_PG |
NIC_V1P1_PG |
NIC_V0P96_PG |
|
|
NIC_3V3_PG |
6 |
r |
0x0 |
Power good for LDO_V3P3
|
|
NIC_V1P5D_PG |
5 |
r |
0x0 |
Power good for V1P5_NIC_PCIE_MEM_A0HP (inverted NIC_TO_SEQ_V1P5D_PG_L net)
|
|
NIC_V1P5A_PG |
4 |
r |
0x0 |
Power good for V1P5_NIC_AVDD_A0HP (inverted NIC_TO_SEQ_V1P5A_PG_L net)
|
|
NIC_V1P2_ENET_PG |
3 |
r |
0x0 |
Power good for V1P2_NIC_ETH (inverted NIC_TO_SEQ_V1P2_PG_L net)
|
|
NIC_V1P2_PG |
2 |
r |
0x0 |
Power good for V1P2_NIC_MDIO_A0HP (inverted NIC_TO_SEQ_V1P2_PG_L net)
|
|
NIC_V1P1_PG |
1 |
r |
0x0 |
Power good for V1P1_NIC_ETH_IO_A0HP (inverted NIC_TO_SEQ_V1P1_PG_L net)
|
|
NIC_V0P96_PG |
0 |
r |
0x0 |
Power good for V0P96_NIC_VDD_A0HP (PWR_CONT_NIC_PG0 net)
|
| CLKGEN_STATUS |
0x21
|
|
Cock Generator GPIO Readbacks |
|
|
7..0 |
RSVD |
GPIO9 |
GPIO8 |
GPIO5 |
GPIO4 |
GPIO3 |
GPIO2 |
GPIO1 |
|
|
GPIO9 |
6 |
rw |
0x0 |
GPIO9
|
|
GPIO8 |
5 |
rw |
0x0 |
GPIO8
|
|
GPIO5 |
4 |
rw |
0x0 |
GPIO5
|
|
GPIO4 |
3 |
rw |
0x0 |
GPIO4
|
|
GPIO3 |
2 |
rw |
0x0 |
GPIO3
|
|
GPIO2 |
1 |
rw |
0x0 |
GPIO2
|
|
GPIO1 |
0 |
rw |
0x0 |
GPIO1
|
| AMD_STATUS |
0x22
|
|
General AMD readbacks |
|
|
7..0 |
RSVD |
NIC_PWREN |
PWRGD_OUT |
FSR_REQ |
THERMTRIP |
|
|
NIC_PWREN |
3 |
rw |
0x0 |
NIC_PWREN (inversion of net SP3_TO_SP_NIC_PWREN_L), available on C and newer Gimlets.
When Asserted high in this register, the net is active low, and NIC power is expected to
be commanded on by Hubris (see NIC_CTRL register). This is a readback-only view, no
autonomous FPGA action occurs on the status of this pin, Hubris also monitors and takes
action. Only valid in A0 and higher power states but is a simple pass-through in the
FPGA, no gating logic
|
|
PWRGD_OUT |
2 |
rw |
0x0 |
Output from the AMD processor that it has effectively acknowledged that power is itself
good. This is connected from the BSP to the AP's PWR_GOOD input in a two socket
system. The FCH may actually control this being generated via the
FCH::PM::RESETCONTROL2 register.
|
|
FSR_REQ |
1 |
rw |
0x0 |
inverted FSR_REQ_L net. Maybe used in host reset detection, see RFD138. No defined use in power-up
|
|
THERMTRIP |
0 |
rw |
0x0 |
inverted CPU's thermtrip_L, 500ms to shut down power planes into S5 state. De-assertion of PWROK resets THERMTRIP_L
|
| FANOUTSTATUS |
0x23
|
|
Fan Output Status |
|
|
7..0 |
RSVD |
FANHP_RESTART |
FAN_HP_EN |
|
|
FANHP_RESTART |
1 |
r |
0x0 |
FANHP_RESTART pin (note actual output is inverted to meet
circuit's active low requirement, so a 1 here means a 0 on the board)
|
|
FAN_HP_EN |
0 |
r |
None |
Enable for fan ADUM1272. (1us glitch filter at ADUM1272)
|
| EARLY_PWR_STATUS |
0x24
|
|
Early Power Output readbacks |
|
|
7..0 |
FANHP_RESTART |
RSVD |
EFGH_SPD_EN |
ABCD_SPD_EN |
FANPWREN |
|
|
FANHP_RESTART |
7 |
rw |
0x0 |
External pull-up give SP control of restarting.
Falling edge triggers restart function which tags 2-25sec
(default 10s) set by PMBus registers. 10us glitch filter at ADM1272.
Writing to this will cause a strobe that exceeds the glitch filter
timing and will self-clear (note actual output is inverted to meet
circuit's active low requirement
|
|
EFGH_SPD_EN |
2 |
rw |
0x0 |
Enables V2P5_DIMM_EFGH_SPD_A0 rail. (SEQ_TO_DIMM_EFGH_V2P5_EN net).
|
|
ABCD_SPD_EN |
1 |
rw |
0x0 |
Enables V2P5_DIMM_ABCD_SPD_A0 rail (SEQ_TO_DIMM_ABCD_V2P5_EN net).
|
|
FANPWREN |
0 |
rw |
0x0 |
Fan power enable
|
| A1_OUT_STATUS |
0x25
|
|
A1 Output readbacks |
|
|
7..0 |
RSVD |
RSMRST |
V0P9_S5_EN |
V1P8_S5_EN |
V1P5_RTC_EN |
V3P3_S5_EN |
|
|
RSMRST |
4 |
r |
0x0 |
De-asserted to processor after GroupA supplies are stable (10ms after S5 rails minimum)
(SEQ_TO_SP3_RSMRST_V3P3_L net inverted from this register)
|
|
V0P9_S5_EN |
3 |
r |
0x0 |
Enables V0P9_SP3_VDD_SOC_S5_A1 rail (SEQ_TO_SP3_V0P9_S5_EN pin)
|
|
V1P8_S5_EN |
2 |
r |
0x0 |
Enables V1P8_SP3_VDD_18_S5_A1 rail (SEQ_TO_SP3_V1P8_S5_EN pin)
|
|
V1P5_RTC_EN |
1 |
r |
0x0 |
Enables V1P5_SP3_VDD_RTC_A1 rail (SEQ_TO_SP3_V1P5_RTC_EN pin)
|
|
V3P3_S5_EN |
0 |
r |
0x0 |
Enables V3P3_SP3_VDD_33_S5_A1 rail (SEQ_TO_SP3_V3P3_S5_EN pin)
|
| A0_OUT_STATUS_1 |
0x26
|
|
A0 Register 1 Output readbacks |
|
|
7..0 |
VTT_EFGH_EN |
VTT_ABCD_EN |
VDD_MEM_EFGH_EN |
VDD_MEM_ABCD_EN |
V1P8_SP3_VDD_EN |
V3P3_SYS_EN |
VPP_EFGH_EN |
VPP_ABCD_EN |
|
|
VTT_EFGH_EN |
7 |
rw |
0x0 |
GroupB2: Enables VTT_EFGH_A0 rail (seq_to_vtt_efgh_en net RevB)
|
|
VTT_ABCD_EN |
6 |
rw |
0x0 |
GroupB2: Enables VTT_ABCD_A0 rail (seq_to_vtt_abcd_en net RevB)
|
|
VDD_MEM_EFGH_EN |
5 |
rw |
0x0 |
GroupB2: Enables VDD_MEM_EFGH_A0 rail (pwr_cont2_sp3_en net RevB)
|
|
VDD_MEM_ABCD_EN |
4 |
rw |
0x0 |
GroupB2: Enables VDD_MEM_ABCD_A0 rail (pwr_cont1_sp3_en net RevB)
|
|
V1P8_SP3_VDD_EN |
3 |
rw |
0x0 |
GroupB1: Enables V1P8_SP3_VDD_18_A0 rail (seq_to_sp3_v1p8_en net RevB)
|
|
V3P3_SYS_EN |
2 |
rw |
0x0 |
GroupB1: Enables V3P3_SYS_A0 rail (seq_to_v3p3_sys_en net RevB)
|
|
VPP_EFGH_EN |
1 |
rw |
0x0 |
GroupB1: Drives VPP_EFGH_A0 rail (pwr_cont_dimm_en1 net RevB)
|
|
VPP_ABCD_EN |
0 |
rw |
0x0 |
GroupB1: Drives VPP_ABCD_A0 rail (pwr_cont_dimm_en0 net RevB)
|
| A0_OUT_STATUS_2 |
0x27
|
|
A0 Register 2 Output readbacks |
|
|
7..0 |
RSVD |
PWR_GOOD |
PWR_BTN |
CONT2_EN |
CONT1_EN |
V1P8_SP3_EN |
U351_PWROK |
U350_PWROK |
|
|
PWR_GOOD |
6 |
rw |
0x0 |
This is asserted to CPU, 1ms before asserting. Set when A0 rails are good. (SEQ_TO_SP3_PWR_GOOD net)
|
|
PWR_BTN |
5 |
rw |
0x0 |
Pulsed according to AMD's EDS min 15ms (SP_TO_SP3_PWR_BTN_L net, inverted from this register)
|
|
CONT2_EN |
4 |
rw |
0x0 |
Enable for RAA229618 (U35) VDD_MEM_EFGH_A0 (and gates SP3_VDDCR_SOC_A0)
(PWR_CONT2_SP3_EN net)
|
|
CONT1_EN |
3 |
rw |
0x0 |
Enable for RAA229618 (U350) VDD_MEM_ABCD_A0 (PWR_CONT1_SP3_EN net)
|
|
V1P8_SP3_EN |
2 |
rw |
0x0 |
Enables V1P8_SP3_VDD_18_A0 rail (SEQ_TO_SP3_V1P8_EN net)
|
|
U351_PWROK |
1 |
rw |
0x1 |
Strap High, no definition yet. PWROK pin to RAA229618 U351 driving
SP3_VDDCR_SOC_A0 and VDD_MEM_EFGH_A0 (PWR_CONT2_SP3_PWROK net)
|
|
U350_PWROK |
0 |
rw |
0x1 |
Strap High, no definition yet. PWROK pin to RAA229618 U350 driving
SP3_VDD_VCORE_A0 and VDD_MEM_ABCD_A0
|
| OUT_STATUS_NIC1 |
0x28
|
|
Readbacks of FPGA outputs (register 1 of 2) to NIC supplies/NIC |
|
|
7..0 |
RSVD |
NIC_V3P3_EN |
NIC_V1P1_EN |
NIC_V1P2_EN |
NIC_V1P5D_EN |
NIC_V1P5A_EN |
NIC_V1P2_ETH_EN |
NIC_V0P9_A0_EN |
|
|
NIC_V3P3_EN |
6 |
rw |
0x0 |
Enables V3PV_NIC_A0HP rail (SEQ_TO_NIC_LDO_V3P3_EN net)
|
|
NIC_V1P1_EN |
5 |
rw |
0x0 |
Turns on V1P1_NIC_ETH_IO_A0HP rail (SEQ_TO_NIC_V1P1_EN net)
|
|
NIC_V1P2_EN |
4 |
rw |
0x0 |
Enable for V1P2_NIC_MDIO_A0HP rail (SEQ_TO_NIC_V1P2_EN net)
|
|
NIC_V1P5D_EN |
3 |
rw |
0x0 |
En for V1P5_NIC_PCIE_MEM_A0HP rail (SEQ_TO_NIC_V1P5D_EN net)
|
|
NIC_V1P5A_EN |
2 |
rw |
0x0 |
En for V1P5_NIC_AVDD_A0HP rail (SEQ_TO_NIC_V1P5A_EN net)
|
|
NIC_V1P2_ETH_EN |
1 |
rw |
0x0 |
Turns on V1P2_NIC_ENET_A0HP, no readback (SEQ_TO_NIC_V1P2_ENET_EN net)
|
|
NIC_V0P9_A0_EN |
0 |
rw |
0x0 |
Enable (U565), V0P96_NIC_VDD_A0HP rail (SEQ_TO_NIC_V0P9_A0HP_EN net)
|
| OUT_STATUS_NIC2 |
0x29
|
|
Readbacks of FPGA outputs (register 2 of 2) to NIC supplies/NIC |
|
|
7..0 |
RSVD |
NIC_EXT_RST |
NIC_PERST |
PWRFLT |
NIC_CLD_RST |
NIC_COMB_PG |
SP3_PERST |
|
|
NIC_EXT_RST |
5 |
rw |
0x0 |
NIC's EXT_RST_L output (inverted). Active when NIC internals in reset
|
|
NIC_PERST |
4 |
rw |
0x0 |
PERST outptut (PERST_L inverted net)
|
|
PWRFLT |
3 |
rw |
0x0 |
Alert SP3 of a NIC power fault (NIC_TO_SP3_PWRFLT_L inverted net)
|
|
NIC_CLD_RST |
2 |
rw |
0x0 |
CLD Reset to Chelsio. De-asserted after NIC power stable (SEQ_TO_NIC_CLD_RST_L net inverted)
|
|
NIC_COMB_PG |
1 |
rw |
0x0 |
Becomes clock enable for clk_100M_TO_RSW (SEQ_TO_NIC_COMB_PG net)
|
|
SP3_PERST |
0 |
rw |
0x0 |
Input to FPGA from SP3 I/O expander (inverted)
|
| CLKGEN_OUT_STATUS |
0x2a
|
|
Readbacks of FPGA outputs to clock generator |
|
|
7..0 |
RSVD |
SEQ_NMR |
|
|
SEQ_NMR |
0 |
rw |
0x0 |
CLK_TO_SEQ_NMR_L inverted to clk generator
|
| AMD_OUT_STATUS |
0x2b
|
|
Readbacks of FPGA outputs to AMD |
|
|
7..0 |
RSVD |
SYS_RESET |
|
|
SYS_RESET |
0 |
rw |
0x0 |
CPU's `SYS_RESET_L`, see EDS. 10ms assertion time, would traditionally be wired to a PC reset button
|
| DBG_CTRL |
0x2c
|
|
Debug Control register |
|
|
7..0 |
RSVD |
NIC_PERST_SOLO |
NIC_PERST_OVERRIDE |
NIC_CLD_RST_OVERRIDE |
REG_CTRL_EN |
ignore_sp |
|
|
NIC_PERST_SOLO |
4 |
rw |
0x0 |
Nic debug control only. Make PERST ignore any SP3 I/O and drive directly from previous bit
|
|
NIC_PERST_OVERRIDE |
3 |
rw |
0x0 |
Nic debug control only. Setting will force Perst_L assert until cleared. When
cleared, PERST will normally be controlled by SP3 I/O expander. Set next bit PERST_FORCE_SOLO to
ignore all SP3 control and have this register directly control I/O regardless of SP3's PERST state
|
|
NIC_CLD_RST_OVERRIDE |
2 |
rw |
0x0 |
Nic debug control only. Seeting will force CLD_RST assert until cleared. When cleared,
CLD_RST will normally be controlled by state machine and NIC Control register
|
|
REG_CTRL_EN |
1 |
rw |
0x0 |
Un-used
|
|
ignore_sp |
0 |
rw |
0x0 |
Debug ONLY. Setting this allows the A0 state machine to ingore SP3 handshakes.
This is potentially useful for power bringup but should not be used when a CPU is actually
installed
|
| AMD_DBG_OUT |
0x2d
|
|
Readbacks of FPGA outputs to AMD |
|
|
7..0 |
RSVD |
SYS_RESET |
|
|
SYS_RESET |
0 |
rw |
0x0 |
CPU's `SYS_RESET_L`, see EDS. 10ms assertion time, would traditionally be wired to a PC reset button
|
| AMD_RSTN_CNTS |
0x2e
|
|
AMD_RSTN_CNTS |
|
|
7..0 |
RESET_CNTS |
|
|
RESET_CNTS |
7..0 |
rw |
0x0 |
Falling edge counter of AMD's reset output while in A0/A0HP. Saturates at 255. Any write clears
|
| AMD_PWROKN_CNTS |
0x2f
|
|
AMD_PWROKN_CNTS |
|
|
7..0 |
RESET_CNTS |
|
|
RESET_CNTS |
7..0 |
rw |
0x0 |
Falling edge counter of AMD's PowerOK output while in A0/A0HP. Saturates at 255. Any write clears
|
| DBG_MAX_A0SMSTATUS |
0x30
|
|
A0 SM status (Max-hold) |
|
|
7..0 |
A0SM |
|
|
A0SM |
7..0 |
r |
None |
State Machine enum
IDLE = 0x0
PBTN = 0x1
WAITSLP = 0x2
GROUPB1_EN = 0x3
GROUPB1_PG = 0x4
GROUPB2_EN = 0x5
GROUPB2_PG = 0x6
GROUPC_PG = 0x7
DELAY_1MS = 0x8
ASSERT_PG = 0x9
WAIT_PWROK = 0xa
WAIT_RESET_L = 0xb
DONE = 0xc
SAFE_DISABLE = 0xd
|
| MAX_GROUPB_PG |
0x31
|
|
Group B PGs (Max-hold) |
|
|
7..0 |
V3P3_SYS_PG |
V1P8_SP3_PG |
VTT_EFGH_PG |
VTT_ABCD_PG |
VDD_MEM_EFGH_PG |
VDD_MEM_ABCD_PG |
VPP_EFGH_PG |
VPP_ABCD_PG |
|
|
V3P3_SYS_PG |
7 |
r |
0x0 |
Readback from V3P3_SYS_A0 rail (PWR_CONT_DIMM_ABCD_PG1)
PG1 from ISL68224 U352, should be configured to represent
V3P3_SYS_A0 rail status
|
|
V1P8_SP3_PG |
6 |
r |
None |
Readback for V1P8_SP3_VDD_18_A0 rail (SEQ_V1P8_SP3_VDD_PG_L) inverted
|
|
VTT_EFGH_PG |
5 |
r |
None |
Readback for VTT_EFGH_A0 rail (VTT_EFGH_A0_TO_SEQ_PG_L) inverted
|
|
VTT_ABCD_PG |
4 |
r |
None |
Readback for VTT_ABCD_A0 rail (VTT_ABCD_A0_TO_SEQ_PG_L) inverted
|
|
VDD_MEM_EFGH_PG |
3 |
r |
None |
Readback from VDD_MEM_EFGH_A0 rail (PWR_CONT2_SP3_PG1)
Power good 1 for RA229618 (U351) is configured for
VDD_MEM_EFGH_A0
|
|
VDD_MEM_ABCD_PG |
2 |
r |
None |
Readback from VDD_MEM_ABCD_A0 rail (PWR_CONT1_SP3_PG1)
Power good 1 for RA229618 (U350) is configured for
VDD_MEM_ABCD_A0
|
|
VPP_EFGH_PG |
1 |
r |
0x0 |
Readback from VPP_EFGH_A0 rail (PWR_CONT_DIMM_EFGH_PG0 net)
|
|
VPP_ABCD_PG |
0 |
r |
0x0 |
Readback from VPP_ABCD_A0 rail (PWR_CONT_DIMM_ABCD_PG0 net)
|
| MAX_GROUPC_PG |
0x32
|
|
Group C PGs (Max-hold) |
|
|
7..0 |
RSVD |
VDD_VCORE |
VDDCR_SOC_PG |
|
|
VDD_VCORE |
1 |
r |
0x0 |
Power good 0 from RA229618 (U350) is configured for
SP3_VDD_VCORE_A0 (PWR_CONT1_SP3_PG0 net)
|
|
VDDCR_SOC_PG |
0 |
r |
0x0 |
Power good 0 for RA229618 (U351) is configured for
SP3_VDDCR_SOC_A0 (PWR_CONT2_SP3_PG0 net)
|
| FLT_A0_SMSTATUS |
0x33
|
|
A0 SM status (latched at fault) |
|
|
7..0 |
A0SM |
|
|
A0SM |
7..0 |
r |
None |
State Machine enum
IDLE = 0x0
PBTN = 0x1
WAITSLP = 0x2
GROUPB1_EN = 0x3
GROUPB1_PG = 0x4
GROUPB2_EN = 0x5
GROUPB2_PG = 0x6
GROUPC_PG = 0x7
DELAY_1MS = 0x8
ASSERT_PG = 0x9
WAIT_PWROK = 0xa
WAIT_RESET_L = 0xb
DONE = 0xc
SAFE_DISABLE = 0xd
|
| FLT_GROUPB_PG |
0x34
|
|
Group B PGs latched at fault |
|
|
7..0 |
V3P3_SYS_PG |
V1P8_SP3_PG |
VTT_EFGH_PG |
VTT_ABCD_PG |
VDD_MEM_EFGH_PG |
VDD_MEM_ABCD_PG |
VPP_EFGH_PG |
VPP_ABCD_PG |
|
|
V3P3_SYS_PG |
7 |
r |
0x0 |
Readback from V3P3_SYS_A0 rail (PWR_CONT_DIMM_ABCD_PG1)
PG1 from ISL68224 U352, should be configured to represent
V3P3_SYS_A0 rail status
|
|
V1P8_SP3_PG |
6 |
r |
None |
Readback for V1P8_SP3_VDD_18_A0 rail (SEQ_V1P8_SP3_VDD_PG_L) inverted
|
|
VTT_EFGH_PG |
5 |
r |
None |
Readback for VTT_EFGH_A0 rail (VTT_EFGH_A0_TO_SEQ_PG_L) inverted
|
|
VTT_ABCD_PG |
4 |
r |
None |
Readback for VTT_ABCD_A0 rail (VTT_ABCD_A0_TO_SEQ_PG_L) inverted
|
|
VDD_MEM_EFGH_PG |
3 |
r |
None |
Readback from VDD_MEM_EFGH_A0 rail (PWR_CONT2_SP3_PG1)
Power good 1 for RA229618 (U351) is configured for
VDD_MEM_EFGH_A0
|
|
VDD_MEM_ABCD_PG |
2 |
r |
None |
Readback from VDD_MEM_ABCD_A0 rail (PWR_CONT1_SP3_PG1)
Power good 1 for RA229618 (U350) is configured for
VDD_MEM_ABCD_A0
|
|
VPP_EFGH_PG |
1 |
r |
0x0 |
Readback from VPP_EFGH_A0 rail (PWR_CONT_DIMM_EFGH_PG0 net)
|
|
VPP_ABCD_PG |
0 |
r |
0x0 |
Readback from VPP_ABCD_A0 rail (PWR_CONT_DIMM_ABCD_PG0 net)
|
| FLT_GROUPC_PG |
0x35
|
|
Group C PGs latched at fault |
|
|
7..0 |
RSVD |
VDD_VCORE |
VDDCR_SOC_PG |
|
|
VDD_VCORE |
1 |
r |
0x0 |
Power good 0 from RA229618 (U350) is configured for
SP3_VDD_VCORE_A0 (PWR_CONT1_SP3_PG0 net)
|
|
VDDCR_SOC_PG |
0 |
r |
0x0 |
Power good 0 for RA229618 (U351) is configured for
SP3_VDDCR_SOC_A0 (PWR_CONT2_SP3_PG0 net)
|