Info: constrained 'seq_to_nic_v1p1_en' to bel 'X4/Y33/io1'
Warning: unmatched constraint 'nic_to_seq_v1p1_pg' (on line 2)
Info: constrained 'seq_to_nic_v1p2_enet_en' to bel 'X8/Y33/io0'
Info: constrained 'seq_rev_id0' to bel 'X22/Y33/io1'
Info: constrained 'seq_rev_id1' to bel 'X22/Y33/io0'
Warning: unmatched constraint 'pwr_cont_nic_pg1' (on line 6)
Warning: unmatched constraint 'pwr_cont_nic_pg0' (on line 7)
Info: constrained 'seq_to_nic_v1p5a_en' to bel 'X0/Y30/io0'
Info: constrained 'seq_to_nic_ldo_v3p3_en' to bel 'X0/Y31/io0'
Info: constrained 'seq_to_nic_v1p2_en' to bel 'X3/Y33/io0'
Warning: unmatched constraint 'testpoint1' (on line 11)
Info: constrained 'seq_rev_id2' to bel 'X24/Y33/io0'
Info: constrained 'seq_to_nic_cld_rst_l' to bel 'X30/Y33/io0'
Info: constrained 'pwr_cont_nic_en0' to bel 'X31/Y33/io0'
Warning: unmatched constraint 'nic_to_seq_v1p5d_pg' (on line 15)
Warning: unmatched constraint 'nic_to_seq_v1p5a_pg' (on line 16)
Warning: unmatched constraint 'nic_to_seq_v1p2_pg' (on line 17)
Warning: unmatched constraint 'testpoint2' (on line 18)
Warning: unmatched constraint 'nic_to_seq_v1p2_enet_pg' (on line 19)
Warning: unmatched constraint 'nic_to_seq_ext_rst_l' (on line 20)
Info: constrained 'pwr_cont_nic_en1' to bel 'X33/Y28/io0'
Info: constrained 'seq_to_nic_v1p5d_en' to bel 'X0/Y25/io0'
Info: constrained 'seq_to_clk_nmr_l' to bel 'X0/Y27/io0'
Warning: unmatched constraint 'sp3_to_sp_nic_pwren_l' (on line 24)
Warning: unmatched constraint 'fanhp_to_seq_fault_l' (on line 26)
Warning: unmatched constraint 'fanhp_to_seq_pwrgd' (on line 27)
Info: constrained 'seq_to_clk_ntest' to bel 'X0/Y23/io0'
Warning: unmatched constraint 'vtt_ef_a0_to_seq_pg' (on line 29)
Warning: unmatched constraint 'vtt_gh_a0_to_seq_pg' (on line 30)
Info: constrained 'seq_to_fan_hp_en' to bel 'X33/Y23/io0'
Warning: unmatched constraint 'seq_to_clk_gpio3' (on line 32)
Warning: unmatched constraint 'seq_to_clk_gpio9' (on line 33)
Info: constrained 'clk50m' to bel 'X16/Y33/io1'
Info: constrained 'seq_to_vtt_efgh_en' to bel 'X33/Y21/io0'
Warning: unmatched constraint 'seq_to_clk_gpio8' (on line 36)
Warning: unmatched constraint 'seq_to_clk_gpio2' (on line 37)
Warning: unmatched constraint 'seq_to_header_misc_i' (on line 38)
Warning: unmatched constraint 'sp3_to_rsw_pwren_l_via_seq' (on line 39)
Warning: unmatched constraint 'seq_proxy_sp3_to_rsw_pwren_l' (on line 40)
Warning: unmatched constraint 'pwr_cont_dimm_efgh_pg0' (on line 41)
Warning: unmatched constraint 'seq_to_clk_gpio1' (on line 42)
Warning: unmatched constraint 'seq_to_clk_gpio4' (on line 43)
Warning: unmatched constraint 'seq_to_header_misc_e' (on line 44)
Warning: unmatched constraint 'seq_to_header_misc_f' (on line 45)
Warning: unmatched constraint 'seq_to_header_misc_g' (on line 46)
Warning: unmatched constraint 'seq_to_header_misc_h' (on line 47)
Warning: unmatched constraint 'seq_to_clk_gpio5' (on line 48)
Warning: unmatched constraint 'vtt_ab_a0_to_seq_pg' (on line 49)
Warning: unmatched constraint 'vtt_cd_a0_to_seq_pg' (on line 50)
Warning: unmatched constraint 'seq_to_sp_interrupt' (on line 51)
Info: constrained 'seq_to_led_en_l' to bel 'X33/Y14/io1'
Info: constrained 'seq_to_nic_v0p9_a0hp_en' to bel 'X33/Y15/io0'
Info: constrained 'pwr_cont_dimm_efgh_en0' to bel 'X33/Y15/io1'
Info: constrained 'seq_to_vtt_abcd_en' to bel 'X0/Y13/io1'
Warning: unmatched constraint 'seq_v1p8_sp3_vdd_pg' (on line 56)
Info: constrained 'seq_to_nic_perst_l' to bel 'X33/Y10/io1'
Warning: unmatched constraint 'sp3_to_seq_nic_perst_l' (on line 58)
Info: constrained 'nic_to_sp3_pwrflt_l' to bel 'X33/Y12/io0'
Info: constrained 'seq_to_sp3_v1p8_en' to bel 'X0/Y12/io0'
Info: constrained 'seq_to_dimm_abcd_v2p5_en' to bel 'X0/Y10/io0'
Warning: unmatched constraint 'seq_to_sp_misc_a' (on line 62)
Info: constrained 'seq_to_v3p3_sys_en' to bel 'X33/Y4/io1'
Info: constrained 'seq_to_dimm_efgh_v2p5_en' to bel 'X33/Y6/io0'
Warning: unmatched constraint 'dimm_to_seq_efgh_v2p5_pg' (on line 65)
Warning: unmatched constraint 'dimm_to_seq_abcd_v2p5_pg' (on line 66)
Info: constrained 'seq_to_sp3_v3p3_s5_en' to bel 'X0/Y9/io0'
Warning: unmatched constraint 'seq_to_sp_misc_d' (on line 68)
Info: constrained 'seq_to_sp3_v1p8_s5_en' to bel 'X27/Y0/io1'
Warning: unmatched constraint 'nic_v0p9_a0hp_pg' (on line 70)
Warning: unmatched constraint 'pwr_cont_dimm_pg0' (on line 71)
Warning: unmatched constraint 'v3p3_sys_to_seq_pg' (on line 72)
Warning: unmatched constraint 'fan_to_seq_fan_fail' (on line 73)
Warning: unmatched constraint 'sp3_to_seq_v3p3_s5_pg' (on line 74)
Warning: unmatched constraint 'sp3_to_seq_v1p8_s5_pg' (on line 75)
Warning: unmatched constraint 'pwr_cont_dimm_pg1' (on line 76)
Warning: unmatched constraint 'pwr_cont1_sp3_cfp' (on line 77)
Warning: unmatched constraint 'pwr_cont1_sp3_nvrhot' (on line 78)
Info: constrained 'pwr_cont1_sp3_pwrok' to bel 'X3/Y0/io0'
Warning: unmatched constraint 'sp3_to_seq_fsr_req_l' (on line 80)
Warning: unmatched constraint 'sp3_to_seq_pwrgd_out' (on line 81)
Info: constrained 'RST_N' to bel 'X17/Y0/io1'
Warning: unmatched constraint 'seq_to_sp_misc_b' (on line 83)
Info: constrained 'copi' to bel 'X30/Y0/io1'
Info: constrained 'cipo' to bel 'X30/Y0/io0'
Warning: unmatched constraint 'pwr_cont2_sp3_pg1' (on line 86)
Warning: unmatched constraint 'pwr_cont2_sp3_cfp' (on line 87)
Warning: unmatched constraint 'pwr_cont_dimm_nvrhot' (on line 88)
Info: constrained 'pwr_cont1_sp3_en' to bel 'X0/Y3/io1'
Warning: unmatched constraint 'pwr_cont1_sp3_pg0' (on line 90)
Info: constrained 'seq_to_sp3_v1p5_rtc_en' to bel 'X5/Y0/io1'
Warning: unmatched constraint 'sp3_to_seq_reset_v3p3_l' (on line 92)
Info: constrained 'seq_to_sp3_rsmrst_v3p3_l' to bel 'X6/Y0/io0'
Info: constrained 'seq_to_sp3_v0p9_s5_en' to bel 'X11/Y0/io1'
Warning: unmatched constraint 'sp3_to_seq_thermtrip_l' (on line 95)
Warning: unmatched constraint 'sp3_to_seq_slp_s3_l' (on line 96)
Info: constrained 'sclk' to bel 'X31/Y0/io0'
Info: constrained 'csn' to bel 'X31/Y0/io1'
Info: constrained 'pwr_cont2_sp3_pwrok' to bel 'X33/Y1/io0'
Info: constrained 'pwr_cont_dimm_en1' to bel 'X33/Y1/io1'
Info: constrained 'pwr_cont_dimm_en0' to bel 'X28/Y0/io0'
Warning: unmatched constraint 'pwr_cont1_sp3_pg1' (on line 102)
Warning: unmatched constraint 'sp3_to_seq_rtc_v1p5_pg' (on line 103)
Warning: unmatched constraint 'sp3_to_seq_pwrok_v3p3' (on line 104)
Warning: unmatched constraint 'sp3_to_seq_v0p9_vdd_soc_s5_pg' (on line 105)
Info: constrained 'seq_to_nic_comb_pg_l' to bel 'X12/Y0/io1'
Info: constrained 'seq_to_sp3_pwr_good' to bel 'X13/Y0/io1'
Info: constrained 'seq_to_sp3_pwr_btn_l' to bel 'X14/Y0/io0'
Warning: unmatched constraint 'seq_to_sp3_sys_rst_l' (on line 109)
Warning: unmatched constraint 'sp3_to_seq_slp_s5_l' (on line 110)
Warning: unmatched constraint 'seq_to_sp_misc_c' (on line 111)
Info: constrained 'pwr_cont2_sp3_en' to bel 'X24/Y0/io0'
Warning: unmatched constraint 'pwr_cont2_sp3_pg0' (on line 113)
Warning: unmatched constraint 'pwr_cont2_sp3_nvrhot' (on line 114)
Warning: unmatched constraint 'pwr_cont_dimm_cfp' (on line 115)

Info: Packing constants..
Info: Packing IOs..
Info: cipo feeds SB_IO cipo_io, removing $nextpnr_iobuf cipo.
Info: Packing LUT-FFs..
Info:      223 LCs used as LUT4 only
Info:      130 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:       45 LCs used as DFF only
Info: Packing carries..
Info:        0 LCs used as CARRY only
Info: Packing indirect carry+LUT pairs...
Info:        0 LUTs merged into carry LCs
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Packing PLLs..
Info: Promoting globals..
Info: promoting clk50m$SB_IO_IN (fanout 177)
Info: promoting RST_N_SB_LUT4_I3_O [reset] (fanout 116)
Info: promoting decode_address_SB_DFFESS_Q_S[1] [reset] (fanout 16)
Info: Constraining chains...
Info:        1 LCs used to legalise carry chains.
Info: Checksum: 0x5b34544e

Info: Device utilisation:
Info: 	         ICESTORM_LC:     401/   7680     5%
Info: 	        ICESTORM_RAM:       0/     32     0%
Info: 	               SB_IO:      46/    256    17%
Info: 	               SB_GB:       3/      8    37%
Info: 	        ICESTORM_PLL:       0/      2     0%
Info: 	         SB_WARMBOOT:       0/      1     0%

Info: Placed 46 cells based on constraints.
Info: Creating initial analytic placement for 389 cells, random placement wirelen = 12632.
Info:     at initial placer iter 0, wirelen = 115
Info:     at initial placer iter 1, wirelen = 115
Info:     at initial placer iter 2, wirelen = 115
Info:     at initial placer iter 3, wirelen = 115
Info: Running main analytical placer, max placement attempts per cell = 25312.
Info:     at iteration #1, type ALL: wirelen solved = 115, spread = 1615, legal = 2054; time = 0.01s
Info:     at iteration #2, type ALL: wirelen solved = 169, spread = 1331, legal = 1670; time = 0.03s
Info:     at iteration #3, type ALL: wirelen solved = 190, spread = 1380, legal = 1630; time = 0.03s
Info:     at iteration #4, type ALL: wirelen solved = 216, spread = 1348, legal = 1579; time = 0.03s
Info:     at iteration #5, type ALL: wirelen solved = 241, spread = 1380, legal = 1662; time = 0.03s
Info:     at iteration #6, type ALL: wirelen solved = 355, spread = 1331, legal = 1654; time = 0.03s
Info:     at iteration #7, type ALL: wirelen solved = 411, spread = 1214, legal = 1605; time = 0.01s
Info:     at iteration #8, type ALL: wirelen solved = 373, spread = 1247, legal = 1583; time = 0.01s
Info:     at iteration #9, type ALL: wirelen solved = 454, spread = 1453, legal = 1591; time = 0.01s
Info: HeAP Placer Time: 0.30s
Info:   of which solving equations: 0.24s
Info:   of which spreading cells: 0.01s
Info:   of which strict legalisation: 0.03s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 86, wirelen = 1579
Info:   at iteration #5: temp = 0.000000, timing cost = 95, wirelen = 1355
Info:   at iteration #10: temp = 0.000000, timing cost = 91, wirelen = 1276
Info:   at iteration #15: temp = 0.000000, timing cost = 123, wirelen = 1254
Info:   at iteration #19: temp = 0.000000, timing cost = 106, wirelen = 1193 
Info: SA placement time 0.23s

Info: Max frequency for clock 'clk50m$SB_IO_IN_$glb_clk': 105.83 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                          -> posedge clk50m$SB_IO_IN_$glb_clk: 4.64 ns
Info: Max delay posedge clk50m$SB_IO_IN_$glb_clk -> <async>                         : 2.65 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 10551,  10951) |********+
Info: [ 10951,  11351) |*+
Info: [ 11351,  11751) |******+
Info: [ 11751,  12151) |+
Info: [ 12151,  12551) |**+
Info: [ 12551,  12951) |****************+
Info: [ 12951,  13351) |****+
Info: [ 13351,  13751) |***************************+
Info: [ 13751,  14151) |*****+
Info: [ 14151,  14551) |****+
Info: [ 14551,  14951) |*****************+
Info: [ 14951,  15351) |**********************************+
Info: [ 15351,  15751) |*************+
Info: [ 15751,  16151) |*******************************************+
Info: [ 16151,  16551) |********+
Info: [ 16551,  16951) |*************************+
Info: [ 16951,  17351) |*+
Info: [ 17351,  17751) |************************************ 
Info: [ 17751,  18151) |********************+
Info: [ 18151,  18551) |************************************************************ 
Info: Checksum: 0xa9248250

Info: Routing..
Info: Setting up routing queue.
Info: Routing 1416 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |      251        748 |  251   748 |       712|       0.16       0.16|
Info:       2000 |      635       1351 |  384   603 |       197|       0.17       0.33|
Info:       2205 |      642       1550 |    7   199 |         0|       0.17       0.50|
Info: Routing complete.
Info: Router1 time 0.50s
Info: Checksum: 0x8da29a24

Info: Critical path report for clock 'clk50m$SB_IO_IN_$glb_clk' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source decode_address_SB_DFFESS_Q_1_D_SB_LUT4_O_LC.O
Info:  0.6  1.1    Net decode_address[11] (29,7) -> (29,6)
Info:                Sink regs_power_control_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_1_LC.I0
Info:                Defined in:
Info:                  ./env/1b683657c28c182a3663ba012c766c2639805582/hdl/projects/gimlet/sequencer/mkGimletPowerSeqTop.v:354.16-354.30
Info:  0.4  1.6  Source regs_power_control_SB_LUT4_I1_I2_SB_LUT4_O_I2_SB_LUT4_O_1_LC.O
Info:  1.0  2.5    Net regs_power_control_SB_LUT4_I1_I2_SB_LUT4_O_I2[3] (29,6) -> (28,3)
Info:                Sink regs_power_control_SB_LUT4_I1_I2_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  2.8  Source regs_power_control_SB_LUT4_I1_I2_SB_LUT4_O_LC.O
Info:  0.6  3.4    Net IF_regs_power_control_14_BIT_1_15_THEN_2_ELSE__ETC___d419_SB_LUT4_I1_O_SB_LUT4_O_1_I0_SB_LUT4_O_I2_SB_LUT4_I1_I2_SB_LUT4_I3_O[2] (28,3) -> (27,3)
Info:                Sink regs_power_control_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I0_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  3.8  Source regs_power_control_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I0_LC.O
Info:  1.3  5.0    Net regs_power_control_SB_LUT4_I1_O_SB_LUT4_O_I2_SB_LUT4_I3_O_SB_LUT4_O_I2_SB_LUT4_I0_O[2] (27,3) -> (23,3)
Info:                Sink regs_dbgCtrl_reg_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  5.3  Source regs_dbgCtrl_reg_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_1_O_SB_LUT4_O_LC.O
Info:  0.6  5.9    Net regs_dbgCtrl_reg_SB_DFFESR_Q_E_SB_LUT4_O_I3_SB_LUT4_I3_1_O[2] (23,3) -> (23,3)
Info:                Sink regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  6.3  Source regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I0_SB_LUT4_O_LC.O
Info:  0.6  6.9    Net regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_I0[2] (23,3) -> (24,3)
Info:                Sink regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  7.3  Source regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_I2_SB_LUT4_O_LC.O
Info:  1.3  8.5    Net regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_I2[0] (24,3) -> (26,4)
Info:                Sink regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.4  8.9  Setup regs_readdata_SB_DFFESS_Q_3_D_SB_LUT4_O_LC.I2
Info: 3.1 ns logic, 5.9 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk50m$SB_IO_IN_$glb_clk':
Info: curr total
Info:  0.0  0.0  Source RST_N$sb_io.D_IN_0
Info:  2.6  2.6    Net RST_N$SB_IO_IN (17,0) -> (30,5)
Info:                Sink decode_reg_read_data_SB_DFFESS_Q_E_SB_LUT4_O_LC.I1
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:4837.14-4837.18
Info:  0.4  3.0  Source decode_reg_read_data_SB_DFFESS_Q_E_SB_LUT4_O_LC.O
Info:  1.9  4.9    Net decode_reg_read_data_SB_DFFESS_Q_E (30,5) -> (30,5)
Info:                Sink decode_reg_read_data_SB_DFFESR_Q_DFFLC.CEN
Info:  0.1  5.0  Setup decode_reg_read_data_SB_DFFESR_Q_DFFLC.CEN
Info: 0.5 ns logic, 4.5 ns routing

Info: Critical path report for cross-domain path 'posedge clk50m$SB_IO_IN_$glb_clk' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source spi_sync_csn_sync.sSyncReg_SB_DFFR_D_DFFLC.O
Info:  0.6  1.1    Net decode_is_read_SB_LUT4_I1_1_O_SB_LUT4_I3_I1[0] (31,3) -> (31,2)
Info:                Sink cipo_io$OUTPUT_ENABLE_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.3  1.4  Source cipo_io$OUTPUT_ENABLE_SB_LUT4_O_LC.O
Info:  1.3  2.7    Net cipo_io$OUTPUT_ENABLE (31,2) -> (30,0)
Info:                Sink cipo_io.OUTPUT_ENABLE
Info:                Defined in:
Info:                  ./env/1b683657c28c182a3663ba012c766c2639805582/hdl/projects/gimlet/sequencer/mkGimletPowerSeqTop.v:559.8-559.29
Info: 0.9 ns logic, 1.9 ns routing

Info: Max frequency for clock 'clk50m$SB_IO_IN_$glb_clk': 111.78 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                          -> posedge clk50m$SB_IO_IN_$glb_clk: 4.98 ns
Info: Max delay posedge clk50m$SB_IO_IN_$glb_clk -> <async>                         : 2.72 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 11054,  11429) |*+
Info: [ 11429,  11804) | 
Info: [ 11804,  12179) |******+
Info: [ 12179,  12554) |**************+
Info: [ 12554,  12929) |************+
Info: [ 12929,  13304) |************************+
Info: [ 13304,  13679) |*******+
Info: [ 13679,  14054) |***********+
Info: [ 14054,  14429) |***+
Info: [ 14429,  14804) |**********+
Info: [ 14804,  15179) |*********************+
Info: [ 15179,  15554) |************************+
Info: [ 15554,  15929) |***************************************+
Info: [ 15929,  16304) |*******************************+
Info: [ 16304,  16679) |********+
Info: [ 16679,  17054) |******+
Info: [ 17054,  17429) |***********+
Info: [ 17429,  17804) |************************************+
Info: [ 17804,  18179) |**************+
Info: [ 18179,  18554) |************************************************************ 
68 warnings, 0 errors

Info: Program finished normally.