Info: constrained 'seq_to_nic_v1p1_en' to bel 'X4/Y33/io1' Info: constrained 'nic_to_seq_v1p1_pg' to bel 'X5/Y33/io1' Info: constrained 'seq_to_nic_v1p2_enet_en' to bel 'X8/Y33/io0' Info: constrained 'seq_rev_id0' to bel 'X22/Y33/io1' Info: constrained 'seq_rev_id1' to bel 'X22/Y33/io0' Info: constrained 'pwr_cont_nic_pg1' to bel 'X27/Y33/io0' Info: constrained 'pwr_cont_nic_pg0' to bel 'X27/Y33/io1' Info: constrained 'seq_to_nic_v1p5a_en' to bel 'X0/Y30/io0' Info: constrained 'seq_to_nic_ldo_v3p3_en' to bel 'X0/Y31/io0' Info: constrained 'seq_to_nic_v1p2_en' to bel 'X3/Y33/io0' Warning: unmatched constraint 'testpoint1' (on line 11) Info: constrained 'seq_rev_id2' to bel 'X24/Y33/io0' Info: constrained 'seq_to_nic_cld_rst_l' to bel 'X30/Y33/io0' Info: constrained 'pwr_cont_nic_en0' to bel 'X31/Y33/io0' Info: constrained 'nic_to_seq_v1p5d_pg' to bel 'X0/Y28/io1' Info: constrained 'nic_to_seq_v1p5a_pg' to bel 'X0/Y28/io0' Info: constrained 'nic_to_seq_v1p2_pg' to bel 'X1/Y33/io0' Warning: unmatched constraint 'testpoint2' (on line 18) Info: constrained 'nic_to_seq_v1p2_enet_pg' to bel 'X10/Y33/io0' Info: constrained 'nic_to_seq_ext_rst_l' to bel 'X28/Y33/io1' Info: constrained 'pwr_cont_nic_en1' to bel 'X33/Y28/io0' Info: constrained 'seq_to_nic_v1p5d_en' to bel 'X0/Y25/io0' Info: constrained 'seq_to_clk_nmr_l' to bel 'X0/Y27/io0' Info: constrained 'sp3_to_sp_nic_pwren_l' to bel 'X2/Y33/io1' Info: constrained 'fanhp_to_seq_fault_l' to bel 'X33/Y26/io0' Info: constrained 'fanhp_to_seq_pwrgd' to bel 'X33/Y24/io0' Info: constrained 'seq_to_clk_ntest' to bel 'X0/Y23/io0' Info: constrained 'vtt_ef_a0_to_seq_pg' to bel 'X33/Y30/io1' Info: constrained 'vtt_gh_a0_to_seq_pg' to bel 'X33/Y27/io1' Info: constrained 'seq_to_fan_hp_en' to bel 'X33/Y23/io0' Info: constrained 'seq_to_clk_gpio3' to bel 'X0/Y20/io0' Info: constrained 'seq_to_clk_gpio9' to bel 'X0/Y21/io0' Info: constrained 'clk50m' to bel 'X16/Y33/io1' Info: constrained 'seq_to_vtt_efgh_en' to bel 'X33/Y21/io0' Info: constrained 'seq_to_clk_gpio8' to bel 'X0/Y17/io0' Info: constrained 'seq_to_clk_gpio2' to bel 'X0/Y19/io0' Info: constrained 'seq_to_header_misc_i' to bel 'X0/Y25/io1' Info: constrained 'sp3_to_rsw_pwren_l_via_seq' to bel 'X33/Y20/io1' Info: constrained 'seq_proxy_sp3_to_rsw_pwren_l' to bel 'X33/Y21/io1' Info: constrained 'pwr_cont_dimm_efgh_pg0' to bel 'X33/Y20/io0' Info: constrained 'seq_to_clk_gpio1' to bel 'X0/Y16/io0' Info: constrained 'seq_to_clk_gpio4' to bel 'X0/Y18/io0' Info: constrained 'seq_to_header_misc_e' to bel 'X0/Y21/io1' Info: constrained 'seq_to_header_misc_f' to bel 'X0/Y19/io1' Info: constrained 'seq_to_header_misc_g' to bel 'X0/Y23/io1' Info: constrained 'seq_to_header_misc_h' to bel 'X0/Y20/io1' Info: constrained 'seq_to_clk_gpio5' to bel 'X0/Y14/io0' Info: constrained 'vtt_ab_a0_to_seq_pg' to bel 'X0/Y14/io1' Info: constrained 'vtt_cd_a0_to_seq_pg' to bel 'X0/Y16/io1' Info: constrained 'seq_to_sp_interrupt' to bel 'X0/Y18/io1' Info: constrained 'seq_to_led_en_l' to bel 'X33/Y14/io1' Info: constrained 'seq_to_nic_v0p9_a0hp_en' to bel 'X33/Y15/io0' Info: constrained 'pwr_cont_dimm_efgh_en0' to bel 'X33/Y15/io1' Info: constrained 'seq_to_vtt_abcd_en' to bel 'X0/Y13/io1' Info: constrained 'seq_v1p8_sp3_vdd_pg' to bel 'X0/Y13/io0' Info: constrained 'seq_to_nic_perst_l' to bel 'X33/Y10/io1' Info: constrained 'sp3_to_seq_nic_perst_l' to bel 'X33/Y11/io0' Info: constrained 'nic_to_sp3_pwrflt_l' to bel 'X33/Y12/io0' Info: constrained 'seq_to_sp3_v1p8_en' to bel 'X0/Y12/io0' Info: constrained 'seq_to_dimm_abcd_v2p5_en' to bel 'X0/Y10/io0' Info: constrained 'seq_to_sp_misc_a' to bel 'X19/Y0/io1' Info: constrained 'seq_to_v3p3_sys_en' to bel 'X33/Y4/io1' Info: constrained 'seq_to_dimm_efgh_v2p5_en' to bel 'X33/Y6/io0' Info: constrained 'dimm_to_seq_efgh_v2p5_pg' to bel 'X33/Y10/io0' Info: constrained 'dimm_to_seq_abcd_v2p5_pg' to bel 'X0/Y11/io0' Info: constrained 'seq_to_sp3_v3p3_s5_en' to bel 'X0/Y9/io0' Info: constrained 'seq_to_sp_misc_d' to bel 'X23/Y0/io1' Info: constrained 'seq_to_sp3_v1p8_s5_en' to bel 'X27/Y0/io1' Info: constrained 'nic_v0p9_a0hp_pg' to bel 'X33/Y3/io1' Info: constrained 'pwr_cont_dimm_pg0' to bel 'X33/Y4/io0' Info: constrained 'v3p3_sys_to_seq_pg' to bel 'X33/Y8/io0' Info: constrained 'fan_to_seq_fan_fail' to bel 'X33/Y7/io0' Info: constrained 'sp3_to_seq_v3p3_s5_pg' to bel 'X0/Y8/io0' Info: constrained 'sp3_to_seq_v1p8_s5_pg' to bel 'X26/Y0/io0' Info: constrained 'pwr_cont_dimm_pg1' to bel 'X33/Y5/io0' Info: constrained 'pwr_cont1_sp3_cfp' to bel 'X0/Y5/io1' Info: constrained 'pwr_cont1_sp3_nvrhot' to bel 'X0/Y4/io1' Info: constrained 'pwr_cont1_sp3_pwrok' to bel 'X3/Y0/io0' Info: constrained 'sp3_to_seq_fsr_req_l' to bel 'X14/Y0/io1' Info: constrained 'sp3_to_seq_pwrgd_out' to bel 'X12/Y0/io0' Info: constrained 'RST_N' to bel 'X17/Y0/io1' Info: constrained 'seq_to_sp_misc_b' to bel 'X20/Y0/io0' Info: constrained 'copi' to bel 'X30/Y0/io1' Info: constrained 'cipo' to bel 'X30/Y0/io0' Info: constrained 'pwr_cont2_sp3_pg1' to bel 'X29/Y0/io1' Info: constrained 'pwr_cont2_sp3_cfp' to bel 'X33/Y2/io0' Info: constrained 'pwr_cont_dimm_nvrhot' to bel 'X33/Y2/io1' Info: constrained 'pwr_cont1_sp3_en' to bel 'X0/Y3/io1' Info: constrained 'pwr_cont1_sp3_pg0' to bel 'X3/Y0/io1' Info: constrained 'seq_to_sp3_v1p5_rtc_en' to bel 'X5/Y0/io1' Info: constrained 'sp3_to_seq_reset_v3p3_l' to bel 'X7/Y0/io1' Info: constrained 'seq_to_sp3_rsmrst_v3p3_l' to bel 'X6/Y0/io0' Info: constrained 'seq_to_sp3_v0p9_s5_en' to bel 'X11/Y0/io1' Info: constrained 'sp3_to_seq_thermtrip_l' to bel 'X16/Y0/io1' Info: constrained 'sp3_to_seq_slp_s3_l' to bel 'X19/Y0/io0' Info: constrained 'sclk' to bel 'X31/Y0/io0' Info: constrained 'csn' to bel 'X31/Y0/io1' Info: constrained 'pwr_cont2_sp3_pwrok' to bel 'X33/Y1/io0' Info: constrained 'pwr_cont_dimm_en1' to bel 'X33/Y1/io1' Info: constrained 'pwr_cont_dimm_en0' to bel 'X28/Y0/io0' Info: constrained 'pwr_cont1_sp3_pg1' to bel 'X2/Y0/io1' Info: constrained 'sp3_to_seq_rtc_v1p5_pg' to bel 'X4/Y0/io1' Info: constrained 'sp3_to_seq_pwrok_v3p3' to bel 'X6/Y0/io1' Info: constrained 'sp3_to_seq_v0p9_vdd_soc_s5_pg' to bel 'X10/Y0/io1' Info: constrained 'seq_to_nic_comb_pg_l' to bel 'X12/Y0/io1' Info: constrained 'seq_to_sp3_pwr_good' to bel 'X13/Y0/io1' Info: constrained 'seq_to_sp3_pwr_btn_l' to bel 'X14/Y0/io0' Info: constrained 'seq_to_sp3_sys_rst_l' to bel 'X15/Y0/io1' Info: constrained 'sp3_to_seq_slp_s5_l' to bel 'X21/Y0/io0' Info: constrained 'seq_to_sp_misc_c' to bel 'X21/Y0/io1' Info: constrained 'pwr_cont2_sp3_en' to bel 'X24/Y0/io0' Info: constrained 'pwr_cont2_sp3_pg0' to bel 'X23/Y0/io0' Info: constrained 'pwr_cont2_sp3_nvrhot' to bel 'X22/Y0/io1' Info: constrained 'pwr_cont_dimm_cfp' to bel 'X27/Y0/io0' Info: Packing constants.. Info: Packing IOs.. Info: seq_to_sp3_sys_rst_l feeds SB_IO seq_to_sp3_sys_rst_l_io, removing $nextpnr_iobuf seq_to_sp3_sys_rst_l. Info: seq_to_sp3_pwr_btn_l feeds SB_IO seq_to_sp3_pwr_btn_l_io, removing $nextpnr_iobuf seq_to_sp3_pwr_btn_l. Info: seq_to_nic_comb_pg_l feeds SB_IO seq_to_nic_comb_pg_l_io, removing $nextpnr_iobuf seq_to_nic_comb_pg_l. Info: nic_to_sp3_pwrflt_l feeds SB_IO nic_to_sp3_pwrflt_l_io, removing $nextpnr_iobuf nic_to_sp3_pwrflt_l. Info: cipo feeds SB_IO cipo_io, removing $nextpnr_iobuf cipo. Info: Packing LUT-FFs.. Info: 673 LCs used as LUT4 only Info: 288 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 261 LCs used as DFF only Info: Packing carries.. Info: 37 LCs used as CARRY only Info: Packing indirect carry+LUT pairs... Info: 35 LUTs merged into carry LCs Info: Packing RAMs.. Info: Placing PLLs.. Info: Packing special functions.. Info: Packing PLLs.. Info: Promoting globals.. Info: promoting clk50m$SB_IO_IN (fanout 559) Info: promoting reset_sync.reset_hold_SB_DFFR_D_Q_SB_LUT4_I3_O [reset] (fanout 320) Info: promoting RST_N_SB_LUT4_I3_O [reset] (fanout 88) Info: promoting inner_decode_address_SB_DFFESS_Q_S[1] [reset] (fanout 16) Info: promoting inner_nic_block_perst_can_deassert_SB_DFFSR_Q_D_SB_LUT4_I3_O [cen] (fanout 25) Info: Constraining chains... Info: 10 LCs used to legalise carry chains. Info: Checksum: 0x503236aa Info: Device utilisation: Info: ICESTORM_LC: 1236/ 7680 16% Info: ICESTORM_RAM: 0/ 32 0% Info: SB_IO: 112/ 256 43% Info: SB_GB: 5/ 8 62% Info: ICESTORM_PLL: 0/ 2 0% Info: SB_WARMBOOT: 0/ 1 0% Info: Placed 112 cells based on constraints. Info: Creating initial analytic placement for 1081 cells, random placement wirelen = 35213. Info: at initial placer iter 0, wirelen = 1857 Info: at initial placer iter 1, wirelen = 1825 Info: at initial placer iter 2, wirelen = 1836 Info: at initial placer iter 3, wirelen = 1843 Info: Running main analytical placer, max placement attempts per cell = 228826. Info: at iteration #1, type ALL: wirelen solved = 1841, spread = 6457, legal = 7243; time = 0.06s Info: at iteration #2, type ALL: wirelen solved = 1857, spread = 5700, legal = 7168; time = 0.07s Info: at iteration #3, type ALL: wirelen solved = 2192, spread = 5320, legal = 6901; time = 0.07s Info: at iteration #4, type ALL: wirelen solved = 2284, spread = 5333, legal = 7326; time = 0.07s Info: at iteration #5, type ALL: wirelen solved = 2359, spread = 5507, legal = 6799; time = 0.05s Info: at iteration #6, type ALL: wirelen solved = 2549, spread = 5732, legal = 6952; time = 0.04s Info: at iteration #7, type ALL: wirelen solved = 2648, spread = 5835, legal = 7688; time = 0.05s Info: at iteration #8, type ALL: wirelen solved = 2718, spread = 6138, legal = 7150; time = 0.04s Info: at iteration #9, type ALL: wirelen solved = 2804, spread = 6237, legal = 7486; time = 0.06s Info: at iteration #10, type ALL: wirelen solved = 2891, spread = 6126, legal = 7239; time = 0.06s Info: HeAP Placer Time: 0.79s Info: of which solving equations: 0.42s Info: of which spreading cells: 0.03s Info: of which strict legalisation: 0.21s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 193, wirelen = 6799 Info: at iteration #5: temp = 0.000000, timing cost = 293, wirelen = 5525 Info: at iteration #10: temp = 0.000000, timing cost = 292, wirelen = 5166 Info: at iteration #15: temp = 0.000000, timing cost = 251, wirelen = 5006 Info: at iteration #20: temp = 0.000000, timing cost = 271, wirelen = 4810 Info: at iteration #25: temp = 0.000000, timing cost = 281, wirelen = 4734 Info: at iteration #27: temp = 0.000000, timing cost = 287, wirelen = 4719 Info: SA placement time 1.67s Info: Max frequency for clock 'clk50m$SB_IO_IN_$glb_clk': 85.81 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge clk50m$SB_IO_IN_$glb_clk: 6.33 ns Info: Max delay posedge clk50m$SB_IO_IN_$glb_clk -> : 4.80 ns Info: Slack histogram: Info: legend: * represents 3 endpoint(s) Info: + represents [1,3) endpoint(s) Info: [ 8346, 8856) |**********+ Info: [ 8856, 9366) |*****+ Info: [ 9366, 9876) |**+ Info: [ 9876, 10386) |+ Info: [ 10386, 10896) |***+ Info: [ 10896, 11406) |*********+ Info: [ 11406, 11916) |***************+ Info: [ 11916, 12426) |*****************+ Info: [ 12426, 12936) |***************************************+ Info: [ 12936, 13446) |********************+ Info: [ 13446, 13956) |***********************************+ Info: [ 13956, 14466) |**************************************************+ Info: [ 14466, 14976) |****************************************************+ Info: [ 14976, 15486) |***************************+ Info: [ 15486, 15996) |**********************************+ Info: [ 15996, 16506) |********************+ Info: [ 16506, 17016) |**************************************+ Info: [ 17016, 17526) |*************************+ Info: [ 17526, 18036) |*******************************************+ Info: [ 18036, 18546) |************************************************************ Info: Checksum: 0x57dcb99c Info: Routing.. Info: Setting up routing queue. Info: Routing 4057 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 153 846 | 153 846 | 3265| 0.44 0.44| Info: 2000 | 458 1520 | 305 674 | 2626| 0.23 0.67| Info: 3000 | 890 2027 | 432 507 | 2188| 0.23 0.90| Info: 4000 | 1123 2785 | 233 758 | 1491| 0.19 1.10| Info: 5000 | 1440 3427 | 317 642 | 861| 0.27 1.37| Info: 6000 | 1576 4285 | 136 858 | 34| 0.56 1.92| Info: 6033 | 1576 4319 | 0 34 | 0| 0.03 1.95| Info: Routing complete. Info: Router1 time 1.95s Info: Checksum: 0x32470ce4 Info: Critical path report for clock 'clk50m$SB_IO_IN_$glb_clk' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source inner_decode_address_SB_DFFESS_Q_1_D_SB_LUT4_O_LC.O Info: 0.6 1.1 Net inner_decode_address[11] (14,11) -> (14,11) Info: Sink inner_decode_state_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_LC.I0 Info: Defined in: Info: ./env/5f31029f59d4174de0404b8c593e1d2c4122a5f8/hdl/projects/gimlet/sequencer/mkGimletSeqTop.v:1245.16-1245.36 Info: 0.4 1.6 Source inner_decode_state_SB_LUT4_I2_O_SB_LUT4_O_I2_SB_LUT4_O_LC.O Info: 1.3 2.8 Net inner_decode_state_SB_LUT4_I2_O_SB_LUT4_O_I2[2] (14,11) -> (11,10) Info: Sink inner_decode_state_SB_LUT4_I2_O_SB_LUT4_O_LC.I2 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 3.2 Source inner_decode_state_SB_LUT4_I2_O_SB_LUT4_O_LC.O Info: 1.6 4.9 Net inner_decode_state_SB_LUT4_I2_O[2] (11,10) -> (6,7) Info: Sink inner_nic_block_seq_to_nic_perst_l_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 5.2 Source inner_nic_block_seq_to_nic_perst_l_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I3_SB_LUT4_I3_O_SB_LUT4_O_I3_SB_LUT4_I2_LC.O Info: 0.6 5.8 Net inner_nic_block_seq_to_nic_perst_l_SB_LUT4_I1_O_SB_LUT4_I2_O_SB_LUT4_O_1_I2_SB_LUT4_O_I2_SB_LUT4_I2_O[2] (6,7) -> (5,7) Info: Sink inner_regs_nic_control_SB_LUT4_I1_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 6.1 Source inner_regs_nic_control_SB_LUT4_I1_LC.O Info: 0.6 6.7 Net inner_a0_block_amd_a0_SB_LUT4_I1_O[0] (5,7) -> (5,7) Info: Sink inner_a1_block_enable$D_IN_SB_LUT4_I1_1_O_SB_LUT4_I0_O_SB_LUT4_O_2_LC.I0 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 7.1 Source inner_a1_block_enable$D_IN_SB_LUT4_I1_1_O_SB_LUT4_I0_O_SB_LUT4_O_2_LC.O Info: 1.3 8.4 Net inner_a1_block_enable$D_IN_SB_LUT4_I1_1_O_SB_LUT4_I0_O[2] (5,7) -> (7,5) Info: Sink inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_O_LC.I2 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 8.8 Source inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_I0_SB_LUT4_O_LC.O Info: 0.6 9.4 Net inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_I0[2] (7,5) -> (7,5) Info: Sink inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_LC.I2 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 9.7 Source inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3_SB_LUT4_O_LC.O Info: 1.3 11.0 Net inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I3[2] (7,5) -> (11,7) Info: Sink inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 11.4 Setup inner_regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_LC.I3 Info: 3.5 ns logic, 7.8 ns routing Info: Critical path report for cross-domain path '' -> 'posedge clk50m$SB_IO_IN_$glb_clk': Info: curr total Info: 0.0 0.0 Source nic_to_seq_ext_rst_l$sb_io.D_IN_0 Info: 3.0 3.0 Net nic_to_seq_ext_rst_l$SB_IO_IN (28,33) -> (18,14) Info: Sink sync_nic_to_seq_ext_rst_l.sSyncReg_SB_DFFR_Q_DFFLC.I0 Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:4839.14-4839.19 Info: 0.5 3.5 Setup sync_nic_to_seq_ext_rst_l.sSyncReg_SB_DFFR_Q_DFFLC.I0 Info: 0.5 ns logic, 3.0 ns routing Info: Critical path report for cross-domain path 'posedge clk50m$SB_IO_IN_$glb_clk' -> '': Info: curr total Info: 0.5 0.5 Source inner_a0_block_vpp_efgh_enabled_r_SB_DFFESR_Q_D_SB_LUT4_O_LC.O Info: 4.5 5.0 Net seq_to_v3p3_sys_en$SB_IO_OUT (3,1) -> (33,15) Info: Sink pwr_cont_dimm_efgh_en0$sb_io.D_OUT_0 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 ns logic, 4.5 ns routing Info: Max frequency for clock 'clk50m$SB_IO_IN_$glb_clk': 88.07 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge clk50m$SB_IO_IN_$glb_clk: 3.49 ns Info: Max delay posedge clk50m$SB_IO_IN_$glb_clk -> : 5.03 ns Info: Slack histogram: Info: legend: * represents 6 endpoint(s) Info: + represents [1,6) endpoint(s) Info: [ 8646, 9141) |*+ Info: [ 9141, 9636) |+ Info: [ 9636, 10131) |*******+ Info: [ 10131, 10626) |***+ Info: [ 10626, 11121) |**+ Info: [ 11121, 11616) |***********+ Info: [ 11616, 12111) |*********+ Info: [ 12111, 12606) |************+ Info: [ 12606, 13101) |***********+ Info: [ 13101, 13596) |******+ Info: [ 13596, 14091) |**+ Info: [ 14091, 14586) |**********+ Info: [ 14586, 15081) |************+ Info: [ 15081, 15576) |*************+ Info: [ 15576, 16071) |************************************************************ Info: [ 16071, 16566) |*************+ Info: [ 16566, 17061) |*************+ Info: [ 17061, 17556) |************+ Info: [ 17556, 18051) |******************+ Info: [ 18051, 18546) |*******************************+ 2 warnings, 0 errors Info: Program finished normally.