Info: constrained 'clk_12mhz' to bel 'X0/Y8/io1' Info: constrained 'RST_N' to bel 'X13/Y8/io0' Info: constrained 'led[0]' to bel 'X13/Y12/io1' Info: constrained 'led[1]' to bel 'X13/Y12/io0' Info: constrained 'led[2]' to bel 'X13/Y11/io1' Info: constrained 'led[3]' to bel 'X13/Y11/io0' Info: constrained 'led[4]' to bel 'X13/Y9/io1' Info: constrained 'ftdi_dcd_n' to bel 'X0/Y14/io1' Info: constrained 'ftdi_dsr_n' to bel 'X0/Y14/io0' Info: constrained 'ftdi_dtr_n' to bel 'X0/Y13/io1' Info: constrained 'ftdi_cts_n' to bel 'X0/Y13/io0' Info: constrained 'ftdi_rts_n' to bel 'X0/Y12/io1' Info: constrained 'ftdi_rxd' to bel 'X0/Y12/io0' Info: constrained 'ftdi_txd' to bel 'X0/Y11/io1' Info: constrained 'irda_txd' to bel 'X13/Y14/io1' Info: constrained 'irda_rxd' to bel 'X13/Y15/io0' Info: constrained 'irda_sd' to bel 'X13/Y15/io1' Info: Packing constants.. Info: Packing IOs.. Info: Packing LUT-FFs.. Info: 9 LCs used as LUT4 only Info: 24 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 0 LCs used as DFF only Info: Packing carries.. Info: 0 LCs used as CARRY only Info: Packing indirect carry+LUT pairs... Info: 0 LUTs merged into carry LCs Info: Packing RAMs.. Info: Placing PLLs.. Info: Packing special functions.. Info: Packing PLLs.. Info: Promoting globals.. Info: promoting clk_12mhz$SB_IO_IN (fanout 24) Info: promoting RST_N_SB_LUT4_I3_O [reset] (fanout 24) Info: Constraining chains... Info: 1 LCs used to legalise carry chains. Info: Checksum: 0xe97a8e66 Info: Device utilisation: Info: ICESTORM_LC: 36/ 1280 2% Info: ICESTORM_RAM: 0/ 16 0% Info: SB_IO: 17/ 112 15% Info: SB_GB: 2/ 8 25% Info: ICESTORM_PLL: 0/ 1 0% Info: SB_WARMBOOT: 0/ 1 0% Info: Placed 17 cells based on constraints. Info: Creating initial analytic placement for 16 cells, random placement wirelen = 422. Info: at initial placer iter 0, wirelen = 52 Info: at initial placer iter 1, wirelen = 47 Info: at initial placer iter 2, wirelen = 47 Info: at initial placer iter 3, wirelen = 47 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ICESTORM_LC: wirelen solved = 47, spread = 75, legal = 77; time = 0.00s Info: at iteration #1, type SB_GB: wirelen solved = 76, spread = 76, legal = 78; time = 0.00s Info: at iteration #1, type ALL: wirelen solved = 42, spread = 79, legal = 84; time = 0.00s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 47, spread = 78, legal = 78; time = 0.00s Info: at iteration #2, type SB_GB: wirelen solved = 76, spread = 76, legal = 78; time = 0.00s Info: at iteration #2, type ALL: wirelen solved = 47, spread = 78, legal = 80; time = 0.00s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 50, spread = 83, legal = 83; time = 0.00s Info: at iteration #3, type SB_GB: wirelen solved = 81, spread = 81, legal = 83; time = 0.00s Info: at iteration #3, type ALL: wirelen solved = 50, spread = 83, legal = 85; time = 0.00s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 56, spread = 78, legal = 78; time = 0.00s Info: at iteration #4, type SB_GB: wirelen solved = 76, spread = 76, legal = 78; time = 0.00s Info: at iteration #4, type ALL: wirelen solved = 50, spread = 80, legal = 82; time = 0.00s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 55, spread = 78, legal = 78; time = 0.00s Info: at iteration #5, type SB_GB: wirelen solved = 76, spread = 76, legal = 78; time = 0.00s Info: at iteration #5, type ALL: wirelen solved = 55, spread = 80, legal = 82; time = 0.00s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 58, spread = 82, legal = 82; time = 0.00s Info: at iteration #6, type SB_GB: wirelen solved = 79, spread = 79, legal = 82; time = 0.00s Info: at iteration #6, type ALL: wirelen solved = 52, spread = 80, legal = 82; time = 0.00s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 60, spread = 86, legal = 86; time = 0.00s Info: at iteration #7, type SB_GB: wirelen solved = 83, spread = 83, legal = 86; time = 0.00s Info: at iteration #7, type ALL: wirelen solved = 60, spread = 84, legal = 86; time = 0.00s Info: HeAP Placer Time: 0.02s Info: of which solving equations: 0.01s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.00s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 15, wirelen = 80 Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 65 Info: at iteration #5: temp = 0.000000, timing cost = 13, wirelen = 65 Info: SA placement time 0.00s Info: Max frequency for clock 'clk_12mhz$SB_IO_IN_$glb_clk': 187.23 MHz (PASS at 12.00 MHz) Info: Max delay -> posedge clk_12mhz$SB_IO_IN_$glb_clk: 3.56 ns Info: Max delay posedge clk_12mhz$SB_IO_IN_$glb_clk -> : 1.13 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 77992, 78186) |******* Info: [ 78186, 78380) |* Info: [ 78380, 78574) |* Info: [ 78574, 78768) |**** Info: [ 78768, 78962) |** Info: [ 78962, 79156) |**** Info: [ 79156, 79350) |*** Info: [ 79350, 79544) | Info: [ 79544, 79738) |*** Info: [ 79738, 79932) |** Info: [ 79932, 80126) |**** Info: [ 80126, 80320) |** Info: [ 80320, 80514) |**** Info: [ 80514, 80708) |* Info: [ 80708, 80902) |* Info: [ 80902, 81096) |** Info: [ 81096, 81290) |**** Info: [ 81290, 81484) |** Info: [ 81484, 81678) |*** Info: [ 81678, 81872) |**** Info: Checksum: 0xeb1890f4 Info: Routing.. Info: Setting up routing queue. Info: Routing 150 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 154 | 4 131 | 4 131 | 0| 0.01 0.01| Info: Routing complete. Info: Router1 time 0.01s Info: Checksum: 0xe0f8baec Info: Critical path report for clock 'clk_12mhz$SB_IO_IN_$glb_clk' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source blinky_c$D_IN_SB_LUT4_O_5_LC.O Info: 0.6 1.1 Net blinky_c$D_IN_SB_LUT4_O_5_I1[0] (11,10) -> (12,10) Info: Sink blinky_c$D_IN_SB_LUT4_O_1_I1_SB_LUT4_O_LC.I0 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 1.6 Source blinky_c$D_IN_SB_LUT4_O_1_I1_SB_LUT4_O_LC.O Info: 0.6 2.2 Net blinky_c$D_IN_SB_LUT4_O_1_I1[3] (12,10) -> (12,10) Info: Sink blinky_c$D_IN_SB_LUT4_O_22_I3_SB_LUT4_I1_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 2.5 Source blinky_c$D_IN_SB_LUT4_O_22_I3_SB_LUT4_I1_LC.O Info: 0.6 3.1 Net blinky_c$D_IN_SB_LUT4_O_22_I3_SB_LUT4_I1_O[2] (12,10) -> (12,11) Info: Sink blinky_c$D_IN_SB_LUT4_O_3_I1_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 3.4 Source blinky_c$D_IN_SB_LUT4_O_3_I1_SB_LUT4_O_LC.O Info: 0.6 4.0 Net blinky_c$D_IN_SB_LUT4_O_3_I1[2] (12,11) -> (12,11) Info: Sink blinky_d0_SB_DFFER_Q_E_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 4.3 Source blinky_d0_SB_DFFER_Q_E_SB_LUT4_O_LC.O Info: 0.6 4.9 Net blinky_d0_SB_DFFER_Q_E[0] (12,11) -> (11,10) Info: Sink blinky_c$D_IN_SB_LUT4_O_5_LC.I0 Info: Defined in: Info: ./env/81d7e933d4d2108980009dfc7bf4bbf17963858e/hdl/projects/icestick/mkBlinky.v:137.43-137.59 Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/arith_map.v:62.5-70.4 Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 5.3 Setup blinky_c$D_IN_SB_LUT4_O_5_LC.I0 Info: 2.4 ns logic, 2.9 ns routing Info: Critical path report for cross-domain path '' -> 'posedge clk_12mhz$SB_IO_IN_$glb_clk': Info: curr total Info: 0.0 0.0 Source RST_N$sb_io.D_IN_0 Info: 0.6 0.6 Net RST_N$SB_IO_IN (13,8) -> (12,9) Info: Sink RST_N_SB_LUT4_I3_LC.I3 Info: Defined in: Info: ./env/81d7e933d4d2108980009dfc7bf4bbf17963858e/hdl/projects/icestick/mkBlinky.v:65.10-65.15 Info: 0.3 0.9 Source RST_N_SB_LUT4_I3_LC.O Info: 0.3 1.2 Net RST_N_SB_LUT4_I3_O (12,9) -> (13,9) Info: Sink $gbuf_RST_N_SB_LUT4_I3_O_$glb_sr.USER_SIGNAL_TO_GLOBAL_BUFFER Info: 0.6 1.8 Source $gbuf_RST_N_SB_LUT4_I3_O_$glb_sr.GLOBAL_BUFFER_OUTPUT Info: 0.5 2.3 Net RST_N_SB_LUT4_I3_O_$glb_sr (13,9) -> (11,10) Info: Sink blinky_c$D_IN_SB_LUT4_O_5_LC.SR Info: 0.1 2.4 Setup blinky_c$D_IN_SB_LUT4_O_5_LC.SR Info: 1.0 ns logic, 1.4 ns routing Info: Critical path report for cross-domain path 'posedge clk_12mhz$SB_IO_IN_$glb_clk' -> '': Info: curr total Info: 0.5 0.5 Source blinky_d0_SB_LUT4_I3_LC.O Info: 0.6 1.1 Net blinky_d0 (12,12) -> (13,12) Info: Sink led[0]$sb_io.D_OUT_0 Info: Defined in: Info: ./env/81d7e933d4d2108980009dfc7bf4bbf17963858e/hdl/projects/icestick/mkBlinky.v:118.16-118.27 Info: 0.5 ns logic, 0.6 ns routing Info: Max frequency for clock 'clk_12mhz$SB_IO_IN_$glb_clk': 187.23 MHz (PASS at 12.00 MHz) Info: Max delay -> posedge clk_12mhz$SB_IO_IN_$glb_clk: 2.41 ns Info: Max delay posedge clk_12mhz$SB_IO_IN_$glb_clk -> : 1.13 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 77992, 78186) |******** Info: [ 78186, 78380) |* Info: [ 78380, 78574) |**** Info: [ 78574, 78768) |** Info: [ 78768, 78962) |**** Info: [ 78962, 79156) |** Info: [ 79156, 79350) |* Info: [ 79350, 79544) |*** Info: [ 79544, 79738) |** Info: [ 79738, 79932) |**** Info: [ 79932, 80126) |** Info: [ 80126, 80320) |**** Info: [ 80320, 80514) |* Info: [ 80514, 80708) |* Info: [ 80708, 80902) |**** Info: [ 80902, 81096) |** Info: [ 81096, 81290) |**** Info: [ 81290, 81484) |* Info: [ 81484, 81678) | Info: [ 81678, 81872) |**** Info: Program finished normally.