Info: constrained 'clk_12mhz' to bel 'X0/Y8/io1' Info: constrained 'RST_N' to bel 'X13/Y8/io0' Info: constrained 'led[0]' to bel 'X13/Y12/io1' Info: constrained 'led[1]' to bel 'X13/Y12/io0' Info: constrained 'led[2]' to bel 'X13/Y11/io1' Info: constrained 'led[3]' to bel 'X13/Y11/io0' Info: constrained 'led[4]' to bel 'X13/Y9/io1' Info: constrained 'ftdi_dcd_n' to bel 'X0/Y14/io1' Info: constrained 'ftdi_dsr_n' to bel 'X0/Y14/io0' Info: constrained 'ftdi_dtr_n' to bel 'X0/Y13/io1' Info: constrained 'ftdi_cts_n' to bel 'X0/Y13/io0' Info: constrained 'ftdi_rts_n' to bel 'X0/Y12/io1' Info: constrained 'ftdi_rxd' to bel 'X0/Y12/io0' Info: constrained 'ftdi_txd' to bel 'X0/Y11/io1' Info: constrained 'irda_txd' to bel 'X13/Y14/io1' Info: constrained 'irda_rxd' to bel 'X13/Y15/io0' Info: constrained 'irda_sd' to bel 'X13/Y15/io1' Info: Packing constants.. Info: Packing IOs.. Info: Packing LUT-FFs.. Info: 16 LCs used as LUT4 only Info: 41 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 32 LCs used as DFF only Info: Packing carries.. Info: 3 LCs used as CARRY only Info: Packing indirect carry+LUT pairs... Info: 1 LUTs merged into carry LCs Info: Packing RAMs.. Info: Placing PLLs.. Info: Packing special functions.. Info: Packing PLLs.. Info: Promoting globals.. Info: promoting clk_12mhz$SB_IO_IN (fanout 73) Info: promoting RST_N_SB_LUT4_I3_O [reset] (fanout 32) Info: Constraining chains... Info: 6 LCs used to legalise carry chains. Info: Checksum: 0x6d1c4b36 Info: Device utilisation: Info: ICESTORM_LC: 99/ 1280 7% Info: ICESTORM_RAM: 0/ 16 0% Info: SB_IO: 17/ 112 15% Info: SB_GB: 2/ 8 25% Info: ICESTORM_PLL: 0/ 1 0% Info: SB_WARMBOOT: 0/ 1 0% Info: Placed 17 cells based on constraints. Info: Creating initial analytic placement for 75 cells, random placement wirelen = 1141. Info: at initial placer iter 0, wirelen = 62 Info: at initial placer iter 1, wirelen = 57 Info: at initial placer iter 2, wirelen = 60 Info: at initial placer iter 3, wirelen = 61 Info: Running main analytical placer, max placement attempts per cell = 10000. Info: at iteration #1, type ICESTORM_LC: wirelen solved = 63, spread = 146, legal = 276; time = 0.00s Info: at iteration #1, type SB_GB: wirelen solved = 276, spread = 276, legal = 278; time = 0.00s Info: at iteration #1, type ALL: wirelen solved = 59, spread = 152, legal = 259; time = 0.00s Info: at iteration #2, type ICESTORM_LC: wirelen solved = 59, spread = 156, legal = 249; time = 0.00s Info: at iteration #2, type SB_GB: wirelen solved = 247, spread = 247, legal = 249; time = 0.00s Info: at iteration #2, type ALL: wirelen solved = 55, spread = 153, legal = 281; time = 0.00s Info: at iteration #3, type ICESTORM_LC: wirelen solved = 69, spread = 202, legal = 259; time = 0.00s Info: at iteration #3, type SB_GB: wirelen solved = 255, spread = 255, legal = 259; time = 0.00s Info: at iteration #3, type ALL: wirelen solved = 70, spread = 168, legal = 231; time = 0.02s Info: at iteration #4, type ICESTORM_LC: wirelen solved = 81, spread = 180, legal = 253; time = 0.00s Info: at iteration #4, type SB_GB: wirelen solved = 249, spread = 249, legal = 253; time = 0.00s Info: at iteration #4, type ALL: wirelen solved = 79, spread = 172, legal = 274; time = 0.00s Info: at iteration #5, type ICESTORM_LC: wirelen solved = 104, spread = 194, legal = 246; time = 0.00s Info: at iteration #5, type SB_GB: wirelen solved = 244, spread = 244, legal = 246; time = 0.00s Info: at iteration #5, type ALL: wirelen solved = 102, spread = 189, legal = 279; time = 0.00s Info: at iteration #6, type ICESTORM_LC: wirelen solved = 108, spread = 216, legal = 267; time = 0.00s Info: at iteration #6, type SB_GB: wirelen solved = 265, spread = 265, legal = 267; time = 0.00s Info: at iteration #6, type ALL: wirelen solved = 102, spread = 221, legal = 292; time = 0.02s Info: at iteration #7, type ICESTORM_LC: wirelen solved = 127, spread = 224, legal = 256; time = 0.00s Info: at iteration #7, type SB_GB: wirelen solved = 253, spread = 253, legal = 256; time = 0.00s Info: at iteration #7, type ALL: wirelen solved = 127, spread = 223, legal = 256; time = 0.00s Info: at iteration #8, type ICESTORM_LC: wirelen solved = 150, spread = 207, legal = 233; time = 0.00s Info: at iteration #8, type SB_GB: wirelen solved = 230, spread = 230, legal = 233; time = 0.00s Info: at iteration #8, type ALL: wirelen solved = 147, spread = 199, legal = 246; time = 0.00s Info: HeAP Placer Time: 0.14s Info: of which solving equations: 0.12s Info: of which spreading cells: 0.00s Info: of which strict legalisation: 0.01s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 16, wirelen = 231 Info: at iteration #5: temp = 0.000000, timing cost = 15, wirelen = 183 Info: at iteration #10: temp = 0.000000, timing cost = 23, wirelen = 169 Info: at iteration #13: temp = 0.000000, timing cost = 19, wirelen = 170 Info: SA placement time 0.03s Info: Max frequency for clock 'clk_12mhz$SB_IO_IN_$glb_clk': 190.44 MHz (PASS at 12.00 MHz) Info: Max delay -> posedge clk_12mhz$SB_IO_IN_$glb_clk: 3.83 ns Info: Max delay posedge clk_12mhz$SB_IO_IN_$glb_clk -> : 2.23 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 78082, 78284) |***** Info: [ 78284, 78486) |** Info: [ 78486, 78688) |********* Info: [ 78688, 78890) |********** Info: [ 78890, 79092) |* Info: [ 79092, 79294) |* Info: [ 79294, 79496) |* Info: [ 79496, 79698) |*** Info: [ 79698, 79900) |****************** Info: [ 79900, 80102) |**** Info: [ 80102, 80304) |*********** Info: [ 80304, 80506) |******* Info: [ 80506, 80708) |**** Info: [ 80708, 80910) |*** Info: [ 80910, 81112) |**** Info: [ 81112, 81314) |********** Info: [ 81314, 81516) |************** Info: [ 81516, 81718) |******* Info: [ 81718, 81920) |******************************************************** Info: [ 81920, 82122) |********** Info: Checksum: 0x5a6ec033 Info: Routing.. Info: Setting up routing queue. Info: Routing 286 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 298 | 12 266 | 12 266 | 0| 0.03 0.03| Info: Routing complete. Info: Router1 time 0.03s Info: Checksum: 0x212a2a90 Info: Critical path report for clock 'clk_12mhz$SB_IO_IN_$glb_clk' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source uart_txr_deserializer_bits_remaining_SB_DFFESS_Q_D_SB_LUT4_O_LC.O Info: 0.6 1.1 Net uart_txr_deserializer_bits_remaining[3] (9,6) -> (9,7) Info: Sink uart_txr_deserializer_bits_remaining$EN_SB_LUT4_O_I3_SB_LUT4_O_LC.I0 Info: Defined in: Info: ./env/57b3cc47447a55fadcafc5c309b688d7cddea188/hdl/projects/icestick/mkLoopbackUART.v:125.15-125.51 Info: 0.4 1.6 Source uart_txr_deserializer_bits_remaining$EN_SB_LUT4_O_I3_SB_LUT4_O_LC.O Info: 0.6 2.2 Net uart_txr_deserializer_bits_remaining$EN_SB_LUT4_O_I3[2] (9,7) -> (9,7) Info: Sink uart_txr_deserializer_bits_remaining$EN_SB_LUT4_O_I3_SB_LUT4_I3_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 2.5 Source uart_txr_deserializer_bits_remaining$EN_SB_LUT4_O_I3_SB_LUT4_I3_LC.O Info: 0.9 3.4 Net RST_N_SB_LUT4_I2_O[3] (9,7) -> (11,7) Info: Sink uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_E_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 3.7 Source uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_E_SB_LUT4_O_LC.O Info: 1.7 5.4 Net uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_E (11,7) -> (11,10) Info: Sink uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_DFFLC.CEN Info: 0.1 5.5 Setup uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_DFFLC.CEN Info: 1.7 ns logic, 3.8 ns routing Info: Critical path report for cross-domain path '' -> 'posedge clk_12mhz$SB_IO_IN_$glb_clk': Info: curr total Info: 0.0 0.0 Source RST_N$sb_io.D_IN_0 Info: 0.6 0.6 Net RST_N$SB_IO_IN (13,8) -> (12,8) Info: Sink RST_N_SB_LUT4_I2_LC.I2 Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2043.26-2043.29 Info: 0.4 1.0 Source RST_N_SB_LUT4_I2_LC.O Info: 0.6 1.6 Net RST_N_SB_LUT4_I2_O[2] (12,8) -> (11,7) Info: Sink uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_E_SB_LUT4_O_LC.I2 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 1.9 Source uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_E_SB_LUT4_O_LC.O Info: 1.7 3.6 Net uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_E (11,7) -> (11,10) Info: Sink uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_DFFLC.CEN Info: 0.1 3.7 Setup uart_txr_deserializer_out_byte.empty_reg_SB_DFFESR_Q_DFFLC.CEN Info: 0.9 ns logic, 2.8 ns routing Info: Critical path report for cross-domain path 'posedge clk_12mhz$SB_IO_IN_$glb_clk' -> '': Info: curr total Info: 0.5 0.5 Source uart_txr_tx_sync_SB_DFFE_Q_DFFLC.O Info: 1.7 2.2 Net ftdi_rxd$SB_IO_OUT (9,11) -> (0,12) Info: Sink ftdi_rxd$sb_io.D_OUT_0 Info: Defined in: Info: ./env/57b3cc47447a55fadcafc5c309b688d7cddea188/hdl/projects/icestick/mkLoopbackUART.v:191.7-191.23 Info: 0.5 ns logic, 1.7 ns routing Info: Max frequency for clock 'clk_12mhz$SB_IO_IN_$glb_clk': 182.78 MHz (PASS at 12.00 MHz) Info: Max delay -> posedge clk_12mhz$SB_IO_IN_$glb_clk: 3.71 ns Info: Max delay posedge clk_12mhz$SB_IO_IN_$glb_clk -> : 2.21 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 77862, 78063) |*********** Info: [ 78063, 78264) |** Info: [ 78264, 78465) |*********** Info: [ 78465, 78666) |* Info: [ 78666, 78867) |** Info: [ 78867, 79068) |* Info: [ 79068, 79269) |* Info: [ 79269, 79470) |** Info: [ 79470, 79671) |**** Info: [ 79671, 79872) |************ Info: [ 79872, 80073) |************* Info: [ 80073, 80274) |************* Info: [ 80274, 80475) |* Info: [ 80475, 80676) |***** Info: [ 80676, 80877) |*************** Info: [ 80877, 81078) |******* Info: [ 81078, 81279) |******** Info: [ 81279, 81480) |*************** Info: [ 81480, 81681) | Info: [ 81681, 81882) |******************************************************** Info: Program finished normally.