Info: constrained 'clk_50mhz' to bel 'X7/Y17/io0'
Info: constrained 'rst_nc' to bel 'X13/Y3/io1'
Info: constrained 'io1[0]' to bel 'X11/Y17/io0'
Info: constrained 'io1[1]' to bel 'X10/Y17/io0'
Info: constrained 'io1[2]' to bel 'X9/Y17/io0'
Info: constrained 'io1[3]' to bel 'X5/Y17/io0'
Info: constrained 'io1[4]' to bel 'X4/Y17/io0'
Info: constrained 'io1[5]' to bel 'X3/Y17/io0'
Info: constrained 'io2[0]' to bel 'X13/Y6/io0'
Info: constrained 'io2[1]' to bel 'X13/Y7/io1'
Info: constrained 'io2[2]' to bel 'X13/Y11/io1'
Info: constrained 'io2[3]' to bel 'X13/Y12/io1'
Info: constrained 'io2[4]' to bel 'X13/Y13/io1'
Info: constrained 'io2[5]' to bel 'X13/Y14/io0'
Info: constrained 'io3[0]' to bel 'X0/Y13/io1'
Info: constrained 'io3[1]' to bel 'X0/Y13/io0'
Info: constrained 'io3[2]' to bel 'X0/Y11/io0'
Info: constrained 'io3[3]' to bel 'X0/Y11/io1'
Info: constrained 'io3[4]' to bel 'X0/Y9/io1'
Info: constrained 'io3[5]' to bel 'X0/Y9/io0'
Info: constrained 'io3[6]' to bel 'X0/Y5/io0'
Info: constrained 'io3[7]' to bel 'X0/Y5/io1'
Info: constrained 'sw' to bel 'X13/Y4/io0'
Info: constrained 'led[0]' to bel 'X4/Y0/io0'
Info: constrained 'led[1]' to bel 'X6/Y0/io1'

Info: Packing constants..
Info: Packing IOs..
Info: Packing LUT-FFs..
Info:       15 LCs used as LUT4 only
Info:       27 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:        0 LCs used as DFF only
Info: Packing carries..
Info:        0 LCs used as CARRY only
Info: Packing indirect carry+LUT pairs...
Info:        0 LUTs merged into carry LCs
Info: Packing RAMs..
Info: Placing PLLs..
Info: Packing special functions..
Info: Packing PLLs..
Info: Promoting globals..
Info: promoting clk_50mhz$SB_IO_IN (fanout 27)
Info: promoting rst_nc_SB_LUT4_I3_O [reset] (fanout 27)
Info: Constraining chains...
Info:        1 LCs used to legalise carry chains.
Info: Checksum: 0x1b4dc327

Info: Device utilisation:
Info: 	         ICESTORM_LC:      45/   1280     3%
Info: 	        ICESTORM_RAM:       0/     16     0%
Info: 	               SB_IO:      25/    112    22%
Info: 	               SB_GB:       2/      8    25%
Info: 	        ICESTORM_PLL:       0/      1     0%
Info: 	         SB_WARMBOOT:       0/      1     0%

Info: Placed 25 cells based on constraints.
Info: Creating initial analytic placement for 22 cells, random placement wirelen = 729.
Info:     at initial placer iter 0, wirelen = 177
Info:     at initial placer iter 1, wirelen = 186
Info:     at initial placer iter 2, wirelen = 178
Info:     at initial placer iter 3, wirelen = 183
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ICESTORM_LC: wirelen solved = 178, spread = 210, legal = 258; time = 0.00s
Info:     at iteration #1, type SB_GB: wirelen solved = 257, spread = 257, legal = 264; time = 0.00s
Info:     at iteration #1, type ALL: wirelen solved = 182, spread = 212, legal = 257; time = 0.00s
Info:     at iteration #2, type ICESTORM_LC: wirelen solved = 166, spread = 215, legal = 246; time = 0.00s
Info:     at iteration #2, type SB_GB: wirelen solved = 242, spread = 242, legal = 246; time = 0.00s
Info:     at iteration #2, type ALL: wirelen solved = 159, spread = 208, legal = 249; time = 0.00s
Info:     at iteration #3, type ICESTORM_LC: wirelen solved = 161, spread = 196, legal = 235; time = 0.00s
Info:     at iteration #3, type SB_GB: wirelen solved = 228, spread = 228, legal = 236; time = 0.00s
Info:     at iteration #3, type ALL: wirelen solved = 158, spread = 196, legal = 240; time = 0.00s
Info:     at iteration #4, type ICESTORM_LC: wirelen solved = 164, spread = 211, legal = 225; time = 0.00s
Info:     at iteration #4, type SB_GB: wirelen solved = 218, spread = 218, legal = 225; time = 0.00s
Info:     at iteration #4, type ALL: wirelen solved = 157, spread = 206, legal = 219; time = 0.00s
Info:     at iteration #5, type ICESTORM_LC: wirelen solved = 160, spread = 198, legal = 217; time = 0.00s
Info:     at iteration #5, type SB_GB: wirelen solved = 210, spread = 210, legal = 217; time = 0.00s
Info:     at iteration #5, type ALL: wirelen solved = 155, spread = 193, legal = 226; time = 0.00s
Info:     at iteration #6, type ICESTORM_LC: wirelen solved = 168, spread = 199, legal = 220; time = 0.00s
Info:     at iteration #6, type SB_GB: wirelen solved = 216, spread = 216, legal = 220; time = 0.00s
Info:     at iteration #6, type ALL: wirelen solved = 157, spread = 193, legal = 216; time = 0.00s
Info:     at iteration #7, type ICESTORM_LC: wirelen solved = 170, spread = 201, legal = 227; time = 0.00s
Info:     at iteration #7, type SB_GB: wirelen solved = 220, spread = 220, legal = 228; time = 0.00s
Info:     at iteration #7, type ALL: wirelen solved = 158, spread = 233, legal = 248; time = 0.00s
Info:     at iteration #8, type ICESTORM_LC: wirelen solved = 166, spread = 211, legal = 216; time = 0.00s
Info:     at iteration #8, type SB_GB: wirelen solved = 214, spread = 214, legal = 216; time = 0.00s
Info:     at iteration #8, type ALL: wirelen solved = 158, spread = 207, legal = 217; time = 0.00s
Info:     at iteration #9, type ICESTORM_LC: wirelen solved = 164, spread = 200, legal = 227; time = 0.00s
Info:     at iteration #9, type SB_GB: wirelen solved = 225, spread = 225, legal = 227; time = 0.02s
Info:     at iteration #9, type ALL: wirelen solved = 157, spread = 197, legal = 235; time = 0.00s
Info:     at iteration #10, type ICESTORM_LC: wirelen solved = 164, spread = 203, legal = 214; time = 0.00s
Info:     at iteration #10, type SB_GB: wirelen solved = 207, spread = 207, legal = 214; time = 0.00s
Info:     at iteration #10, type ALL: wirelen solved = 156, spread = 195, legal = 236; time = 0.00s
Info:     at iteration #11, type ICESTORM_LC: wirelen solved = 170, spread = 200, legal = 221; time = 0.00s
Info:     at iteration #11, type SB_GB: wirelen solved = 219, spread = 219, legal = 221; time = 0.00s
Info:     at iteration #11, type ALL: wirelen solved = 167, spread = 202, legal = 231; time = 0.00s
Info: HeAP Placer Time: 0.08s
Info:   of which solving equations: 0.08s
Info:   of which spreading cells: 0.00s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 24, wirelen = 216
Info:   at iteration #3: temp = 0.000000, timing cost = 21, wirelen = 203 
Info: SA placement time 0.00s

Info: Max frequency for clock 'clk_50mhz$SB_IO_IN_$glb_clk': 126.95 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                             -> posedge clk_50mhz$SB_IO_IN_$glb_clk: 10.32 ns
Info: Max delay posedge clk_50mhz$SB_IO_IN_$glb_clk -> <async>                            : 3.70 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 12123,  12410) |******** 
Info: [ 12410,  12697) |** 
Info: [ 12697,  12984) |*** 
Info: [ 12984,  13271) |**** 
Info: [ 13271,  13558) |*** 
Info: [ 13558,  13845) |*** 
Info: [ 13845,  14132) |* 
Info: [ 14132,  14419) |*** 
Info: [ 14419,  14706) |** 
Info: [ 14706,  14993) |**** 
Info: [ 14993,  15280) |** 
Info: [ 15280,  15567) |**** 
Info: [ 15567,  15854) |* 
Info: [ 15854,  16141) |*** 
Info: [ 16141,  16428) |** 
Info: [ 16428,  16715) |*** 
Info: [ 16715,  17002) |*** 
Info: [ 17002,  17289) |**** 
Info: [ 17289,  17576) | 
Info: [ 17576,  17863) |**** 
Info: Checksum: 0xb1e4bb4d

Info: Routing..
Info: Setting up routing queue.
Info: Routing 185 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        194 |        8        165 |    8   165 |         0|       0.03       0.03|
Info: Routing complete.
Info: Router1 time 0.03s
Info: Checksum: 0x0d348e4f

Info: Critical path report for clock 'clk_50mhz$SB_IO_IN_$glb_clk' (posedge -> posedge):
Info: curr total
Info:  0.8  0.8  Source blinky_c$D_IN_SB_LUT4_O_11_LC.O
Info:  0.9  1.7    Net blinky_c$D_IN_SB_LUT4_O_8_I1[0] (2,6) -> (1,5)
Info:                Sink blinky_c$D_IN_SB_LUT4_O_3_I1_SB_LUT4_O_LC.I0
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.7  2.3  Source blinky_c$D_IN_SB_LUT4_O_3_I1_SB_LUT4_O_LC.O
Info:  0.9  3.2    Net blinky_c$D_IN_SB_LUT4_O_3_I1[3] (1,5) -> (1,6)
Info:                Sink blinky_c$D_IN_SB_LUT4_O_13_I1_SB_LUT4_O_1_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.5  3.7  Source blinky_c$D_IN_SB_LUT4_O_13_I1_SB_LUT4_O_1_LC.O
Info:  0.9  4.5    Net blinky_c$D_IN_SB_LUT4_O_13_I1[3] (1,6) -> (1,5)
Info:                Sink blinky_c$D_IN_SB_LUT4_O_17_I1_SB_LUT4_I1_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.5  5.0  Source blinky_c$D_IN_SB_LUT4_O_17_I1_SB_LUT4_I1_LC.O
Info:  0.9  5.9    Net blinky_c$D_IN_SB_LUT4_O_17_I1_SB_LUT4_I1_O[3] (1,5) -> (1,5)
Info:                Sink blinky_c$D_IN_SB_LUT4_O_17_I1_SB_LUT4_I1_O_SB_LUT4_I0_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.5  6.3  Source blinky_c$D_IN_SB_LUT4_O_17_I1_SB_LUT4_I1_O_SB_LUT4_I0_LC.O
Info:  1.9  8.2    Net blinky_d0_SB_DFFER_Q_E (1,5) -> (1,4)
Info:                Sink blinky_d0_SB_LUT4_I3_LC.CEN
Info:                Defined in:
Info:                  ./env/8fcfc6faa944b340c30b6ddfa660c4d4763db33d/hdl/projects/ignitionlet/mkSequencerBlinky.v:111.3-123.8
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/ff_map.v:14.63-14.116
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_sim.v:656.8-656.9
Info:  0.1  8.3  Setup blinky_d0_SB_LUT4_I3_LC.CEN
Info: 3.0 ns logic, 5.4 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_50mhz$SB_IO_IN_$glb_clk':
Info: curr total
Info:  0.0  0.0  Source io3[3]$sb_io.D_IN_0
Info:  1.9  1.9    Net io3[3]$SB_IO_IN (0,11) -> (1,9)
Info:                Sink sw_SB_LUT4_I0_I3_SB_LUT4_O_LC.I2
Info:                Defined in:
Info:                  ./env/8fcfc6faa944b340c30b6ddfa660c4d4763db33d/hdl/projects/ignitionlet/mkSequencerBlinky.v:56.18-56.21
Info:  0.6  2.4  Source sw_SB_LUT4_I0_I3_SB_LUT4_O_LC.O
Info:  1.9  4.3    Net sw_SB_LUT4_I0_I3[3] (1,9) -> (4,5)
Info:                Sink sw_SB_LUT4_I0_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.5  4.8  Source sw_SB_LUT4_I0_LC.O
Info:  2.4  7.2    Net sw_SB_LUT4_I0_O[2] (4,5) -> (6,12)
Info:                Sink sw_SB_LUT4_I0_O_SB_LUT4_I1_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.5  7.7  Source sw_SB_LUT4_I0_O_SB_LUT4_I1_LC.O
Info:  1.4  9.1    Net blinky_button_pressed_$whas_SB_LUT4_O_I2[3] (6,12) -> (6,15)
Info:                Sink blinky_button_pressed_$whas_SB_LUT4_O_LC.I3
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:  0.5  9.6  Setup blinky_button_pressed_$whas_SB_LUT4_O_LC.I3
Info: 2.0 ns logic, 7.6 ns routing

Info: Critical path report for cross-domain path 'posedge clk_50mhz$SB_IO_IN_$glb_clk' -> '<async>':
Info: curr total
Info:  0.8  0.8  Source blinky_button_pressed_$whas_SB_LUT4_O_LC.O
Info:  2.5  3.3    Net blinky_d1 (6,15) -> (6,0)
Info:                Sink led[1]$sb_io.D_OUT_0
Info:                Defined in:
Info:                  ./env/8fcfc6faa944b340c30b6ddfa660c4d4763db33d/hdl/projects/ignitionlet/mkSequencerBlinky.v:62.18-62.21
Info: 0.8 ns logic, 2.5 ns routing

Info: Max frequency for clock 'clk_50mhz$SB_IO_IN_$glb_clk': 119.92 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                             -> posedge clk_50mhz$SB_IO_IN_$glb_clk: 9.59 ns
Info: Max delay posedge clk_50mhz$SB_IO_IN_$glb_clk -> <async>                            : 3.25 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 11661,  11971) |** 
Info: [ 11971,  12281) |********* 
Info: [ 12281,  12591) |*** 
Info: [ 12591,  12901) |**** 
Info: [ 12901,  13211) |*** 
Info: [ 13211,  13521) |** 
Info: [ 13521,  13831) |*** 
Info: [ 13831,  14141) |** 
Info: [ 14141,  14451) |*** 
Info: [ 14451,  14761) |**** 
Info: [ 14761,  15071) |*** 
Info: [ 15071,  15381) |** 
Info: [ 15381,  15691) |*** 
Info: [ 15691,  16001) |** 
Info: [ 16001,  16311) |*** 
Info: [ 16311,  16621) |**** 
Info: [ 16621,  16931) |*** 
Info: [ 16931,  17241) | 
Info: [ 17241,  17551) | 
Info: [ 17551,  17861) |**** 

Info: Program finished normally.