Info: constrained 'clk_50mhz' to bel 'X7/Y17/io0' Info: constrained 'system_power_enable' to bel 'X4/Y0/io0' Info: constrained 'led[0]' to bel 'X6/Y0/io1' Info: constrained 'led[1]' to bel 'X6/Y0/io0' Info: constrained 'btn' to bel 'X13/Y4/io0' Info: constrained 'aux0_rx_p' to bel 'X0/Y11/io0' Info: constrained 'aux0_tx_p' to bel 'X0/Y13/io0' Info: constrained 'aux0_tx_n' to bel 'X0/Y13/io1' Info: constrained 'aux1_rx_p' to bel 'X0/Y5/io0' Info: constrained 'aux1_tx_p' to bel 'X0/Y9/io0' Info: constrained 'aux1_tx_n' to bel 'X0/Y9/io1' Info: constrained 'debug[0]' to bel 'X13/Y6/io0' Info: constrained 'debug[1]' to bel 'X13/Y7/io1' Info: constrained 'debug[2]' to bel 'X13/Y11/io1' Info: constrained 'debug[3]' to bel 'X13/Y12/io1' Info: constrained 'debug[4]' to bel 'X13/Y13/io1' Info: constrained 'debug[5]' to bel 'X13/Y14/io0' Info: constrained 'debug[6]' to bel 'X11/Y17/io0' Info: constrained 'debug[7]' to bel 'X10/Y17/io0' Info: constrained 'debug[8]' to bel 'X9/Y17/io0' Info: constrained 'debug[9]' to bel 'X5/Y17/io0' Info: constrained 'debug[10]' to bel 'X4/Y17/io0' Info: constrained 'debug[11]' to bel 'X3/Y17/io0' Info: Packing constants.. Info: Packing IOs.. Info: aux1_tx_n feeds SB_IO aux1_tx_n_io, removing $nextpnr_iobuf aux1_tx_n. Info: aux1_rx_p feeds SB_IO aux1_rx_p_io, removing $nextpnr_iobuf aux1_rx_p. Info: aux0_tx_p feeds SB_IO aux0_tx_p_io, removing $nextpnr_iobuf aux0_tx_p. Info: aux0_tx_n feeds SB_IO aux0_tx_n_io, removing $nextpnr_iobuf aux0_tx_n. Info: aux0_rx_p feeds SB_IO aux0_rx_p_io, removing $nextpnr_iobuf aux0_rx_p. Info: aux1_tx_p feeds SB_IO aux1_tx_p_io, removing $nextpnr_iobuf aux1_tx_p. Info: Packing LUT-FFs.. Info: 444 LCs used as LUT4 only Info: 185 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 138 LCs used as DFF only Info: Packing carries.. Info: 11 LCs used as CARRY only Info: Packing indirect carry+LUT pairs... Info: 11 LUTs merged into carry LCs Info: Packing RAMs.. Info: Placing PLLs.. Info: Packing special functions.. Info: Packing PLLs.. Info: Promoting globals.. Info: promoting clk_50mhz$SB_IO_IN (fanout 335) Info: promoting reset_sync$RST_SB_LUT4_I3_O [reset] (fanout 67) Info: promoting txr_serializer_bit_valid$EN [cen] (fanout 20) Info: promoting aux0_io_sampler_sample0_valid [cen] (fanout 19) Info: promoting aux1_io_sampler_sample0_valid [cen] (fanout 19) Info: Constraining chains... Info: 9 LCs used to legalise carry chains. Info: Checksum: 0x3e9faaca Info: Device utilisation: Info: ICESTORM_LC: 780/ 1280 60% Info: ICESTORM_RAM: 0/ 16 0% Info: SB_IO: 23/ 112 20% Info: SB_GB: 5/ 8 62% Info: ICESTORM_PLL: 0/ 1 0% Info: SB_WARMBOOT: 0/ 1 0% Info: Placed 23 cells based on constraints. Info: Creating initial analytic placement for 740 cells, random placement wirelen = 10359. Info: at initial placer iter 0, wirelen = 215 Info: at initial placer iter 1, wirelen = 212 Info: at initial placer iter 2, wirelen = 176 Info: at initial placer iter 3, wirelen = 197 Info: Running main analytical placer, max placement attempts per cell = 81608. Info: at iteration #1, type ALL: wirelen solved = 179, spread = 3045, legal = 3748; time = 0.03s Info: at iteration #2, type ALL: wirelen solved = 269, spread = 2572, legal = 3459; time = 0.03s Info: at iteration #3, type ALL: wirelen solved = 385, spread = 2346, legal = 3507; time = 0.03s Info: at iteration #4, type ALL: wirelen solved = 358, spread = 2014, legal = 3326; time = 0.03s Info: at iteration #5, type ALL: wirelen solved = 486, spread = 1945, legal = 2946; time = 0.04s Info: at iteration #6, type ALL: wirelen solved = 546, spread = 1917, legal = 2944; time = 0.05s Info: at iteration #7, type ALL: wirelen solved = 611, spread = 1890, legal = 2804; time = 0.05s Info: at iteration #8, type ALL: wirelen solved = 676, spread = 1936, legal = 2872; time = 0.04s Info: at iteration #9, type ALL: wirelen solved = 737, spread = 1885, legal = 2656; time = 0.04s Info: at iteration #10, type ALL: wirelen solved = 746, spread = 1813, legal = 2947; time = 0.04s Info: at iteration #11, type ALL: wirelen solved = 810, spread = 1888, legal = 2949; time = 0.04s Info: at iteration #12, type ALL: wirelen solved = 822, spread = 1878, legal = 2801; time = 0.03s Info: at iteration #13, type ALL: wirelen solved = 837, spread = 1823, legal = 2711; time = 0.02s Info: at iteration #14, type ALL: wirelen solved = 822, spread = 1978, legal = 2952; time = 0.03s Info: HeAP Placer Time: 0.76s Info: of which solving equations: 0.49s Info: of which spreading cells: 0.03s Info: of which strict legalisation: 0.11s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 224, wirelen = 2656 Info: at iteration #5: temp = 0.000000, timing cost = 167, wirelen = 2161 Info: at iteration #10: temp = 0.000000, timing cost = 216, wirelen = 1991 Info: at iteration #15: temp = 0.000000, timing cost = 321, wirelen = 1904 Info: at iteration #20: temp = 0.000000, timing cost = 341, wirelen = 1803 Info: at iteration #25: temp = 0.000000, timing cost = 293, wirelen = 1740 Info: at iteration #26: temp = 0.000000, timing cost = 293, wirelen = 1729 Info: SA placement time 0.69s Info: Max frequency for clock 'clk_50mhz$SB_IO_IN_$glb_clk': 84.25 MHz (PASS at 50.00 MHz) Info: Max delay posedge clk_50mhz$SB_IO_IN_$glb_clk -> : 3.44 ns Info: Slack histogram: Info: legend: * represents 2 endpoint(s) Info: + represents [1,2) endpoint(s) Info: [ 8130, 8636) |***+ Info: [ 8636, 9142) |**********+ Info: [ 9142, 9648) |************+ Info: [ 9648, 10154) |****************+ Info: [ 10154, 10660) |***********+ Info: [ 10660, 11166) |**********************************+ Info: [ 11166, 11672) |*************************************+ Info: [ 11672, 12178) |************************+ Info: [ 12178, 12684) |**************+ Info: [ 12684, 13190) |***************************+ Info: [ 13190, 13696) |******+ Info: [ 13696, 14202) |*************+ Info: [ 14202, 14708) |******************+ Info: [ 14708, 15214) |************+ Info: [ 15214, 15720) |*************+ Info: [ 15720, 16226) |************+ Info: [ 16226, 16732) |***************************************+ Info: [ 16732, 17238) |**************+ Info: [ 17238, 17744) |************************************************************ Info: [ 17744, 18250) |*****************************+ Info: Checksum: 0x398a1865 Info: Routing.. Info: Setting up routing queue. Info: Routing 2417 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 142 846 | 142 846 | 1591| 0.19 0.19| Info: 2000 | 414 1573 | 272 727 | 929| 0.11 0.30| Info: 3000 | 771 2193 | 357 620 | 331| 0.13 0.43| Info: 3425 | 854 2536 | 83 343 | 0| 0.07 0.49| Info: Routing complete. Info: Router1 time 0.49s Info: Checksum: 0xbed37534 Info: Critical path report for clock 'clk_50mhz$SB_IO_IN_$glb_clk' (posedge -> posedge): Info: curr total Info: 0.8 0.8 Source txr_tx_even_SB_DFFESS_Q_D_SB_LUT4_O_LC.O Info: 1.9 2.7 Net txr_tx_even (2,11) -> (5,10) Info: Sink txr_tx_idle_SB_LUT4_I1_1_I3_SB_LUT4_O_LC.I2 Info: Defined in: Info: ./env/311e21c9542d6ebe4576af19f0cca4f6784fd8b3/hdl/projects/ignitionlet/mkTransceiverDebugTop.v:477.7-477.18 Info: 0.6 3.2 Source txr_tx_idle_SB_LUT4_I1_1_I3_SB_LUT4_O_LC.O Info: 0.9 4.1 Net txr_tx_idle_SB_LUT4_I1_1_I3[2] (5,10) -> (4,10) Info: Sink txr_tx_idle_SB_LUT4_I1_1_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 4.6 Source txr_tx_idle_SB_LUT4_I1_1_LC.O Info: 0.9 5.4 Net txr_tx_idle_SB_LUT4_I1_1_O[1] (4,10) -> (4,11) Info: Sink txr_tx_idle_SB_LUT4_I1_1_O_SB_LUT4_I3_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 5.9 Source txr_tx_idle_SB_LUT4_I1_1_O_SB_LUT4_I3_LC.O Info: 0.9 6.8 Net txr_tx_idle_SB_LUT4_I1_1_O_SB_LUT4_I3_O[1] (4,11) -> (4,12) Info: Sink txr_tx_idle_SB_LUT4_I1_O_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 7.2 Source txr_tx_idle_SB_LUT4_I1_O_SB_LUT4_O_LC.O Info: 0.9 8.1 Net txr_tx_idle_SB_LUT4_I1_O[1] (4,12) -> (4,12) Info: Sink txr_tx_idle_SB_LUT4_I1_O_SB_LUT4_I2_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 8.6 Source txr_tx_idle_SB_LUT4_I1_O_SB_LUT4_I2_LC.O Info: 1.4 10.0 Net txr_tx_deparser_SB_DFF_Q_10_D_SB_LUT4_O_I1[3] (4,12) -> (4,14) Info: Sink txr_tx_phase_SB_DFFESR_Q_E_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.5 10.4 Source txr_tx_phase_SB_DFFESR_Q_E_SB_LUT4_O_LC.O Info: 2.4 12.8 Net txr_tx_phase_SB_DFFESR_Q_E (4,14) -> (4,15) Info: Sink txr_tx_phase_SB_DFFESR_Q_D_SB_LUT4_O_LC.CEN Info: 0.1 12.9 Setup txr_tx_phase_SB_DFFESR_Q_D_SB_LUT4_O_LC.CEN Info: 3.8 ns logic, 9.1 ns routing Info: Critical path report for cross-domain path 'posedge clk_50mhz$SB_IO_IN_$glb_clk' -> '': Info: curr total Info: 0.8 0.8 Source txr_rx_channels_0_locked_SB_LUT4_I1_LC.O Info: 3.0 3.8 Net debug[3]$SB_IO_OUT (11,2) -> (13,12) Info: Sink debug[3]$sb_io.D_OUT_0 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.8 ns logic, 3.0 ns routing Info: Max frequency for clock 'clk_50mhz$SB_IO_IN_$glb_clk': 77.38 MHz (PASS at 50.00 MHz) Info: Max delay posedge clk_50mhz$SB_IO_IN_$glb_clk -> : 3.77 ns Info: Slack histogram: Info: legend: * represents 2 endpoint(s) Info: + represents [1,2) endpoint(s) Info: [ 7076, 7634) |+ Info: [ 7634, 8192) |*+ Info: [ 8192, 8750) |*************+ Info: [ 8750, 9308) |**********+ Info: [ 9308, 9866) |*******************+ Info: [ 9866, 10424) |*************************+ Info: [ 10424, 10982) |*************************+ Info: [ 10982, 11540) |**************************************+ Info: [ 11540, 12098) |****************+ Info: [ 12098, 12656) |***********************************+ Info: [ 12656, 13214) |****+ Info: [ 13214, 13772) |******************************************+ Info: [ 13772, 14330) |****************************+ Info: [ 14330, 14888) |************************+ Info: [ 14888, 15446) |****************************+ Info: [ 15446, 16004) |*******************+ Info: [ 16004, 16562) |*************************+ Info: [ 16562, 17120) |*************************************+ Info: [ 17120, 17678) |************************************************************ Info: [ 17678, 18236) |****************************************************+ Info: Program finished normally.