Info: constraining clock net 'clk_12mhz' to 12.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      5377/83640     6%
Info:         logic LUTs:   4617/83640     5%
Info:         carry LUTs:    760/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:      2940/83640     3%

Info: Packing IOs..
Info: $aux1_tx$iobuf_i: aux1_tx_$_TBUF__Y.Y
Info: pin 'aux1_tx$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: $aux0_tx$iobuf_i: aux0_tx_$_TBUF__Y.Y
Info: pin 'aux0_tx$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X9/Y95/PIOB'.
Info: pin 'spi_csn$tr_io' constrained to Bel 'X13/Y95/PIOA'.
Info: pin 'spi_copi$tr_io' constrained to Bel 'X11/Y95/PIOB'.
Info: pin 'spi_cipo$tr_io' constrained to Bel 'X11/Y95/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X114/Y0/PIOA'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X116/Y0/PIOA'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X114/Y0/PIOB'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X116/Y0/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X119/Y0/PIOA'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X119/Y0/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X76/Y0/PIOA'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X76/Y0/PIOB'.
Info: pin 'design_reset_l$tr_io' constrained to Bel 'X18/Y95/PIOA'.
Info: pin 'debug$tr_io' constrained to Bel 'X63/Y0/PIOB'.
Info: pin 'clk_12mhz$tr_io' constrained to Bel 'X63/Y0/PIOA'.
Info: pin 'aux1_rx$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'aux0_rx$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     1692 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info:     Input frequency of PLL 'pll_pll.pll_i' is constrained to 12.0 MHz
Info:     Derived frequency constraint of 100.0 MHz for net pll_pll.CLKOP
Info:     Derived frequency constraint of 50.0 MHz for net controller_ignition_controllers__0_tx.CLK
Info:     Derived frequency constraint of inf MHz for net pll_pll.CLKOS2
Info:     Derived frequency constraint of inf MHz for net pll_pll.CLKOS3
Info: Promoting globals...
Info:     promoting clock net controller_ignition_controllers__0_tx.CLK to global network
Info: Checksum: 0xe263f15c

Info: Device utilisation:
Info: 	          TRELLIS_IO:      19/    365     5%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       1/    208     0%
Info: 	          MULT18X18D:       0/    156     0%
Info: 	              ALU54B:       0/     78     0%
Info: 	             EHXPLLL:       1/      4    25%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    224     0%
Info: 	            SIOLOGIC:       0/    141     0%
Info: 	                 GSR:       0/      1     0%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     14     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:    2940/  83640     3%
Info: 	        TRELLIS_COMB:    5665/  83640     6%
Info: 	        TRELLIS_RAMW:       0/  10455     0%

Info: Placed 20 cells based on constraints.
Info: Creating initial analytic placement for 5326 cells, random placement wirelen = 622273.
Info:     at initial placer iter 0, wirelen = 3457
Info:     at initial placer iter 1, wirelen = 2524
Info:     at initial placer iter 2, wirelen = 2520
Info:     at initial placer iter 3, wirelen = 2538
Info: Running main analytical placer, max placement attempts per cell = 9303141.
Info:     at iteration #1, type ALL: wirelen solved = 2333, spread = 53536, legal = 55538; time = 0.20s
Info:     at iteration #2, type ALL: wirelen solved = 6594, spread = 25365, legal = 28677; time = 0.15s
Info:     at iteration #3, type ALL: wirelen solved = 8544, spread = 21778, legal = 24825; time = 0.14s
Info:     at iteration #4, type ALL: wirelen solved = 9977, spread = 19951, legal = 23175; time = 0.13s
Info:     at iteration #5, type ALL: wirelen solved = 10409, spread = 19440, legal = 22104; time = 0.13s
Info:     at iteration #6, type ALL: wirelen solved = 11085, spread = 18828, legal = 21869; time = 0.13s
Info:     at iteration #7, type ALL: wirelen solved = 11633, spread = 19988, legal = 22281; time = 0.13s
Info:     at iteration #8, type ALL: wirelen solved = 12435, spread = 19496, legal = 21806; time = 0.12s
Info:     at iteration #9, type ALL: wirelen solved = 12469, spread = 18860, legal = 21416; time = 0.12s
Info:     at iteration #10, type ALL: wirelen solved = 12540, spread = 18483, legal = 21335; time = 0.12s
Info:     at iteration #11, type ALL: wirelen solved = 12816, spread = 18523, legal = 21336; time = 0.12s
Info:     at iteration #12, type ALL: wirelen solved = 13097, spread = 18412, legal = 21290; time = 0.12s
Info:     at iteration #13, type ALL: wirelen solved = 13131, spread = 18457, legal = 21420; time = 0.12s
Info:     at iteration #14, type ALL: wirelen solved = 13546, spread = 18263, legal = 21985; time = 0.13s
Info:     at iteration #15, type ALL: wirelen solved = 13426, spread = 18715, legal = 21842; time = 0.13s
Info:     at iteration #16, type ALL: wirelen solved = 13657, spread = 18478, legal = 21047; time = 0.12s
Info:     at iteration #17, type ALL: wirelen solved = 13833, spread = 18689, legal = 21748; time = 0.13s
Info:     at iteration #18, type ALL: wirelen solved = 14420, spread = 18787, legal = 21622; time = 0.13s
Info:     at iteration #19, type ALL: wirelen solved = 14561, spread = 18273, legal = 21338; time = 0.12s
Info:     at iteration #20, type ALL: wirelen solved = 14509, spread = 18962, legal = 21874; time = 0.12s
Info:     at iteration #21, type ALL: wirelen solved = 14885, spread = 18661, legal = 21387; time = 0.11s
Info: HeAP Placer Time: 4.29s
Info:   of which solving equations: 2.29s
Info:   of which spreading cells: 0.49s
Info:   of which strict legalisation: 0.34s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 704, wirelen = 21047
Info:   at iteration #5: temp = 0.000000, timing cost = 510, wirelen = 18598
Info:   at iteration #10: temp = 0.000000, timing cost = 693, wirelen = 17786
Info:   at iteration #15: temp = 0.000000, timing cost = 531, wirelen = 17358
Info:   at iteration #20: temp = 0.000000, timing cost = 500, wirelen = 17146
Info:   at iteration #25: temp = 0.000000, timing cost = 610, wirelen = 17081
Info:   at iteration #27: temp = 0.000000, timing cost = 490, wirelen = 17078 
Info: SA placement time 11.05s

Info: Max frequency for clock                           'clk_12mhz$TRELLIS_IO_IN': 1594.90 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$controller_ignition_controllers__0_tx.CLK': 155.26 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                                                   -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 4.13 ns
Info: Max delay <async>                                                   -> posedge clk_12mhz$TRELLIS_IO_IN                          : 5.40 ns
Info: Max delay posedge $glbnet$controller_ignition_controllers__0_tx.CLK -> <async>                                                  : 6.35 ns
Info: Max delay posedge clk_12mhz$TRELLIS_IO_IN                           -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 4.91 ns

Info: Slack histogram:
Info:  legend: * represents 54 endpoint(s)
Info:          + represents [1,54) endpoint(s)
Info: [ 13558,  17016) |***************************************************+
Info: [ 17016,  20474) |************************************************************ 
Info: [ 20474,  23932) | 
Info: [ 23932,  27390) | 
Info: [ 27390,  30848) | 
Info: [ 30848,  34306) | 
Info: [ 34306,  37764) | 
Info: [ 37764,  41222) | 
Info: [ 41222,  44680) | 
Info: [ 44680,  48138) | 
Info: [ 48138,  51596) | 
Info: [ 51596,  55054) | 
Info: [ 55054,  58512) | 
Info: [ 58512,  61970) | 
Info: [ 61970,  65428) | 
Info: [ 65428,  68886) | 
Info: [ 68886,  72344) | 
Info: [ 72344,  75802) | 
Info: [ 75802,  79260) | 
Info: [ 79260,  82718) |+
Info: Checksum: 0x1cdf09b2
Info: Routing globals...
Info:     routing clock net $glbnet$controller_ignition_controllers__0_tx.CLK using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 22550 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |       53        946 |   53   946 |     21611|       0.42       0.42|
Info:       2000 |      172       1827 |  119   881 |     20747|       0.19       0.61|
Info:       3000 |      305       2694 |  133   867 |     19894|       0.21       0.81|
Info:       4000 |      519       3480 |  214   786 |     19154|       0.21       1.03|
Info:       5000 |      653       4346 |  134   866 |     18317|       0.20       1.22|
Info:       6000 |      800       5199 |  147   853 |     17480|       0.19       1.42|
Info:       7000 |      963       6028 |  163   829 |     16679|       0.20       1.61|
Info:       8000 |     1103       6841 |  140   813 |     15847|       0.17       1.79|
Info:       9000 |     1254       7648 |  151   807 |     15013|       0.16       1.95|
Info:      10000 |     1416       8433 |  162   785 |     14186|       0.18       2.13|
Info:      11000 |     1570       9210 |  154   777 |     13357|       0.17       2.30|
Info:      12000 |     1755       9998 |  185   788 |     12575|       0.17       2.48|
Info:      13000 |     1888      10832 |  133   834 |     11729|       0.15       2.63|
Info:      14000 |     2052      11631 |  164   799 |     10913|       0.17       2.80|
Info:      15000 |     2190      12439 |  138   808 |     10064|       0.16       2.96|
Info:      16000 |     2305      13240 |  115   801 |      9187|       0.15       3.12|
Info:      17000 |     2464      14021 |  159   781 |      8357|       0.17       3.29|
Info:      18000 |     2620      14750 |  156   729 |      7531|       0.19       3.48|
Info:      19000 |     2782      15543 |  162   793 |      6707|       0.18       3.66|
Info:      20000 |     2954      16324 |  172   781 |      5891|       0.19       3.84|
Info:      21000 |     3087      17146 |  133   822 |      5043|       0.23       4.08|
Info:      22000 |     3304      17879 |  217   733 |      4353|       0.23       4.31|
Info:      23000 |     3441      18714 |  137   835 |      3504|       0.19       4.50|
Info:      24000 |     3651      19500 |  210   786 |      2781|       0.24       4.74|
Info:      25000 |     3805      20342 |  154   842 |      1952|       0.21       4.94|
Info:      26000 |     4018      21129 |  213   787 |      1249|       0.38       5.32|
Info:      27000 |     4200      21860 |  182   731 |       462|       0.22       5.54|
Info:      27467 |     4205      22185 |    5   325 |         0|       0.08       5.62|
Info: Routing complete.
Info: Router1 time 5.62s
Info: Checksum: 0x8602952d

Info: Critical path report for clock 'clk_12mhz$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source reset_sync.reset_hold_TRELLIS_FF_Q.Q
Info:  0.3  0.6    Net reset_sync.next_reset[1] (20,25) -> (20,25)
Info:                Sink reset_sync.reset_hold_TRELLIS_FF_DI.M
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:7404.23-7404.33
Info:  0.0  0.6  Setup reset_sync.reset_hold_TRELLIS_FF_DI.M
Info: 0.3 ns logic, 0.3 ns routing

Info: Critical path report for clock '$glbnet$controller_ignition_controllers__0_tx.CLK' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source spi_server_page_request_7_TRELLIS_FF_Q_3.Q
Info:  0.6  0.9    Net spi_server_page_request_7[15] (8,17) -> (8,17)
Info:                Sink controller_ignition_controllers__3_always_transmit_LUT4_C_Z_LUT4_Z_D_LUT4_Z.A
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  1.1  Source controller_ignition_controllers__3_always_transmit_LUT4_C_Z_LUT4_Z_D_LUT4_Z.F
Info:  0.8  1.8    Net controller_ignition_controllers__3_always_transmit_LUT4_C_Z_LUT4_Z_D[3] (8,17) -> (7,16)
Info:                Sink controller_ignition_controllers__3_always_transmit_LUT4_C_Z_LUT4_Z_D_LUT4_D_1.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  2.0  Source controller_ignition_controllers__3_always_transmit_LUT4_C_Z_LUT4_Z_D_LUT4_D_1.F
Info:  0.9  2.9    Net controller_ignition_controllers__3_always_transmit_LUT4_C_Z_LUT4_Z_D_LUT4_D_Z[2] (7,16) -> (2,15)
Info:                Sink IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1_B0_LUT4_Z.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  3.0  Source IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1_B0_LUT4_Z.F
Info:  0.7  3.8    Net IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1_B0 (2,15) -> (3,15)
Info:                Sink IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1$CCU2_COMB0.B
Info:  0.3  4.0  Source IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1$CCU2_COMB0.FCO
Info:  0.0  4.0    Net IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1$CCU2_FCI_INT (3,15) -> (3,15)
Info:                Sink IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1$CCU2_COMB1.FCI
Info:  0.0  4.0  Source IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1$CCU2_COMB1.FCO
Info:  0.0  4.0    Net IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0_1_COUT (3,15) -> (4,15)
Info:                Sink IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0$CCU2_COMB0.FCI
Info:                Defined in:
Info:                  ./env/6cd12454e733fdf05b47cb62cf1366e6f75f072e/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:22642.7-22643.65
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v:74.7-80.4
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:82.9-82.13
Info:  0.0  4.1  Source IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0$CCU2_COMB0.FCO
Info:  0.0  4.1    Net IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0$CCU2_FCI_INT (4,15) -> (4,15)
Info:                Sink IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0$CCU2_COMB1.FCI
Info:  0.2  4.3  Source IF_controller_ignition_controllers__3_n_status_ETC___d5279_CCU2C_S0$CCU2_COMB1.F
Info:  0.4  4.7    Net IF_controller_ignition_controllers__3_n_status_ETC___d5279[7] (4,15) -> (4,15)
Info:                Sink NOT_IF_controller_ignition_controllers__3_n_st_ETC___d5284_LUT4_Z.D
Info:                Defined in:
Info:                  ./env/6cd12454e733fdf05b47cb62cf1366e6f75f072e/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:5771.9-5771.67
Info:  0.1  4.9  Source NOT_IF_controller_ignition_controllers__3_n_st_ETC___d5284_LUT4_Z.F
Info:  0.4  5.3    Net NOT_IF_controller_ignition_controllers__3_n_st_ETC___d5284 (4,15) -> (3,15)
Info:                Sink controller_ignition_controllers__3_n_status_received_count_TRELLIS_FF_Q_5.LSR
Info:                Defined in:
Info:                  ./env/6cd12454e733fdf05b47cb62cf1366e6f75f072e/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:6277.8-6277.66
Info:  0.2  5.5  Setup controller_ignition_controllers__3_n_status_received_count_TRELLIS_FF_Q_5.LSR
Info: 1.6 ns logic, 3.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$controller_ignition_controllers__0_tx.CLK':
Info: curr total
Info:  0.0  0.0  Source spi_copi$tr_io.O
Info:  2.9  2.9    Net spi_copi$TRELLIS_IO_IN (11,95) -> (26,48)
Info:                Sink copi_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  ./env/6cd12454e733fdf05b47cb62cf1366e6f75f072e/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:73.10-73.18
Info:  0.0  2.9  Setup copi_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 2.9 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_12mhz$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source design_reset_l$tr_io.O
Info:  1.0  1.0    Net design_reset_l$TRELLIS_IO_IN (18,95) -> (20,91)
Info:                Sink design_reset_l_LUT4_D.D
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:7401.23-7401.29
Info:  0.1  1.1  Source design_reset_l_LUT4_D.F
Info:  3.1  4.2    Net design_reset_l_LUT4_D_Z (20,91) -> (20,25)
Info:                Sink reset_sync.reset_hold_TRELLIS_FF_Q.LSR
Info:  0.2  4.5  Setup reset_sync.reset_hold_TRELLIS_FF_Q.LSR
Info: 0.4 ns logic, 4.1 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$controller_ignition_controllers__0_tx.CLK' -> '<async>':
Info: curr total
Info:  0.3  0.3  Source led_r_TRELLIS_FF_Q_1.Q
Info:  4.1  4.4    Net led[6]$TRELLIS_IO_OUT (23,5) -> (116,0)
Info:                Sink led[6]$tr_io.I
Info:                Defined in:
Info:                  ./env/6cd12454e733fdf05b47cb62cf1366e6f75f072e/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:3407.15-3407.20
Info: 0.3 ns logic, 4.1 ns routing

Info: Critical path report for cross-domain path 'posedge clk_12mhz$TRELLIS_IO_IN' -> 'posedge $glbnet$controller_ignition_controllers__0_tx.CLK':
Info: curr total
Info:  0.3  0.3  Source reset_sync.reset_hold_TRELLIS_FF_DI.Q
Info:  1.8  2.1    Net controller_tofino_sequencer_delay_q_LUT4_B_Z_LUT4_A_Z[0] (20,25) -> (40,15)
Info:                Sink controller_tofino_sequencer_tofino2_power_up_seq_start_reg$D_IN_LUT4_D_Z_LUT4_Z.B
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  2.2  Source controller_tofino_sequencer_tofino2_power_up_seq_start_reg$D_IN_LUT4_D_Z_LUT4_Z.F
Info:  0.7  2.9    Net controller_tofino_sequencer_delay_q_LUT4_B_D_LUT4_D_Z[3] (40,15) -> (43,16)
Info:                Sink controller_tofino_sequencer_delay_q_LUT4_C_1_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_3_D1_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.1  Source controller_tofino_sequencer_delay_q_LUT4_C_1_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_3_D1_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.0  3.1    Net controller_tofino_sequencer_delay_q_LUT4_C_1_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_3_D1 (43,16) -> (43,16)
Info:                Sink controller_tofino_sequencer_delay_q_LUT4_C_1_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_3_D1_PFUMX_Z_ALUT_LUT4_Z.FXB
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.38-141.40
Info:  0.1  3.2  Source controller_tofino_sequencer_delay_q_LUT4_C_1_Z_LUT4_B_Z_PFUMX_ALUT_Z_L6MUX21_Z_3_D1_PFUMX_Z_ALUT_LUT4_Z.OFX
Info:  0.4  3.6    Net controller_tofino_sequencer_delay_q_LUT4_C_1_Z_LUT4_B_Z_PFUMX_ALUT_Z[11] (43,16) -> (44,16)
Info:                Sink controller_tofino_sequencer_tofino2_power_up_seq_state_mkFSMstate_TRELLIS_FF_Q_11.M
Info:  0.0  3.6  Setup controller_tofino_sequencer_tofino2_power_up_seq_state_mkFSMstate_TRELLIS_FF_Q_11.M
Info: 0.7 ns logic, 2.9 ns routing

Info: Max frequency for clock                           'clk_12mhz$TRELLIS_IO_IN': 1694.92 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$controller_ignition_controllers__0_tx.CLK': 182.02 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                                                   -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 2.91 ns
Info: Max delay <async>                                                   -> posedge clk_12mhz$TRELLIS_IO_IN                          : 4.46 ns
Info: Max delay posedge $glbnet$controller_ignition_controllers__0_tx.CLK -> <async>                                                  : 4.43 ns
Info: Max delay posedge clk_12mhz$TRELLIS_IO_IN                           -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 3.63 ns

Info: Slack histogram:
Info:  legend: * represents 65 endpoint(s)
Info:          + represents [1,65) endpoint(s)
Info: [ 14505,  17917) |************************************************************ 
Info: [ 17917,  21329) |********************************+
Info: [ 21329,  24741) | 
Info: [ 24741,  28153) | 
Info: [ 28153,  31565) | 
Info: [ 31565,  34977) | 
Info: [ 34977,  38389) | 
Info: [ 38389,  41801) | 
Info: [ 41801,  45213) | 
Info: [ 45213,  48625) | 
Info: [ 48625,  52037) | 
Info: [ 52037,  55449) | 
Info: [ 55449,  58861) | 
Info: [ 58861,  62273) | 
Info: [ 62273,  65685) | 
Info: [ 65685,  69097) | 
Info: [ 69097,  72509) | 
Info: [ 72509,  75921) | 
Info: [ 75921,  79333) | 
Info: [ 79333,  82745) |+

Info: Program finished normally.