Info: constraining clock net 'clk_50m_fpga_refclk' to 50.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 25596/43848 58% Info: logic LUTs: 23624/43848 53% Info: carry LUTs: 1972/43848 4% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 15068/43848 34% Info: Packing IOs.. Info: $rsw_s9_aux_dc_p$iobuf_i: rsw_s9_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s9_aux_dc_p$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: $rsw_s8_aux_dc_p$iobuf_i: rsw_s8_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s8_aux_dc_p$tr_io' constrained to Bel 'X90/Y44/PIOA'. Info: $rsw_s7_aux_dc_p$iobuf_i: rsw_s7_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s7_aux_dc_p$tr_io' constrained to Bel 'X90/Y50/PIOA'. Info: $rsw_s6_aux_dc_p$iobuf_i: rsw_s6_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s6_aux_dc_p$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: $rsw_s5_aux_dc_p$iobuf_i: rsw_s5_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s5_aux_dc_p$tr_io' constrained to Bel 'X90/Y62/PIOA'. Info: $rsw_s4_aux_dc_p$iobuf_i: rsw_s4_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s4_aux_dc_p$tr_io' constrained to Bel 'X90/Y47/PIOA'. Info: $rsw_s3_aux_dc_p$iobuf_i: rsw_s3_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s3_aux_dc_p$tr_io' constrained to Bel 'X90/Y65/PIOA'. Info: $rsw_s31_aux_dc_p$iobuf_i: rsw_s31_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s31_aux_dc_p$tr_io' constrained to Bel 'X0/Y56/PIOA'. Info: $rsw_s30_aux_dc_p$iobuf_i: rsw_s30_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s30_aux_dc_p$tr_io' constrained to Bel 'X0/Y53/PIOA'. Info: $rsw_s2_aux_dc_p$iobuf_i: rsw_s2_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s2_aux_dc_p$tr_io' constrained to Bel 'X90/Y68/PIOA'. Info: $rsw_s29_aux_dc_p$iobuf_i: rsw_s29_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s29_aux_dc_p$tr_io' constrained to Bel 'X0/Y68/PIOA'. Info: $rsw_s28_aux_dc_p$iobuf_i: rsw_s28_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s28_aux_dc_p$tr_io' constrained to Bel 'X0/Y65/PIOA'. Info: $rsw_s27_aux_dc_p$iobuf_i: rsw_s27_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s27_aux_dc_p$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: $rsw_s26_aux_dc_p$iobuf_i: rsw_s26_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s26_aux_dc_p$tr_io' constrained to Bel 'X0/Y62/PIOA'. Info: $rsw_s25_aux_dc_p$iobuf_i: rsw_s25_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s25_aux_dc_p$tr_io' constrained to Bel 'X0/Y50/PIOA'. Info: $rsw_s24_aux_dc_p$iobuf_i: rsw_s24_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s24_aux_dc_p$tr_io' constrained to Bel 'X0/Y47/PIOA'. Info: $rsw_s23_aux_dc_p$iobuf_i: rsw_s23_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s23_aux_dc_p$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $rsw_s22_aux_dc_p$iobuf_i: rsw_s22_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s22_aux_dc_p$tr_io' constrained to Bel 'X0/Y41/PIOA'. Info: $rsw_s21_aux_dc_p$iobuf_i: rsw_s21_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s21_aux_dc_p$tr_io' constrained to Bel 'X0/Y38/PIOA'. Info: $rsw_s20_aux_dc_p$iobuf_i: rsw_s20_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s20_aux_dc_p$tr_io' constrained to Bel 'X0/Y35/PIOA'. Info: $rsw_s1_aux_dc_p$iobuf_i: rsw_s1_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s1_aux_dc_p$tr_io' constrained to Bel 'X90/Y53/PIOA'. Info: $rsw_s19_aux_dc_p$iobuf_i: rsw_s19_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s19_aux_dc_p$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: $rsw_s18_aux_dc_p$iobuf_i: rsw_s18_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s18_aux_dc_p$tr_io' constrained to Bel 'X90/Y35/PIOA'. Info: $rsw_s17_aux_dc_p$iobuf_i: rsw_s17_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s17_aux_dc_p$tr_io' constrained to Bel 'X90/Y38/PIOA'. Info: $rsw_s16_aux_dc_p$iobuf_i: rsw_s16_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s16_aux_dc_p$tr_io' constrained to Bel 'X90/Y41/PIOA'. Info: $rsw_s15_aux_dc_p$iobuf_i: rsw_s15_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s15_aux_dc_p$tr_io' constrained to Bel 'X90/Y11/PIOA'. Info: $rsw_s14_aux_dc_p$iobuf_i: rsw_s14_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s14_aux_dc_p$tr_io' constrained to Bel 'X90/Y14/PIOA'. Info: $rsw_s13_aux_dc_p$iobuf_i: rsw_s13_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s13_aux_dc_p$tr_io' constrained to Bel 'X90/Y17/PIOA'. Info: $rsw_s12_aux_dc_p$iobuf_i: rsw_s12_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s12_aux_dc_p$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: $rsw_s11_aux_dc_p$iobuf_i: rsw_s11_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s11_aux_dc_p$tr_io' constrained to Bel 'X90/Y23/PIOA'. Info: $rsw_s10_aux_dc_p$iobuf_i: rsw_s10_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s10_aux_dc_p$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: $rsw_s0_aux_dc_p$iobuf_i: rsw_s0_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s0_aux_dc_p$tr_io' constrained to Bel 'X90/Y56/PIOA'. Info: $ignition_ctrl_to_rsw_b_dc_p$iobuf_i: ignition_ctrl_to_rsw_b_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_rsw_b_dc_p$tr_io' constrained to Bel 'X0/Y17/PIOA'. Info: $ignition_ctrl_to_psc1_dc_p$iobuf_i: ignition_ctrl_to_psc1_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc1_dc_p$tr_io' constrained to Bel 'X0/Y14/PIOA'. Info: $ignition_ctrl_to_psc0_dc_p$iobuf_i: ignition_ctrl_to_psc0_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc0_dc_p$tr_io' constrained to Bel 'X0/Y11/PIOA'. Info: $i2c_fpga_to_tf_sda$iobuf_i: i2c_fpga_to_tf_sda_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_sda$tr_io' constrained to Bel 'X69/Y0/PIOA'. Info: $i2c_fpga_to_tf_scl$iobuf_i: i2c_fpga_to_tf_scl_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_scl$tr_io' constrained to Bel 'X51/Y0/PIOB'. Info: pin 'vr_v1p0_mgmt_to_fpga_pg$tr_io' constrained to Bel 'X85/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_vrhot_l$tr_io' constrained to Bel 'X53/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vddt_pg$tr_io' constrained to Bel 'X47/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vdda15_pg$tr_io' constrained to Bel 'X47/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_fault$tr_io' constrained to Bel 'X27/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_vrhot_l$tr_io' constrained to Bel 'X58/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_pg$tr_io' constrained to Bel 'X58/Y0/PIOB'. Info: pin 'vr_tf_vddcore_to_fpga_fault$tr_io' constrained to Bel 'X31/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vr_hot_l$tr_io' constrained to Bel 'X53/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdda1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdd1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOA'. Info: pin 'vr_tf_v1p8_to_fpga_fault$tr_io' constrained to Bel 'X13/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[2]$tr_io' constrained to Bel 'X83/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[1]$tr_io' constrained to Bel 'X83/Y0/PIOA'. Info: pin 'tf_to_fpga_vid[0]$tr_io' constrained to Bel 'X80/Y0/PIOB'. Info: pin 'tf_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOB'. Info: pin 'tf_pg_led$tr_io' constrained to Bel 'X38/Y0/PIOB'. Info: pin 'spi_sp_to_fpga_sck$tr_io' constrained to Bel 'X18/Y71/PIOA'. Info: pin 'spi_sp_to_fpga_mosi$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_miso_r$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_cs1_l$tr_io' constrained to Bel 'X13/Y71/PIOB'. Info: pin 'sp_to_fpga_design_reset_l$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 's9_rsw_aux_p$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 's8_rsw_aux_p$tr_io' constrained to Bel 'X90/Y44/PIOC'. Info: pin 's7_rsw_aux_p$tr_io' constrained to Bel 'X90/Y50/PIOC'. Info: pin 's6_rsw_aux_p$tr_io' constrained to Bel 'X90/Y59/PIOC'. Info: pin 's5_rsw_aux_p$tr_io' constrained to Bel 'X90/Y62/PIOC'. Info: pin 's4_rsw_aux_p$tr_io' constrained to Bel 'X90/Y47/PIOC'. Info: pin 's3_rsw_aux_p$tr_io' constrained to Bel 'X90/Y65/PIOC'. Info: pin 's31_rsw_aux_p$tr_io' constrained to Bel 'X0/Y56/PIOC'. Info: pin 's30_rsw_aux_p$tr_io' constrained to Bel 'X0/Y53/PIOC'. Info: pin 's2_rsw_aux_p$tr_io' constrained to Bel 'X90/Y68/PIOC'. Info: pin 's29_rsw_aux_p$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: pin 's28_rsw_aux_p$tr_io' constrained to Bel 'X0/Y65/PIOC'. Info: pin 's27_rsw_aux_p$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 's26_rsw_aux_p$tr_io' constrained to Bel 'X0/Y62/PIOC'. Info: pin 's25_rsw_aux_p$tr_io' constrained to Bel 'X0/Y50/PIOC'. Info: pin 's24_rsw_aux_p$tr_io' constrained to Bel 'X0/Y47/PIOC'. Info: pin 's23_rsw_aux_p$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 's22_rsw_aux_p$tr_io' constrained to Bel 'X0/Y41/PIOC'. Info: pin 's21_rsw_aux_p$tr_io' constrained to Bel 'X0/Y38/PIOC'. Info: pin 's20_rsw_aux_p$tr_io' constrained to Bel 'X0/Y35/PIOC'. Info: pin 's1_rsw_aux_p$tr_io' constrained to Bel 'X90/Y53/PIOC'. Info: pin 's19_rsw_aux_p$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: pin 's18_rsw_aux_p$tr_io' constrained to Bel 'X90/Y35/PIOC'. Info: pin 's17_rsw_aux_p$tr_io' constrained to Bel 'X90/Y38/PIOC'. Info: pin 's16_rsw_aux_p$tr_io' constrained to Bel 'X90/Y41/PIOC'. Info: pin 's15_rsw_aux_p$tr_io' constrained to Bel 'X90/Y11/PIOC'. Info: pin 's14_rsw_aux_p$tr_io' constrained to Bel 'X90/Y14/PIOC'. Info: pin 's13_rsw_aux_p$tr_io' constrained to Bel 'X90/Y17/PIOC'. Info: pin 's12_rsw_aux_p$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 's11_rsw_aux_p$tr_io' constrained to Bel 'X90/Y23/PIOC'. Info: pin 's10_rsw_aux_p$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 's0_rsw_aux_p$tr_io' constrained to Bel 'X90/Y56/PIOC'. Info: pin 'pcie_host_to_fpga_perst$tr_io' constrained to Bel 'X9/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_pwrflt$tr_io' constrained to Bel 'X4/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_prsnt_l$tr_io' constrained to Bel 'X4/Y0/PIOA'. Info: pin 'mgmt_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_mgmt_pg$tr_io' constrained to Bel 'X44/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p2_mgmt_pg$tr_io' constrained to Bel 'X49/Y0/PIOB'. Info: pin 'ldo_to_fpga_v0p75_tf_pcie_pg$tr_io' constrained to Bel 'X42/Y0/PIOB'. Info: pin 'ldo_to_fpga_smu_pg$tr_io' constrained to Bel 'X15/Y0/PIOA'. Info: pin 'ignition_rsw_b_to_ctrl_p$tr_io' constrained to Bel 'X0/Y17/PIOC'. Info: pin 'ignition_psc1_to_ctrl_p$tr_io' constrained to Bel 'X0/Y14/PIOC'. Info: pin 'ignition_psc0_to_ctrl_p$tr_io' constrained to Bel 'X0/Y11/PIOC'. Info: pin 'front_io_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y26/PIOD'. Info: pin 'fpga_to_vr_v1p0_mgmt_en$tr_io' constrained to Bel 'X85/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vddx_en$tr_io' constrained to Bel 'X27/Y0/PIOB'. Info: pin 'fpga_to_vr_tf_vddcore_en$tr_io' constrained to Bel 'X33/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdda1p8_en$tr_io' constrained to Bel 'X20/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdd1p8_en$tr_io' constrained to Bel 'X18/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[3]$tr_io' constrained to Bel 'X76/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[2]$tr_io' constrained to Bel 'X78/Y0/PIOA'. Info: pin 'fpga_to_tf_test_jtsel[1]$tr_io' constrained to Bel 'X78/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[0]$tr_io' constrained to Bel 'X80/Y0/PIOA'. Info: pin 'fpga_to_tf_test_core_tap_l$tr_io' constrained to Bel 'X76/Y0/PIOA'. Info: pin 'fpga_to_tf_pwron_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOB'. Info: pin 'fpga_to_tf_pcie_rst_l$tr_io' constrained to Bel 'X71/Y0/PIOB'. Info: pin 'fpga_to_tf_core_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOA'. Info: pin 'fpga_to_smu_tf_clk_en_l$tr_io' constrained to Bel 'X20/Y0/PIOB'. Info: pin 'fpga_to_smu_reset_l$tr_io' constrained to Bel 'X31/Y0/PIOA'. Info: pin 'fpga_to_smu_mgmt_clk_en_l$tr_io' constrained to Bel 'X38/Y0/PIOA'. Info: pin 'fpga_to_phy4_reset_l$tr_io' constrained to Bel 'X0/Y29/PIOB'. Info: pin 'fpga_to_mgmt_reset_l$tr_io' constrained to Bel 'X29/Y0/PIOB'. Info: pin 'fpga_to_ldo_v2p5_mgmt_en$tr_io' constrained to Bel 'X44/Y0/PIOA'. Info: pin 'fpga_to_ldo_v1p2_mgmt_en$tr_io' constrained to Bel 'X49/Y0/PIOA'. Info: pin 'fpga_to_ldo_v0p75_tf_pcie_en$tr_io' constrained to Bel 'X42/Y0/PIOA'. Info: pin 'fpga_to_ldo_smu_en$tr_io' constrained to Bel 'X15/Y0/PIOB'. Info: pin 'fpga_to_front_io_hsc_en$tr_io' constrained to Bel 'X0/Y26/PIOC'. Info: pin 'fpga_to_fan3_led_l$tr_io' constrained to Bel 'X29/Y0/PIOA'. Info: pin 'fpga_to_fan3_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: pin 'fpga_to_fan2_led_l$tr_io' constrained to Bel 'X22/Y0/PIOA'. Info: pin 'fpga_to_fan2_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: pin 'fpga_to_fan1_led_l$tr_io' constrained to Bel 'X18/Y0/PIOA'. Info: pin 'fpga_to_fan1_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOA'. Info: pin 'fpga_to_fan0_led_l$tr_io' constrained to Bel 'X13/Y0/PIOA'. Info: pin 'fpga_to_fan0_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOC'. Info: pin 'fpga_led0$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'fpga_debug1$tr_io' constrained to Bel 'X33/Y0/PIOB'. Info: pin 'fpga_debug0$tr_io' constrained to Bel 'X36/Y0/PIOB'. Info: pin 'fan3_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOB'. Info: pin 'fan3_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOB'. Info: pin 'fan2_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOA'. Info: pin 'fan2_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOD'. Info: pin 'fan1_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOD'. Info: pin 'fan1_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOB'. Info: pin 'fan0_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOC'. Info: pin 'fan0_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOD'. Info: pin 'clk_50m_fpga_refclk$tr_io' constrained to Bel 'X36/Y0/PIOA'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 7297 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk_50m_fpga_refclk$TRELLIS_IO_IN to global network Info: Checksum: 0x045cfe53 Info: Device utilisation: Info: TRELLIS_IO: 146/ 245 59% Info: DCCA: 1/ 56 1% Info: DP16KD: 2/ 108 1% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 15068/ 43848 34% Info: TRELLIS_COMB: 26671/ 43848 60% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 146 cells based on constraints. Info: Creating initial analytic placement for 29016 cells, random placement wirelen = 2329894. Info: at initial placer iter 0, wirelen = 26190 Info: at initial placer iter 1, wirelen = 16910 Info: at initial placer iter 2, wirelen = 15733 Info: at initial placer iter 3, wirelen = 16079 Info: Running main analytical placer, max placement attempts per cell = 219325568. Info: at iteration #1, type ALL: wirelen solved = 15973, spread = 285387, legal = 309337; time = 1.54s Info: at iteration #2, type ALL: wirelen solved = 53889, spread = 149077, legal = 166533; time = 0.95s Info: at iteration #3, type ALL: wirelen solved = 66695, spread = 125955, legal = 143711; time = 0.90s Info: at iteration #4, type ALL: wirelen solved = 71641, spread = 116336, legal = 134355; time = 0.89s Info: at iteration #5, type ALL: wirelen solved = 74834, spread = 112432, legal = 130749; time = 0.88s Info: at iteration #6, type ALL: wirelen solved = 77874, spread = 109723, legal = 127535; time = 0.88s Info: at iteration #7, type ALL: wirelen solved = 79446, spread = 108148, legal = 125382; time = 0.88s Info: at iteration #8, type ALL: wirelen solved = 81165, spread = 106630, legal = 123744; time = 0.87s Info: at iteration #9, type ALL: wirelen solved = 82765, spread = 105368, legal = 123232; time = 0.85s Info: at iteration #10, type ALL: wirelen solved = 84108, spread = 115652, legal = 126280; time = 0.83s Info: at iteration #11, type ALL: wirelen solved = 90783, spread = 113001, legal = 124318; time = 0.82s Info: at iteration #12, type ALL: wirelen solved = 91428, spread = 112315, legal = 124045; time = 0.84s Info: at iteration #13, type ALL: wirelen solved = 91547, spread = 113289, legal = 124715; time = 0.82s Info: at iteration #14, type ALL: wirelen solved = 93254, spread = 111966, legal = 122726; time = 0.82s Info: at iteration #15, type ALL: wirelen solved = 93473, spread = 111094, legal = 122275; time = 0.82s Info: at iteration #16, type ALL: wirelen solved = 93343, spread = 112131, legal = 123964; time = 0.80s Info: at iteration #17, type ALL: wirelen solved = 93857, spread = 113783, legal = 125750; time = 0.82s Info: at iteration #18, type ALL: wirelen solved = 95369, spread = 113623, legal = 124582; time = 0.81s Info: at iteration #19, type ALL: wirelen solved = 96178, spread = 114740, legal = 124767; time = 0.80s Info: at iteration #20, type ALL: wirelen solved = 96627, spread = 113630, legal = 124811; time = 0.79s Info: HeAP Placer Time: 26.44s Info: of which solving equations: 14.00s Info: of which spreading cells: 3.62s Info: of which strict legalisation: 2.55s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 1983, wirelen = 122275 Info: at iteration #5: temp = 0.000000, timing cost = 2413, wirelen = 109604 Info: at iteration #10: temp = 0.000000, timing cost = 1612, wirelen = 106038 Info: at iteration #15: temp = 0.000000, timing cost = 1351, wirelen = 103993 Info: at iteration #20: temp = 0.000000, timing cost = 2066, wirelen = 103344 Info: at iteration #25: temp = 0.000000, timing cost = 1538, wirelen = 103117 Info: at iteration #30: temp = 0.000000, timing cost = 1880, wirelen = 102993 Info: at iteration #30: temp = 0.000000, timing cost = 1844, wirelen = 103005 Info: SA placement time 76.61s Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 64.01 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 5.06 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 8.68 ns Info: Slack histogram: Info: legend: * represents 74 endpoint(s) Info: + represents [1,74) endpoint(s) Info: [ 4378, 5122) |+ Info: [ 5122, 5866) |+ Info: [ 5866, 6610) |**+ Info: [ 6610, 7354) |*****+ Info: [ 7354, 8098) |*********+ Info: [ 8098, 8842) |********+ Info: [ 8842, 9586) |**********+ Info: [ 9586, 10330) |************+ Info: [ 10330, 11074) |***************+ Info: [ 11074, 11818) |*********************+ Info: [ 11818, 12562) |***********************+ Info: [ 12562, 13306) |***************************+ Info: [ 13306, 14050) |***********************************+ Info: [ 14050, 14794) |***********************************+ Info: [ 14794, 15538) |**************************************+ Info: [ 15538, 16282) |****************************************+ Info: [ 16282, 17026) |**************************************+ Info: [ 17026, 17770) |*******************************+ Info: [ 17770, 18514) |**************+ Info: [ 18514, 19258) |************************************************************ Info: Checksum: 0x9271677c Info: Routing globals... Info: routing clock net $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 109281 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 8 991 | 8 991 | 108299| 1.62 1.62| Info: 2000 | 51 1948 | 43 957 | 107356| 0.25 1.87| Info: 3000 | 133 2866 | 82 918 | 106509| 0.25 2.12| Info: 4000 | 222 3777 | 89 911 | 105630| 0.27 2.39| Info: 5000 | 316 4683 | 94 906 | 104767| 0.24 2.63| Info: 6000 | 419 5580 | 103 897 | 103911| 0.24 2.87| Info: 7000 | 511 6488 | 92 908 | 103034| 0.25 3.12| Info: 8000 | 586 7413 | 75 925 | 102135| 0.27 3.38| Info: 9000 | 678 8321 | 92 908 | 101251| 0.25 3.63| Info: 10000 | 807 9192 | 129 871 | 100415| 0.26 3.89| Info: 11000 | 906 10093 | 99 901 | 99527| 0.25 4.15| Info: 12000 | 1043 10956 | 137 863 | 98690| 0.26 4.41| Info: 13000 | 1162 11837 | 119 881 | 97822| 0.25 4.66| Info: 14000 | 1266 12733 | 104 896 | 96937| 0.24 4.90| Info: 15000 | 1374 13625 | 108 892 | 96067| 0.26 5.16| Info: 16000 | 1523 14476 | 149 851 | 95239| 0.28 5.44| Info: 17000 | 1716 15283 | 193 807 | 94490| 0.25 5.69| Info: 18000 | 1888 16111 | 172 828 | 93704| 0.26 5.94| Info: 19000 | 1993 17006 | 105 895 | 92826| 0.23 6.18| Info: 20000 | 2108 17891 | 115 885 | 92038| 0.26 6.44| Info: 21000 | 2230 18769 | 122 878 | 91228| 0.28 6.72| Info: 22000 | 2328 19671 | 98 902 | 90353| 0.24 6.96| Info: 23000 | 2501 20495 | 173 824 | 89561| 0.25 7.20| Info: 24000 | 2697 21297 | 196 802 | 88772| 0.24 7.44| Info: 25000 | 2851 22137 | 154 840 | 87934| 0.26 7.70| Info: 26000 | 3009 22958 | 158 821 | 87128| 0.24 7.94| Info: 27000 | 3188 23755 | 179 797 | 86317| 0.23 8.17| Info: 28000 | 3350 24573 | 162 818 | 85483| 0.25 8.42| Info: 29000 | 3471 25431 | 121 858 | 84608| 0.24 8.67| Info: 30000 | 3588 26290 | 117 859 | 83738| 0.25 8.91| Info: 31000 | 3715 27139 | 127 849 | 82883| 0.24 9.16| Info: 32000 | 3842 27992 | 127 853 | 82015| 0.24 9.39| Info: 33000 | 3988 28820 | 146 828 | 81170| 0.24 9.63| Info: 34000 | 4114 29654 | 126 834 | 80304| 0.28 9.91| Info: 35000 | 4242 30495 | 128 841 | 79455| 0.24 10.15| Info: 36000 | 4338 31355 | 96 860 | 78559| 0.23 10.38| Info: 37000 | 4437 32225 | 99 870 | 77673| 0.25 10.63| Info: 38000 | 4543 33080 | 106 855 | 76786| 0.25 10.88| Info: 39000 | 4644 33956 | 101 876 | 75888| 0.23 11.10| Info: 40000 | 4763 34809 | 119 853 | 75015| 0.25 11.35| Info: 41000 | 4879 35666 | 116 857 | 74137| 0.26 11.61| Info: 42000 | 5022 36499 | 143 833 | 73289| 0.25 11.87| Info: 43000 | 5131 37358 | 109 859 | 72404| 0.26 12.12| Info: 44000 | 5247 38213 | 116 855 | 71537| 0.25 12.37| Info: 45000 | 5332 39092 | 85 879 | 70622| 0.25 12.62| Info: 46000 | 5441 39948 | 109 856 | 69747| 0.25 12.87| Info: 47000 | 5566 40767 | 125 819 | 68884| 0.24 13.11| Info: 48000 | 5670 41608 | 104 841 | 68008| 0.26 13.37| Info: 49000 | 5761 42461 | 91 853 | 67109| 0.27 13.64| Info: 50000 | 5871 43306 | 110 845 | 66228| 0.25 13.89| Info: 51000 | 5973 44133 | 102 827 | 65334| 0.26 14.15| Info: 52000 | 6050 45026 | 77 893 | 64419| 0.25 14.40| Info: 53000 | 6148 45883 | 98 857 | 63541| 0.30 14.70| Info: 54000 | 6265 46733 | 117 850 | 62668| 0.29 14.99| Info: 55000 | 6375 47596 | 110 863 | 61782| 0.27 15.26| Info: 56000 | 6507 48438 | 132 842 | 60924| 0.28 15.53| Info: 57000 | 6603 49323 | 96 885 | 60026| 0.27 15.81| Info: 58000 | 6702 50207 | 99 884 | 59126| 0.30 16.11| Info: 59000 | 6837 51053 | 135 846 | 58275| 0.28 16.39| Info: 60000 | 6944 51928 | 107 875 | 57414| 0.28 16.67| Info: 61000 | 7043 52802 | 99 874 | 56515| 0.26 16.93| Info: 62000 | 7158 53672 | 115 870 | 55661| 0.26 17.19| Info: 63000 | 7250 54565 | 92 893 | 54764| 0.26 17.45| Info: 64000 | 7376 55420 | 126 855 | 53905| 0.31 17.76| Info: 65000 | 7516 56263 | 140 843 | 53088| 0.29 18.05| Info: 66000 | 7641 57122 | 125 859 | 52234| 0.29 18.34| Info: 67000 | 7784 57949 | 143 827 | 51394| 0.28 18.62| Info: 68000 | 7913 58803 | 129 854 | 50546| 0.28 18.89| Info: 69000 | 8045 59653 | 132 850 | 49679| 0.27 19.17| Info: 70000 | 8174 60502 | 129 849 | 48824| 0.29 19.46| Info: 71000 | 8327 61325 | 153 823 | 47988| 0.29 19.74| Info: 72000 | 8482 62148 | 155 823 | 47159| 0.27 20.02| Info: 73000 | 8589 63006 | 107 858 | 46278| 0.36 20.37| Info: 74000 | 8727 63842 | 138 836 | 45447| 0.28 20.66| Info: 75000 | 8864 64667 | 137 825 | 44595| 0.27 20.93| Info: 76000 | 8967 65544 | 103 877 | 43739| 0.30 21.23| Info: 77000 | 9113 66368 | 146 824 | 42894| 0.29 21.51| Info: 78000 | 9231 67209 | 118 841 | 42026| 0.28 21.79| Info: 79000 | 9359 68056 | 128 847 | 41168| 0.29 22.08| Info: 80000 | 9476 68904 | 117 848 | 40309| 0.30 22.38| Info: 81000 | 9610 69701 | 134 797 | 39474| 0.30 22.68| Info: 82000 | 9767 70506 | 157 805 | 38659| 0.29 22.97| Info: 83000 | 9905 71305 | 138 799 | 37808| 0.30 23.27| Info: 84000 | 10060 72108 | 155 803 | 36970| 0.29 23.56| Info: 85000 | 10214 72889 | 154 781 | 36134| 0.28 23.84| Info: 86000 | 10348 73710 | 134 821 | 35286| 0.30 24.14| Info: 87000 | 10512 74520 | 164 810 | 34470| 0.31 24.44| Info: 88000 | 10661 75288 | 149 768 | 33634| 0.31 24.76| Info: 89000 | 10779 76146 | 118 858 | 32772| 0.28 25.04| Info: 90000 | 10947 76914 | 168 768 | 31954| 0.31 25.35| Info: 91000 | 11055 77705 | 108 791 | 31073| 0.27 25.62| Info: 92000 | 11200 78505 | 145 800 | 30219| 0.31 25.93| Info: 93000 | 11318 79365 | 118 860 | 29356| 0.33 26.26| Info: 94000 | 11428 80152 | 110 787 | 28475| 0.29 26.55| Info: 95000 | 11559 80982 | 131 830 | 27615| 0.31 26.85| Info: 96000 | 11757 81742 | 198 760 | 27108| 0.37 27.22| Info: 97000 | 12075 82424 | 318 682 | 27156| 0.64 27.86| Info: 98000 | 12339 83160 | 264 736 | 26848| 0.60 28.46| Info: 99000 | 12491 83941 | 152 781 | 26012| 0.30 28.77| Info: 100000 | 12641 84726 | 150 785 | 25170| 0.33 29.10| Info: 101000 | 12772 85552 | 131 826 | 24321| 0.36 29.46| Info: 102000 | 12921 86349 | 149 797 | 23474| 0.32 29.78| Info: 103000 | 13070 87173 | 149 824 | 22637| 0.34 30.12| Info: 104000 | 13234 87935 | 164 762 | 21821| 0.32 30.44| Info: 105000 | 13354 88774 | 120 839 | 20951| 0.35 30.79| Info: 106000 | 13519 89585 | 165 811 | 20132| 0.34 31.13| Info: 107000 | 13624 90418 | 105 833 | 19243| 0.29 31.43| Info: 108000 | 13734 91250 | 110 832 | 18356| 0.29 31.72| Info: 109000 | 13915 92053 | 181 803 | 17595| 0.37 32.08| Info: 110000 | 14073 92875 | 158 822 | 16781| 0.46 32.55| Info: 111000 | 14195 93744 | 122 869 | 15919| 0.30 32.85| Info: 112000 | 14336 94599 | 141 855 | 15075| 0.35 33.20| Info: 113000 | 14456 95479 | 120 880 | 14203| 0.37 33.57| Info: 114000 | 14651 96283 | 195 804 | 13422| 0.35 33.92| Info: 115000 | 14923 96999 | 272 716 | 12724| 0.43 34.34| Info: 116000 | 15089 97821 | 166 822 | 11917| 0.44 34.78| Info: 117000 | 15289 98621 | 200 800 | 11150| 0.51 35.29| Info: 118000 | 15478 99432 | 189 811 | 10355| 0.36 35.65| Info: 119000 | 15649 100261 | 171 829 | 9539| 0.36 36.00| Info: 120000 | 15805 101105 | 156 844 | 8702| 0.37 36.37| Info: 121000 | 16003 101907 | 198 802 | 7949| 0.61 36.98| Info: 122000 | 16226 102684 | 223 777 | 7246| 0.72 37.70| Info: 123000 | 16315 103595 | 89 911 | 6342| 0.33 38.03| Info: 124000 | 16487 104423 | 172 828 | 5571| 0.44 38.47| Info: 125000 | 16735 105175 | 248 752 | 4893| 0.52 38.98| Info: 126000 | 16976 105934 | 241 759 | 4219| 0.52 39.51| Info: 127000 | 17229 106681 | 253 747 | 3516| 0.48 39.98| Info: 128000 | 17477 107433 | 248 752 | 2771| 0.37 40.35| Info: 129000 | 17569 108088 | 92 655 | 1891| 0.35 40.70| Info: 130000 | 17574 108709 | 5 621 | 899| 0.34 41.04| Info: 130918 | 17587 109278 | 13 569 | 0| 0.36 41.40| Info: Routing complete. Info: Router1 time 41.40s Info: Checksum: 0x6fd74a43 Info: Critical path report for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source ignition_io_bank6_0_txrs_rx_decode_result.empty_reg_TRELLIS_FF_Q.Q Info: 0.9 1.5 Net WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z[2] (22,43) -> (22,42) Info: Sink ignition_io_bank6_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_D_LUT4_Z_1.D Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2056.27-2056.36 Info: 0.2 1.7 Source ignition_io_bank6_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_D_LUT4_Z_1.F Info: 0.7 2.4 Net ignition_io_bank6_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_D[3] (22,42) -> (23,44) Info: Sink WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_2_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 2.7 Source WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_2_LUT4_Z.F Info: 1.0 3.7 Net WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_2 (23,44) -> (22,43) Info: Sink WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_5_LUT4_Z_C_LUT4_D_Z_LUT4_Z_D_LUT4_Z.C Info: Defined in: Info: ./env/46b265dee1eb4a823cc4a1a589f3c07cccc65612/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:18709.8-18709.66 Info: 0.2 3.9 Source WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_5_LUT4_Z_C_LUT4_D_Z_LUT4_Z_D_LUT4_Z.F Info: 0.0 3.9 Net WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_5_LUT4_Z_C_LUT4_D_Z_LUT4_Z_D[2] (22,43) -> (22,43) Info: Sink WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_5_LUT4_Z_C_LUT4_D_Z_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.2 Source WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_5_LUT4_Z_C_LUT4_D_Z_LUT4_Z.F Info: 0.8 4.9 Net WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z[4] (22,43) -> (23,44) Info: Sink ignition_io_bank6_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_C_LUT4_C_Z_LUT4_D_1.M Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 5.2 Source ignition_io_bank6_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_C_LUT4_C_Z_LUT4_D_1.OFX Info: 1.8 7.0 Net ignition_io_bank6_0_txrs_rx_channels_2_phase$D_IN_LUT4_Z_1_C_LUT4_C_Z_LUT4_D_Z_PFUMX_ALUT_Z[1] (23,44) -> (23,61) Info: Sink ignition_io_bank6_0_txrs_rx_parser_state$D_IN_LUT4_Z_36_B_LUT4_Z_B_LUT4_Z_1_C_LUT4_D_Z_LUT4_Z_2_C_LUT4_Z_B_LUT4_C_D_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.B Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 7.4 Source ignition_io_bank6_0_txrs_rx_parser_state$D_IN_LUT4_Z_36_B_LUT4_Z_B_LUT4_Z_1_C_LUT4_D_Z_LUT4_Z_2_C_LUT4_Z_B_LUT4_C_D_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.2 7.6 Net WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z[5] (23,61) -> (23,61) Info: Sink ignition_io_bank6_0_txrs_rx_parser_state$D_IN_LUT4_Z_36_B_LUT4_Z_B_LUT4_Z_1_C_LUT4_D_Z_LUT4_Z_2_C_LUT4_Z_B_LUT4_C_D_LUT4_D_Z_LUT4_Z_2.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 7.8 Source ignition_io_bank6_0_txrs_rx_parser_state$D_IN_LUT4_Z_36_B_LUT4_Z_B_LUT4_Z_1_C_LUT4_D_Z_LUT4_Z_2_C_LUT4_Z_B_LUT4_C_D_LUT4_D_Z_LUT4_Z_2.F Info: 1.8 9.6 Net WILL_FIRE_RL_ignition_io_bank6_0_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_LUT4_Z_D_LUT4_Z_B_LUT4_B_Z_LUT4_B_D_LUT4_C_Z[5] (23,61) -> (19,43) Info: Sink ignition_io_bank6_0_txrs_rx_decode_input$FULL_N_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 9.8 Source ignition_io_bank6_0_txrs_rx_decode_input$FULL_N_LUT4_Z.F Info: 0.5 10.3 Net ignition_io_bank6_0_txrs_rx_decode_input.FULL_N (19,43) -> (19,43) Info: Sink ignition_io_bank6_0_txrs_deserializers_1_out.empty_reg_LUT4_B.C Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2050.26-2050.32 Info: 0.2 10.5 Source ignition_io_bank6_0_txrs_deserializers_1_out.empty_reg_LUT4_B.F Info: 1.1 11.7 Net ignition_io_bank6_0_txrs_deserializers_1_out.empty_reg_LUT4_B_Z[3] (19,43) -> (20,42) Info: Sink ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 11.9 Source ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z.F Info: 0.9 12.8 Net ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI[12] (20,42) -> (19,42) Info: Sink ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_D.D Info: Defined in: Info: ./env/46b265dee1eb4a823cc4a1a589f3c07cccc65612/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:0.0-0.0 Info: ./env/46b265dee1eb4a823cc4a1a589f3c07cccc65612/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:102720.5-102741.12 Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/techmap.v:578.19-578.22 Info: 0.2 13.0 Source ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_D.F Info: 0.7 13.7 Net ignition_io_bank6_0_txrs_deserializers_0_out.empty_reg_LUT4_B_Z[1] (19,42) -> (19,42) Info: Sink ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 13.9 Source ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR_LUT4_Z.F Info: 0.6 14.5 Net ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR (19,42) -> (20,42) Info: Sink ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_1.LSR Info: 0.4 14.9 Setup ignition_io_bank6_0_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_1.LSR Info: 4.0 ns logic, 10.9 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source sp_to_fpga_design_reset_l$tr_io.O Info: 1.2 1.2 Net sp_to_fpga_design_reset_l$TRELLIS_IO_IN (4,71) -> (6,66) Info: Sink sp_to_fpga_design_reset_l_LUT4_D.D Info: Defined in: Info: ./env/46b265dee1eb4a823cc4a1a589f3c07cccc65612/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:413.10-413.35 Info: 0.2 1.4 Source sp_to_fpga_design_reset_l_LUT4_D.F Info: 1.7 3.1 Net sp_to_fpga_design_reset_l_LUT4_D_Z (6,66) -> (28,65) Info: Sink reset_sync.reset_hold_TRELLIS_FF_DI.LSR Info: 0.4 3.6 Setup reset_sync.reset_hold_TRELLIS_FF_DI.LSR Info: 0.7 ns logic, 2.9 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' -> '': Info: curr total Info: 0.5 0.5 Source controller_vsc7448_sequencer_in_reset_TRELLIS_FF_Q.Q Info: 0.5 1.0 Net controller_vsc7448_sequencer_in_reset (49,3) -> (47,3) Info: Sink fpga_to_mgmt_reset_l_LUT4_Z.D Info: Defined in: Info: ./env/46b265dee1eb4a823cc4a1a589f3c07cccc65612/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:13764.7-13764.44 Info: 0.2 1.2 Source fpga_to_mgmt_reset_l_LUT4_Z.F Info: 4.5 5.8 Net fpga_to_phy4_reset_l$TRELLIS_IO_OUT (47,3) -> (0,29) Info: Sink fpga_to_phy4_reset_l$tr_io.I Info: Defined in: Info: ./env/46b265dee1eb4a823cc4a1a589f3c07cccc65612/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:598.10-598.30 Info: 0.8 ns logic, 5.0 ns routing Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 67.09 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 3.56 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 5.77 ns Info: Slack histogram: Info: legend: * represents 75 endpoint(s) Info: + represents [1,75) endpoint(s) Info: [ 5094, 5793) |+ Info: [ 5793, 6492) |+ Info: [ 6492, 7191) |+ Info: [ 7191, 7890) |+ Info: [ 7890, 8589) |*+ Info: [ 8589, 9288) |**+ Info: [ 9288, 9987) |***+ Info: [ 9987, 10686) |******+ Info: [ 10686, 11385) |***************+ Info: [ 11385, 12084) |*********************+ Info: [ 12084, 12783) |*****************************+ Info: [ 12783, 13482) |*************************************+ Info: [ 13482, 14181) |****************************************+ Info: [ 14181, 14880) |**********************************+ Info: [ 14880, 15579) |*****************************+ Info: [ 15579, 16278) |***********************************+ Info: [ 16278, 16977) |***************************************+ Info: [ 16977, 17676) |*********************************+ Info: [ 17676, 18375) |***************************+ Info: [ 18375, 19074) |************************************************************ Info: Program finished normally.