Info: constraining clock net 'clk_50m_fpga_refclk' to 50.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 25758/43848 58% Info: logic LUTs: 23786/43848 54% Info: carry LUTs: 1972/43848 4% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 15131/43848 34% Info: Packing IOs.. Info: $rsw_s9_aux_dc_p$iobuf_i: rsw_s9_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s9_aux_dc_p$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: $rsw_s8_aux_dc_p$iobuf_i: rsw_s8_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s8_aux_dc_p$tr_io' constrained to Bel 'X90/Y44/PIOA'. Info: $rsw_s7_aux_dc_p$iobuf_i: rsw_s7_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s7_aux_dc_p$tr_io' constrained to Bel 'X90/Y50/PIOA'. Info: $rsw_s6_aux_dc_p$iobuf_i: rsw_s6_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s6_aux_dc_p$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: $rsw_s5_aux_dc_p$iobuf_i: rsw_s5_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s5_aux_dc_p$tr_io' constrained to Bel 'X90/Y62/PIOA'. Info: $rsw_s4_aux_dc_p$iobuf_i: rsw_s4_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s4_aux_dc_p$tr_io' constrained to Bel 'X90/Y47/PIOA'. Info: $rsw_s3_aux_dc_p$iobuf_i: rsw_s3_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s3_aux_dc_p$tr_io' constrained to Bel 'X90/Y65/PIOA'. Info: $rsw_s31_aux_dc_p$iobuf_i: rsw_s31_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s31_aux_dc_p$tr_io' constrained to Bel 'X0/Y56/PIOA'. Info: $rsw_s30_aux_dc_p$iobuf_i: rsw_s30_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s30_aux_dc_p$tr_io' constrained to Bel 'X0/Y53/PIOA'. Info: $rsw_s2_aux_dc_p$iobuf_i: rsw_s2_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s2_aux_dc_p$tr_io' constrained to Bel 'X90/Y68/PIOA'. Info: $rsw_s29_aux_dc_p$iobuf_i: rsw_s29_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s29_aux_dc_p$tr_io' constrained to Bel 'X0/Y68/PIOA'. Info: $rsw_s28_aux_dc_p$iobuf_i: rsw_s28_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s28_aux_dc_p$tr_io' constrained to Bel 'X0/Y65/PIOA'. Info: $rsw_s27_aux_dc_p$iobuf_i: rsw_s27_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s27_aux_dc_p$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: $rsw_s26_aux_dc_p$iobuf_i: rsw_s26_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s26_aux_dc_p$tr_io' constrained to Bel 'X0/Y62/PIOA'. Info: $rsw_s25_aux_dc_p$iobuf_i: rsw_s25_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s25_aux_dc_p$tr_io' constrained to Bel 'X0/Y50/PIOA'. Info: $rsw_s24_aux_dc_p$iobuf_i: rsw_s24_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s24_aux_dc_p$tr_io' constrained to Bel 'X0/Y47/PIOA'. Info: $rsw_s23_aux_dc_p$iobuf_i: rsw_s23_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s23_aux_dc_p$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $rsw_s22_aux_dc_p$iobuf_i: rsw_s22_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s22_aux_dc_p$tr_io' constrained to Bel 'X0/Y41/PIOA'. Info: $rsw_s21_aux_dc_p$iobuf_i: rsw_s21_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s21_aux_dc_p$tr_io' constrained to Bel 'X0/Y38/PIOA'. Info: $rsw_s20_aux_dc_p$iobuf_i: rsw_s20_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s20_aux_dc_p$tr_io' constrained to Bel 'X0/Y35/PIOA'. Info: $rsw_s1_aux_dc_p$iobuf_i: rsw_s1_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s1_aux_dc_p$tr_io' constrained to Bel 'X90/Y53/PIOA'. Info: $rsw_s19_aux_dc_p$iobuf_i: rsw_s19_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s19_aux_dc_p$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: $rsw_s18_aux_dc_p$iobuf_i: rsw_s18_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s18_aux_dc_p$tr_io' constrained to Bel 'X90/Y35/PIOA'. Info: $rsw_s17_aux_dc_p$iobuf_i: rsw_s17_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s17_aux_dc_p$tr_io' constrained to Bel 'X90/Y38/PIOA'. Info: $rsw_s16_aux_dc_p$iobuf_i: rsw_s16_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s16_aux_dc_p$tr_io' constrained to Bel 'X90/Y41/PIOA'. Info: $rsw_s15_aux_dc_p$iobuf_i: rsw_s15_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s15_aux_dc_p$tr_io' constrained to Bel 'X90/Y11/PIOA'. Info: $rsw_s14_aux_dc_p$iobuf_i: rsw_s14_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s14_aux_dc_p$tr_io' constrained to Bel 'X90/Y14/PIOA'. Info: $rsw_s13_aux_dc_p$iobuf_i: rsw_s13_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s13_aux_dc_p$tr_io' constrained to Bel 'X90/Y17/PIOA'. Info: $rsw_s12_aux_dc_p$iobuf_i: rsw_s12_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s12_aux_dc_p$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: $rsw_s11_aux_dc_p$iobuf_i: rsw_s11_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s11_aux_dc_p$tr_io' constrained to Bel 'X90/Y23/PIOA'. Info: $rsw_s10_aux_dc_p$iobuf_i: rsw_s10_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s10_aux_dc_p$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: $rsw_s0_aux_dc_p$iobuf_i: rsw_s0_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s0_aux_dc_p$tr_io' constrained to Bel 'X90/Y56/PIOA'. Info: $ignition_ctrl_to_self_dc_p$iobuf_i: ignition_ctrl_to_self_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_self_dc_p$tr_io' constrained to Bel 'X0/Y32/PIOA'. Info: $ignition_ctrl_to_rsw_b_dc_p$iobuf_i: ignition_ctrl_to_rsw_b_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_rsw_b_dc_p$tr_io' constrained to Bel 'X0/Y17/PIOA'. Info: $ignition_ctrl_to_psc1_dc_p$iobuf_i: ignition_ctrl_to_psc1_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc1_dc_p$tr_io' constrained to Bel 'X0/Y14/PIOA'. Info: $ignition_ctrl_to_psc0_dc_p$iobuf_i: ignition_ctrl_to_psc0_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc0_dc_p$tr_io' constrained to Bel 'X0/Y11/PIOA'. Info: $i2c_fpga_to_tf_sda$iobuf_i: i2c_fpga_to_tf_sda_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_sda$tr_io' constrained to Bel 'X69/Y0/PIOA'. Info: $i2c_fpga_to_tf_scl$iobuf_i: i2c_fpga_to_tf_scl_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_scl$tr_io' constrained to Bel 'X51/Y0/PIOB'. Info: pin 'vr_v1p0_mgmt_to_fpga_pg$tr_io' constrained to Bel 'X85/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_vrhot_l$tr_io' constrained to Bel 'X53/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vddt_pg$tr_io' constrained to Bel 'X47/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vdda15_pg$tr_io' constrained to Bel 'X47/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_fault$tr_io' constrained to Bel 'X27/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_vrhot_l$tr_io' constrained to Bel 'X58/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_pg$tr_io' constrained to Bel 'X58/Y0/PIOB'. Info: pin 'vr_tf_vddcore_to_fpga_fault$tr_io' constrained to Bel 'X31/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vr_hot_l$tr_io' constrained to Bel 'X53/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdda1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdd1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOA'. Info: pin 'vr_tf_v1p8_to_fpga_fault$tr_io' constrained to Bel 'X13/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[2]$tr_io' constrained to Bel 'X83/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[1]$tr_io' constrained to Bel 'X83/Y0/PIOA'. Info: pin 'tf_to_fpga_vid[0]$tr_io' constrained to Bel 'X80/Y0/PIOB'. Info: pin 'tf_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOB'. Info: pin 'tf_pg_led$tr_io' constrained to Bel 'X38/Y0/PIOB'. Info: pin 'spi_sp_to_fpga_sck$tr_io' constrained to Bel 'X18/Y71/PIOA'. Info: pin 'spi_sp_to_fpga_mosi$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_miso_r$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_cs1_l$tr_io' constrained to Bel 'X13/Y71/PIOB'. Info: pin 'sp_to_fpga_design_reset_l$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 's9_rsw_aux_p$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 's8_rsw_aux_p$tr_io' constrained to Bel 'X90/Y44/PIOC'. Info: pin 's7_rsw_aux_p$tr_io' constrained to Bel 'X90/Y50/PIOC'. Info: pin 's6_rsw_aux_p$tr_io' constrained to Bel 'X90/Y59/PIOC'. Info: pin 's5_rsw_aux_p$tr_io' constrained to Bel 'X90/Y62/PIOC'. Info: pin 's4_rsw_aux_p$tr_io' constrained to Bel 'X90/Y47/PIOC'. Info: pin 's3_rsw_aux_p$tr_io' constrained to Bel 'X90/Y65/PIOC'. Info: pin 's31_rsw_aux_p$tr_io' constrained to Bel 'X0/Y56/PIOC'. Info: pin 's30_rsw_aux_p$tr_io' constrained to Bel 'X0/Y53/PIOC'. Info: pin 's2_rsw_aux_p$tr_io' constrained to Bel 'X90/Y68/PIOC'. Info: pin 's29_rsw_aux_p$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: pin 's28_rsw_aux_p$tr_io' constrained to Bel 'X0/Y65/PIOC'. Info: pin 's27_rsw_aux_p$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 's26_rsw_aux_p$tr_io' constrained to Bel 'X0/Y62/PIOC'. Info: pin 's25_rsw_aux_p$tr_io' constrained to Bel 'X0/Y50/PIOC'. Info: pin 's24_rsw_aux_p$tr_io' constrained to Bel 'X0/Y47/PIOC'. Info: pin 's23_rsw_aux_p$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 's22_rsw_aux_p$tr_io' constrained to Bel 'X0/Y41/PIOC'. Info: pin 's21_rsw_aux_p$tr_io' constrained to Bel 'X0/Y38/PIOC'. Info: pin 's20_rsw_aux_p$tr_io' constrained to Bel 'X0/Y35/PIOC'. Info: pin 's1_rsw_aux_p$tr_io' constrained to Bel 'X90/Y53/PIOC'. Info: pin 's19_rsw_aux_p$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: pin 's18_rsw_aux_p$tr_io' constrained to Bel 'X90/Y35/PIOC'. Info: pin 's17_rsw_aux_p$tr_io' constrained to Bel 'X90/Y38/PIOC'. Info: pin 's16_rsw_aux_p$tr_io' constrained to Bel 'X90/Y41/PIOC'. Info: pin 's15_rsw_aux_p$tr_io' constrained to Bel 'X90/Y11/PIOC'. Info: pin 's14_rsw_aux_p$tr_io' constrained to Bel 'X90/Y14/PIOC'. Info: pin 's13_rsw_aux_p$tr_io' constrained to Bel 'X90/Y17/PIOC'. Info: pin 's12_rsw_aux_p$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 's11_rsw_aux_p$tr_io' constrained to Bel 'X90/Y23/PIOC'. Info: pin 's10_rsw_aux_p$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 's0_rsw_aux_p$tr_io' constrained to Bel 'X90/Y56/PIOC'. Info: pin 'pcie_host_to_fpga_perst$tr_io' constrained to Bel 'X9/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_pwrflt$tr_io' constrained to Bel 'X4/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_prsnt_l$tr_io' constrained to Bel 'X4/Y0/PIOA'. Info: pin 'mgmt_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_phy4_pg$tr_io' constrained to Bel 'X51/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_mgmt_pg$tr_io' constrained to Bel 'X44/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p2_mgmt_pg$tr_io' constrained to Bel 'X49/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p0_phy4_pg$tr_io' constrained to Bel 'X69/Y0/PIOB'. Info: pin 'ldo_to_fpga_v0p75_tf_pcie_pg$tr_io' constrained to Bel 'X42/Y0/PIOB'. Info: pin 'ldo_to_fpga_smu_pg$tr_io' constrained to Bel 'X15/Y0/PIOA'. Info: pin 'ignition_target_to_self_p$tr_io' constrained to Bel 'X0/Y32/PIOC'. Info: pin 'ignition_rsw_b_to_ctrl_p$tr_io' constrained to Bel 'X0/Y17/PIOC'. Info: pin 'ignition_psc1_to_ctrl_p$tr_io' constrained to Bel 'X0/Y14/PIOC'. Info: pin 'ignition_psc0_to_ctrl_p$tr_io' constrained to Bel 'X0/Y11/PIOC'. Info: pin 'front_io_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y26/PIOD'. Info: pin 'fpga_to_vr_v1p0_mgmt_en$tr_io' constrained to Bel 'X85/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vddx_en$tr_io' constrained to Bel 'X27/Y0/PIOB'. Info: pin 'fpga_to_vr_tf_vddcore_en$tr_io' constrained to Bel 'X33/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdda1p8_en$tr_io' constrained to Bel 'X20/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdd1p8_en$tr_io' constrained to Bel 'X18/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[3]$tr_io' constrained to Bel 'X76/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[2]$tr_io' constrained to Bel 'X78/Y0/PIOA'. Info: pin 'fpga_to_tf_test_jtsel[1]$tr_io' constrained to Bel 'X78/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[0]$tr_io' constrained to Bel 'X80/Y0/PIOA'. Info: pin 'fpga_to_tf_test_core_tap_l$tr_io' constrained to Bel 'X76/Y0/PIOA'. Info: pin 'fpga_to_tf_pwron_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOB'. Info: pin 'fpga_to_tf_pcie_rst_l$tr_io' constrained to Bel 'X71/Y0/PIOB'. Info: pin 'fpga_to_tf_core_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOA'. Info: pin 'fpga_to_smu_tf_clk_en_l$tr_io' constrained to Bel 'X20/Y0/PIOB'. Info: pin 'fpga_to_smu_reset_l$tr_io' constrained to Bel 'X31/Y0/PIOA'. Info: pin 'fpga_to_smu_mgmt_clk_en_l$tr_io' constrained to Bel 'X38/Y0/PIOA'. Info: pin 'fpga_to_phy4_reset_l$tr_io' constrained to Bel 'X0/Y29/PIOB'. Info: pin 'fpga_to_mgmt_reset_l$tr_io' constrained to Bel 'X29/Y0/PIOB'. Info: pin 'fpga_to_ldo_v2p5_mgmt_en$tr_io' constrained to Bel 'X44/Y0/PIOA'. Info: pin 'fpga_to_ldo_v1p2_mgmt_en$tr_io' constrained to Bel 'X49/Y0/PIOA'. Info: pin 'fpga_to_ldo_v0p75_tf_pcie_en$tr_io' constrained to Bel 'X42/Y0/PIOA'. Info: pin 'fpga_to_ldo_smu_en$tr_io' constrained to Bel 'X15/Y0/PIOB'. Info: pin 'fpga_to_ldo_phy4_en$tr_io' constrained to Bel 'X24/Y0/PIOA'. Info: pin 'fpga_to_front_io_hsc_en$tr_io' constrained to Bel 'X0/Y26/PIOC'. Info: pin 'fpga_to_fan3_led_l$tr_io' constrained to Bel 'X29/Y0/PIOA'. Info: pin 'fpga_to_fan3_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: pin 'fpga_to_fan2_led_l$tr_io' constrained to Bel 'X22/Y0/PIOA'. Info: pin 'fpga_to_fan2_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: pin 'fpga_to_fan1_led_l$tr_io' constrained to Bel 'X18/Y0/PIOA'. Info: pin 'fpga_to_fan1_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOA'. Info: pin 'fpga_to_fan0_led_l$tr_io' constrained to Bel 'X13/Y0/PIOA'. Info: pin 'fpga_to_fan0_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOC'. Info: pin 'fpga_led0$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'fpga_debug1$tr_io' constrained to Bel 'X33/Y0/PIOB'. Info: pin 'fpga_debug0$tr_io' constrained to Bel 'X36/Y0/PIOB'. Info: pin 'fan3_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOB'. Info: pin 'fan3_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOB'. Info: pin 'fan2_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOA'. Info: pin 'fan2_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOD'. Info: pin 'fan1_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOD'. Info: pin 'fan1_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOB'. Info: pin 'fan0_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOC'. Info: pin 'fan0_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOD'. Info: pin 'clk_50m_fpga_refclk$tr_io' constrained to Bel 'X36/Y0/PIOA'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 7353 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk_50m_fpga_refclk$TRELLIS_IO_IN to global network Info: Checksum: 0xf8ddbb09 Info: Device utilisation: Info: TRELLIS_IO: 151/ 245 61% Info: DCCA: 1/ 56 1% Info: DP16KD: 2/ 108 1% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 15131/ 43848 34% Info: TRELLIS_COMB: 26834/ 43848 61% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 151 cells based on constraints. Info: Creating initial analytic placement for 29099 cells, random placement wirelen = 2342703. Info: at initial placer iter 0, wirelen = 25849 Info: at initial placer iter 1, wirelen = 17914 Info: at initial placer iter 2, wirelen = 16132 Info: at initial placer iter 3, wirelen = 15554 Info: Running main analytical placer, max placement attempts per cell = 221751270. Info: at iteration #1, type ALL: wirelen solved = 15260, spread = 303903, legal = 338811; time = 1.93s Info: at iteration #2, type ALL: wirelen solved = 52506, spread = 160329, legal = 185984; time = 1.54s Info: at iteration #3, type ALL: wirelen solved = 68984, spread = 130563, legal = 153509; time = 1.38s Info: at iteration #4, type ALL: wirelen solved = 73798, spread = 121365, legal = 143419; time = 1.44s Info: at iteration #5, type ALL: wirelen solved = 78096, spread = 116103, legal = 138246; time = 1.37s Info: at iteration #6, type ALL: wirelen solved = 80816, spread = 114007, legal = 132790; time = 1.34s Info: at iteration #7, type ALL: wirelen solved = 83785, spread = 111866, legal = 132742; time = 1.40s Info: at iteration #8, type ALL: wirelen solved = 85293, spread = 110836, legal = 130752; time = 1.35s Info: at iteration #9, type ALL: wirelen solved = 86612, spread = 109700, legal = 128396; time = 1.35s Info: at iteration #10, type ALL: wirelen solved = 87721, spread = 109364, legal = 126994; time = 1.35s Info: at iteration #11, type ALL: wirelen solved = 88903, spread = 108956, legal = 127787; time = 1.41s Info: at iteration #12, type ALL: wirelen solved = 90723, spread = 109308, legal = 127056; time = 1.35s Info: at iteration #13, type ALL: wirelen solved = 91584, spread = 109982, legal = 129400; time = 1.40s Info: at iteration #14, type ALL: wirelen solved = 93192, spread = 112105, legal = 128457; time = 1.31s Info: at iteration #15, type ALL: wirelen solved = 94349, spread = 111405, legal = 128906; time = 1.36s Info: HeAP Placer Time: 28.82s Info: of which solving equations: 11.69s Info: of which spreading cells: 2.86s Info: of which strict legalisation: 9.48s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 2872, wirelen = 126994 Info: at iteration #5: temp = 0.000000, timing cost = 1840, wirelen = 114030 Info: at iteration #10: temp = 0.000000, timing cost = 1666, wirelen = 110004 Info: at iteration #15: temp = 0.000000, timing cost = 1755, wirelen = 107596 Info: at iteration #20: temp = 0.000000, timing cost = 1237, wirelen = 106938 Info: at iteration #25: temp = 0.000000, timing cost = 1176, wirelen = 106695 Info: at iteration #25: temp = 0.000000, timing cost = 1165, wirelen = 106712 Info: SA placement time 64.03s Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 64.09 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 5.14 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 9.09 ns Info: Slack histogram: Info: legend: * represents 75 endpoint(s) Info: + represents [1,75) endpoint(s) Info: [ 4396, 5139) |+ Info: [ 5139, 5882) |+ Info: [ 5882, 6625) |*+ Info: [ 6625, 7368) |**+ Info: [ 7368, 8111) |*****+ Info: [ 8111, 8854) |**********+ Info: [ 8854, 9597) |***********+ Info: [ 9597, 10340) |**************+ Info: [ 10340, 11083) |*******************+ Info: [ 11083, 11826) |***********************+ Info: [ 11826, 12569) |********************+ Info: [ 12569, 13312) |***************************+ Info: [ 13312, 14055) |************************************+ Info: [ 14055, 14798) |**********************************+ Info: [ 14798, 15541) |************************************+ Info: [ 15541, 16284) |****************************************+ Info: [ 16284, 17027) |************************************+ Info: [ 17027, 17770) |****************************+ Info: [ 17770, 18513) |***************+ Info: [ 18513, 19256) |************************************************************ Info: Checksum: 0x9c9d811e Info: Routing globals... Info: routing clock net $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 110274 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 19 980 | 19 980 | 109299| 1.62 1.62| Info: 2000 | 92 1907 | 73 927 | 108408| 0.30 1.92| Info: 3000 | 230 2769 | 138 862 | 107862| 0.35 2.27| Info: 4000 | 347 3652 | 117 883 | 107223| 0.37 2.64| Info: 5000 | 415 4584 | 68 932 | 106316| 0.27 2.91| Info: 6000 | 536 5463 | 121 879 | 105482| 0.28 3.19| Info: 7000 | 662 6337 | 126 874 | 104635| 0.26 3.45| Info: 8000 | 775 7224 | 113 887 | 103764| 0.26 3.71| Info: 9000 | 879 8120 | 104 896 | 102915| 0.26 3.97| Info: 10000 | 991 9008 | 112 888 | 102039| 0.25 4.22| Info: 11000 | 1094 9905 | 103 897 | 101170| 0.25 4.47| Info: 12000 | 1187 10812 | 93 907 | 100290| 0.25 4.72| Info: 13000 | 1299 11700 | 112 888 | 99435| 0.25 4.97| Info: 14000 | 1429 12570 | 130 870 | 98633| 0.26 5.23| Info: 15000 | 1535 13464 | 106 894 | 97775| 0.27 5.50| Info: 16000 | 1641 14358 | 106 894 | 96905| 0.27 5.77| Info: 17000 | 1751 15248 | 110 890 | 96056| 0.27 6.05| Info: 18000 | 1886 16113 | 135 865 | 95206| 0.27 6.31| Info: 19000 | 2010 16989 | 124 876 | 94360| 0.27 6.59| Info: 20000 | 2133 17866 | 123 877 | 93530| 0.28 6.87| Info: 21000 | 2259 18740 | 126 874 | 92671| 0.26 7.13| Info: 22000 | 2387 19612 | 128 872 | 91817| 0.26 7.39| Info: 23000 | 2525 20474 | 138 862 | 91004| 0.28 7.67| Info: 24000 | 2629 21366 | 104 892 | 90137| 0.26 7.93| Info: 25000 | 2761 22231 | 132 865 | 89295| 0.25 8.18| Info: 26000 | 2915 23077 | 154 846 | 88478| 0.26 8.44| Info: 27000 | 3048 23939 | 133 862 | 87634| 0.26 8.69| Info: 28000 | 3175 24799 | 127 860 | 86818| 0.26 8.95| Info: 29000 | 3295 25673 | 120 874 | 85958| 0.25 9.20| Info: 30000 | 3372 26588 | 77 915 | 85040| 0.25 9.45| Info: 31000 | 3508 27427 | 136 839 | 84192| 0.25 9.70| Info: 32000 | 3638 28274 | 130 847 | 83348| 0.26 9.95| Info: 33000 | 3772 29122 | 134 848 | 82488| 0.24 10.20| Info: 34000 | 3895 29982 | 123 860 | 81624| 0.29 10.49| Info: 35000 | 4034 30819 | 139 837 | 80783| 0.24 10.73| Info: 36000 | 4141 31671 | 107 852 | 79919| 0.24 10.97| Info: 37000 | 4253 32529 | 112 858 | 79064| 0.25 11.21| Info: 38000 | 4359 33380 | 106 851 | 78181| 0.25 11.47| Info: 39000 | 4479 34218 | 120 838 | 77305| 0.24 11.71| Info: 40000 | 4590 35075 | 111 857 | 76432| 0.25 11.96| Info: 41000 | 4732 35902 | 142 827 | 75601| 0.26 12.23| Info: 42000 | 4847 36749 | 115 847 | 74738| 0.27 12.50| Info: 43000 | 4963 37580 | 116 831 | 73868| 0.25 12.75| Info: 44000 | 5072 38438 | 109 858 | 72998| 0.25 13.00| Info: 45000 | 5193 39297 | 121 859 | 72135| 0.26 13.27| Info: 46000 | 5320 40134 | 127 837 | 71298| 0.28 13.55| Info: 47000 | 5425 40989 | 105 855 | 70425| 0.27 13.82| Info: 48000 | 5543 41837 | 118 848 | 69574| 0.28 14.09| Info: 49000 | 5660 42676 | 117 839 | 68729| 0.26 14.35| Info: 50000 | 5771 43510 | 111 834 | 67858| 0.28 14.64| Info: 51000 | 5873 44345 | 102 835 | 66970| 0.25 14.89| Info: 52000 | 5986 45186 | 113 841 | 66088| 0.26 15.15| Info: 53000 | 6099 46009 | 113 823 | 65220| 0.27 15.42| Info: 54000 | 6212 46850 | 113 841 | 64342| 0.27 15.69| Info: 55000 | 6311 47700 | 99 850 | 63453| 0.29 15.98| Info: 56000 | 6444 48523 | 133 823 | 62601| 0.28 16.26| Info: 57000 | 6565 49374 | 121 851 | 61733| 0.27 16.53| Info: 58000 | 6699 50205 | 134 831 | 60903| 0.28 16.81| Info: 59000 | 6816 51062 | 117 857 | 60069| 0.30 17.12| Info: 60000 | 6922 51937 | 106 875 | 59195| 0.29 17.41| Info: 61000 | 7061 52758 | 139 821 | 58353| 0.28 17.70| Info: 62000 | 7212 53591 | 151 833 | 57545| 0.32 18.02| Info: 63000 | 7345 54428 | 133 837 | 56697| 0.28 18.30| Info: 64000 | 7480 55284 | 135 856 | 55851| 0.30 18.61| Info: 65000 | 7586 56142 | 106 858 | 54974| 0.27 18.88| Info: 66000 | 7727 56984 | 141 842 | 54131| 0.32 19.20| Info: 67000 | 7843 57855 | 116 871 | 53271| 0.30 19.49| Info: 68000 | 7980 58688 | 137 833 | 52442| 0.29 19.79| Info: 69000 | 8117 59527 | 137 839 | 51601| 0.30 20.09| Info: 70000 | 8266 60353 | 149 826 | 50759| 0.31 20.40| Info: 71000 | 8394 61203 | 128 850 | 49910| 0.29 20.69| Info: 72000 | 8504 62080 | 110 877 | 49029| 0.29 20.98| Info: 73000 | 8647 62912 | 143 832 | 48195| 0.30 21.27| Info: 74000 | 8800 63746 | 153 834 | 47377| 0.40 21.67| Info: 75000 | 8948 64557 | 148 811 | 46538| 0.31 21.97| Info: 76000 | 9100 65391 | 152 834 | 45748| 0.34 22.31| Info: 77000 | 9255 66209 | 155 818 | 44931| 0.30 22.61| Info: 78000 | 9393 67045 | 138 836 | 44095| 0.30 22.92| Info: 79000 | 9523 67888 | 130 843 | 43243| 0.33 23.25| Info: 80000 | 9659 68718 | 136 830 | 42400| 0.32 23.57| Info: 81000 | 9799 69541 | 140 823 | 41562| 0.33 23.90| Info: 82000 | 9957 70311 | 158 770 | 40735| 0.30 24.20| Info: 83000 | 10115 71120 | 158 809 | 39917| 0.33 24.54| Info: 84000 | 10241 71936 | 126 816 | 39052| 0.32 24.86| Info: 85000 | 10409 72718 | 168 782 | 38245| 0.32 25.17| Info: 86000 | 10569 73505 | 160 787 | 37413| 0.32 25.50| Info: 87000 | 10773 74253 | 204 748 | 36645| 0.36 25.86| Info: 88000 | 10944 75032 | 171 779 | 35842| 0.34 26.20| Info: 89000 | 11117 75828 | 173 796 | 35071| 0.37 26.56| Info: 90000 | 11260 76645 | 143 817 | 34225| 0.34 26.90| Info: 91000 | 11398 77429 | 138 784 | 33418| 0.38 27.29| Info: 92000 | 11534 78267 | 136 838 | 32574| 0.32 27.61| Info: 93000 | 11700 79019 | 166 752 | 31763| 0.33 27.94| Info: 94000 | 11839 79782 | 139 763 | 30918| 0.30 28.24| Info: 95000 | 11959 80618 | 120 836 | 30045| 0.32 28.56| Info: 96000 | 12083 81469 | 124 851 | 29200| 0.37 28.93| Info: 97000 | 12208 82243 | 125 774 | 28378| 0.34 29.27| Info: 98000 | 12346 83059 | 138 816 | 27534| 0.34 29.60| Info: 99000 | 12493 83877 | 147 818 | 26686| 0.35 29.95| Info: 100000 | 12659 84635 | 166 758 | 25870| 0.36 30.31| Info: 101000 | 12817 85432 | 158 797 | 25043| 0.39 30.69| Info: 102000 | 12930 86290 | 113 858 | 24170| 0.40 31.10| Info: 103000 | 13115 87034 | 185 744 | 23376| 0.35 31.45| Info: 104000 | 13292 87834 | 177 800 | 22602| 0.39 31.84| Info: 105000 | 13502 88570 | 210 736 | 21910| 0.42 32.26| Info: 106000 | 13623 89440 | 121 870 | 21037| 0.37 32.63| Info: 107000 | 13795 90220 | 172 780 | 20242| 0.36 32.99| Info: 108000 | 13932 91046 | 137 826 | 19426| 0.34 33.33| Info: 109000 | 14094 91823 | 162 777 | 18606| 0.34 33.67| Info: 110000 | 14279 92608 | 185 785 | 17825| 0.36 34.03| Info: 111000 | 14448 93413 | 169 805 | 17027| 0.42 34.45| Info: 112000 | 14578 94262 | 130 849 | 16203| 0.45 34.91| Info: 113000 | 14761 95066 | 183 804 | 15396| 0.36 35.27| Info: 114000 | 14944 95882 | 183 816 | 14636| 0.40 35.67| Info: 115000 | 15063 96759 | 119 877 | 13765| 0.37 36.04| Info: 116000 | 15286 97536 | 223 777 | 13049| 0.40 36.44| Info: 117000 | 15572 98250 | 286 714 | 12404| 0.49 36.92| Info: 118000 | 15758 99052 | 186 802 | 11628| 0.49 37.41| Info: 119000 | 15991 99819 | 233 767 | 10909| 0.55 37.97| Info: 120000 | 16204 100606 | 213 787 | 10143| 0.39 38.36| Info: 121000 | 16380 101430 | 176 824 | 9325| 0.39 38.75| Info: 122000 | 16551 102259 | 171 829 | 8512| 0.40 39.15| Info: 123000 | 16804 103006 | 253 747 | 7809| 0.62 39.78| Info: 124000 | 17056 103754 | 252 748 | 7130| 0.76 40.54| Info: 125000 | 17233 104577 | 177 823 | 6337| 0.48 41.02| Info: 126000 | 17382 105428 | 149 851 | 5533| 0.43 41.45| Info: 127000 | 17699 106111 | 317 683 | 4964| 0.65 42.10| Info: 128000 | 18036 106774 | 337 663 | 4439| 0.66 42.76| Info: 129000 | 18376 107434 | 340 660 | 3924| 0.62 43.38| Info: 130000 | 18664 108146 | 288 712 | 3249| 0.48 43.86| Info: 131000 | 18894 108906 | 230 760 | 2503| 0.39 44.25| Info: 132000 | 18902 109540 | 8 634 | 1517| 0.35 44.60| Info: 133000 | 18909 110172 | 7 632 | 529| 0.34 44.94| Info: 133533 | 18912 110513 | 3 341 | 0| 0.30 45.24| Info: Routing complete. Info: Router1 time 45.24s Info: Checksum: 0xb770de11 Info: Critical path report for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source ignition_io_bank6_1_txrs_rx_decode_result.D_OUT_TRELLIS_FF_Q_2.Q Info: 1.2 1.7 Net ignition_io_bank6_1_txrs_rx_decode_result.D_OUT[11] (19,44) -> (19,47) Info: Sink ignition_io_bank6_1_txrs_rx_channels_3_phase$D_IN_PFUMX_Z_1_C0_LUT4_Z.C Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2052.27-2052.32 Info: 0.2 1.9 Source ignition_io_bank6_1_txrs_rx_channels_3_phase$D_IN_PFUMX_Z_1_C0_LUT4_Z.F Info: 0.7 2.6 Net ignition_io_bank6_1_txrs_rx_channels_3_phase$D_IN_PFUMX_Z_1_C0[4] (19,47) -> (19,48) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_3_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 2.8 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_3_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 1.2 4.0 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_3 (19,48) -> (17,44) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_4_LUT4_Z_C_LUT4_D_Z_LUT4_Z.C Info: Defined in: Info: ./env/68687a94401cf588fc00f65ef8336b4cd149791a/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:20103.8-20103.66 Info: 0.2 4.3 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_4_LUT4_Z_C_LUT4_D_Z_LUT4_Z.F Info: 0.7 4.9 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z[5] (17,44) -> (17,45) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z_LUT4_D.M Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 5.2 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z_LUT4_D.OFX Info: 0.0 5.2 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z (17,45) -> (17,45) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z_LUT4_D_2.FXB Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:157.70-157.72 Info: 0.2 5.4 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z_LUT4_D_2.OFX Info: 1.1 6.5 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_1_LUT4_Z_C_LUT4_D_Z_LUT4_D_Z_PFUMX_ALUT_Z_L6MUX21_D1_Z_L6MUX21_D1_Z[2] (17,45) -> (18,48) Info: Sink ignition_io_bank6_1_txrs_rx_channels_0_phase$D_IN_LUT4_Z_D_LUT4_A_C_LUT4_Z.C Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 6.8 Source ignition_io_bank6_1_txrs_rx_channels_0_phase$D_IN_LUT4_Z_D_LUT4_A_C_LUT4_Z.F Info: 0.6 7.4 Net ignition_io_bank6_1_txrs_rx_channels_0_phase$D_IN_LUT4_Z_D[3] (18,48) -> (18,48) Info: Sink ignition_io_bank6_1_txrs_rx_channels_0_phase$D_IN_LUT4_Z_D_LUT4_A.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 7.6 Source ignition_io_bank6_1_txrs_rx_channels_0_phase$D_IN_LUT4_Z_D_LUT4_A.F Info: 0.4 8.1 Net MUX_ignition_io_bank6_1_txrs_rx_channels_0_parser_state$write_1__VAL_2_TRELLIS_FF_Q_14_CE_LUT4_Z_B_LUT4_C_D_LUT4_B_C_LUT4_D_Z_LUT4_Z_C[2] (18,48) -> (17,47) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input$FULL_N_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 8.3 Source ignition_io_bank6_1_txrs_rx_decode_input$FULL_N_LUT4_Z.F Info: 0.2 8.6 Net ignition_io_bank6_1_txrs_rx_decode_input.FULL_N (17,47) -> (17,47) Info: Sink ignition_io_bank6_1_txrs_deserializers_1_out.empty_reg_LUT4_B.A Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2050.26-2050.32 Info: 0.2 8.8 Source ignition_io_bank6_1_txrs_deserializers_1_out.empty_reg_LUT4_B.F Info: 0.7 9.5 Net ignition_io_bank6_1_txrs_deserializers_1_out.empty_reg_LUT4_B_Z[3] (17,47) -> (17,47) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z.C Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 9.7 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z.F Info: 0.9 10.5 Net ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI[12] (17,47) -> (16,47) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_D.D Info: Defined in: Info: ./env/68687a94401cf588fc00f65ef8336b4cd149791a/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:0.0-0.0 Info: ./env/68687a94401cf588fc00f65ef8336b4cd149791a/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:103085.5-103106.12 Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/techmap.v:578.19-578.22 Info: 0.2 10.8 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_D.F Info: 0.9 11.7 Net ignition_io_bank6_1_txrs_deserializers_0_out.empty_reg_LUT4_C_Z[1] (16,47) -> (18,48) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input$ENQ_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 12.0 Source ignition_io_bank6_1_txrs_rx_decode_input$ENQ_LUT4_Z.F Info: 1.3 13.2 Net ignition_io_bank6_1_txrs_rx_decode_input.ENQ (18,48) -> (15,44) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_8.CE Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2046.26-2046.29 Info: 0.0 13.2 Setup ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_8.CE Info: 3.4 ns logic, 9.8 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source sp_to_fpga_design_reset_l$tr_io.O Info: 0.9 0.9 Net sp_to_fpga_design_reset_l$TRELLIS_IO_IN (4,71) -> (6,68) Info: Sink sp_to_fpga_design_reset_l_LUT4_D.D Info: Defined in: Info: ./env/68687a94401cf588fc00f65ef8336b4cd149791a/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:427.10-427.35 Info: 0.2 1.1 Source sp_to_fpga_design_reset_l_LUT4_D.F Info: 2.1 3.2 Net sp_to_fpga_design_reset_l_LUT4_D_Z (6,68) -> (35,68) Info: Sink reset_sync.reset_hold_TRELLIS_FF_Q.LSR Info: 0.4 3.6 Setup reset_sync.reset_hold_TRELLIS_FF_Q.LSR Info: 0.7 ns logic, 2.9 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' -> '': Info: curr total Info: 0.5 0.5 Source controller_vsc7448_sequencer_in_reset_TRELLIS_FF_Q.Q Info: 1.0 1.5 Net controller_vsc7448_sequencer_in_reset (48,3) -> (42,3) Info: Sink fpga_to_mgmt_reset_l_LUT4_Z.D Info: Defined in: Info: ./env/68687a94401cf588fc00f65ef8336b4cd149791a/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:13793.7-13793.44 Info: 0.2 1.7 Source fpga_to_mgmt_reset_l_LUT4_Z.F Info: 4.8 6.5 Net fpga_to_phy4_reset_l$TRELLIS_IO_OUT (42,3) -> (0,29) Info: Sink fpga_to_phy4_reset_l$tr_io.I Info: Defined in: Info: ./env/68687a94401cf588fc00f65ef8336b4cd149791a/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:622.10-622.30 Info: 0.8 ns logic, 5.7 ns routing Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 75.47 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 3.59 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 6.50 ns Info: Slack histogram: Info: legend: * represents 71 endpoint(s) Info: + represents [1,71) endpoint(s) Info: [ 6750, 7366) |+ Info: [ 7366, 7982) |+ Info: [ 7982, 8598) |*+ Info: [ 8598, 9214) |**+ Info: [ 9214, 9830) |***+ Info: [ 9830, 10446) |****+ Info: [ 10446, 11062) |*************+ Info: [ 11062, 11678) |****************+ Info: [ 11678, 12294) |***********************+ Info: [ 12294, 12910) |******************************+ Info: [ 12910, 13526) |**************************************+ Info: [ 13526, 14142) |************************************+ Info: [ 14142, 14758) |********************************+ Info: [ 14758, 15374) |*****************************+ Info: [ 15374, 15990) |******************************+ Info: [ 15990, 16606) |**********************************+ Info: [ 16606, 17222) |*********************************+ Info: [ 17222, 17838) |****************************+ Info: [ 17838, 18454) |**************************+ Info: [ 18454, 19070) |************************************************************ Info: Program finished normally.