RegisterMap

ID0

Identification 0

ID1

Identification 1

ID2

Identification 2

ID3

Identification 3

CHECKSUM_SCRATCHPAD0

Checksum Scratchpad part 0

CHECKSUM_SCRATCHPAD1

Checksum Scratchpad part 1

CHECKSUM_SCRATCHPAD2

Checksum Scratchpad part 2

CHECKSUM_SCRATCHPAD3

Checksum Scratchpad part 3

SCRATCHPAD

General Scratchpad

FPGA_ID

QSFP FPGA ID

LED_CTRL

LED Controller (PCA9956B) Control Bits

FPGA_BOARD_VER

QSFP Board Version

VSC8562_PHY_STATUS

Status bits related to VSC8562 (valid on FPGA1 only)

VSC8562_PHY_CTRL

Control bits related to VSC8562 (valid on FPGA1 only)

VSC8562_PHY_OSC

State bits indicating the PHY oscillator is operating nominal

VSC8562_PHY_SMI_STATUS

Status bits for the SMI interface to the VSC8562 (valid on FPGA1 only)

VSC8562_PHY_SMI_RDATA0

SMI Read Data [7:0] (valid on FPGA1 only)

VSC8562_PHY_SMI_RDATA1

SMI Read Data [15:8] (valid on FPGA1 only)

VSC8562_PHY_SMI_WDATA0

SMI Write Data [7:0] (valid on FPGA1 only)

VSC8562_PHY_SMI_WDATA1

SMI Write Data [15:8] (valid on FPGA1 only)

VSC8562_PHY_SMI_PHY_ADDR

PHY Address (valid on FPGA1 only)

VSC8562_PHY_SMI_REG_ADDR

Register Address (valid on FPGA1 only)

VSC8562_PHY_SMI_CTRL

SMI control bits, these are one-shot registers and intended to be written in the same transaction. (valid on FPGA1 only)

VSC8562_PHY_RAIL_STATES

PHY PowerRail state (internal to FPGA)

QSFP_I2C_BUS_ADDR

QSFP module I2C address

QSFP_I2C_REG_ADDR

QSFP module register address

QSFP_I2C_NUM_BYTES

I2C_NUM_BYTES

QSFP_I2C_BCAST0

Ports 0 -> 7 Broadcast Control

QSFP_I2C_BCAST1

Ports 8 -> 15 Broadcast Control

QSFP_I2C_CTRL

Control bits for I2C communication.

QSFP_I2C_BUSY0

Ports 0 -> 7 I2C core status. '1' is busy.

QSFP_I2C_BUSY1

Ports 8 -> 15 I2C core status. '1' is busy.

PORT0_STATUS

PORT1_STATUS

PORT2_STATUS

PORT3_STATUS

PORT4_STATUS

PORT5_STATUS

PORT6_STATUS

PORT7_STATUS

PORT8_STATUS

PORT9_STATUS

PORT10_STATUS

PORT11_STATUS

PORT12_STATUS

PORT13_STATUS

PORT14_STATUS

PORT15_STATUS

PORT0_CONTROL

PORT1_CONTROL

PORT2_CONTROL

PORT3_CONTROL

PORT4_CONTROL

PORT5_CONTROL

PORT6_CONTROL

PORT7_CONTROL

PORT8_CONTROL

PORT9_CONTROL

PORT10_CONTROL

PORT11_CONTROL

PORT12_CONTROL

PORT13_CONTROL

PORT14_CONTROL

PORT15_CONTROL

Ports 0 -> 7 HSC Enable. Clear bit to remove module power.

QSFP_POWER_EN1

Ports 8 -> 15 HSC Enable. Clear bit to remove module power.

QSFP_POWER_GOOD0

Ports 0 -> 7 HSC power good

QSFP_POWER_GOOD1

Ports 8 -> 15 HSC power good

QSFP_POWER_GOOD_TIMEOUT0

Ports 0 -> 7 HSC power good not asserted within period after enabled

QSFP_POWER_GOOD_TIMEOUT1

Ports 8 -> 15 HSC power good not asserted within period after enabled

QSFP_POWER_GOOD_LOST0

Ports 0 -> 7 HSC power good lost after successful enable

QSFP_POWER_GOOD_LOST1

Ports 8 -> 15 HSC power good lost after successful enable

QSFP_MOD_RESETL0

Ports 0 -> 7 Module ResetL

QSFP_MOD_RESETL1

Ports 8 -> 15 Module ResetL

QSFP_MOD_LPMODE0

Ports 0 -> 7 Module LPMode/TxDis

QSFP_MOD_LPMODE1

Ports 8 -> 15 Module LPMode/TxDis

QSFP_MOD_MODPRSL0

Ports 0 -> 7 Module ModPrsL

QSFP_MOD_MODPRSL1

Ports 8 -> 15 Module ModPrsL

QSFP_MOD_INTL0

Ports 0 -> 7 Module IntL/RxLOS

QSFP_MOD_INTL1

Ports 8 -> 15 Module IntL/RxLOS

QSFP_PORT0_I2C_DATA

Port 0 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT1_I2C_DATA

Port 1 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT2_I2C_DATA

Port 2 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT3_I2C_DATA

Port 3 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT4_I2C_DATA

Port 4 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT5_I2C_DATA

Port 5 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT6_I2C_DATA

Port 6 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT7_I2C_DATA

Port 7 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT8_I2C_DATA

Port 8 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT9_I2C_DATA

Port 9 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT10_I2C_DATA

Port 10 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT11_I2C_DATA

Port 11 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT12_I2C_DATA

Port 12 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT13_I2C_DATA

Port 13 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT14_I2C_DATA

Port 14 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

QSFP_PORT15_I2C_DATA

Port 15 I2C data FIFOs. Reading this address pulls from the rdata FIFO, writing it pushes to the wdata FIFO.

qsfp_x32_controller