Info: constraining clock net 'clk_25mhz' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:        47/83640     0%
Info:         logic LUTs:     23/83640     0%
Info:         carry LUTs:     24/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:        26/83640     0%

Info: Packing IOs..
Info: pin 'wifi_gpio0$tr_io' constrained to Bel 'X0/Y86/PIOD'.
Info: pin 'sw[3]$tr_io' constrained to Bel 'X9/Y0/PIOA'.
Info: pin 'sw[2]$tr_io' constrained to Bel 'X9/Y0/PIOB'.
Info: pin 'sw[1]$tr_io' constrained to Bel 'X13/Y0/PIOB'.
Info: pin 'sw[0]$tr_io' constrained to Bel 'X13/Y0/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X0/Y38/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y35/PIOD'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y35/PIOC'.
Info: pin 'ftdi_txd$tr_io' constrained to Bel 'X0/Y89/PIOB'.
Info: pin 'ftdi_rxd$tr_io' constrained to Bel 'X0/Y56/PIOC'.
Info: pin 'clk_25mhz$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'btn_pwr$tr_io' constrained to Bel 'X6/Y0/PIOB'.
Info: pin 'btn[5]$tr_io' constrained to Bel 'X126/Y17/PIOD'.
Info: pin 'btn[4]$tr_io' constrained to Bel 'X6/Y95/PIOA'.
Info: pin 'btn[3]$tr_io' constrained to Bel 'X6/Y95/PIOB'.
Info: pin 'btn[2]$tr_io' constrained to Bel 'X126/Y89/PIOB'.
Info: pin 'btn[1]$tr_io' constrained to Bel 'X4/Y95/PIOB'.
Info: pin 'btn[0]$tr_io' constrained to Bel 'X4/Y95/PIOA'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     26 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_25mhz$TRELLIS_IO_IN to global network
Info: Checksum: 0x9b3edd9a

Info: Device utilisation:
Info: 	          TRELLIS_IO:      23/    365     6%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    208     0%
Info: 	          MULT18X18D:       0/    156     0%
Info: 	              ALU54B:       0/     78     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    224     0%
Info: 	            SIOLOGIC:       0/    141     0%
Info: 	                 GSR:       1/      1   100%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     14     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:      26/  83640     0%
Info: 	        TRELLIS_COMB:      53/  83640     0%
Info: 	        TRELLIS_RAMW:       0/  10455     0%

Info: Placed 24 cells based on constraints.
Info: Creating initial analytic placement for 22 cells, random placement wirelen = 4393.
Info:     at initial placer iter 0, wirelen = 589
Info:     at initial placer iter 1, wirelen = 588
Info:     at initial placer iter 2, wirelen = 586
Info:     at initial placer iter 3, wirelen = 588
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type TRELLIS_COMB: wirelen solved = 588, spread = 588, legal = 713; time = 0.02s
Info: HeAP Placer Time: 0.11s
Info:   of which solving equations: 0.00s
Info:   of which spreading cells: 0.00s
Info:   of which strict legalisation: 0.00s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 17, wirelen = 713
Info:   at iteration #5: temp = 0.000000, timing cost = 22, wirelen = 627
Info:   at iteration #8: temp = 0.000000, timing cost = 13, wirelen = 618 
Info: SA placement time 0.02s

Info: Max frequency for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN': 237.98 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                                 -> <async>                                : 8.72 ns
Info: Max delay <async>                                 -> posedge $glbnet$clk_25mhz$TRELLIS_IO_IN: 18.23 ns
Info: Max delay posedge $glbnet$clk_25mhz$TRELLIS_IO_IN -> <async>                                : 6.68 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 35798,  35971) |* 
Info: [ 35971,  36144) |* 
Info: [ 36144,  36317) |** 
Info: [ 36317,  36490) |***** 
Info: [ 36490,  36663) | 
Info: [ 36663,  36836) | 
Info: [ 36836,  37009) |*** 
Info: [ 37009,  37182) |**** 
Info: [ 37182,  37355) |**** 
Info: [ 37355,  37528) | 
Info: [ 37528,  37701) |**** 
Info: [ 37701,  37874) | 
Info: [ 37874,  38047) | 
Info: [ 38047,  38220) | 
Info: [ 38220,  38393) | 
Info: [ 38393,  38566) | 
Info: [ 38566,  38739) | 
Info: [ 38739,  38912) | 
Info: [ 38912,  39085) | 
Info: [ 39085,  39258) |** 
Info: Checksum: 0xc872b74e
Info: Routing globals...
Info:     routing clock net $glbnet$clk_25mhz$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 162 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        273 |      110        146 |  110   146 |         0|       0.06       0.06|
Info: Routing complete.
Info: Router1 time 0.06s
Info: Checksum: 0xaf43e647

Info: Critical path report for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source blinky_c_TRELLIS_FF_Q_12.Q
Info:  1.1  1.6    Net blinky_c[11] (3,40) -> (3,39)
Info:                Sink blinky_c$D_IN_LUT4_Z_6_B_LUT4_Z_1.A
Info:                Defined in:
Info:                  ./env/91f6112c8cef0f00074d135d5d5f7318b20bfdaa/hdl/projects/ulx3s/mkBlinky.v:75.16-75.24
Info:  0.2  1.9  Source blinky_c$D_IN_LUT4_Z_6_B_LUT4_Z_1.F
Info:  0.7  2.5    Net blinky_c$D_IN_LUT4_Z_6_B[3] (3,39) -> (2,39)
Info:                Sink blinky_c$D_IN_LUT4_Z_6_B_LUT4_C.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.8  Source blinky_c$D_IN_LUT4_Z_6_B_LUT4_C.F
Info:  0.6  3.4    Net blinky_c$D_IN_CCU2C_S0_S1[3] (2,39) -> (2,39)
Info:                Sink blinky_d0_TRELLIS_FF_Q_CE_LUT4_Z.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.6  Source blinky_d0_TRELLIS_FF_Q_CE_LUT4_Z.F
Info:  0.7  4.3    Net blinky_d0_TRELLIS_FF_Q_CE (2,39) -> (2,38)
Info:                Sink blinky_d0_TRELLIS_FF_Q.CE
Info:  0.0  4.3  Setup blinky_d0_TRELLIS_FF_Q.CE
Info: 1.2 ns logic, 3.1 ns routing

Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info:  0.0  0.0  Source btn_pwr$tr_io.O
Info:  6.1  6.1    Net btn_pwr$TRELLIS_IO_IN (6,0) -> (4,94)
Info:                Sink gsr.GSR
Info:                Defined in:
Info:                  ./env/91f6112c8cef0f00074d135d5d5f7318b20bfdaa/hdl/projects/ulx3s/mkBlinky.v:50.10-50.17
Info: 0.0 ns logic, 6.1 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_25mhz$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source btn[5]$tr_io.O
Info: 10.8 10.8    Net btn[5]$TRELLIS_IO_IN (126,17) -> (6,93)
Info:                Sink blinky_d1$D_IN_LUT4_Z_D_LUT4_Z.A
Info:                Defined in:
Info:                  ./env/91f6112c8cef0f00074d135d5d5f7318b20bfdaa/hdl/projects/ulx3s/mkBlinky.v:65.18-65.21
Info:  0.2 11.1  Source blinky_d1$D_IN_LUT4_Z_D_LUT4_Z.F
Info:  0.9 12.0    Net blinky_d1$D_IN_LUT4_Z_D[2] (6,93) -> (4,93)
Info:                Sink blinky_d1$D_IN_LUT4_Z.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2 12.2  Source blinky_d1$D_IN_LUT4_Z.F
Info:  0.1 12.3    Net blinky_d1$D_IN (4,93) -> (4,93)
Info:                Sink blinky_d1_TRELLIS_FF_Q.DI
Info:                Defined in:
Info:                  ./env/91f6112c8cef0f00074d135d5d5f7318b20bfdaa/hdl/projects/ulx3s/mkBlinky.v:85.8-85.22
Info:  0.0 12.3  Setup blinky_d1_TRELLIS_FF_Q.DI
Info: 0.5 ns logic, 11.9 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_25mhz$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source blinky_d1_TRELLIS_FF_Q.Q
Info:  4.1  4.6    Net blinky_d1 (4,93) -> (0,35)
Info:                Sink led[1]$tr_io.I
Info:                Defined in:
Info:                  ./env/91f6112c8cef0f00074d135d5d5f7318b20bfdaa/hdl/projects/ulx3s/mkBlinky.v:88.16-88.27
Info: 0.5 ns logic, 4.1 ns routing

Info: Max frequency for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN': 230.63 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                                 -> <async>                                : 6.15 ns
Info: Max delay <async>                                 -> posedge $glbnet$clk_25mhz$TRELLIS_IO_IN: 12.32 ns
Info: Max delay posedge $glbnet$clk_25mhz$TRELLIS_IO_IN -> <async>                                : 4.62 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 35664,  35825) |* 
Info: [ 35825,  35986) |*** 
Info: [ 35986,  36147) |***** 
Info: [ 36147,  36308) | 
Info: [ 36308,  36469) | 
Info: [ 36469,  36630) |* 
Info: [ 36630,  36791) |**** 
Info: [ 36791,  36952) |*** 
Info: [ 36952,  37113) |*** 
Info: [ 37113,  37274) |* 
Info: [ 37274,  37435) |*** 
Info: [ 37435,  37596) | 
Info: [ 37596,  37757) | 
Info: [ 37757,  37918) | 
Info: [ 37918,  38079) | 
Info: [ 38079,  38240) | 
Info: [ 38240,  38401) | 
Info: [ 38401,  38562) | 
Info: [ 38562,  38723) | 
Info: [ 38723,  38884) |** 

Info: Program finished normally.