Info: constraining clock net 'clk_25mhz' to 25.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:        74/83640     0%
Info:         logic LUTs:     56/83640     0%
Info:         carry LUTs:     18/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:        76/83640     0%

Info: Packing IOs..
Info: pin 'wifi_gpio0$tr_io' constrained to Bel 'X0/Y86/PIOD'.
Info: pin 'sw[3]$tr_io' constrained to Bel 'X9/Y0/PIOA'.
Info: pin 'sw[2]$tr_io' constrained to Bel 'X9/Y0/PIOB'.
Info: pin 'sw[1]$tr_io' constrained to Bel 'X13/Y0/PIOB'.
Info: pin 'sw[0]$tr_io' constrained to Bel 'X13/Y0/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X0/Y41/PIOD'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X0/Y38/PIOD'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X0/Y44/PIOD'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X0/Y38/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X0/Y38/PIOC'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X0/Y38/PIOA'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X0/Y35/PIOD'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X0/Y35/PIOC'.
Info: pin 'ftdi_txd$tr_io' constrained to Bel 'X0/Y89/PIOB'.
Info: pin 'ftdi_rxd$tr_io' constrained to Bel 'X0/Y56/PIOC'.
Info: pin 'clk_25mhz$tr_io' constrained to Bel 'X0/Y47/PIOA'.
Info: pin 'btn_pwr$tr_io' constrained to Bel 'X6/Y0/PIOB'.
Info: pin 'btn[5]$tr_io' constrained to Bel 'X126/Y17/PIOD'.
Info: pin 'btn[4]$tr_io' constrained to Bel 'X6/Y95/PIOA'.
Info: pin 'btn[3]$tr_io' constrained to Bel 'X6/Y95/PIOB'.
Info: pin 'btn[2]$tr_io' constrained to Bel 'X126/Y89/PIOB'.
Info: pin 'btn[1]$tr_io' constrained to Bel 'X4/Y95/PIOB'.
Info: pin 'btn[0]$tr_io' constrained to Bel 'X4/Y95/PIOA'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     43 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info: Promoting globals...
Info:     promoting clock net clk_25mhz$TRELLIS_IO_IN to global network
Info: Checksum: 0x753932ce

Info: Device utilisation:
Info: 	          TRELLIS_IO:      23/    365     6%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       0/    208     0%
Info: 	          MULT18X18D:       0/    156     0%
Info: 	              ALU54B:       0/     78     0%
Info: 	             EHXPLLL:       0/      4     0%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    224     0%
Info: 	            SIOLOGIC:       0/    141     0%
Info: 	                 GSR:       1/      1   100%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     14     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:      76/  83640     0%
Info: 	        TRELLIS_COMB:      80/  83640     0%
Info: 	        TRELLIS_RAMW:       0/  10455     0%

Info: Placed 24 cells based on constraints.
Info: Creating initial analytic placement for 78 cells, random placement wirelen = 9301.
Info:     at initial placer iter 0, wirelen = 239
Info:     at initial placer iter 1, wirelen = 206
Info:     at initial placer iter 2, wirelen = 213
Info:     at initial placer iter 3, wirelen = 208
Info: Running main analytical placer, max placement attempts per cell = 10000.
Info:     at iteration #1, type ALL: wirelen solved = 209, spread = 421, legal = 473; time = 0.04s
Info:     at iteration #2, type ALL: wirelen solved = 237, spread = 301, legal = 420; time = 0.01s
Info:     at iteration #3, type ALL: wirelen solved = 230, spread = 306, legal = 419; time = 0.01s
Info:     at iteration #4, type ALL: wirelen solved = 243, spread = 339, legal = 452; time = 0.01s
Info:     at iteration #5, type ALL: wirelen solved = 259, spread = 309, legal = 417; time = 0.02s
Info:     at iteration #6, type ALL: wirelen solved = 242, spread = 308, legal = 412; time = 0.01s
Info:     at iteration #7, type ALL: wirelen solved = 245, spread = 318, legal = 407; time = 0.01s
Info:     at iteration #8, type ALL: wirelen solved = 269, spread = 375, legal = 417; time = 0.02s
Info:     at iteration #9, type ALL: wirelen solved = 262, spread = 314, legal = 403; time = 0.02s
Info:     at iteration #10, type ALL: wirelen solved = 272, spread = 314, legal = 402; time = 0.01s
Info:     at iteration #11, type ALL: wirelen solved = 263, spread = 335, legal = 387; time = 0.00s
Info:     at iteration #12, type ALL: wirelen solved = 272, spread = 328, legal = 375; time = 0.00s
Info:     at iteration #13, type ALL: wirelen solved = 266, spread = 319, legal = 365; time = 0.02s
Info:     at iteration #14, type ALL: wirelen solved = 266, spread = 316, legal = 419; time = 0.01s
Info:     at iteration #15, type ALL: wirelen solved = 284, spread = 331, legal = 416; time = 0.02s
Info:     at iteration #16, type ALL: wirelen solved = 275, spread = 378, legal = 438; time = 0.00s
Info:     at iteration #17, type ALL: wirelen solved = 297, spread = 364, legal = 403; time = 0.00s
Info:     at iteration #18, type ALL: wirelen solved = 310, spread = 377, legal = 437; time = 0.02s
Info: HeAP Placer Time: 0.36s
Info:   of which solving equations: 0.14s
Info:   of which spreading cells: 0.06s
Info:   of which strict legalisation: 0.01s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 16, wirelen = 365
Info:   at iteration #5: temp = 0.000000, timing cost = 17, wirelen = 341
Info:   at iteration #6: temp = 0.000000, timing cost = 18, wirelen = 340 
Info: SA placement time 0.02s

Info: Max frequency for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN': 262.67 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                                 -> <async>                                : 8.72 ns
Info: Max delay <async>                                 -> posedge $glbnet$clk_25mhz$TRELLIS_IO_IN: 5.78 ns
Info: Max delay posedge $glbnet$clk_25mhz$TRELLIS_IO_IN -> <async>                                : 3.01 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 36193,  36346) |*** 
Info: [ 36346,  36499) |***** 
Info: [ 36499,  36652) |** 
Info: [ 36652,  36805) |****** 
Info: [ 36805,  36958) |**** 
Info: [ 36958,  37111) |**** 
Info: [ 37111,  37264) |****** 
Info: [ 37264,  37417) |******** 
Info: [ 37417,  37570) |************ 
Info: [ 37570,  37723) |*********** 
Info: [ 37723,  37876) |********* 
Info: [ 37876,  38029) |*** 
Info: [ 38029,  38182) |** 
Info: [ 38182,  38335) |*** 
Info: [ 38335,  38488) |******* 
Info: [ 38488,  38641) |*********************** 
Info: [ 38641,  38794) |********* 
Info: [ 38794,  38947) |*********** 
Info: [ 38947,  39100) |******** 
Info: [ 39100,  39253) |***** 
Info: Checksum: 0x84dbee73
Info: Routing globals...
Info:     routing clock net $glbnet$clk_25mhz$TRELLIS_IO_IN using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 334 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:        428 |       89        320 |   89   320 |         0|       0.09       0.09|
Info: Routing complete.
Info: Router1 time 0.09s
Info: Checksum: 0x26a5b3b1

Info: Critical path report for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.5  0.5  Source uart_txr_deserializer_bits_remaining_TRELLIS_FF_Q.Q
Info:  0.9  1.4    Net uart_txr_deserializer_bits_remaining[3] (4,36) -> (4,36)
Info:                Sink uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_Z.A
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  1.7  Source uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_Z.F
Info:  0.8  2.5    Net uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D[6] (4,36) -> (4,36)
Info:                Sink uart_txr_deserializer_bits_remaining$EN_LUT4_Z.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  2.7  Source uart_txr_deserializer_bits_remaining$EN_LUT4_Z.F
Info:  0.6  3.3    Net uart_txr_deserializer_bits_remaining$EN (4,36) -> (4,36)
Info:                Sink uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_D.A
Info:                Defined in:
Info:                  ./env/5b6a3f38f56795b8fbf4e297042185afaf7f26aa/hdl/projects/ulx3s/mkLoopbackUART.v:97.8-97.47
Info:  0.2  3.6  Source uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_D.F
Info:  0.6  4.2    Net uart_txr_deserializer_bits_remaining$EN_LUT4_Z_D_LUT4_D_Z (4,36) -> (4,35)
Info:                Sink uart_txr_deserializer_bits_remaining_TRELLIS_FF_Q_3.LSR
Info:  0.4  4.6  Setup uart_txr_deserializer_bits_remaining_TRELLIS_FF_Q_3.LSR
Info: 1.7 ns logic, 3.0 ns routing

Info: Critical path report for cross-domain path '<async>' -> '<async>':
Info: curr total
Info:  0.0  0.0  Source btn_pwr$tr_io.O
Info:  6.8  6.8    Net btn_pwr$TRELLIS_IO_IN (6,0) -> (4,94)
Info:                Sink gsr.GSR
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2043.26-2043.29
Info: 0.0 ns logic, 6.8 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$clk_25mhz$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source btn_pwr$tr_io.O
Info:  3.0  3.0    Net btn_pwr$TRELLIS_IO_IN (6,0) -> (4,35)
Info:                Sink btn_pwr_LUT4_D.D
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2043.26-2043.29
Info:  0.2  3.2  Source btn_pwr_LUT4_D.F
Info:  0.6  3.8    Net btn_pwr_LUT4_D_Z (4,35) -> (2,37)
Info:                Sink uart_txr_tx_sync$D_IN_TRELLIS_FF_Q.LSR
Info:  0.4  4.3  Setup uart_txr_tx_sync$D_IN_TRELLIS_FF_Q.LSR
Info: 0.7 ns logic, 3.6 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$clk_25mhz$TRELLIS_IO_IN' -> '<async>':
Info: curr total
Info:  0.5  0.5  Source uart_txr_tx_sync_TRELLIS_FF_Q.Q
Info:  1.7  2.2    Net ftdi_rxd$TRELLIS_IO_OUT (2,40) -> (0,56)
Info:                Sink ftdi_rxd$tr_io.I
Info:                Defined in:
Info:                  ./env/5b6a3f38f56795b8fbf4e297042185afaf7f26aa/hdl/projects/ulx3s/mkLoopbackUART.v:161.7-161.23
Info: 0.5 ns logic, 1.7 ns routing

Info: Max frequency for clock '$glbnet$clk_25mhz$TRELLIS_IO_IN': 216.22 MHz (PASS at 25.00 MHz)

Info: Max delay <async>                                 -> <async>                                : 6.81 ns
Info: Max delay <async>                                 -> posedge $glbnet$clk_25mhz$TRELLIS_IO_IN: 4.26 ns
Info: Max delay posedge $glbnet$clk_25mhz$TRELLIS_IO_IN -> <async>                                : 2.22 ns

Info: Slack histogram:
Info:  legend: * represents 1 endpoint(s)
Info:          + represents [1,1) endpoint(s)
Info: [ 35375,  35560) |* 
Info: [ 35560,  35745) |*** 
Info: [ 35745,  35930) | 
Info: [ 35930,  36115) | 
Info: [ 36115,  36300) | 
Info: [ 36300,  36485) | 
Info: [ 36485,  36670) |**** 
Info: [ 36670,  36855) |*************** 
Info: [ 36855,  37040) |*** 
Info: [ 37040,  37225) |********** 
Info: [ 37225,  37410) |************ 
Info: [ 37410,  37595) |************** 
Info: [ 37595,  37780) |************ 
Info: [ 37780,  37965) |* 
Info: [ 37965,  38150) |* 
Info: [ 38150,  38335) |*** 
Info: [ 38335,  38520) |****************** 
Info: [ 38520,  38705) |************ 
Info: [ 38705,  38890) |************************* 
Info: [ 38890,  39075) |******* 

Info: Program finished normally.