Info: constrained 'seq_to_nic_v1p1_en' to bel 'X4/Y33/io1' Warning: unmatched constraint 'nic_to_seq_v1p1_pg' (on line 2) Info: constrained 'seq_to_nic_v1p2_enet_en' to bel 'X8/Y33/io0' Info: constrained 'seq_rev_id0' to bel 'X22/Y33/io1' Info: constrained 'seq_rev_id1' to bel 'X22/Y33/io0' Warning: unmatched constraint 'pwr_cont_nic_pg1' (on line 6) Warning: unmatched constraint 'pwr_cont_nic_pg0' (on line 7) Info: constrained 'seq_to_nic_v1p5a_en' to bel 'X0/Y30/io0' Info: constrained 'seq_to_nic_ldo_v3p3_en' to bel 'X0/Y31/io0' Info: constrained 'seq_to_nic_v1p2_en' to bel 'X3/Y33/io0' Warning: unmatched constraint 'testpoint1' (on line 11) Info: constrained 'seq_rev_id2' to bel 'X24/Y33/io0' Info: constrained 'seq_to_nic_cld_rst_l' to bel 'X30/Y33/io0' Info: constrained 'pwr_cont_nic_en0' to bel 'X31/Y33/io0' Warning: unmatched constraint 'nic_to_seq_v1p5d_pg' (on line 15) Warning: unmatched constraint 'nic_to_seq_v1p5a_pg' (on line 16) Warning: unmatched constraint 'nic_to_seq_v1p2_pg' (on line 17) Warning: unmatched constraint 'testpoint2' (on line 18) Warning: unmatched constraint 'nic_to_seq_v1p2_enet_pg' (on line 19) Warning: unmatched constraint 'nic_to_seq_ext_rst_l' (on line 20) Info: constrained 'pwr_cont_nic_en1' to bel 'X33/Y28/io0' Info: constrained 'seq_to_nic_v1p5d_en' to bel 'X0/Y25/io0' Info: constrained 'seq_to_clk_nmr_l' to bel 'X0/Y27/io0' Warning: unmatched constraint 'sp3_to_sp_nic_pwren_l' (on line 24) Warning: unmatched constraint 'fanhp_to_seq_fault_l' (on line 26) Warning: unmatched constraint 'fanhp_to_seq_pwrgd' (on line 27) Info: constrained 'seq_to_clk_ntest' to bel 'X0/Y23/io0' Warning: unmatched constraint 'vtt_ef_a0_to_seq_pg' (on line 29) Warning: unmatched constraint 'vtt_gh_a0_to_seq_pg' (on line 30) Info: constrained 'seq_to_fan_hp_en' to bel 'X33/Y23/io0' Warning: unmatched constraint 'seq_to_clk_gpio3' (on line 32) Warning: unmatched constraint 'seq_to_clk_gpio9' (on line 33) Info: constrained 'clk50m' to bel 'X16/Y33/io1' Info: constrained 'seq_to_vtt_efgh_en' to bel 'X33/Y21/io0' Warning: unmatched constraint 'seq_to_clk_gpio8' (on line 36) Warning: unmatched constraint 'seq_to_clk_gpio2' (on line 37) Warning: unmatched constraint 'seq_to_header_misc_i' (on line 38) Warning: unmatched constraint 'sp3_to_rsw_pwren_l_via_seq' (on line 39) Warning: unmatched constraint 'seq_proxy_sp3_to_rsw_pwren_l' (on line 40) Warning: unmatched constraint 'pwr_cont_dimm_efgh_pg0' (on line 41) Warning: unmatched constraint 'seq_to_clk_gpio1' (on line 42) Warning: unmatched constraint 'seq_to_clk_gpio4' (on line 43) Warning: unmatched constraint 'seq_to_header_misc_e' (on line 44) Warning: unmatched constraint 'seq_to_header_misc_f' (on line 45) Warning: unmatched constraint 'seq_to_header_misc_g' (on line 46) Warning: unmatched constraint 'seq_to_header_misc_h' (on line 47) Warning: unmatched constraint 'seq_to_clk_gpio5' (on line 48) Warning: unmatched constraint 'vtt_ab_a0_to_seq_pg' (on line 49) Warning: unmatched constraint 'vtt_cd_a0_to_seq_pg' (on line 50) Warning: unmatched constraint 'seq_to_sp_interrupt' (on line 51) Info: constrained 'seq_to_led_en_l' to bel 'X33/Y14/io1' Info: constrained 'seq_to_nic_v0p9_a0hp_en' to bel 'X33/Y15/io0' Info: constrained 'pwr_cont_dimm_efgh_en0' to bel 'X33/Y15/io1' Info: constrained 'seq_to_vtt_abcd_en' to bel 'X0/Y13/io1' Warning: unmatched constraint 'seq_v1p8_sp3_vdd_pg' (on line 56) Info: constrained 'seq_to_nic_perst_l' to bel 'X33/Y10/io1' Warning: unmatched constraint 'sp3_to_seq_nic_perst_l' (on line 58) Info: constrained 'nic_to_sp3_pwrflt_l' to bel 'X33/Y12/io0' Info: constrained 'seq_to_sp3_v1p8_en' to bel 'X0/Y12/io0' Info: constrained 'seq_to_dimm_abcd_v2p5_en' to bel 'X0/Y10/io0' Warning: unmatched constraint 'seq_to_sp_misc_a' (on line 62) Info: constrained 'seq_to_v3p3_sys_en' to bel 'X33/Y4/io1' Info: constrained 'seq_to_dimm_efgh_v2p5_en' to bel 'X33/Y6/io0' Warning: unmatched constraint 'dimm_to_seq_efgh_v2p5_pg' (on line 65) Warning: unmatched constraint 'dimm_to_seq_abcd_v2p5_pg' (on line 66) Info: constrained 'seq_to_sp3_v3p3_s5_en' to bel 'X0/Y9/io0' Warning: unmatched constraint 'seq_to_sp_misc_d' (on line 68) Info: constrained 'seq_to_sp3_v1p8_s5_en' to bel 'X27/Y0/io1' Warning: unmatched constraint 'nic_v0p9_a0hp_pg' (on line 70) Warning: unmatched constraint 'pwr_cont_dimm_pg0' (on line 71) Warning: unmatched constraint 'v3p3_sys_to_seq_pg' (on line 72) Warning: unmatched constraint 'fan_to_seq_fan_fail' (on line 73) Warning: unmatched constraint 'sp3_to_seq_v3p3_s5_pg' (on line 74) Warning: unmatched constraint 'sp3_to_seq_v1p8_s5_pg' (on line 75) Warning: unmatched constraint 'pwr_cont_dimm_pg1' (on line 76) Warning: unmatched constraint 'pwr_cont1_sp3_cfp' (on line 77) Warning: unmatched constraint 'pwr_cont1_sp3_nvrhot' (on line 78) Info: constrained 'pwr_cont1_sp3_pwrok' to bel 'X3/Y0/io0' Warning: unmatched constraint 'sp3_to_seq_fsr_req_l' (on line 80) Warning: unmatched constraint 'sp3_to_seq_pwrgd_out' (on line 81) Info: constrained 'RST_N' to bel 'X17/Y0/io1' Warning: unmatched constraint 'seq_to_sp_misc_b' (on line 83) Info: constrained 'copi' to bel 'X30/Y0/io1' Info: constrained 'cipo' to bel 'X30/Y0/io0' Warning: unmatched constraint 'pwr_cont2_sp3_pg1' (on line 86) Warning: unmatched constraint 'pwr_cont2_sp3_cfp' (on line 87) Warning: unmatched constraint 'pwr_cont_dimm_nvrhot' (on line 88) Info: constrained 'pwr_cont1_sp3_en' to bel 'X0/Y3/io1' Warning: unmatched constraint 'pwr_cont1_sp3_pg0' (on line 90) Info: constrained 'seq_to_sp3_v1p5_rtc_en' to bel 'X5/Y0/io1' Warning: unmatched constraint 'sp3_to_seq_reset_v3p3_l' (on line 92) Info: constrained 'seq_to_sp3_rsmrst_v3p3_l' to bel 'X6/Y0/io0' Info: constrained 'seq_to_sp3_v0p9_s5_en' to bel 'X11/Y0/io1' Warning: unmatched constraint 'sp3_to_seq_thermtrip_l' (on line 95) Warning: unmatched constraint 'sp3_to_seq_slp_s3_l' (on line 96) Info: constrained 'sclk' to bel 'X31/Y0/io0' Info: constrained 'csn' to bel 'X31/Y0/io1' Info: constrained 'pwr_cont2_sp3_pwrok' to bel 'X33/Y1/io0' Info: constrained 'pwr_cont_dimm_en1' to bel 'X33/Y1/io1' Info: constrained 'pwr_cont_dimm_en0' to bel 'X28/Y0/io0' Warning: unmatched constraint 'pwr_cont1_sp3_pg1' (on line 102) Warning: unmatched constraint 'sp3_to_seq_rtc_v1p5_pg' (on line 103) Warning: unmatched constraint 'sp3_to_seq_pwrok_v3p3' (on line 104) Warning: unmatched constraint 'sp3_to_seq_v0p9_vdd_soc_s5_pg' (on line 105) Info: constrained 'seq_to_nic_comb_pg_l' to bel 'X12/Y0/io1' Info: constrained 'seq_to_sp3_pwr_good' to bel 'X13/Y0/io1' Info: constrained 'seq_to_sp3_pwr_btn_l' to bel 'X14/Y0/io0' Warning: unmatched constraint 'seq_to_sp3_sys_rst_l' (on line 109) Warning: unmatched constraint 'sp3_to_seq_slp_s5_l' (on line 110) Warning: unmatched constraint 'seq_to_sp_misc_c' (on line 111) Info: constrained 'pwr_cont2_sp3_en' to bel 'X24/Y0/io0' Warning: unmatched constraint 'pwr_cont2_sp3_pg0' (on line 113) Warning: unmatched constraint 'pwr_cont2_sp3_nvrhot' (on line 114) Warning: unmatched constraint 'pwr_cont_dimm_cfp' (on line 115) Info: Packing constants.. Info: Packing IOs.. Info: cipo feeds SB_IO cipo_io, removing $nextpnr_iobuf cipo. Info: Packing LUT-FFs.. Info: 226 LCs used as LUT4 only Info: 130 LCs used as LUT4 and DFF Info: Packing non-LUT FFs.. Info: 45 LCs used as DFF only Info: Packing carries.. Info: 0 LCs used as CARRY only Info: Packing indirect carry+LUT pairs... Info: 0 LUTs merged into carry LCs Info: Packing RAMs.. Info: Placing PLLs.. Info: Packing special functions.. Info: Packing PLLs.. Info: Promoting globals.. Info: promoting clk50m$SB_IO_IN (fanout 177) Info: promoting RST_N_SB_LUT4_I3_O [reset] (fanout 116) Info: promoting decode_address_SB_DFFESS_Q_3_D_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI_SB_LUT4_I3_O_SB_LUT4_I1_O[1] [reset] (fanout 16) Info: Constraining chains... Info: 1 LCs used to legalise carry chains. Info: Checksum: 0x2120c4e7 Info: Device utilisation: Info: ICESTORM_LC: 404/ 7680 5% Info: ICESTORM_RAM: 0/ 32 0% Info: SB_IO: 46/ 256 17% Info: SB_GB: 3/ 8 37% Info: ICESTORM_PLL: 0/ 2 0% Info: SB_WARMBOOT: 0/ 1 0% Info: Placed 46 cells based on constraints. Info: Creating initial analytic placement for 392 cells, random placement wirelen = 12858. Info: at initial placer iter 0, wirelen = 115 Info: at initial placer iter 1, wirelen = 115 Info: at initial placer iter 2, wirelen = 115 Info: at initial placer iter 3, wirelen = 115 Info: Running main analytical placer, max placement attempts per cell = 25651. Info: at iteration #1, type ALL: wirelen solved = 115, spread = 1606, legal = 2139; time = 0.01s Info: at iteration #2, type ALL: wirelen solved = 184, spread = 1429, legal = 1777; time = 0.03s Info: at iteration #3, type ALL: wirelen solved = 160, spread = 1426, legal = 1879; time = 0.03s Info: at iteration #4, type ALL: wirelen solved = 214, spread = 1443, legal = 1764; time = 0.01s Info: at iteration #5, type ALL: wirelen solved = 230, spread = 1449, legal = 1791; time = 0.01s Info: at iteration #6, type ALL: wirelen solved = 314, spread = 1469, legal = 1886; time = 0.02s Info: at iteration #7, type ALL: wirelen solved = 355, spread = 1443, legal = 1881; time = 0.01s Info: at iteration #8, type ALL: wirelen solved = 399, spread = 1342, legal = 1725; time = 0.01s Info: at iteration #9, type ALL: wirelen solved = 381, spread = 1401, legal = 1704; time = 0.01s Info: at iteration #10, type ALL: wirelen solved = 519, spread = 1341, legal = 1619; time = 0.01s Info: at iteration #11, type ALL: wirelen solved = 478, spread = 1569, legal = 1697; time = 0.01s Info: at iteration #12, type ALL: wirelen solved = 547, spread = 1292, legal = 1544; time = 0.01s Info: at iteration #13, type ALL: wirelen solved = 618, spread = 1347, legal = 1564; time = 0.01s Info: at iteration #14, type ALL: wirelen solved = 610, spread = 1374, legal = 1632; time = 0.01s Info: at iteration #15, type ALL: wirelen solved = 618, spread = 1519, legal = 1689; time = 0.03s Info: at iteration #16, type ALL: wirelen solved = 659, spread = 1433, legal = 1614; time = 0.03s Info: at iteration #17, type ALL: wirelen solved = 726, spread = 1219, legal = 1533; time = 0.03s Info: at iteration #18, type ALL: wirelen solved = 676, spread = 1191, legal = 1517; time = 0.01s Info: at iteration #19, type ALL: wirelen solved = 664, spread = 1323, legal = 1544; time = 0.01s Info: at iteration #20, type ALL: wirelen solved = 723, spread = 1202, legal = 1433; time = 0.01s Info: at iteration #21, type ALL: wirelen solved = 641, spread = 1216, legal = 1471; time = 0.01s Info: at iteration #22, type ALL: wirelen solved = 690, spread = 1279, legal = 1507; time = 0.01s Info: at iteration #23, type ALL: wirelen solved = 707, spread = 1156, legal = 1433; time = 0.01s Info: at iteration #24, type ALL: wirelen solved = 730, spread = 1384, legal = 1550; time = 0.01s Info: at iteration #25, type ALL: wirelen solved = 828, spread = 1199, legal = 1451; time = 0.01s Info: HeAP Placer Time: 0.55s Info: of which solving equations: 0.35s Info: of which spreading cells: 0.04s Info: of which strict legalisation: 0.07s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 90, wirelen = 1433 Info: at iteration #5: temp = 0.000000, timing cost = 122, wirelen = 1280 Info: at iteration #10: temp = 0.000000, timing cost = 114, wirelen = 1205 Info: at iteration #12: temp = 0.000000, timing cost = 106, wirelen = 1192 Info: SA placement time 0.17s Info: Max frequency for clock 'clk50m$SB_IO_IN_$glb_clk': 110.08 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge clk50m$SB_IO_IN_$glb_clk: 9.34 ns Info: Max delay posedge clk50m$SB_IO_IN_$glb_clk -> : 3.06 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 10916, 11294) |***********+ Info: [ 11294, 11672) |+ Info: [ 11672, 12050) |*****+ Info: [ 12050, 12428) |*****+ Info: [ 12428, 12806) |*************+ Info: [ 12806, 13184) |***+ Info: [ 13184, 13562) |*************************+ Info: [ 13562, 13940) |********** Info: [ 13940, 14318) |****************************+ Info: [ 14318, 14696) |*********+ Info: [ 14696, 15074) |***********************+ Info: [ 15074, 15452) |********************************+ Info: [ 15452, 15830) |***************************+ Info: [ 15830, 16208) |*******************************+ Info: [ 16208, 16586) |*********+ Info: [ 16586, 16964) |************+ Info: [ 16964, 17342) |****+ Info: [ 17342, 17720) |******************************************+ Info: [ 17720, 18098) |********+ Info: [ 18098, 18476) |************************************************************ Info: Checksum: 0xa1882ada Info: Routing.. Info: Setting up routing queue. Info: Routing 1409 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 234 765 | 234 765 | 675| 0.17 0.17| Info: 2000 | 579 1407 | 345 642 | 91| 0.36 0.52| Info: 2106 | 595 1498 | 16 91 | 0| 0.08 0.60| Info: Routing complete. Info: Router1 time 0.60s Info: Checksum: 0x7d2f63af Info: Critical path report for clock 'clk50m$SB_IO_IN_$glb_clk' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source decode_address_SB_DFFESS_Q_1_D_SB_LUT4_O_LC.O Info: 0.6 1.1 Net decode_address[11] (22,6) -> (22,6) Info: Sink regs_status_SB_LUT4_I0_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I0 Info: Defined in: Info: ./env/e220d3dd35fcc1249622910e8f0be4721962889b/hdl/projects/gimlet/sequencer/mkGimletPowerSeqTop.v:354.16-354.30 Info: 0.4 1.6 Source regs_status_SB_LUT4_I0_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O Info: 1.3 2.8 Net regs_status_SB_LUT4_I0_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_I2[3] (22,6) -> (19,3) Info: Sink regs_status_SB_LUT4_I0_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 3.2 Source regs_status_SB_LUT4_I0_O_SB_LUT4_O_I3_SB_LUT4_O_I2_SB_LUT4_O_1_LC.O Info: 0.6 3.8 Net regs_dbgCtrl_reg_SB_DFFESR_Q_E_SB_LUT4_O_I3[1] (19,3) -> (20,3) Info: Sink regs_status_SB_LUT4_I0_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 4.1 Source regs_status_SB_LUT4_I0_I2_SB_LUT4_O_1_I2_SB_LUT4_O_1_LC.O Info: 1.7 5.7 Net regs_status_SB_LUT4_I0_I2_SB_LUT4_O_1_I2[1] (20,3) -> (17,1) Info: Sink regs_power_control_SB_LUT4_I0_I2_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 6.0 Source regs_power_control_SB_LUT4_I0_I2_SB_LUT4_O_LC.O Info: 0.6 6.6 Net IF_regs_power_control_14_BIT_1_15_THEN_2_ELSE__ETC___d419_SB_LUT4_I1_1_I3[1] (17,1) -> (17,1) Info: Sink IF_regs_power_control_14_BIT_1_15_THEN_2_ELSE__ETC___d419_SB_LUT4_I1_1_LC.I2 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 7.0 Source IF_regs_power_control_14_BIT_1_15_THEN_2_ELSE__ETC___d419_SB_LUT4_I1_1_LC.O Info: 0.6 7.6 Net IF_regs_power_control_14_BIT_1_15_THEN_2_ELSE__ETC___d419_SB_LUT4_I1_1_O[1] (17,1) -> (17,1) Info: Sink regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I2_SB_LUT4_O_LC.I1 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 8.0 Source regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I2_SB_LUT4_O_LC.O Info: 0.6 8.6 Net regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_I2[1] (17,1) -> (18,1) Info: Sink regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_LC.I2 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.4 9.0 Setup regs_readdata_SB_DFFESR_Q_4_D_SB_LUT4_O_LC.I2 Info: 3.1 ns logic, 5.9 ns routing Info: Critical path report for cross-domain path '' -> 'posedge clk50m$SB_IO_IN_$glb_clk': Info: curr total Info: 0.0 0.0 Source RST_N$sb_io.D_IN_0 Info: 1.7 1.7 Net RST_N$SB_IO_IN (17,0) -> (6,11) Info: Sink RST_N_SB_LUT4_I3_LC.I3 Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:4837.14-4837.18 Info: 0.3 2.0 Source RST_N_SB_LUT4_I3_LC.O Info: 1.7 3.7 Net RST_N_SB_LUT4_I3_O (6,11) -> (0,16) Info: Sink $gbuf_RST_N_SB_LUT4_I3_O_$glb_sr.USER_SIGNAL_TO_GLOBAL_BUFFER Info: 0.6 4.3 Source $gbuf_RST_N_SB_LUT4_I3_O_$glb_sr.GLOBAL_BUFFER_OUTPUT Info: 0.5 4.8 Net RST_N_SB_LUT4_I3_O_$glb_sr (0,16) -> (15,3) Info: Sink regs_irq_block_cause_SB_DFFSR_Q_6_DFFLC.SR Info: 0.1 4.9 Setup regs_irq_block_cause_SB_DFFSR_Q_6_DFFLC.SR Info: 1.0 ns logic, 3.8 ns routing Info: Critical path report for cross-domain path 'posedge clk50m$SB_IO_IN_$glb_clk' -> '': Info: curr total Info: 0.5 0.5 Source spi_sync_csn_sync.sSyncReg_SB_DFFR_D_DFFLC.O Info: 1.6 2.1 Net decode_is_read_SB_LUT4_I1_1_O_SB_LUT4_I3_I1[0] (24,5) -> (29,1) Info: Sink cipo_io$OUTPUT_ENABLE_SB_LUT4_O_LC.I3 Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ice40/cells_map.v:6.21-6.22 Info: 0.3 2.4 Source cipo_io$OUTPUT_ENABLE_SB_LUT4_O_LC.O Info: 0.6 3.0 Net cipo_io$OUTPUT_ENABLE (29,1) -> (30,0) Info: Sink cipo_io.OUTPUT_ENABLE Info: Defined in: Info: ./env/e220d3dd35fcc1249622910e8f0be4721962889b/hdl/projects/gimlet/sequencer/mkGimletPowerSeqTop.v:559.8-559.29 Info: 0.9 ns logic, 2.2 ns routing Info: Max frequency for clock 'clk50m$SB_IO_IN_$glb_clk': 111.43 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge clk50m$SB_IO_IN_$glb_clk: 4.87 ns Info: Max delay posedge clk50m$SB_IO_IN_$glb_clk -> : 3.03 ns Info: Slack histogram: Info: legend: * represents 1 endpoint(s) Info: + represents [1,1) endpoint(s) Info: [ 11026, 11399) |**+ Info: [ 11399, 11772) | Info: [ 11772, 12145) |**+ Info: [ 12145, 12518) |*********+ Info: [ 12518, 12891) |*******************************+ Info: [ 12891, 13264) |*********************+ Info: [ 13264, 13637) |*************+ Info: [ 13637, 14010) |************ Info: [ 14010, 14383) |*********+ Info: [ 14383, 14756) |**************+ Info: [ 14756, 15129) |*********************+ Info: [ 15129, 15502) |*************************+ Info: [ 15502, 15875) |**********************************+ Info: [ 15875, 16248) |*************************+ Info: [ 16248, 16621) |**************+ Info: [ 16621, 16994) |**** Info: [ 16994, 17367) |*******+ Info: [ 17367, 17740) |********************************+ Info: [ 17740, 18113) |***********+ Info: [ 18113, 18486) |************************************************************ 68 warnings, 0 errors Info: Program finished normally.