Info: constraining clock net 'clk_12mhz' to 12.00 MHz

Info: Logic utilisation before packing:
Info:     Total LUT4s:      5357/83640     6%
Info:         logic LUTs:   4597/83640     5%
Info:         carry LUTs:    760/83640     0%
Info:           RAM LUTs:      0/10455     0%
Info:          RAMW LUTs:      0/20910     0%

Info:      Total DFFs:      2940/83640     3%

Info: Packing IOs..
Info: $aux1_tx$iobuf_i: aux1_tx_$_TBUF__Y.Y
Info: pin 'aux1_tx$tr_io' constrained to Bel 'X0/Y17/PIOA'.
Info: $aux0_tx$iobuf_i: aux0_tx_$_TBUF__Y.Y
Info: pin 'aux0_tx$tr_io' constrained to Bel 'X0/Y14/PIOA'.
Info: pin 'spi_sclk$tr_io' constrained to Bel 'X9/Y95/PIOB'.
Info: pin 'spi_csn$tr_io' constrained to Bel 'X13/Y95/PIOA'.
Info: pin 'spi_copi$tr_io' constrained to Bel 'X11/Y95/PIOB'.
Info: pin 'spi_cipo$tr_io' constrained to Bel 'X11/Y95/PIOA'.
Info: pin 'led[7]$tr_io' constrained to Bel 'X114/Y0/PIOA'.
Info: pin 'led[6]$tr_io' constrained to Bel 'X116/Y0/PIOA'.
Info: pin 'led[5]$tr_io' constrained to Bel 'X114/Y0/PIOB'.
Info: pin 'led[4]$tr_io' constrained to Bel 'X116/Y0/PIOB'.
Info: pin 'led[3]$tr_io' constrained to Bel 'X119/Y0/PIOA'.
Info: pin 'led[2]$tr_io' constrained to Bel 'X119/Y0/PIOB'.
Info: pin 'led[1]$tr_io' constrained to Bel 'X76/Y0/PIOA'.
Info: pin 'led[0]$tr_io' constrained to Bel 'X76/Y0/PIOB'.
Info: pin 'design_reset_l$tr_io' constrained to Bel 'X18/Y95/PIOA'.
Info: pin 'debug$tr_io' constrained to Bel 'X63/Y0/PIOB'.
Info: pin 'clk_12mhz$tr_io' constrained to Bel 'X63/Y0/PIOA'.
Info: pin 'aux1_rx$tr_io' constrained to Bel 'X0/Y17/PIOC'.
Info: pin 'aux0_rx$tr_io' constrained to Bel 'X0/Y14/PIOC'.
Info: Packing constants..
Info: Packing carries...
Info: Packing LUTs...
Info: Packing LUT5-7s...
Info: Packing FFs...
Info:     1727 FFs paired with LUTs.
Info: Generating derived timing constraints...
Info:     Input frequency of PLL 'pll_pll.pll_i' is constrained to 12.0 MHz
Info:     Derived frequency constraint of 100.0 MHz for net pll_pll.CLKOP
Info:     Derived frequency constraint of 50.0 MHz for net controller_ignition_controllers__0_tx.CLK
Info:     Derived frequency constraint of inf MHz for net pll_pll.CLKOS2
Info:     Derived frequency constraint of inf MHz for net pll_pll.CLKOS3
Info: Promoting globals...
Info:     promoting clock net controller_ignition_controllers__0_tx.CLK to global network
Info: Checksum: 0x05f55830

Info: Device utilisation:
Info: 	          TRELLIS_IO:      19/    365     5%
Info: 	                DCCA:       1/     56     1%
Info: 	              DP16KD:       1/    208     0%
Info: 	          MULT18X18D:       0/    156     0%
Info: 	              ALU54B:       0/     78     0%
Info: 	             EHXPLLL:       1/      4    25%
Info: 	             EXTREFB:       0/      2     0%
Info: 	                DCUA:       0/      2     0%
Info: 	           PCSCLKDIV:       0/      2     0%
Info: 	             IOLOGIC:       0/    224     0%
Info: 	            SIOLOGIC:       0/    141     0%
Info: 	                 GSR:       0/      1     0%
Info: 	               JTAGG:       0/      1     0%
Info: 	                OSCG:       0/      1     0%
Info: 	               SEDGA:       0/      1     0%
Info: 	                 DTR:       0/      1     0%
Info: 	             USRMCLK:       0/      1     0%
Info: 	             CLKDIVF:       0/      4     0%
Info: 	           ECLKSYNCB:       0/     10     0%
Info: 	             DLLDELD:       0/      8     0%
Info: 	              DDRDLL:       0/      4     0%
Info: 	             DQSBUFM:       0/     14     0%
Info: 	     TRELLIS_ECLKBUF:       0/      8     0%
Info: 	        ECLKBRIDGECS:       0/      2     0%
Info: 	                DCSC:       0/      2     0%
Info: 	          TRELLIS_FF:    2940/  83640     3%
Info: 	        TRELLIS_COMB:    5645/  83640     6%
Info: 	        TRELLIS_RAMW:       0/  10455     0%

Info: Placed 20 cells based on constraints.
Info: Creating initial analytic placement for 5324 cells, random placement wirelen = 623064.
Info:     at initial placer iter 0, wirelen = 3293
Info:     at initial placer iter 1, wirelen = 2694
Info:     at initial placer iter 2, wirelen = 2565
Info:     at initial placer iter 3, wirelen = 2361
Info: Running main analytical placer, max placement attempts per cell = 9260056.
Info:     at iteration #1, type ALL: wirelen solved = 2344, spread = 55016, legal = 57361; time = 0.20s
Info:     at iteration #2, type ALL: wirelen solved = 6484, spread = 28142, legal = 30985; time = 0.15s
Info:     at iteration #3, type ALL: wirelen solved = 8860, spread = 24578, legal = 27718; time = 0.14s
Info:     at iteration #4, type ALL: wirelen solved = 10119, spread = 22249, legal = 25615; time = 0.14s
Info:     at iteration #5, type ALL: wirelen solved = 10499, spread = 21302, legal = 24100; time = 0.17s
Info:     at iteration #6, type ALL: wirelen solved = 11337, spread = 20477, legal = 23400; time = 0.15s
Info:     at iteration #7, type ALL: wirelen solved = 11995, spread = 19223, legal = 22851; time = 0.14s
Info:     at iteration #8, type ALL: wirelen solved = 12390, spread = 19021, legal = 22443; time = 0.14s
Info:     at iteration #9, type ALL: wirelen solved = 12788, spread = 19203, legal = 22084; time = 0.14s
Info:     at iteration #10, type ALL: wirelen solved = 13184, spread = 18891, legal = 22729; time = 0.15s
Info:     at iteration #11, type ALL: wirelen solved = 13132, spread = 18656, legal = 22244; time = 0.14s
Info:     at iteration #12, type ALL: wirelen solved = 13293, spread = 18846, legal = 22198; time = 0.14s
Info:     at iteration #13, type ALL: wirelen solved = 13671, spread = 18799, legal = 21759; time = 0.14s
Info:     at iteration #14, type ALL: wirelen solved = 13882, spread = 18787, legal = 21666; time = 0.13s
Info:     at iteration #15, type ALL: wirelen solved = 13858, spread = 18712, legal = 22107; time = 0.16s
Info:     at iteration #16, type ALL: wirelen solved = 14088, spread = 18731, legal = 21277; time = 0.14s
Info:     at iteration #17, type ALL: wirelen solved = 14250, spread = 18492, legal = 21218; time = 0.12s
Info:     at iteration #18, type ALL: wirelen solved = 14639, spread = 18408, legal = 20844; time = 0.13s
Info:     at iteration #19, type ALL: wirelen solved = 14536, spread = 18905, legal = 22094; time = 0.12s
Info:     at iteration #20, type ALL: wirelen solved = 14614, spread = 18626, legal = 21715; time = 0.13s
Info:     at iteration #21, type ALL: wirelen solved = 14781, spread = 19162, legal = 21939; time = 0.18s
Info:     at iteration #22, type ALL: wirelen solved = 14841, spread = 18840, legal = 21761; time = 0.16s
Info:     at iteration #23, type ALL: wirelen solved = 14981, spread = 18718, legal = 21445; time = 0.13s
Info: HeAP Placer Time: 5.25s
Info:   of which solving equations: 2.69s
Info:   of which spreading cells: 0.56s
Info:   of which strict legalisation: 0.44s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 568, wirelen = 20844
Info:   at iteration #5: temp = 0.000000, timing cost = 568, wirelen = 18916
Info:   at iteration #10: temp = 0.000000, timing cost = 408, wirelen = 18195
Info:   at iteration #15: temp = 0.000000, timing cost = 568, wirelen = 17739
Info:   at iteration #15: temp = 0.000000, timing cost = 557, wirelen = 17748 
Info: SA placement time 7.88s

Info: Max frequency for clock                           'clk_12mhz$TRELLIS_IO_IN': 1594.90 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$controller_ignition_controllers__0_tx.CLK': 145.71 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                                                   -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 4.51 ns
Info: Max delay <async>                                                   -> posedge clk_12mhz$TRELLIS_IO_IN                          : 5.93 ns
Info: Max delay posedge $glbnet$controller_ignition_controllers__0_tx.CLK -> <async>                                                  : 6.24 ns
Info: Max delay posedge clk_12mhz$TRELLIS_IO_IN                           -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 4.70 ns

Info: Slack histogram:
Info:  legend: * represents 62 endpoint(s)
Info:          + represents [1,62) endpoint(s)
Info: [ 13136,  16615) |************************************+
Info: [ 16615,  20094) |************************************************************ 
Info: [ 20094,  23573) | 
Info: [ 23573,  27052) | 
Info: [ 27052,  30531) | 
Info: [ 30531,  34010) | 
Info: [ 34010,  37489) | 
Info: [ 37489,  40968) | 
Info: [ 40968,  44447) | 
Info: [ 44447,  47926) | 
Info: [ 47926,  51405) | 
Info: [ 51405,  54884) | 
Info: [ 54884,  58363) | 
Info: [ 58363,  61842) | 
Info: [ 61842,  65321) | 
Info: [ 65321,  68800) | 
Info: [ 68800,  72279) | 
Info: [ 72279,  75758) | 
Info: [ 75758,  79237) | 
Info: [ 79237,  82716) |+
Info: Checksum: 0xd1e51b81
Info: Routing globals...
Info:     routing clock net $glbnet$controller_ignition_controllers__0_tx.CLK using global 0

Info: Routing..
Info: Setting up routing queue.
Info: Routing 22372 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |       55        944 |   55   944 |     21467|       0.43       0.43|
Info:       2000 |      173       1826 |  118   882 |     20625|       0.25       0.68|
Info:       3000 |      301       2698 |  128   872 |     19776|       0.23       0.91|
Info:       4000 |      449       3550 |  148   852 |     18926|       0.20       1.11|
Info:       5000 |      565       4434 |  116   884 |     18050|       0.20       1.31|
Info:       6000 |      697       5299 |  132   865 |     17190|       0.19       1.50|
Info:       7000 |      852       6132 |  155   833 |     16365|       0.23       1.72|
Info:       8000 |      985       6967 |  133   835 |     15511|       0.21       1.94|
Info:       9000 |     1128       7810 |  143   843 |     14667|       0.20       2.14|
Info:      10000 |     1289       8615 |  161   805 |     13855|       0.19       2.33|
Info:      11000 |     1405       9441 |  116   826 |     12979|       0.18       2.51|
Info:      12000 |     1525      10285 |  120   844 |     12108|       0.16       2.66|
Info:      13000 |     1680      11090 |  155   805 |     11276|       0.23       2.89|
Info:      14000 |     1854      11861 |  174   771 |     10494|       0.31       3.20|
Info:      15000 |     1980      12655 |  126   794 |      9633|       0.17       3.38|
Info:      16000 |     2105      13464 |  125   809 |      8766|       0.18       3.56|
Info:      17000 |     2274      14222 |  169   758 |      7949|       0.20       3.76|
Info:      18000 |     2396      15011 |  122   789 |      7087|       0.17       3.92|
Info:      19000 |     2517      15841 |  121   830 |      6249|       0.18       4.11|
Info:      20000 |     2652      16667 |  135   826 |      5391|       0.23       4.34|
Info:      21000 |     2783      17482 |  131   815 |      4550|       0.20       4.54|
Info:      22000 |     2930      18308 |  147   826 |      3711|       0.23       4.76|
Info:      23000 |     3063      19169 |  133   861 |      2860|       0.19       4.95|
Info:      24000 |     3180      20048 |  117   879 |      1986|       0.24       5.19|
Info:      25000 |     3377      20851 |  197   803 |      1252|       0.38       5.57|
Info:      26000 |     3536      21581 |  159   730 |       437|       0.24       5.81|
Info:      26447 |     3542      21879 |    6   298 |         0|       0.09       5.90|
Info: Routing complete.
Info: Router1 time 5.90s
Info: Checksum: 0xf83168dd

Info: Critical path report for clock 'clk_12mhz$TRELLIS_IO_IN' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source reset_sync.reset_hold_TRELLIS_FF_Q.Q
Info:  0.3  0.7    Net reset_sync.next_reset[1] (25,25) -> (25,25)
Info:                Sink reset_sync.reset_hold_TRELLIS_FF_DI.M
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:7404.23-7404.33
Info:  0.0  0.7  Setup reset_sync.reset_hold_TRELLIS_FF_DI.M
Info: 0.3 ns logic, 0.3 ns routing

Info: Critical path report for clock '$glbnet$controller_ignition_controllers__0_tx.CLK' (posedge -> posedge):
Info: curr total
Info:  0.3  0.3  Source controller_txrs_rx_channels_0_phase_TRELLIS_FF_Q.Q
Info:  0.8  1.1    Net controller_txrs_rx_channels_0_phase[2] (21,17) -> (20,19)
Info:                Sink WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_LUT4_Z_D_LUT4_Z.A
Info:                Defined in:
Info:                  ./env/e29ef048a8ec3d3b5deea6fd1a3df167298b6907/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:2699.15-2699.50
Info:  0.1  1.2  Source WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_LUT4_Z_D_LUT4_Z.F
Info:  0.6  1.8    Net WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_LUT4_Z_D[3] (20,19) -> (20,19)
Info:                Sink WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_3_LUT4_Z_C_LUT4_D_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_ALUT_LUT4_Z.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  1.9  Source WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_3_LUT4_Z_C_LUT4_D_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_ALUT_LUT4_Z.F
Info:  0.0  1.9    Net WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_3_LUT4_Z_C_LUT4_D_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_ALUT (20,19) -> (20,19)
Info:                Sink WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_3_LUT4_Z_C_LUT4_D_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.F1
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:133.22-133.24
Info:  0.1  2.0  Source WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_3_LUT4_Z_C_LUT4_D_Z_PFUMX_Z_C0_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  0.5  2.5    Net WILL_FIRE_RL_controller_txrs_rx_do_channel_receive_3_LUT4_Z_C_LUT4_D_Z_PFUMX_Z_C0_LUT4_D_Z[3] (20,19) -> (15,19)
Info:                Sink controller_txrs_rx_channels_2_phase$D_IN_PFUMX_Z_1_C0_LUT4_A.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  2.7  Source controller_txrs_rx_channels_2_phase$D_IN_PFUMX_Z_1_C0_LUT4_A.F
Info:  0.9  3.6    Net controller_txrs_deserializers_2_out.empty_reg_LUT4_C_Z[4] (15,19) -> (13,12)
Info:                Sink controller_txrs_rx_channels_1_phase$D_IN_PFUMX_Z_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  3.7  Source controller_txrs_rx_channels_1_phase$D_IN_PFUMX_Z_BLUT_LUT4_Z.OFX
Info:  1.1  4.8    Net controller_txrs_rx_channels_1_phase$D_IN[1] (13,12) -> (12,2)
Info:                Sink controller_txrs_rx_parser_state$D_IN_PFUMX_Z_6_C0_LUT4_Z_2.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  5.0  Source controller_txrs_rx_parser_state$D_IN_PFUMX_Z_6_C0_LUT4_Z_2.F
Info:  0.3  5.3    Net controller_txrs_rx_parser_state$D_IN_PFUMX_Z_6_C0[4] (12,2) -> (12,2)
Info:                Sink controller_txrs_rx_parser_state$D_IN_PFUMX_Z_6_BLUT_LUT4_Z.M
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.2  5.4  Source controller_txrs_rx_parser_state$D_IN_PFUMX_Z_6_BLUT_LUT4_Z.OFX
Info:  0.4  5.8    Net controller_txrs_rx_parser_state$D_IN[14] (12,2) -> (12,3)
Info:                Sink MUX_controller_txrs_rx_channels_0_parser_state$write_1__VAL_2_TRELLIS_FF_Q_33.M
Info:                Defined in:
Info:                  ./env/e29ef048a8ec3d3b5deea6fd1a3df167298b6907/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:3004.16-3004.52
Info:  0.0  5.8  Setup MUX_controller_txrs_rx_channels_0_parser_state$write_1__VAL_2_TRELLIS_FF_Q_33.M
Info: 1.3 ns logic, 4.6 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge $glbnet$controller_ignition_controllers__0_tx.CLK':
Info: curr total
Info:  0.0  0.0  Source spi_sclk$tr_io.O
Info:  3.3  3.3    Net spi_sclk$TRELLIS_IO_IN (9,95) -> (30,47)
Info:                Sink sclk_TRELLIS_FF_Q.M
Info:                Defined in:
Info:                  ./env/e29ef048a8ec3d3b5deea6fd1a3df167298b6907/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:70.10-70.18
Info:  0.0  3.3  Setup sclk_TRELLIS_FF_Q.M
Info: 0.0 ns logic, 3.3 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_12mhz$TRELLIS_IO_IN':
Info: curr total
Info:  0.0  0.0  Source design_reset_l$tr_io.O
Info:  1.5  1.5    Net design_reset_l$TRELLIS_IO_IN (18,95) -> (24,74)
Info:                Sink design_reset_l_LUT4_D.D
Info:                Defined in:
Info:                  ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:7401.23-7401.29
Info:  0.1  1.6  Source design_reset_l_LUT4_D.F
Info:  2.1  3.7    Net design_reset_l_LUT4_D_Z (24,74) -> (25,25)
Info:                Sink reset_sync.reset_hold_TRELLIS_FF_Q.LSR
Info:  0.2  3.9  Setup reset_sync.reset_hold_TRELLIS_FF_Q.LSR
Info: 0.4 ns logic, 3.6 ns routing

Info: Critical path report for cross-domain path 'posedge $glbnet$controller_ignition_controllers__0_tx.CLK' -> '<async>':
Info: curr total
Info:  0.3  0.3  Source spi_cipo_TRELLIS_FF_Q.Q
Info:  4.1  4.4    Net spi_cipo$TRELLIS_IO_OUT (30,24) -> (11,95)
Info:                Sink spi_cipo$tr_io.I
Info:                Defined in:
Info:                  ./env/e29ef048a8ec3d3b5deea6fd1a3df167298b6907/hdl/projects/sidecar/mainboard/emulator/mkSidecarMainboardEmulatorOnEcp5Evn.v:3463.15-3463.31
Info: 0.3 ns logic, 4.1 ns routing

Info: Critical path report for cross-domain path 'posedge clk_12mhz$TRELLIS_IO_IN' -> 'posedge $glbnet$controller_ignition_controllers__0_tx.CLK':
Info: curr total
Info:  0.3  0.3  Source reset_sync.reset_hold_TRELLIS_FF_DI.Q
Info:  1.0  1.3    Net WILL_FIRE_RL_controller_txrs_tx_2_do_deparse_message_LUT4_D_Z[0] (25,25) -> (26,11)
Info:                Sink reset_sync.reset_hold_TRELLIS_FF_DI_Q_LUT4_D.D
Info:                Defined in:
Info:                  /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24
Info:  0.1  1.4  Source reset_sync.reset_hold_TRELLIS_FF_DI_Q_LUT4_D.F
Info:  1.7  3.2    Net reset_sync.reset_hold_TRELLIS_FF_DI_Q_LUT4_D_Z (26,11) -> (48,21)
Info:                Sink controller_tofino_debug_port_request_seq_start_reg_TRELLIS_FF_Q.LSR
Info:  0.2  3.4  Setup controller_tofino_debug_port_request_seq_start_reg_TRELLIS_FF_Q.LSR
Info: 0.7 ns logic, 2.7 ns routing

Info: Max frequency for clock                           'clk_12mhz$TRELLIS_IO_IN': 1524.39 MHz (PASS at 12.00 MHz)
Info: Max frequency for clock '$glbnet$controller_ignition_controllers__0_tx.CLK': 171.67 MHz (PASS at 50.00 MHz)

Info: Max delay <async>                                                   -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 3.28 ns
Info: Max delay <async>                                                   -> posedge clk_12mhz$TRELLIS_IO_IN                          : 3.93 ns
Info: Max delay posedge $glbnet$controller_ignition_controllers__0_tx.CLK -> <async>                                                  : 4.38 ns
Info: Max delay posedge clk_12mhz$TRELLIS_IO_IN                           -> posedge $glbnet$controller_ignition_controllers__0_tx.CLK: 3.39 ns

Info: Slack histogram:
Info:  legend: * represents 60 endpoint(s)
Info:          + represents [1,60) endpoint(s)
Info: [ 14174,  17600) |************************************************************ 
Info: [ 17600,  21026) |****************************************+
Info: [ 21026,  24452) | 
Info: [ 24452,  27878) | 
Info: [ 27878,  31304) | 
Info: [ 31304,  34730) | 
Info: [ 34730,  38156) | 
Info: [ 38156,  41582) | 
Info: [ 41582,  45008) | 
Info: [ 45008,  48434) | 
Info: [ 48434,  51860) | 
Info: [ 51860,  55286) | 
Info: [ 55286,  58712) | 
Info: [ 58712,  62138) | 
Info: [ 62138,  65564) | 
Info: [ 65564,  68990) | 
Info: [ 68990,  72416) | 
Info: [ 72416,  75842) | 
Info: [ 75842,  79268) | 
Info: [ 79268,  82694) |+

Info: Program finished normally.