Info: constraining clock net 'clk_50m_fpga_refclk' to 50.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 25875/43848 59% Info: logic LUTs: 23903/43848 54% Info: carry LUTs: 1972/43848 4% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 15068/43848 34% Info: Packing IOs.. Info: $rsw_s9_aux_dc_p$iobuf_i: rsw_s9_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s9_aux_dc_p$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: $rsw_s8_aux_dc_p$iobuf_i: rsw_s8_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s8_aux_dc_p$tr_io' constrained to Bel 'X90/Y44/PIOA'. Info: $rsw_s7_aux_dc_p$iobuf_i: rsw_s7_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s7_aux_dc_p$tr_io' constrained to Bel 'X90/Y50/PIOA'. Info: $rsw_s6_aux_dc_p$iobuf_i: rsw_s6_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s6_aux_dc_p$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: $rsw_s5_aux_dc_p$iobuf_i: rsw_s5_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s5_aux_dc_p$tr_io' constrained to Bel 'X90/Y62/PIOA'. Info: $rsw_s4_aux_dc_p$iobuf_i: rsw_s4_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s4_aux_dc_p$tr_io' constrained to Bel 'X90/Y47/PIOA'. Info: $rsw_s3_aux_dc_p$iobuf_i: rsw_s3_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s3_aux_dc_p$tr_io' constrained to Bel 'X90/Y65/PIOA'. Info: $rsw_s31_aux_dc_p$iobuf_i: rsw_s31_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s31_aux_dc_p$tr_io' constrained to Bel 'X0/Y56/PIOA'. Info: $rsw_s30_aux_dc_p$iobuf_i: rsw_s30_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s30_aux_dc_p$tr_io' constrained to Bel 'X0/Y53/PIOA'. Info: $rsw_s2_aux_dc_p$iobuf_i: rsw_s2_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s2_aux_dc_p$tr_io' constrained to Bel 'X90/Y68/PIOA'. Info: $rsw_s29_aux_dc_p$iobuf_i: rsw_s29_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s29_aux_dc_p$tr_io' constrained to Bel 'X0/Y68/PIOA'. Info: $rsw_s28_aux_dc_p$iobuf_i: rsw_s28_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s28_aux_dc_p$tr_io' constrained to Bel 'X0/Y65/PIOA'. Info: $rsw_s27_aux_dc_p$iobuf_i: rsw_s27_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s27_aux_dc_p$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: $rsw_s26_aux_dc_p$iobuf_i: rsw_s26_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s26_aux_dc_p$tr_io' constrained to Bel 'X0/Y62/PIOA'. Info: $rsw_s25_aux_dc_p$iobuf_i: rsw_s25_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s25_aux_dc_p$tr_io' constrained to Bel 'X0/Y50/PIOA'. Info: $rsw_s24_aux_dc_p$iobuf_i: rsw_s24_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s24_aux_dc_p$tr_io' constrained to Bel 'X0/Y47/PIOA'. Info: $rsw_s23_aux_dc_p$iobuf_i: rsw_s23_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s23_aux_dc_p$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $rsw_s22_aux_dc_p$iobuf_i: rsw_s22_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s22_aux_dc_p$tr_io' constrained to Bel 'X0/Y41/PIOA'. Info: $rsw_s21_aux_dc_p$iobuf_i: rsw_s21_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s21_aux_dc_p$tr_io' constrained to Bel 'X0/Y38/PIOA'. Info: $rsw_s20_aux_dc_p$iobuf_i: rsw_s20_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s20_aux_dc_p$tr_io' constrained to Bel 'X0/Y35/PIOA'. Info: $rsw_s1_aux_dc_p$iobuf_i: rsw_s1_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s1_aux_dc_p$tr_io' constrained to Bel 'X90/Y53/PIOA'. Info: $rsw_s19_aux_dc_p$iobuf_i: rsw_s19_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s19_aux_dc_p$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: $rsw_s18_aux_dc_p$iobuf_i: rsw_s18_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s18_aux_dc_p$tr_io' constrained to Bel 'X90/Y35/PIOA'. Info: $rsw_s17_aux_dc_p$iobuf_i: rsw_s17_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s17_aux_dc_p$tr_io' constrained to Bel 'X90/Y38/PIOA'. Info: $rsw_s16_aux_dc_p$iobuf_i: rsw_s16_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s16_aux_dc_p$tr_io' constrained to Bel 'X90/Y41/PIOA'. Info: $rsw_s15_aux_dc_p$iobuf_i: rsw_s15_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s15_aux_dc_p$tr_io' constrained to Bel 'X90/Y11/PIOA'. Info: $rsw_s14_aux_dc_p$iobuf_i: rsw_s14_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s14_aux_dc_p$tr_io' constrained to Bel 'X90/Y14/PIOA'. Info: $rsw_s13_aux_dc_p$iobuf_i: rsw_s13_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s13_aux_dc_p$tr_io' constrained to Bel 'X90/Y17/PIOA'. Info: $rsw_s12_aux_dc_p$iobuf_i: rsw_s12_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s12_aux_dc_p$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: $rsw_s11_aux_dc_p$iobuf_i: rsw_s11_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s11_aux_dc_p$tr_io' constrained to Bel 'X90/Y23/PIOA'. Info: $rsw_s10_aux_dc_p$iobuf_i: rsw_s10_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s10_aux_dc_p$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: $rsw_s0_aux_dc_p$iobuf_i: rsw_s0_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s0_aux_dc_p$tr_io' constrained to Bel 'X90/Y56/PIOA'. Info: $ignition_ctrl_to_rsw_b_dc_p$iobuf_i: ignition_ctrl_to_rsw_b_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_rsw_b_dc_p$tr_io' constrained to Bel 'X0/Y17/PIOA'. Info: $ignition_ctrl_to_psc1_dc_p$iobuf_i: ignition_ctrl_to_psc1_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc1_dc_p$tr_io' constrained to Bel 'X0/Y14/PIOA'. Info: $ignition_ctrl_to_psc0_dc_p$iobuf_i: ignition_ctrl_to_psc0_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc0_dc_p$tr_io' constrained to Bel 'X0/Y11/PIOA'. Info: $i2c_fpga_to_tf_sda$iobuf_i: i2c_fpga_to_tf_sda_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_sda$tr_io' constrained to Bel 'X69/Y0/PIOA'. Info: $i2c_fpga_to_tf_scl$iobuf_i: i2c_fpga_to_tf_scl_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_scl$tr_io' constrained to Bel 'X51/Y0/PIOB'. Info: pin 'vr_v1p0_mgmt_to_fpga_pg$tr_io' constrained to Bel 'X85/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_vrhot_l$tr_io' constrained to Bel 'X53/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vddt_pg$tr_io' constrained to Bel 'X47/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vdda15_pg$tr_io' constrained to Bel 'X47/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_fault$tr_io' constrained to Bel 'X27/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_vrhot_l$tr_io' constrained to Bel 'X58/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_pg$tr_io' constrained to Bel 'X58/Y0/PIOB'. Info: pin 'vr_tf_vddcore_to_fpga_fault$tr_io' constrained to Bel 'X31/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vr_hot_l$tr_io' constrained to Bel 'X53/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdda1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdd1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOA'. Info: pin 'vr_tf_v1p8_to_fpga_fault$tr_io' constrained to Bel 'X13/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[2]$tr_io' constrained to Bel 'X83/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[1]$tr_io' constrained to Bel 'X83/Y0/PIOA'. Info: pin 'tf_to_fpga_vid[0]$tr_io' constrained to Bel 'X80/Y0/PIOB'. Info: pin 'tf_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOB'. Info: pin 'tf_pg_led$tr_io' constrained to Bel 'X38/Y0/PIOB'. Info: pin 'spi_sp_to_fpga_sck$tr_io' constrained to Bel 'X18/Y71/PIOA'. Info: pin 'spi_sp_to_fpga_mosi$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_miso_r$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_cs1_l$tr_io' constrained to Bel 'X13/Y71/PIOB'. Info: pin 'sp_to_fpga_design_reset_l$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 's9_rsw_aux_p$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 's8_rsw_aux_p$tr_io' constrained to Bel 'X90/Y44/PIOC'. Info: pin 's7_rsw_aux_p$tr_io' constrained to Bel 'X90/Y50/PIOC'. Info: pin 's6_rsw_aux_p$tr_io' constrained to Bel 'X90/Y59/PIOC'. Info: pin 's5_rsw_aux_p$tr_io' constrained to Bel 'X90/Y62/PIOC'. Info: pin 's4_rsw_aux_p$tr_io' constrained to Bel 'X90/Y47/PIOC'. Info: pin 's3_rsw_aux_p$tr_io' constrained to Bel 'X90/Y65/PIOC'. Info: pin 's31_rsw_aux_p$tr_io' constrained to Bel 'X0/Y56/PIOC'. Info: pin 's30_rsw_aux_p$tr_io' constrained to Bel 'X0/Y53/PIOC'. Info: pin 's2_rsw_aux_p$tr_io' constrained to Bel 'X90/Y68/PIOC'. Info: pin 's29_rsw_aux_p$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: pin 's28_rsw_aux_p$tr_io' constrained to Bel 'X0/Y65/PIOC'. Info: pin 's27_rsw_aux_p$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 's26_rsw_aux_p$tr_io' constrained to Bel 'X0/Y62/PIOC'. Info: pin 's25_rsw_aux_p$tr_io' constrained to Bel 'X0/Y50/PIOC'. Info: pin 's24_rsw_aux_p$tr_io' constrained to Bel 'X0/Y47/PIOC'. Info: pin 's23_rsw_aux_p$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 's22_rsw_aux_p$tr_io' constrained to Bel 'X0/Y41/PIOC'. Info: pin 's21_rsw_aux_p$tr_io' constrained to Bel 'X0/Y38/PIOC'. Info: pin 's20_rsw_aux_p$tr_io' constrained to Bel 'X0/Y35/PIOC'. Info: pin 's1_rsw_aux_p$tr_io' constrained to Bel 'X90/Y53/PIOC'. Info: pin 's19_rsw_aux_p$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: pin 's18_rsw_aux_p$tr_io' constrained to Bel 'X90/Y35/PIOC'. Info: pin 's17_rsw_aux_p$tr_io' constrained to Bel 'X90/Y38/PIOC'. Info: pin 's16_rsw_aux_p$tr_io' constrained to Bel 'X90/Y41/PIOC'. Info: pin 's15_rsw_aux_p$tr_io' constrained to Bel 'X90/Y11/PIOC'. Info: pin 's14_rsw_aux_p$tr_io' constrained to Bel 'X90/Y14/PIOC'. Info: pin 's13_rsw_aux_p$tr_io' constrained to Bel 'X90/Y17/PIOC'. Info: pin 's12_rsw_aux_p$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 's11_rsw_aux_p$tr_io' constrained to Bel 'X90/Y23/PIOC'. Info: pin 's10_rsw_aux_p$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 's0_rsw_aux_p$tr_io' constrained to Bel 'X90/Y56/PIOC'. Info: pin 'pcie_host_to_fpga_perst$tr_io' constrained to Bel 'X9/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_pwrflt$tr_io' constrained to Bel 'X4/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_prsnt_l$tr_io' constrained to Bel 'X4/Y0/PIOA'. Info: pin 'mgmt_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_mgmt_pg$tr_io' constrained to Bel 'X44/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p2_mgmt_pg$tr_io' constrained to Bel 'X49/Y0/PIOB'. Info: pin 'ldo_to_fpga_v0p75_tf_pcie_pg$tr_io' constrained to Bel 'X42/Y0/PIOB'. Info: pin 'ldo_to_fpga_smu_pg$tr_io' constrained to Bel 'X15/Y0/PIOA'. Info: pin 'ignition_rsw_b_to_ctrl_p$tr_io' constrained to Bel 'X0/Y17/PIOC'. Info: pin 'ignition_psc1_to_ctrl_p$tr_io' constrained to Bel 'X0/Y14/PIOC'. Info: pin 'ignition_psc0_to_ctrl_p$tr_io' constrained to Bel 'X0/Y11/PIOC'. Info: pin 'front_io_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y26/PIOD'. Info: pin 'fpga_to_vr_v1p0_mgmt_en$tr_io' constrained to Bel 'X85/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vddx_en$tr_io' constrained to Bel 'X27/Y0/PIOB'. Info: pin 'fpga_to_vr_tf_vddcore_en$tr_io' constrained to Bel 'X33/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdda1p8_en$tr_io' constrained to Bel 'X20/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdd1p8_en$tr_io' constrained to Bel 'X18/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[3]$tr_io' constrained to Bel 'X76/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[2]$tr_io' constrained to Bel 'X78/Y0/PIOA'. Info: pin 'fpga_to_tf_test_jtsel[1]$tr_io' constrained to Bel 'X78/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[0]$tr_io' constrained to Bel 'X80/Y0/PIOA'. Info: pin 'fpga_to_tf_test_core_tap_l$tr_io' constrained to Bel 'X76/Y0/PIOA'. Info: pin 'fpga_to_tf_pwron_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOB'. Info: pin 'fpga_to_tf_pcie_rst_l$tr_io' constrained to Bel 'X71/Y0/PIOB'. Info: pin 'fpga_to_tf_core_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOA'. Info: pin 'fpga_to_smu_tf_clk_en_l$tr_io' constrained to Bel 'X20/Y0/PIOB'. Info: pin 'fpga_to_smu_reset_l$tr_io' constrained to Bel 'X31/Y0/PIOA'. Info: pin 'fpga_to_smu_mgmt_clk_en_l$tr_io' constrained to Bel 'X38/Y0/PIOA'. Info: pin 'fpga_to_phy4_reset_l$tr_io' constrained to Bel 'X0/Y29/PIOB'. Info: pin 'fpga_to_mgmt_reset_l$tr_io' constrained to Bel 'X29/Y0/PIOB'. Info: pin 'fpga_to_ldo_v2p5_mgmt_en$tr_io' constrained to Bel 'X44/Y0/PIOA'. Info: pin 'fpga_to_ldo_v1p2_mgmt_en$tr_io' constrained to Bel 'X49/Y0/PIOA'. Info: pin 'fpga_to_ldo_v0p75_tf_pcie_en$tr_io' constrained to Bel 'X42/Y0/PIOA'. Info: pin 'fpga_to_ldo_smu_en$tr_io' constrained to Bel 'X15/Y0/PIOB'. Info: pin 'fpga_to_front_io_hsc_en$tr_io' constrained to Bel 'X0/Y26/PIOC'. Info: pin 'fpga_to_fan3_led_l$tr_io' constrained to Bel 'X29/Y0/PIOA'. Info: pin 'fpga_to_fan3_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: pin 'fpga_to_fan2_led_l$tr_io' constrained to Bel 'X22/Y0/PIOA'. Info: pin 'fpga_to_fan2_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: pin 'fpga_to_fan1_led_l$tr_io' constrained to Bel 'X18/Y0/PIOA'. Info: pin 'fpga_to_fan1_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOA'. Info: pin 'fpga_to_fan0_led_l$tr_io' constrained to Bel 'X13/Y0/PIOA'. Info: pin 'fpga_to_fan0_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOC'. Info: pin 'fpga_led0$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'fpga_debug1$tr_io' constrained to Bel 'X33/Y0/PIOB'. Info: pin 'fpga_debug0$tr_io' constrained to Bel 'X36/Y0/PIOB'. Info: pin 'fan3_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOB'. Info: pin 'fan3_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOB'. Info: pin 'fan2_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOA'. Info: pin 'fan2_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOD'. Info: pin 'fan1_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOD'. Info: pin 'fan1_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOB'. Info: pin 'fan0_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOC'. Info: pin 'fan0_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOD'. Info: pin 'clk_50m_fpga_refclk$tr_io' constrained to Bel 'X36/Y0/PIOA'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 7334 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk_50m_fpga_refclk$TRELLIS_IO_IN to global network Info: Checksum: 0x81ebb258 Info: Device utilisation: Info: TRELLIS_IO: 146/ 245 59% Info: DCCA: 1/ 56 1% Info: DP16KD: 2/ 108 1% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 15068/ 43848 34% Info: TRELLIS_COMB: 26950/ 43848 61% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 146 cells based on constraints. Info: Creating initial analytic placement for 28985 cells, random placement wirelen = 2338080. Info: at initial placer iter 0, wirelen = 25558 Info: at initial placer iter 1, wirelen = 17023 Info: at initial placer iter 2, wirelen = 16054 Info: at initial placer iter 3, wirelen = 15368 Info: Running main analytical placer, max placement attempts per cell = 222256986. Info: at iteration #1, type ALL: wirelen solved = 14414, spread = 288116, legal = 313033; time = 1.74s Info: at iteration #2, type ALL: wirelen solved = 53530, spread = 147199, legal = 161936; time = 1.04s Info: at iteration #3, type ALL: wirelen solved = 66786, spread = 120487, legal = 140215; time = 0.98s Info: at iteration #4, type ALL: wirelen solved = 69707, spread = 114320, legal = 133529; time = 0.96s Info: at iteration #5, type ALL: wirelen solved = 73440, spread = 110866, legal = 128918; time = 0.98s Info: at iteration #6, type ALL: wirelen solved = 76689, spread = 112948, legal = 127547; time = 0.87s Info: at iteration #7, type ALL: wirelen solved = 81210, spread = 109721, legal = 124394; time = 0.92s Info: at iteration #8, type ALL: wirelen solved = 82522, spread = 107575, legal = 123998; time = 0.92s Info: at iteration #9, type ALL: wirelen solved = 83836, spread = 107051, legal = 123161; time = 0.94s Info: at iteration #10, type ALL: wirelen solved = 84588, spread = 106590, legal = 122030; time = 0.93s Info: at iteration #11, type ALL: wirelen solved = 85345, spread = 106405, legal = 122722; time = 0.86s Info: at iteration #12, type ALL: wirelen solved = 86039, spread = 107752, legal = 122761; time = 0.92s Info: at iteration #13, type ALL: wirelen solved = 87051, spread = 107164, legal = 122643; time = 0.94s Info: at iteration #14, type ALL: wirelen solved = 88632, spread = 110045, legal = 123034; time = 0.88s Info: at iteration #15, type ALL: wirelen solved = 90832, spread = 108297, legal = 120446; time = 0.87s Info: at iteration #16, type ALL: wirelen solved = 90171, spread = 108782, legal = 120445; time = 0.91s Info: at iteration #17, type ALL: wirelen solved = 91276, spread = 109895, legal = 122332; time = 0.91s Info: at iteration #18, type ALL: wirelen solved = 92381, spread = 110795, legal = 122357; time = 0.87s Info: at iteration #19, type ALL: wirelen solved = 92900, spread = 110852, legal = 122067; time = 0.90s Info: at iteration #20, type ALL: wirelen solved = 93698, spread = 110908, legal = 122874; time = 0.86s Info: at iteration #21, type ALL: wirelen solved = 94186, spread = 110514, legal = 122377; time = 0.89s Info: HeAP Placer Time: 30.20s Info: of which solving equations: 15.44s Info: of which spreading cells: 4.30s Info: of which strict legalisation: 2.96s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 2693, wirelen = 120445 Info: at iteration #5: temp = 0.000000, timing cost = 3004, wirelen = 107415 Info: at iteration #10: temp = 0.000000, timing cost = 1786, wirelen = 104261 Info: at iteration #15: temp = 0.000000, timing cost = 1658, wirelen = 102148 Info: at iteration #20: temp = 0.000000, timing cost = 1582, wirelen = 101540 Info: at iteration #25: temp = 0.000000, timing cost = 1903, wirelen = 101154 Info: at iteration #27: temp = 0.000000, timing cost = 1822, wirelen = 101088 Info: SA placement time 76.79s Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 64.75 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 4.90 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 8.84 ns Info: Slack histogram: Info: legend: * represents 68 endpoint(s) Info: + represents [1,68) endpoint(s) Info: [ 4556, 5291) |+ Info: [ 5291, 6026) |+ Info: [ 6026, 6761) |*+ Info: [ 6761, 7496) |****+ Info: [ 7496, 8231) |*********+ Info: [ 8231, 8966) |*********+ Info: [ 8966, 9701) |***********+ Info: [ 9701, 10436) |*************+ Info: [ 10436, 11171) |*********************+ Info: [ 11171, 11906) |**********************+ Info: [ 11906, 12641) |********************+ Info: [ 12641, 13376) |*****************************+ Info: [ 13376, 14111) |**************************************+ Info: [ 14111, 14846) |***************************************+ Info: [ 14846, 15581) |***************************************+ Info: [ 15581, 16316) |****************************************+ Info: [ 16316, 17051) |******************************************+ Info: [ 17051, 17786) |***********************************+ Info: [ 17786, 18521) |*********************+ Info: [ 18521, 19256) |************************************************************ Info: Checksum: 0x79c8c25a Info: Routing globals... Info: routing clock net $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 110327 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 19 980 | 19 980 | 109417| 1.72 1.72| Info: 2000 | 54 1945 | 35 965 | 108504| 0.31 2.03| Info: 3000 | 111 2888 | 57 943 | 107571| 0.26 2.29| Info: 4000 | 189 3810 | 78 922 | 106659| 0.26 2.55| Info: 5000 | 275 4724 | 86 914 | 105752| 0.23 2.78| Info: 6000 | 354 5645 | 79 921 | 104884| 0.26 3.04| Info: 7000 | 438 6561 | 84 916 | 103976| 0.27 3.31| Info: 8000 | 516 7483 | 78 922 | 103067| 0.27 3.58| Info: 9000 | 613 8386 | 97 903 | 102180| 0.25 3.83| Info: 10000 | 692 9307 | 79 921 | 101291| 0.24 4.07| Info: 11000 | 780 10219 | 88 912 | 100388| 0.25 4.32| Info: 12000 | 899 11100 | 119 881 | 99520| 0.27 4.59| Info: 13000 | 986 12013 | 87 913 | 98607| 0.25 4.84| Info: 14000 | 1099 12900 | 113 887 | 97734| 0.26 5.11| Info: 15000 | 1215 13784 | 116 884 | 96871| 0.26 5.37| Info: 16000 | 1323 14676 | 108 892 | 95994| 0.30 5.68| Info: 17000 | 1460 15539 | 137 863 | 95141| 0.26 5.93| Info: 18000 | 1587 16412 | 127 873 | 94281| 0.26 6.20| Info: 19000 | 1692 17307 | 105 895 | 93396| 0.26 6.46| Info: 20000 | 1834 18165 | 142 858 | 92556| 0.28 6.73| Info: 21000 | 1963 19036 | 129 871 | 91716| 0.27 7.01| Info: 22000 | 2078 19917 | 115 881 | 90844| 0.26 7.26| Info: 23000 | 2198 20797 | 120 880 | 89970| 0.26 7.52| Info: 24000 | 2320 21674 | 122 877 | 89100| 0.27 7.79| Info: 25000 | 2422 22572 | 102 898 | 88243| 0.25 8.04| Info: 26000 | 2554 23429 | 132 857 | 87380| 0.27 8.31| Info: 27000 | 2696 24280 | 142 851 | 86536| 0.25 8.56| Info: 28000 | 2843 25115 | 147 835 | 85690| 0.25 8.81| Info: 29000 | 2989 25944 | 146 829 | 84861| 0.27 9.08| Info: 30000 | 3105 26799 | 116 855 | 83984| 0.24 9.32| Info: 31000 | 3241 27623 | 136 824 | 83149| 0.25 9.57| Info: 32000 | 3337 28500 | 96 877 | 82254| 0.26 9.82| Info: 33000 | 3437 29366 | 100 866 | 81371| 0.27 10.09| Info: 34000 | 3512 30268 | 75 902 | 80457| 0.31 10.39| Info: 35000 | 3598 31163 | 86 895 | 79550| 0.25 10.65| Info: 36000 | 3739 31987 | 141 824 | 78697| 0.24 10.89| Info: 37000 | 3852 32842 | 113 855 | 77845| 0.26 11.15| Info: 38000 | 3973 33691 | 121 849 | 76969| 0.27 11.42| Info: 39000 | 4071 34565 | 98 874 | 76070| 0.27 11.69| Info: 40000 | 4178 35428 | 107 863 | 75187| 0.26 11.95| Info: 41000 | 4292 36275 | 114 847 | 74315| 0.25 12.20| Info: 42000 | 4393 37159 | 101 884 | 73431| 0.27 12.47| Info: 43000 | 4476 38033 | 83 874 | 72516| 0.28 12.75| Info: 44000 | 4611 38868 | 135 835 | 71659| 0.26 13.01| Info: 45000 | 4712 39703 | 101 835 | 70771| 0.25 13.26| Info: 46000 | 4825 40538 | 113 835 | 69888| 0.28 13.54| Info: 47000 | 4935 41360 | 110 822 | 69003| 0.29 13.82| Info: 48000 | 5044 42160 | 109 800 | 68115| 0.26 14.08| Info: 49000 | 5172 42981 | 128 821 | 67280| 0.31 14.39| Info: 50000 | 5263 43834 | 91 853 | 66372| 0.27 14.66| Info: 51000 | 5387 44634 | 124 800 | 65505| 0.27 14.93| Info: 52000 | 5505 45487 | 118 853 | 64649| 0.29 15.23| Info: 53000 | 5629 46334 | 124 847 | 63781| 0.30 15.52| Info: 54000 | 5741 47197 | 112 863 | 62895| 0.29 15.82| Info: 55000 | 5878 48012 | 137 815 | 62040| 0.29 16.10| Info: 56000 | 5966 48889 | 88 877 | 61135| 0.27 16.37| Info: 57000 | 6083 49748 | 117 859 | 60266| 0.28 16.65| Info: 58000 | 6209 50599 | 126 851 | 59404| 0.30 16.96| Info: 59000 | 6322 51472 | 113 873 | 58531| 0.31 17.27| Info: 60000 | 6452 52319 | 130 847 | 57677| 0.29 17.56| Info: 61000 | 6570 53183 | 118 864 | 56806| 0.30 17.86| Info: 62000 | 6667 54068 | 97 885 | 55910| 0.30 18.16| Info: 63000 | 6798 54922 | 131 854 | 55048| 0.31 18.47| Info: 64000 | 6924 55788 | 126 866 | 54179| 0.30 18.77| Info: 65000 | 7053 56638 | 129 850 | 53333| 0.28 19.05| Info: 66000 | 7160 57520 | 107 882 | 52444| 0.28 19.33| Info: 67000 | 7312 58343 | 152 823 | 51614| 0.31 19.63| Info: 68000 | 7456 59180 | 144 837 | 50779| 0.30 19.93| Info: 69000 | 7583 60038 | 127 858 | 49916| 0.31 20.24| Info: 70000 | 7716 60886 | 133 848 | 49064| 0.30 20.55| Info: 71000 | 7830 61756 | 114 870 | 48189| 0.30 20.84| Info: 72000 | 7973 62595 | 143 839 | 47346| 0.33 21.17| Info: 73000 | 8094 63443 | 121 848 | 46479| 0.40 21.57| Info: 74000 | 8217 64284 | 123 841 | 45607| 0.29 21.86| Info: 75000 | 8350 65132 | 133 848 | 44762| 0.32 22.18| Info: 76000 | 8444 65998 | 94 866 | 43865| 0.34 22.52| Info: 77000 | 8588 66798 | 144 800 | 43046| 0.32 22.84| Info: 78000 | 8712 67660 | 124 862 | 42187| 0.31 23.15| Info: 79000 | 8879 68435 | 167 775 | 41368| 0.32 23.47| Info: 80000 | 9032 69261 | 153 826 | 40548| 0.35 23.82| Info: 81000 | 9162 70087 | 130 826 | 39686| 0.34 24.16| Info: 82000 | 9323 70879 | 161 792 | 38865| 0.33 24.49| Info: 83000 | 9450 71692 | 127 813 | 37999| 0.31 24.79| Info: 84000 | 9597 72475 | 147 783 | 37159| 0.30 25.09| Info: 85000 | 9739 73309 | 142 834 | 36311| 0.31 25.40| Info: 86000 | 9883 74115 | 144 806 | 35462| 0.33 25.73| Info: 87000 | 10030 74946 | 147 831 | 34679| 0.37 26.11| Info: 88000 | 10135 75777 | 105 831 | 33791| 0.33 26.44| Info: 89000 | 10255 76619 | 120 842 | 32921| 0.33 26.77| Info: 90000 | 10416 77400 | 161 781 | 32123| 0.33 27.10| Info: 91000 | 10556 78161 | 140 761 | 31308| 0.32 27.43| Info: 92000 | 10701 78972 | 145 811 | 30459| 0.34 27.77| Info: 93000 | 10815 79770 | 114 798 | 29584| 0.32 28.09| Info: 94000 | 10968 80551 | 153 781 | 28750| 0.30 28.39| Info: 95000 | 11094 81341 | 126 790 | 27880| 0.31 28.70| Info: 96000 | 11219 82180 | 125 839 | 27016| 0.32 29.02| Info: 97000 | 11363 82991 | 144 811 | 26175| 0.32 29.34| Info: 98000 | 11492 83821 | 129 830 | 25307| 0.37 29.70| Info: 99000 | 11589 84690 | 97 869 | 24413| 0.46 30.16| Info: 100000 | 11756 85466 | 167 776 | 23594| 0.38 30.53| Info: 101000 | 11926 86267 | 170 801 | 22789| 0.37 30.91| Info: 102000 | 12074 87040 | 148 773 | 21952| 0.34 31.24| Info: 103000 | 12231 87828 | 157 788 | 21131| 0.40 31.64| Info: 104000 | 12397 88647 | 166 819 | 20325| 0.36 32.00| Info: 105000 | 12549 89426 | 152 779 | 19489| 0.36 32.37| Info: 106000 | 12687 90218 | 138 792 | 18643| 0.33 32.70| Info: 107000 | 12832 91051 | 145 833 | 17797| 0.36 33.06| Info: 108000 | 12982 91894 | 150 843 | 16985| 0.51 33.57| Info: 109000 | 13154 92707 | 172 813 | 16194| 0.37 33.94| Info: 110000 | 13286 93572 | 132 865 | 15336| 0.33 34.26| Info: 111000 | 13430 94428 | 144 856 | 14484| 0.40 34.66| Info: 112000 | 13598 95260 | 168 832 | 13659| 0.37 35.03| Info: 113000 | 13820 96026 | 222 766 | 12897| 0.44 35.46| Info: 114000 | 13964 96874 | 144 848 | 12062| 0.46 35.93| Info: 115000 | 14142 97696 | 178 822 | 11276| 0.50 36.43| Info: 116000 | 14309 98529 | 167 833 | 10456| 0.40 36.83| Info: 117000 | 14489 99349 | 180 820 | 9661| 0.40 37.23| Info: 118000 | 14668 100170 | 179 821 | 8856| 0.41 37.63| Info: 119000 | 14868 100970 | 200 800 | 8104| 0.61 38.24| Info: 120000 | 15084 101754 | 216 784 | 7391| 0.80 39.04| Info: 121000 | 15210 102628 | 126 874 | 6535| 0.44 39.48| Info: 122000 | 15352 103486 | 142 858 | 5727| 0.45 39.93| Info: 123000 | 15578 104260 | 226 774 | 5015| 0.63 40.56| Info: 124000 | 15844 104994 | 266 734 | 4362| 0.68 41.23| Info: 125000 | 16102 105736 | 258 742 | 3820| 0.56 41.79| Info: 126000 | 16350 106488 | 248 752 | 3075| 0.48 42.27| Info: 127000 | 16532 107169 | 182 681 | 2265| 0.42 42.70| Info: 128000 | 16541 107780 | 9 611 | 1281| 0.46 43.16| Info: 129000 | 16565 108391 | 24 611 | 315| 0.37 43.52| Info: 129316 | 16566 108591 | 1 200 | 0| 0.30 43.83| Info: Routing complete. Info: Router1 time 43.83s Info: Checksum: 0x0c93ac0f Info: Critical path report for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source ignition_io_bank6_1_txrs_rx_decode_result.D_OUT_TRELLIS_FF_Q.Q Info: 0.9 1.4 Net ignition_io_bank6_1_txrs_rx_decode_result.D_OUT[13] (18,47) -> (18,47) Info: Sink ignition_io_bank6_1_txrs_rx_decode_result.empty_reg_LUT4_D.A Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2052.27-2052.32 Info: 0.2 1.7 Source ignition_io_bank6_1_txrs_rx_decode_result.empty_reg_LUT4_D.F Info: 1.0 2.7 Net ignition_io_bank6_1_txrs_rx_channels_4_phase$D_IN_LUT4_Z_1_D[3] (18,47) -> (20,44) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_4_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 2.9 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_4_LUT4_Z.F Info: 1.1 4.0 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_4 (20,44) -> (19,45) Info: Sink ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_Z_D_LUT4_Z.B Info: Defined in: Info: ./env/07f530d0893a5a6d4332fb9670c37e32dca19f8d/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:20164.8-20164.66 Info: 0.2 4.3 Source ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_Z_D_LUT4_Z.F Info: 0.4 4.7 Net ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_Z_D[2] (19,45) -> (19,45) Info: Sink ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 4.9 Source ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_Z.F Info: 0.7 5.7 Net ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D[2] (19,45) -> (19,48) Info: Sink ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 5.9 Source ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z.F Info: 1.3 7.2 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z[2] (19,48) -> (23,51) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.M Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 7.4 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D1_L6MUX21_Z_D0_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 0.8 8.2 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z[4] (23,51) -> (19,49) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input$FULL_N_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 8.5 Source ignition_io_bank6_1_txrs_rx_decode_input$FULL_N_LUT4_Z.F Info: 0.7 9.2 Net ignition_io_bank6_1_txrs_rx_decode_input.FULL_N (19,49) -> (19,48) Info: Sink ignition_io_bank6_1_txrs_deserializers_5_out.empty_reg_LUT4_A_1.C Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2050.26-2050.32 Info: 0.2 9.4 Source ignition_io_bank6_1_txrs_deserializers_5_out.empty_reg_LUT4_A_1.F Info: 1.0 10.4 Net ignition_io_bank6_1_txrs_deserializers_5_out.empty_reg_LUT4_A_1_Z[1] (19,48) -> (19,45) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z_1.C Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 10.6 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z_1.F Info: 1.1 11.7 Net ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI[14] (19,45) -> (19,51) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_C.C Info: Defined in: Info: ./env/07f530d0893a5a6d4332fb9670c37e32dca19f8d/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:0.0-0.0 Info: ./env/07f530d0893a5a6d4332fb9670c37e32dca19f8d/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:103034.5-103055.12 Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/techmap.v:578.19-578.22 Info: 0.2 12.0 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_C.F Info: 1.2 13.2 Net ignition_io_bank6_1_txrs_rx_channels_1_rd_LUT4_A_Z[3] (19,51) -> (19,45) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 13.4 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR_LUT4_Z.F Info: 0.2 13.6 Net ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR (19,45) -> (19,45) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_2.LSR Info: 0.4 14.0 Setup ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_2.LSR Info: 3.6 ns logic, 10.5 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source sp_to_fpga_design_reset_l$tr_io.O Info: 1.3 1.3 Net sp_to_fpga_design_reset_l$TRELLIS_IO_IN (4,71) -> (7,67) Info: Sink sp_to_fpga_design_reset_l_LUT4_D.D Info: Defined in: Info: ./env/07f530d0893a5a6d4332fb9670c37e32dca19f8d/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:413.10-413.35 Info: 0.2 1.5 Source sp_to_fpga_design_reset_l_LUT4_D.F Info: 1.5 3.0 Net sp_to_fpga_design_reset_l_LUT4_D_Z (7,67) -> (25,65) Info: Sink reset_sync.reset_hold_TRELLIS_FF_DI.LSR Info: 0.4 3.4 Setup reset_sync.reset_hold_TRELLIS_FF_DI.LSR Info: 0.7 ns logic, 2.7 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' -> '': Info: curr total Info: 0.5 0.5 Source ignition_io_bank3_1_io_4_tx_enable_sync_TRELLIS_FF_Q.Q Info: 3.1 3.7 Net ignition_io_bank3_1_io_4_tx_enable_sync (62,33) -> (78,55) Info: Sink rsw_s3_aux_dc_p$tr_io$invert_T.A Info: Defined in: Info: ./env/07f530d0893a5a6d4332fb9670c37e32dca19f8d/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTopRevB.v:16992.7-16992.46 Info: 0.2 3.9 Source rsw_s3_aux_dc_p$tr_io$invert_T.F Info: 2.3 6.2 Net rsw_s3_aux_dc_p$tr_io$invert_T$conn$Z (78,55) -> (90,65) Info: Sink rsw_s3_aux_dc_p$tr_io.T Info: 0.8 ns logic, 5.4 ns routing Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 71.26 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 3.38 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 6.17 ns Info: Slack histogram: Info: legend: * represents 74 endpoint(s) Info: + represents [1,74) endpoint(s) Info: [ 5967, 6623) |+ Info: [ 6623, 7279) |+ Info: [ 7279, 7935) |+ Info: [ 7935, 8591) |*+ Info: [ 8591, 9247) |*+ Info: [ 9247, 9903) |***+ Info: [ 9903, 10559) |*****+ Info: [ 10559, 11215) |*************+ Info: [ 11215, 11871) |***************+ Info: [ 11871, 12527) |**************************+ Info: [ 12527, 13183) |*******************************+ Info: [ 13183, 13839) |**************************************+ Info: [ 13839, 14495) |*****************************************+ Info: [ 14495, 15151) |*******************************+ Info: [ 15151, 15807) |****************************+ Info: [ 15807, 16463) |******************************+ Info: [ 16463, 17119) |****************************************+ Info: [ 17119, 17775) |*******************************+ Info: [ 17775, 18431) |***************************+ Info: [ 18431, 19087) |************************************************************ Info: Program finished normally.