Info: constraining clock net 'clk_50m_fpga_refclk' to 50.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 26399/43848 60% Info: logic LUTs: 24427/43848 55% Info: carry LUTs: 1972/43848 4% Info: RAM LUTs: 0/ 5481 0% Info: RAMW LUTs: 0/10962 0% Info: Total DFFs: 15131/43848 34% Info: Packing IOs.. Info: $rsw_s9_aux_dc_p$iobuf_i: rsw_s9_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s9_aux_dc_p$tr_io' constrained to Bel 'X90/Y29/PIOA'. Info: $rsw_s8_aux_dc_p$iobuf_i: rsw_s8_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s8_aux_dc_p$tr_io' constrained to Bel 'X90/Y44/PIOA'. Info: $rsw_s7_aux_dc_p$iobuf_i: rsw_s7_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s7_aux_dc_p$tr_io' constrained to Bel 'X90/Y50/PIOA'. Info: $rsw_s6_aux_dc_p$iobuf_i: rsw_s6_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s6_aux_dc_p$tr_io' constrained to Bel 'X90/Y59/PIOA'. Info: $rsw_s5_aux_dc_p$iobuf_i: rsw_s5_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s5_aux_dc_p$tr_io' constrained to Bel 'X90/Y62/PIOA'. Info: $rsw_s4_aux_dc_p$iobuf_i: rsw_s4_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s4_aux_dc_p$tr_io' constrained to Bel 'X90/Y47/PIOA'. Info: $rsw_s3_aux_dc_p$iobuf_i: rsw_s3_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s3_aux_dc_p$tr_io' constrained to Bel 'X90/Y65/PIOA'. Info: $rsw_s31_aux_dc_p$iobuf_i: rsw_s31_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s31_aux_dc_p$tr_io' constrained to Bel 'X0/Y56/PIOA'. Info: $rsw_s30_aux_dc_p$iobuf_i: rsw_s30_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s30_aux_dc_p$tr_io' constrained to Bel 'X0/Y53/PIOA'. Info: $rsw_s2_aux_dc_p$iobuf_i: rsw_s2_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s2_aux_dc_p$tr_io' constrained to Bel 'X90/Y68/PIOA'. Info: $rsw_s29_aux_dc_p$iobuf_i: rsw_s29_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s29_aux_dc_p$tr_io' constrained to Bel 'X0/Y68/PIOA'. Info: $rsw_s28_aux_dc_p$iobuf_i: rsw_s28_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s28_aux_dc_p$tr_io' constrained to Bel 'X0/Y65/PIOA'. Info: $rsw_s27_aux_dc_p$iobuf_i: rsw_s27_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s27_aux_dc_p$tr_io' constrained to Bel 'X0/Y59/PIOA'. Info: $rsw_s26_aux_dc_p$iobuf_i: rsw_s26_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s26_aux_dc_p$tr_io' constrained to Bel 'X0/Y62/PIOA'. Info: $rsw_s25_aux_dc_p$iobuf_i: rsw_s25_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s25_aux_dc_p$tr_io' constrained to Bel 'X0/Y50/PIOA'. Info: $rsw_s24_aux_dc_p$iobuf_i: rsw_s24_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s24_aux_dc_p$tr_io' constrained to Bel 'X0/Y47/PIOA'. Info: $rsw_s23_aux_dc_p$iobuf_i: rsw_s23_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s23_aux_dc_p$tr_io' constrained to Bel 'X0/Y44/PIOA'. Info: $rsw_s22_aux_dc_p$iobuf_i: rsw_s22_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s22_aux_dc_p$tr_io' constrained to Bel 'X0/Y41/PIOA'. Info: $rsw_s21_aux_dc_p$iobuf_i: rsw_s21_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s21_aux_dc_p$tr_io' constrained to Bel 'X0/Y38/PIOA'. Info: $rsw_s20_aux_dc_p$iobuf_i: rsw_s20_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s20_aux_dc_p$tr_io' constrained to Bel 'X0/Y35/PIOA'. Info: $rsw_s1_aux_dc_p$iobuf_i: rsw_s1_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s1_aux_dc_p$tr_io' constrained to Bel 'X90/Y53/PIOA'. Info: $rsw_s19_aux_dc_p$iobuf_i: rsw_s19_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s19_aux_dc_p$tr_io' constrained to Bel 'X90/Y32/PIOA'. Info: $rsw_s18_aux_dc_p$iobuf_i: rsw_s18_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s18_aux_dc_p$tr_io' constrained to Bel 'X90/Y35/PIOA'. Info: $rsw_s17_aux_dc_p$iobuf_i: rsw_s17_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s17_aux_dc_p$tr_io' constrained to Bel 'X90/Y38/PIOA'. Info: $rsw_s16_aux_dc_p$iobuf_i: rsw_s16_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s16_aux_dc_p$tr_io' constrained to Bel 'X90/Y41/PIOA'. Info: $rsw_s15_aux_dc_p$iobuf_i: rsw_s15_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s15_aux_dc_p$tr_io' constrained to Bel 'X90/Y11/PIOA'. Info: $rsw_s14_aux_dc_p$iobuf_i: rsw_s14_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s14_aux_dc_p$tr_io' constrained to Bel 'X90/Y14/PIOA'. Info: $rsw_s13_aux_dc_p$iobuf_i: rsw_s13_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s13_aux_dc_p$tr_io' constrained to Bel 'X90/Y17/PIOA'. Info: $rsw_s12_aux_dc_p$iobuf_i: rsw_s12_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s12_aux_dc_p$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: $rsw_s11_aux_dc_p$iobuf_i: rsw_s11_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s11_aux_dc_p$tr_io' constrained to Bel 'X90/Y23/PIOA'. Info: $rsw_s10_aux_dc_p$iobuf_i: rsw_s10_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s10_aux_dc_p$tr_io' constrained to Bel 'X90/Y26/PIOA'. Info: $rsw_s0_aux_dc_p$iobuf_i: rsw_s0_aux_dc_p_$_TBUF__Y.Y Info: pin 'rsw_s0_aux_dc_p$tr_io' constrained to Bel 'X90/Y56/PIOA'. Info: $ignition_ctrl_to_self_dc_p$iobuf_i: ignition_ctrl_to_self_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_self_dc_p$tr_io' constrained to Bel 'X0/Y32/PIOA'. Info: $ignition_ctrl_to_rsw_b_dc_p$iobuf_i: ignition_ctrl_to_rsw_b_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_rsw_b_dc_p$tr_io' constrained to Bel 'X0/Y17/PIOA'. Info: $ignition_ctrl_to_psc1_dc_p$iobuf_i: ignition_ctrl_to_psc1_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc1_dc_p$tr_io' constrained to Bel 'X0/Y14/PIOA'. Info: $ignition_ctrl_to_psc0_dc_p$iobuf_i: ignition_ctrl_to_psc0_dc_p_$_TBUF__Y.Y Info: pin 'ignition_ctrl_to_psc0_dc_p$tr_io' constrained to Bel 'X0/Y11/PIOA'. Info: $i2c_fpga_to_tf_sda$iobuf_i: i2c_fpga_to_tf_sda_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_sda$tr_io' constrained to Bel 'X69/Y0/PIOA'. Info: $i2c_fpga_to_tf_scl$iobuf_i: i2c_fpga_to_tf_scl_$_TBUF__Y.Y Info: pin 'i2c_fpga_to_tf_scl$tr_io' constrained to Bel 'X51/Y0/PIOB'. Info: pin 'vr_v1p0_mgmt_to_fpga_pg$tr_io' constrained to Bel 'X85/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_vrhot_l$tr_io' constrained to Bel 'X53/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vddt_pg$tr_io' constrained to Bel 'X47/Y0/PIOA'. Info: pin 'vr_tf_vddx_to_fpga_vdda15_pg$tr_io' constrained to Bel 'X47/Y0/PIOB'. Info: pin 'vr_tf_vddx_to_fpga_fault$tr_io' constrained to Bel 'X27/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_vrhot_l$tr_io' constrained to Bel 'X58/Y0/PIOA'. Info: pin 'vr_tf_vddcore_to_fpga_pg$tr_io' constrained to Bel 'X58/Y0/PIOB'. Info: pin 'vr_tf_vddcore_to_fpga_fault$tr_io' constrained to Bel 'X31/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vr_hot_l$tr_io' constrained to Bel 'X53/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdda1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOB'. Info: pin 'vr_tf_v1p8_to_fpga_vdd1p8_pg$tr_io' constrained to Bel 'X56/Y0/PIOA'. Info: pin 'vr_tf_v1p8_to_fpga_fault$tr_io' constrained to Bel 'X13/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[2]$tr_io' constrained to Bel 'X83/Y0/PIOB'. Info: pin 'tf_to_fpga_vid[1]$tr_io' constrained to Bel 'X83/Y0/PIOA'. Info: pin 'tf_to_fpga_vid[0]$tr_io' constrained to Bel 'X80/Y0/PIOB'. Info: pin 'tf_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOB'. Info: pin 'tf_pg_led$tr_io' constrained to Bel 'X38/Y0/PIOB'. Info: pin 'spi_sp_to_fpga_sck$tr_io' constrained to Bel 'X18/Y71/PIOA'. Info: pin 'spi_sp_to_fpga_mosi$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_miso_r$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'spi_sp_to_fpga_cs1_l$tr_io' constrained to Bel 'X13/Y71/PIOB'. Info: pin 'sp_to_fpga_design_reset_l$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 's9_rsw_aux_p$tr_io' constrained to Bel 'X90/Y29/PIOC'. Info: pin 's8_rsw_aux_p$tr_io' constrained to Bel 'X90/Y44/PIOC'. Info: pin 's7_rsw_aux_p$tr_io' constrained to Bel 'X90/Y50/PIOC'. Info: pin 's6_rsw_aux_p$tr_io' constrained to Bel 'X90/Y59/PIOC'. Info: pin 's5_rsw_aux_p$tr_io' constrained to Bel 'X90/Y62/PIOC'. Info: pin 's4_rsw_aux_p$tr_io' constrained to Bel 'X90/Y47/PIOC'. Info: pin 's3_rsw_aux_p$tr_io' constrained to Bel 'X90/Y65/PIOC'. Info: pin 's31_rsw_aux_p$tr_io' constrained to Bel 'X0/Y56/PIOC'. Info: pin 's30_rsw_aux_p$tr_io' constrained to Bel 'X0/Y53/PIOC'. Info: pin 's2_rsw_aux_p$tr_io' constrained to Bel 'X90/Y68/PIOC'. Info: pin 's29_rsw_aux_p$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: pin 's28_rsw_aux_p$tr_io' constrained to Bel 'X0/Y65/PIOC'. Info: pin 's27_rsw_aux_p$tr_io' constrained to Bel 'X0/Y59/PIOC'. Info: pin 's26_rsw_aux_p$tr_io' constrained to Bel 'X0/Y62/PIOC'. Info: pin 's25_rsw_aux_p$tr_io' constrained to Bel 'X0/Y50/PIOC'. Info: pin 's24_rsw_aux_p$tr_io' constrained to Bel 'X0/Y47/PIOC'. Info: pin 's23_rsw_aux_p$tr_io' constrained to Bel 'X0/Y44/PIOC'. Info: pin 's22_rsw_aux_p$tr_io' constrained to Bel 'X0/Y41/PIOC'. Info: pin 's21_rsw_aux_p$tr_io' constrained to Bel 'X0/Y38/PIOC'. Info: pin 's20_rsw_aux_p$tr_io' constrained to Bel 'X0/Y35/PIOC'. Info: pin 's1_rsw_aux_p$tr_io' constrained to Bel 'X90/Y53/PIOC'. Info: pin 's19_rsw_aux_p$tr_io' constrained to Bel 'X90/Y32/PIOC'. Info: pin 's18_rsw_aux_p$tr_io' constrained to Bel 'X90/Y35/PIOC'. Info: pin 's17_rsw_aux_p$tr_io' constrained to Bel 'X90/Y38/PIOC'. Info: pin 's16_rsw_aux_p$tr_io' constrained to Bel 'X90/Y41/PIOC'. Info: pin 's15_rsw_aux_p$tr_io' constrained to Bel 'X90/Y11/PIOC'. Info: pin 's14_rsw_aux_p$tr_io' constrained to Bel 'X90/Y14/PIOC'. Info: pin 's13_rsw_aux_p$tr_io' constrained to Bel 'X90/Y17/PIOC'. Info: pin 's12_rsw_aux_p$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 's11_rsw_aux_p$tr_io' constrained to Bel 'X90/Y23/PIOC'. Info: pin 's10_rsw_aux_p$tr_io' constrained to Bel 'X90/Y26/PIOC'. Info: pin 's0_rsw_aux_p$tr_io' constrained to Bel 'X90/Y56/PIOC'. Info: pin 'pcie_host_to_fpga_perst$tr_io' constrained to Bel 'X9/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_pwrflt$tr_io' constrained to Bel 'X4/Y0/PIOB'. Info: pin 'pcie_fpga_to_host_prsnt_l$tr_io' constrained to Bel 'X4/Y0/PIOA'. Info: pin 'mgmt_to_fpga_temp_therm_l$tr_io' constrained to Bel 'X11/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_phy4_pg$tr_io' constrained to Bel 'X51/Y0/PIOA'. Info: pin 'ldo_to_fpga_v2p5_mgmt_pg$tr_io' constrained to Bel 'X44/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p2_mgmt_pg$tr_io' constrained to Bel 'X49/Y0/PIOB'. Info: pin 'ldo_to_fpga_v1p0_phy4_pg$tr_io' constrained to Bel 'X69/Y0/PIOB'. Info: pin 'ldo_to_fpga_v0p75_tf_pcie_pg$tr_io' constrained to Bel 'X42/Y0/PIOB'. Info: pin 'ldo_to_fpga_smu_pg$tr_io' constrained to Bel 'X15/Y0/PIOA'. Info: pin 'ignition_target_to_self_p$tr_io' constrained to Bel 'X0/Y32/PIOC'. Info: pin 'ignition_rsw_b_to_ctrl_p$tr_io' constrained to Bel 'X0/Y17/PIOC'. Info: pin 'ignition_psc1_to_ctrl_p$tr_io' constrained to Bel 'X0/Y14/PIOC'. Info: pin 'ignition_psc0_to_ctrl_p$tr_io' constrained to Bel 'X0/Y11/PIOC'. Info: pin 'front_io_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y26/PIOD'. Info: pin 'fpga_to_vr_v1p0_mgmt_en$tr_io' constrained to Bel 'X85/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vddx_en$tr_io' constrained to Bel 'X27/Y0/PIOB'. Info: pin 'fpga_to_vr_tf_vddcore_en$tr_io' constrained to Bel 'X33/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdda1p8_en$tr_io' constrained to Bel 'X20/Y0/PIOA'. Info: pin 'fpga_to_vr_tf_vdd1p8_en$tr_io' constrained to Bel 'X18/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[3]$tr_io' constrained to Bel 'X76/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[2]$tr_io' constrained to Bel 'X78/Y0/PIOA'. Info: pin 'fpga_to_tf_test_jtsel[1]$tr_io' constrained to Bel 'X78/Y0/PIOB'. Info: pin 'fpga_to_tf_test_jtsel[0]$tr_io' constrained to Bel 'X80/Y0/PIOA'. Info: pin 'fpga_to_tf_test_core_tap_l$tr_io' constrained to Bel 'X76/Y0/PIOA'. Info: pin 'fpga_to_tf_pwron_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOB'. Info: pin 'fpga_to_tf_pcie_rst_l$tr_io' constrained to Bel 'X71/Y0/PIOB'. Info: pin 'fpga_to_tf_core_rst_l$tr_io' constrained to Bel 'X74/Y0/PIOA'. Info: pin 'fpga_to_smu_tf_clk_en_l$tr_io' constrained to Bel 'X20/Y0/PIOB'. Info: pin 'fpga_to_smu_reset_l$tr_io' constrained to Bel 'X31/Y0/PIOA'. Info: pin 'fpga_to_smu_mgmt_clk_en_l$tr_io' constrained to Bel 'X38/Y0/PIOA'. Info: pin 'fpga_to_phy4_reset_l$tr_io' constrained to Bel 'X0/Y29/PIOB'. Info: pin 'fpga_to_mgmt_reset_l$tr_io' constrained to Bel 'X29/Y0/PIOB'. Info: pin 'fpga_to_ldo_v2p5_mgmt_en$tr_io' constrained to Bel 'X44/Y0/PIOA'. Info: pin 'fpga_to_ldo_v1p2_mgmt_en$tr_io' constrained to Bel 'X49/Y0/PIOA'. Info: pin 'fpga_to_ldo_v0p75_tf_pcie_en$tr_io' constrained to Bel 'X42/Y0/PIOA'. Info: pin 'fpga_to_ldo_smu_en$tr_io' constrained to Bel 'X15/Y0/PIOB'. Info: pin 'fpga_to_ldo_phy4_en$tr_io' constrained to Bel 'X24/Y0/PIOA'. Info: pin 'fpga_to_front_io_hsc_en$tr_io' constrained to Bel 'X0/Y26/PIOC'. Info: pin 'fpga_to_fan3_led_l$tr_io' constrained to Bel 'X29/Y0/PIOA'. Info: pin 'fpga_to_fan3_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOA'. Info: pin 'fpga_to_fan2_led_l$tr_io' constrained to Bel 'X22/Y0/PIOA'. Info: pin 'fpga_to_fan2_hsc_en$tr_io' constrained to Bel 'X0/Y23/PIOC'. Info: pin 'fpga_to_fan1_led_l$tr_io' constrained to Bel 'X18/Y0/PIOA'. Info: pin 'fpga_to_fan1_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOA'. Info: pin 'fpga_to_fan0_led_l$tr_io' constrained to Bel 'X13/Y0/PIOA'. Info: pin 'fpga_to_fan0_hsc_en$tr_io' constrained to Bel 'X0/Y20/PIOC'. Info: pin 'fpga_led0$tr_io' constrained to Bel 'X15/Y71/PIOB'. Info: pin 'fpga_debug1$tr_io' constrained to Bel 'X33/Y0/PIOB'. Info: pin 'fpga_debug0$tr_io' constrained to Bel 'X36/Y0/PIOB'. Info: pin 'fan3_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOB'. Info: pin 'fan3_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOB'. Info: pin 'fan2_to_fpga_present$tr_io' constrained to Bel 'X0/Y26/PIOA'. Info: pin 'fan2_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y23/PIOD'. Info: pin 'fan1_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOD'. Info: pin 'fan1_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOB'. Info: pin 'fan0_to_fpga_present$tr_io' constrained to Bel 'X0/Y29/PIOC'. Info: pin 'fan0_hsc_to_fpga_pg$tr_io' constrained to Bel 'X0/Y20/PIOD'. Info: pin 'clk_50m_fpga_refclk$tr_io' constrained to Bel 'X36/Y0/PIOA'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 7285 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk_50m_fpga_refclk$TRELLIS_IO_IN to global network Info: Checksum: 0xe37f5768 Info: Device utilisation: Info: TRELLIS_IO: 151/ 245 61% Info: DCCA: 1/ 56 1% Info: DP16KD: 2/ 108 1% Info: MULT18X18D: 0/ 72 0% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 15131/ 43848 34% Info: TRELLIS_COMB: 27475/ 43848 62% Info: TRELLIS_RAMW: 0/ 5481 0% Info: Placed 151 cells based on constraints. Info: Creating initial analytic placement for 29143 cells, random placement wirelen = 2333541. Info: at initial placer iter 0, wirelen = 25764 Info: at initial placer iter 1, wirelen = 17515 Info: at initial placer iter 2, wirelen = 16014 Info: at initial placer iter 3, wirelen = 15322 Info: Running main analytical placer, max placement attempts per cell = 228552200. Info: at iteration #1, type ALL: wirelen solved = 16391, spread = 303530, legal = 323283; time = 1.41s Info: at iteration #2, type ALL: wirelen solved = 54486, spread = 155282, legal = 175130; time = 1.36s Info: at iteration #3, type ALL: wirelen solved = 68068, spread = 127772, legal = 145831; time = 1.02s Info: at iteration #4, type ALL: wirelen solved = 72803, spread = 118675, legal = 136580; time = 0.92s Info: at iteration #5, type ALL: wirelen solved = 76462, spread = 115379, legal = 133499; time = 0.93s Info: at iteration #6, type ALL: wirelen solved = 79013, spread = 110467, legal = 129414; time = 0.98s Info: at iteration #7, type ALL: wirelen solved = 80637, spread = 109737, legal = 128339; time = 0.84s Info: at iteration #8, type ALL: wirelen solved = 83043, spread = 108294, legal = 126315; time = 0.84s Info: at iteration #9, type ALL: wirelen solved = 84458, spread = 107394, legal = 125881; time = 0.96s Info: at iteration #10, type ALL: wirelen solved = 85819, spread = 108973, legal = 125614; time = 0.91s Info: at iteration #11, type ALL: wirelen solved = 87774, spread = 107568, legal = 124855; time = 0.94s Info: at iteration #12, type ALL: wirelen solved = 87927, spread = 108820, legal = 125111; time = 0.93s Info: at iteration #13, type ALL: wirelen solved = 89026, spread = 108008, legal = 124288; time = 0.90s Info: at iteration #14, type ALL: wirelen solved = 89835, spread = 108135, legal = 123674; time = 0.83s Info: at iteration #15, type ALL: wirelen solved = 90744, spread = 107951, legal = 123904; time = 0.91s Info: at iteration #16, type ALL: wirelen solved = 91257, spread = 107704, legal = 123815; time = 0.92s Info: at iteration #17, type ALL: wirelen solved = 92375, spread = 109863, legal = 124611; time = 0.91s Info: at iteration #18, type ALL: wirelen solved = 93832, spread = 109025, legal = 124284; time = 0.90s Info: at iteration #19, type ALL: wirelen solved = 93921, spread = 109392, legal = 123871; time = 0.93s Info: HeAP Placer Time: 28.00s Info: of which solving equations: 14.51s Info: of which spreading cells: 3.84s Info: of which strict legalisation: 2.81s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 2660, wirelen = 123674 Info: at iteration #5: temp = 0.000000, timing cost = 4325, wirelen = 110129 Info: at iteration #10: temp = 0.000000, timing cost = 3880, wirelen = 106222 Info: at iteration #15: temp = 0.000000, timing cost = 3604, wirelen = 103991 Info: at iteration #20: temp = 0.000000, timing cost = 4024, wirelen = 103277 Info: at iteration #25: temp = 0.000000, timing cost = 3499, wirelen = 102936 Info: at iteration #30: temp = 0.000000, timing cost = 3803, wirelen = 102845 Info: at iteration #31: temp = 0.000000, timing cost = 3030, wirelen = 102821 Info: SA placement time 89.63s Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 66.91 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 3.22 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 8.68 ns Info: Slack histogram: Info: legend: * represents 69 endpoint(s) Info: + represents [1,69) endpoint(s) Info: [ 5055, 5765) |*+ Info: [ 5765, 6475) |****+ Info: [ 6475, 7185) |*******+ Info: [ 7185, 7895) |*********+ Info: [ 7895, 8605) |*********+ Info: [ 8605, 9315) |********+ Info: [ 9315, 10025) |**********+ Info: [ 10025, 10735) |*************+ Info: [ 10735, 11445) |********************+ Info: [ 11445, 12155) |**********************+ Info: [ 12155, 12865) |*********************+ Info: [ 12865, 13575) |***************************+ Info: [ 13575, 14285) |************************************+ Info: [ 14285, 14995) |************************************+ Info: [ 14995, 15705) |*****************************************+ Info: [ 15705, 16415) |********************************************* Info: [ 16415, 17125) |******************************************+ Info: [ 17125, 17835) |****************************+ Info: [ 17835, 18545) |*****************+ Info: [ 18545, 19255) |************************************************************ Info: Checksum: 0x12c4c239 Info: Routing globals... Info: routing clock net $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN using global 0 Info: Routing.. Info: Setting up routing queue. Info: Routing 111942 arcs. Info: | (re-)routed arcs | delta | remaining| time spent | Info: IterCnt | w/ripup wo/ripup | w/r wo/r | arcs| batch(sec) total(sec)| Info: 1000 | 24 975 | 24 975 | 110979| 1.89 1.89| Info: 2000 | 85 1914 | 61 939 | 110115| 0.31 2.19| Info: 3000 | 145 2854 | 60 940 | 109260| 0.28 2.48| Info: 4000 | 213 3786 | 68 932 | 108347| 0.27 2.74| Info: 5000 | 303 4696 | 90 910 | 107439| 0.25 2.99| Info: 6000 | 409 5590 | 106 894 | 106600| 0.25 3.25| Info: 7000 | 513 6486 | 104 896 | 105786| 0.28 3.53| Info: 8000 | 602 7397 | 89 911 | 104881| 0.26 3.79| Info: 9000 | 685 8314 | 83 917 | 104015| 0.26 4.05| Info: 10000 | 789 9210 | 104 896 | 103189| 0.28 4.33| Info: 11000 | 905 10094 | 116 884 | 102337| 0.25 4.58| Info: 12000 | 1017 10982 | 112 888 | 101487| 0.26 4.85| Info: 13000 | 1128 11871 | 111 889 | 100654| 0.28 5.13| Info: 14000 | 1222 12777 | 94 906 | 99764| 0.27 5.40| Info: 15000 | 1367 13632 | 145 855 | 98955| 0.27 5.67| Info: 16000 | 1465 14534 | 98 902 | 98104| 0.30 5.97| Info: 17000 | 1574 15425 | 109 891 | 97240| 0.28 6.25| Info: 18000 | 1693 16306 | 119 881 | 96377| 0.29 6.53| Info: 19000 | 1839 17160 | 146 854 | 95584| 0.30 6.84| Info: 20000 | 1962 18037 | 123 877 | 94713| 0.26 7.10| Info: 21000 | 2094 18905 | 132 868 | 93898| 0.30 7.39| Info: 22000 | 2224 19775 | 130 870 | 93040| 0.25 7.65| Info: 23000 | 2349 20650 | 125 875 | 92172| 0.29 7.94| Info: 24000 | 2461 21538 | 112 888 | 91294| 0.27 8.21| Info: 25000 | 2593 22406 | 132 868 | 90516| 0.27 8.48| Info: 26000 | 2704 23295 | 111 889 | 89650| 0.27 8.75| Info: 27000 | 2842 24150 | 138 855 | 88806| 0.26 9.01| Info: 28000 | 3007 24985 | 165 835 | 88019| 0.27 9.28| Info: 29000 | 3158 25824 | 151 839 | 87209| 0.29 9.57| Info: 30000 | 3324 26644 | 166 820 | 86406| 0.26 9.83| Info: 31000 | 3455 27495 | 131 851 | 85584| 0.28 10.11| Info: 32000 | 3736 28204 | 281 709 | 85425| 0.41 10.52| Info: 33000 | 4057 28881 | 321 677 | 85130| 0.50 11.02| Info: 34000 | 4219 29690 | 162 809 | 84308| 0.26 11.28| Info: 35000 | 4350 30520 | 131 830 | 83454| 0.26 11.54| Info: 36000 | 4481 31364 | 131 844 | 82592| 0.33 11.87| Info: 37000 | 4614 32193 | 133 829 | 81740| 0.24 12.11| Info: 38000 | 4741 33027 | 127 834 | 80878| 0.25 12.36| Info: 39000 | 4858 33884 | 117 857 | 80004| 0.26 12.62| Info: 40000 | 4980 34747 | 122 863 | 79150| 0.28 12.90| Info: 41000 | 5136 35560 | 156 813 | 78362| 0.27 13.17| Info: 42000 | 5249 36422 | 113 862 | 77485| 0.25 13.42| Info: 43000 | 5346 37284 | 97 862 | 76598| 0.25 13.67| Info: 44000 | 5469 38133 | 123 849 | 75742| 0.29 13.96| Info: 45000 | 5590 38980 | 121 847 | 74877| 0.27 14.24| Info: 46000 | 5709 39845 | 119 865 | 74006| 0.28 14.51| Info: 47000 | 5816 40687 | 107 842 | 73127| 0.29 14.81| Info: 48000 | 5919 41536 | 103 849 | 72239| 0.29 15.10| Info: 49000 | 6036 42345 | 117 809 | 71362| 0.27 15.37| Info: 50000 | 6147 43184 | 111 839 | 70477| 0.27 15.64| Info: 51000 | 6263 44005 | 116 821 | 69612| 0.28 15.92| Info: 52000 | 6395 44806 | 132 801 | 68772| 0.28 16.20| Info: 53000 | 6522 45601 | 127 795 | 67927| 0.28 16.48| Info: 54000 | 6634 46418 | 112 817 | 67048| 0.28 16.76| Info: 55000 | 6733 47274 | 99 856 | 66161| 0.29 17.05| Info: 56000 | 6819 48147 | 86 873 | 65262| 0.28 17.34| Info: 57000 | 6923 49002 | 104 855 | 64373| 0.29 17.62| Info: 58000 | 7042 49836 | 119 834 | 63498| 0.27 17.89| Info: 59000 | 7146 50703 | 104 867 | 62614| 0.27 18.16| Info: 60000 | 7273 51549 | 127 846 | 61758| 0.28 18.43| Info: 61000 | 7382 52405 | 109 856 | 60873| 0.29 18.72| Info: 62000 | 7496 53265 | 114 860 | 59996| 0.28 19.00| Info: 63000 | 7632 54109 | 136 844 | 59144| 0.30 19.30| Info: 64000 | 7747 54985 | 115 876 | 58278| 0.30 19.60| Info: 65000 | 7867 55830 | 120 845 | 57410| 0.30 19.90| Info: 66000 | 7995 56685 | 128 855 | 56554| 0.30 20.21| Info: 67000 | 8125 57532 | 130 847 | 55730| 0.31 20.51| Info: 68000 | 8251 58383 | 126 851 | 54878| 0.31 20.82| Info: 69000 | 8383 59225 | 132 842 | 54025| 0.31 21.13| Info: 70000 | 8538 60029 | 155 804 | 53216| 0.29 21.43| Info: 71000 | 8690 60860 | 152 831 | 52379| 0.30 21.73| Info: 72000 | 8830 61692 | 140 832 | 51549| 0.31 22.04| Info: 73000 | 8959 62537 | 129 845 | 50709| 0.33 22.37| Info: 74000 | 9085 63405 | 126 868 | 49853| 0.33 22.69| Info: 75000 | 9210 64256 | 125 851 | 48994| 0.32 23.01| Info: 76000 | 9349 65077 | 139 821 | 48161| 0.40 23.41| Info: 77000 | 9523 65876 | 174 799 | 47364| 0.34 23.75| Info: 78000 | 9647 66707 | 124 831 | 46492| 0.32 24.07| Info: 79000 | 9831 67490 | 184 783 | 45714| 0.32 24.39| Info: 80000 | 9981 68298 | 150 808 | 44876| 0.31 24.71| Info: 81000 | 10103 69137 | 122 839 | 44035| 0.36 25.06| Info: 82000 | 10235 69964 | 132 827 | 43176| 0.33 25.39| Info: 83000 | 10399 70754 | 164 790 | 42366| 0.34 25.73| Info: 84000 | 10538 71579 | 139 825 | 41516| 0.33 26.07| Info: 85000 | 10685 72377 | 147 798 | 40684| 0.35 26.42| Info: 86000 | 10817 73203 | 132 826 | 39845| 0.38 26.80| Info: 87000 | 10984 73983 | 167 780 | 39093| 0.36 27.16| Info: 88000 | 11126 74783 | 142 800 | 38242| 0.31 27.47| Info: 89000 | 11304 75570 | 178 787 | 37436| 0.35 27.82| Info: 90000 | 11467 76341 | 163 771 | 36631| 0.34 28.16| Info: 91000 | 11627 77133 | 160 792 | 35799| 0.35 28.52| Info: 92000 | 11780 77924 | 153 791 | 34964| 0.37 28.88| Info: 93000 | 11935 78681 | 155 757 | 34134| 0.40 29.28| Info: 94000 | 12076 79527 | 141 846 | 33307| 0.35 29.63| Info: 95000 | 12229 80315 | 153 788 | 32481| 0.37 30.01| Info: 96000 | 12381 81089 | 152 774 | 31679| 0.36 30.37| Info: 97000 | 12546 81850 | 165 761 | 30864| 0.35 30.72| Info: 98000 | 12659 82697 | 113 847 | 29989| 0.35 31.07| Info: 99000 | 12801 83460 | 142 763 | 29142| 0.38 31.45| Info: 100000 | 12971 84236 | 170 776 | 28397| 0.37 31.82| Info: 101000 | 13124 85003 | 153 767 | 27592| 0.37 32.19| Info: 102000 | 13262 85831 | 138 828 | 26740| 0.37 32.56| Info: 103000 | 13401 86647 | 139 816 | 25890| 0.35 32.91| Info: 104000 | 13540 87472 | 139 825 | 25044| 0.39 33.30| Info: 105000 | 13697 88273 | 157 801 | 24217| 0.46 33.75| Info: 106000 | 13882 89050 | 185 777 | 23430| 0.40 34.16| Info: 107000 | 14101 89807 | 219 757 | 22693| 0.41 34.57| Info: 108000 | 14302 90537 | 201 730 | 21912| 0.40 34.97| Info: 109000 | 14468 91366 | 166 829 | 21091| 0.42 35.38| Info: 110000 | 14670 92121 | 202 755 | 20314| 0.39 35.78| Info: 111000 | 14833 92926 | 163 805 | 19498| 0.36 36.13| Info: 112000 | 14990 93693 | 157 767 | 18683| 0.39 36.52| Info: 113000 | 15161 94482 | 171 789 | 17874| 0.42 36.93| Info: 114000 | 15372 95253 | 211 771 | 17100| 0.43 37.37| Info: 115000 | 15522 96093 | 150 840 | 16272| 0.50 37.87| Info: 116000 | 15733 96870 | 211 777 | 15537| 0.42 38.29| Info: 117000 | 15884 97719 | 151 849 | 14694| 0.43 38.72| Info: 118000 | 16025 98578 | 141 859 | 13849| 0.40 39.13| Info: 119000 | 16246 99344 | 221 766 | 13095| 0.43 39.55| Info: 120000 | 16521 100069 | 275 725 | 12403| 0.49 40.05| Info: 121000 | 16695 100887 | 174 818 | 11618| 0.62 40.67| Info: 122000 | 16904 101678 | 209 791 | 10851| 0.51 41.18| Info: 123000 | 17134 102448 | 230 770 | 10094| 0.43 41.61| Info: 124000 | 17326 103256 | 192 808 | 9303| 0.46 42.07| Info: 125000 | 17516 104066 | 190 810 | 8516| 0.45 42.53| Info: 126000 | 17730 104852 | 214 786 | 7826| 0.82 43.34| Info: 127000 | 17955 105627 | 225 775 | 7122| 0.87 44.21| Info: 128000 | 18039 106543 | 84 916 | 6230| 0.40 44.62| Info: 129000 | 18236 107346 | 197 803 | 5509| 0.50 45.11| Info: 130000 | 18540 108042 | 304 696 | 4907| 0.61 45.72| Info: 131000 | 18848 108734 | 308 692 | 4349| 0.60 46.32| Info: 132000 | 19180 109402 | 332 668 | 3783| 0.62 46.94| Info: 133000 | 19426 110156 | 246 754 | 3037| 0.42 47.36| Info: 134000 | 19561 110795 | 135 639 | 2174| 0.39 47.75| Info: 135000 | 19581 111381 | 20 586 | 1202| 0.41 48.16| Info: 136000 | 19590 111973 | 9 592 | 211| 0.37 48.52| Info: 136210 | 19590 112103 | 0 130 | 0| 0.27 48.79| Info: Routing complete. Info: Router1 time 48.79s Info: Checksum: 0x3953e5ad Info: Critical path report for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' (posedge -> posedge): Info: curr total Info: 0.5 0.5 Source ignition_io_bank6_1_txrs_rx_decode_result.empty_reg_TRELLIS_FF_Q.Q Info: 0.9 1.4 Net ignition_io_bank6_1_txrs_rx_decode_result.EMPTY_N (19,49) -> (19,48) Info: Sink ignition_io_bank6_1_txrs_rx_channels_5_phase$D_IN_LUT4_Z_2_D_LUT4_Z.D Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2056.27-2056.36 Info: 0.2 1.7 Source ignition_io_bank6_1_txrs_rx_channels_5_phase$D_IN_LUT4_Z_2_D_LUT4_Z.F Info: 0.8 2.4 Net ignition_io_bank6_1_txrs_rx_channels_5_phase$D_IN_LUT4_Z_2_D[4] (19,48) -> (17,47) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_5_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 2.7 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_5_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 1.4 4.0 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_5 (17,47) -> (18,51) Info: Sink ignition_io_bank6_1_txrs_rx_channels_4_phase$D_IN_LUT4_Z_2_C_LUT4_B_Z_LUT4_Z_1.A Info: Defined in: Info: ./env/4ec60555ef603e5fb7beffbcbfa5f2a0b1c3ef2b/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:20283.8-20283.66 Info: 0.2 4.3 Source ignition_io_bank6_1_txrs_rx_channels_4_phase$D_IN_LUT4_Z_2_C_LUT4_B_Z_LUT4_Z_1.F Info: 1.7 5.9 Net ignition_io_bank6_1_txrs_rx_channels_4_phase$D_IN_LUT4_Z_2_C_LUT4_B_Z[4] (18,51) -> (21,64) Info: Sink ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.M Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.3 6.2 Source ignition_io_bank6_1_txrs_rx_decode_done$whas_LUT4_Z_D_LUT4_D_Z_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.7 6.9 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_LUT4_Z_D_LUT4_Z_C_PFUMX_Z_C0_LUT4_A_Z_LUT4_Z_D_LUT4_Z_D_LUT4_B_C_LUT4_C_Z_LUT4_D_Z[3] (21,64) -> (20,64) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.4 7.3 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D0_PFUMX_Z_BLUT_LUT4_Z.OFX Info: 0.0 7.3 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D0 (20,64) -> (20,64) Info: Sink WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.FXA Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:141.34-141.36 Info: 0.2 7.5 Source WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z_L6MUX21_Z_D1_PFUMX_Z_ALUT_LUT4_Z.OFX Info: 1.7 9.2 Net WILL_FIRE_RL_ignition_io_bank6_1_txrs_rx_do_channel_receive_LUT4_Z_C_LUT4_D_Z_LUT4_C_Z[4] (20,64) -> (17,49) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input$FULL_N_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 9.4 Source ignition_io_bank6_1_txrs_rx_decode_input$FULL_N_LUT4_Z.F Info: 0.5 9.9 Net ignition_io_bank6_1_txrs_rx_decode_input.FULL_N (17,49) -> (17,49) Info: Sink ignition_io_bank6_1_txrs_deserializers_5_out.empty_reg_LUT4_A_1.B Info: Defined in: Info: ./env/a5100b25f626625e4edb22f8924275785c36bbdb/vnd/bluespec/Verilog.v:2050.26-2050.32 Info: 0.2 10.1 Source ignition_io_bank6_1_txrs_deserializers_5_out.empty_reg_LUT4_A_1.F Info: 0.4 10.6 Net ignition_io_bank6_1_txrs_deserializers_1_out.empty_reg_LUT4_A_1_Z[2] (17,49) -> (17,49) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z.B Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 10.8 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_Z.F Info: 0.7 11.5 Net ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI[12] (17,49) -> (16,48) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_D.D Info: Defined in: Info: ./env/4ec60555ef603e5fb7beffbcbfa5f2a0b1c3ef2b/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:0.0-0.0 Info: ./env/4ec60555ef603e5fb7beffbcbfa5f2a0b1c3ef2b/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:103085.5-103106.12 Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/techmap.v:578.19-578.22 Info: 0.2 11.8 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_DI_LUT4_D.F Info: 0.9 12.6 Net ignition_io_bank6_1_txrs_deserializers_0_out.empty_reg_LUT4_B_Z[1] (16,48) -> (18,48) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR_LUT4_Z.D Info: Defined in: Info: /work/oxidecomputer/quartz/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v:108.23-108.24 Info: 0.2 12.9 Source ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR_LUT4_Z.F Info: 0.6 13.5 Net ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_LSR (18,48) -> (18,50) Info: Sink ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_2.LSR Info: 0.4 13.9 Setup ignition_io_bank6_1_txrs_rx_decode_input.D_OUT_TRELLIS_FF_Q_2.LSR Info: 3.8 ns logic, 10.2 ns routing Info: Critical path report for cross-domain path '' -> 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': Info: curr total Info: 0.0 0.0 Source sp_to_fpga_design_reset_l$tr_io.O Info: 1.2 1.2 Net sp_to_fpga_design_reset_l$TRELLIS_IO_IN (4,71) -> (9,68) Info: Sink sp_to_fpga_design_reset_l_LUT4_D.D Info: Defined in: Info: ./env/4ec60555ef603e5fb7beffbcbfa5f2a0b1c3ef2b/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:427.10-427.35 Info: 0.2 1.5 Source sp_to_fpga_design_reset_l_LUT4_D.F Info: 0.5 2.0 Net sp_to_fpga_design_reset_l_LUT4_D_Z (9,68) -> (11,68) Info: Sink reset_sync.reset_hold_TRELLIS_FF_Q.LSR Info: 0.4 2.4 Setup reset_sync.reset_hold_TRELLIS_FF_Q.LSR Info: 0.7 ns logic, 1.8 ns routing Info: Critical path report for cross-domain path 'posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN' -> '': Info: curr total Info: 0.5 0.5 Source controller_vsc7448_sequencer_in_reset_TRELLIS_FF_Q.Q Info: 1.4 2.0 Net controller_vsc7448_sequencer_in_reset (45,2) -> (35,2) Info: Sink fpga_to_mgmt_reset_l_LUT4_Z.D Info: Defined in: Info: ./env/4ec60555ef603e5fb7beffbcbfa5f2a0b1c3ef2b/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:13793.7-13793.44 Info: 0.2 2.2 Source fpga_to_mgmt_reset_l_LUT4_Z.F Info: 4.3 6.5 Net fpga_to_phy4_reset_l$TRELLIS_IO_OUT (35,2) -> (0,29) Info: Sink fpga_to_phy4_reset_l$tr_io.I Info: Defined in: Info: ./env/4ec60555ef603e5fb7beffbcbfa5f2a0b1c3ef2b/hdl/projects/sidecar/mainboard/mkSidecarMainboardControllerTop.v:622.10-622.30 Info: 0.8 ns logic, 5.7 ns routing Info: Max frequency for clock '$glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN': 71.92 MHz (PASS at 50.00 MHz) Info: Max delay -> posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN: 2.43 ns Info: Max delay posedge $glbnet$clk_50m_fpga_refclk$TRELLIS_IO_IN -> : 6.46 ns Info: Slack histogram: Info: legend: * represents 72 endpoint(s) Info: + represents [1,72) endpoint(s) Info: [ 6095, 6744) |+ Info: [ 6744, 7393) |+ Info: [ 7393, 8042) |+ Info: [ 8042, 8691) |*+ Info: [ 8691, 9340) |**+ Info: [ 9340, 9989) |***+ Info: [ 9989, 10638) |*********+ Info: [ 10638, 11287) |*****************+ Info: [ 11287, 11936) |***********************+ Info: [ 11936, 12585) |*****************************+ Info: [ 12585, 13234) |*******************************+ Info: [ 13234, 13883) |*******************************+ Info: [ 13883, 14532) |***********************************+ Info: [ 14532, 15181) |******************************+ Info: [ 15181, 15830) |*****************************+ Info: [ 15830, 16479) |************************************+ Info: [ 16479, 17128) |****************************************+ Info: [ 17128, 17777) |********************************+ Info: [ 17777, 18426) |***************************+ Info: [ 18426, 19075) |************************************************************ Info: Program finished normally.