+---------------------------------------------------------------------+ | Log file: mau.resources.log | | Compiler version: 9.13.4 | | Created on: Wed May 7 21:31:15 2025 | | Run ID: ed9cd4c419f94042 | +---------------------------------------------------------------------+ --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 10 | 23 | 19 | 2 | 7 | 10 | 8 | 6 | 6 | 0 | 4 | 0 | 6 | 2 | 5 | 6 | 0 | 0 | 0 | 9 | | 1 | 1 | 28 | 0 | 0 | 2 | 17 | 5 | 22 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 52 | 0 | 0 | 0 | 2 | | 2 | 0 | 20 | 0 | 0 | 0 | 4 | 2 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 1 | | 3 | 6 | 0 | 20 | 0 | 6 | 4 | 2 | 0 | 5 | 0 | 1 | 0 | 6 | 2 | 7 | 6 | 0 | 0 | 0 | 9 | | 4 | 3 | 0 | 0 | 0 | 2 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 4 | 48 | 0 | 0 | 0 | 4 | | 5 | 5 | 9 | 1 | 0 | 2 | 4 | 2 | 2 | 6 | 0 | 1 | 0 | 2 | 0 | 3 | 6 | 0 | 0 | 0 | 3 | | 6 | 4 | 0 | 10 | 0 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | 2 | 1 | 0 | 10 | 0 | 0 | 0 | 2 | | 7 | 21 | 20 | 18 | 1 | 7 | 14 | 7 | 22 | 6 | 0 | 2 | 0 | 6 | 3 | 6 | 40 | 0 | 0 | 0 | 10 | | 8 | 7 | 0 | 40 | 0 | 4 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | 4 | 1 | 6 | 22 | 0 | 0 | 0 | 7 | | 9 | 16 | 0 | 40 | 0 | 0 | 12 | 3 | 0 | 3 | 0 | 1 | 0 | 1 | 1 | 1 | 6 | 0 | 0 | 0 | 2 | | 10 | 2 | 0 | 40 | 0 | 0 | 13 | 5 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 10 | 0 | 0 | 0 | 1 | | 11 | 3 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 4 | 16 | 0 | 0 | 0 | 4 | | 12 | 4 | 0 | 40 | 0 | 0 | 8 | 3 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 6 | 0 | 0 | 0 | 1 | | 13 | 9 | 0 | 36 | 3 | 5 | 8 | 6 | 0 | 2 | 0 | 3 | 0 | 4 | 4 | 2 | 6 | 0 | 0 | 0 | 5 | | | | | | | | | | | | | | | | | | | | | | | | Totals | 91 | 100 | 264 | 6 | 38 | 108 | 43 | 60 | 52 | 0 | 17 | 0 | 38 | 16 | 40 | 260 | 0 | 0 | 0 | 60 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 7.81% | 34.85% | 4.57% | 33.33% | 43.75% | 12.50% | 16.67% | 25.00% | 18.75% | 0.00% | 100.00% | 0.00% | 37.50% | 12.50% | 31.25% | 4.69% | 0.00% | 0.00% | 0.00% | 56.25% | | 1 | 0.78% | 42.42% | 0.00% | 0.00% | 12.50% | 21.25% | 10.42% | 91.67% | 6.25% | 0.00% | 50.00% | 0.00% | 12.50% | 0.00% | 12.50% | 40.62% | 0.00% | 0.00% | 0.00% | 12.50% | | 2 | 0.00% | 30.30% | 0.00% | 0.00% | 0.00% | 5.00% | 4.17% | 33.33% | 3.12% | 0.00% | 25.00% | 0.00% | 0.00% | 0.00% | 0.00% | 20.31% | 0.00% | 0.00% | 0.00% | 6.25% | | 3 | 4.69% | 0.00% | 4.81% | 0.00% | 37.50% | 5.00% | 4.17% | 0.00% | 15.62% | 0.00% | 25.00% | 0.00% | 37.50% | 12.50% | 43.75% | 4.69% | 0.00% | 0.00% | 0.00% | 56.25% | | 4 | 2.34% | 0.00% | 0.00% | 0.00% | 12.50% | 5.00% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 25.00% | 37.50% | 0.00% | 0.00% | 0.00% | 25.00% | | 5 | 3.91% | 13.64% | 0.24% | 0.00% | 12.50% | 5.00% | 4.17% | 8.33% | 18.75% | 0.00% | 25.00% | 0.00% | 12.50% | 0.00% | 18.75% | 4.69% | 0.00% | 0.00% | 0.00% | 18.75% | | 6 | 3.12% | 0.00% | 2.40% | 0.00% | 12.50% | 2.50% | 0.00% | 0.00% | 21.88% | 0.00% | 0.00% | 0.00% | 12.50% | 6.25% | 0.00% | 7.81% | 0.00% | 0.00% | 0.00% | 12.50% | | 7 | 16.41% | 30.30% | 4.33% | 16.67% | 43.75% | 17.50% | 14.58% | 91.67% | 18.75% | 0.00% | 50.00% | 0.00% | 37.50% | 18.75% | 37.50% | 31.25% | 0.00% | 0.00% | 0.00% | 62.50% | | 8 | 5.47% | 0.00% | 9.62% | 0.00% | 25.00% | 7.50% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 25.00% | 6.25% | 37.50% | 17.19% | 0.00% | 0.00% | 0.00% | 43.75% | | 9 | 12.50% | 0.00% | 9.62% | 0.00% | 0.00% | 15.00% | 6.25% | 0.00% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 6.25% | 4.69% | 0.00% | 0.00% | 0.00% | 12.50% | | 10 | 1.56% | 0.00% | 9.62% | 0.00% | 0.00% | 16.25% | 10.42% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 7.81% | 0.00% | 0.00% | 0.00% | 6.25% | | 11 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 25.00% | 12.50% | 0.00% | 0.00% | 0.00% | 25.00% | | 12 | 3.12% | 0.00% | 9.62% | 0.00% | 0.00% | 10.00% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 4.69% | 0.00% | 0.00% | 0.00% | 6.25% | | 13 | 7.03% | 0.00% | 8.65% | 50.00% | 31.25% | 10.00% | 12.50% | 0.00% | 6.25% | 0.00% | 75.00% | 0.00% | 25.00% | 25.00% | 12.50% | 4.69% | 0.00% | 0.00% | 0.00% | 31.25% | | | | | | | | | | | | | | | | | | | | | | | | Average | 5.08% | 10.82% | 4.53% | 7.14% | 16.96% | 9.64% | 6.40% | 17.86% | 11.61% | 0.00% | 30.36% | 0.00% | 16.96% | 7.14% | 17.86% | 14.51% | 0.00% | 0.00% | 0.00% | 26.79% | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Allocated Resource Usage --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind | | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result | | | | | | | | | | Bus | | Bus | Bus | Bus | | | | | | | | | | Bytes | | | | | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv6_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 | | Ingress.filter.switch_ipv6_addr | 0 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 | | Ingress.ingress_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.packet_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-33 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-34 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-35 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-36 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-37 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1064 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1064-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1065 | 0 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1065-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar445 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar75 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4 | 1 | 8 | 0 | 0 | 1 | 10 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4$action | 1 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6 | 1 | 20 | 0 | 0 | 1 | 12 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv6$action | 1 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_counter | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv6_ingress_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-38 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-39 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv6 | 2 | 20 | 0 | 0 | 0 | 8 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6$action | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv6_ingress_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_set_len | 3 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.nat_only | 3 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.nat_only_counter | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-40 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-41 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-42 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-43 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-44 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-47 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar456 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar457 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar460 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar461 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar464 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar465 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | cond-45 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-48 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_nat_ingress_encap_ipv4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4$action | 4 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_nat_ingress_encap_ipv6 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv6$action | 4 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_nat_ingress_invert | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar250 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | Ingress.services.service | 5 | 9 | 0 | 0 | 1 | 2 | 0 | 6 | 7 | 0 | 0 | 1 | | Ingress.services.service$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.services.service_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-46 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-49 | 5 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar253 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar481 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.nat_egress.nat_egress | 6 | 3 | 10 | 0 | 1 | 0 | 0 | 10 | 7 | 1 | 1 | 0 | | Ingress.nat_egress.nat_egress$action | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-50 | 6 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-51 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.index_counter | 7 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.lookup | 7 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.lookup$action | 7 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup.counter | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup.tbl | 7 | 16 | 0 | 0 | 1 | 6 | 0 | 24 | 3 | 0 | 0 | 1 | | Ingress.l3_router.Router6.lookup.tbl$action | 7 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-52 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-53 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-54 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-58 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-59 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_3-gateway | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_3_ingress | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | | ingresshdr.udp.checksum_encode_update_condition_2_ingress | 7 | 3 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | tbl_sidecar917 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar921 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar933 | 7 | 12 | 8 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 0 | | tbl_sidecar933-gateway | 7 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar981 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.select_route | 8 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | cond-55 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-56 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-60 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-61 | 8 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_Router6_icmp_error | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error$action | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router6_icmp_error_0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error_0$action | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar943 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar991 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar994 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar996 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router6.Ndp.counter | 9 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.Ndp.tbl | 9 | 16 | 40 | 0 | 8 | 0 | 0 | 6 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.Ndp.tbl$action | 9 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar792 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.forward_counter | 10 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.route | 10 | 2 | 40 | 0 | 4 | 0 | 0 | 10 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router4.lookup_idx.route$action | 10 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-57 | 11 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_Router4_icmp_error | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error$action | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router4_icmp_error_0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error_0$action | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar946 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar948 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.Arp.counter | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.Arp.tbl | 12 | 4 | 40 | 0 | 4 | 0 | 0 | 6 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router4.Arp.tbl$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.drop_port_ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.drop_reason_ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.egress_ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.mac_rewrite | 13 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 | | Ingress.mac_rewrite.mac_rewrite$action | 13 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-62 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-63 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-64 | 13 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1077 | 13 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1077-gateway | 13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1078 | 13 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1080 | 13 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1080-gateway | 13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1084 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 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