Max level shown:
1 +---------------------------------------------------------------------+
2 | Log file: mau.resources.log |
3 | Compiler version: 9.13.4 |
4 | Created on: Wed May 7 21:31:15 2025 |
5 | Run ID: ed9cd4c419f94042 |
6 +---------------------------------------------------------------------+
7 
8 
9 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
11 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
12 | 0 | 10 | 23 | 19 | 2 | 7 | 10 | 8 | 6 | 6 | 0 | 4 | 0 | 6 | 2 | 5 | 6 | 0 | 0 | 0 | 9 |
13 | 1 | 1 | 28 | 0 | 0 | 2 | 17 | 5 | 22 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 52 | 0 | 0 | 0 | 2 |
14 | 2 | 0 | 20 | 0 | 0 | 0 | 4 | 2 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 1 |
15 | 3 | 6 | 0 | 20 | 0 | 6 | 4 | 2 | 0 | 5 | 0 | 1 | 0 | 6 | 2 | 7 | 6 | 0 | 0 | 0 | 9 |
16 | 4 | 3 | 0 | 0 | 0 | 2 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 4 | 48 | 0 | 0 | 0 | 4 |
17 | 5 | 5 | 9 | 1 | 0 | 2 | 4 | 2 | 2 | 6 | 0 | 1 | 0 | 2 | 0 | 3 | 6 | 0 | 0 | 0 | 3 |
18 | 6 | 4 | 0 | 10 | 0 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | 2 | 1 | 0 | 10 | 0 | 0 | 0 | 2 |
19 | 7 | 21 | 20 | 18 | 1 | 7 | 14 | 7 | 22 | 6 | 0 | 2 | 0 | 6 | 3 | 6 | 40 | 0 | 0 | 0 | 10 |
20 | 8 | 7 | 0 | 40 | 0 | 4 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | 4 | 1 | 6 | 22 | 0 | 0 | 0 | 7 |
21 | 9 | 16 | 0 | 40 | 0 | 0 | 12 | 3 | 0 | 3 | 0 | 1 | 0 | 1 | 1 | 1 | 6 | 0 | 0 | 0 | 2 |
22 | 10 | 2 | 0 | 40 | 0 | 0 | 13 | 5 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 10 | 0 | 0 | 0 | 1 |
23 | 11 | 3 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 4 | 16 | 0 | 0 | 0 | 4 |
24 | 12 | 4 | 0 | 40 | 0 | 0 | 8 | 3 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 6 | 0 | 0 | 0 | 1 |
25 | 13 | 9 | 0 | 36 | 3 | 5 | 8 | 6 | 0 | 2 | 0 | 3 | 0 | 4 | 4 | 2 | 6 | 0 | 0 | 0 | 5 |
26 | | | | | | | | | | | | | | | | | | | | | |
27 | Totals | 91 | 100 | 264 | 6 | 38 | 108 | 43 | 60 | 52 | 0 | 17 | 0 | 38 | 16 | 40 | 260 | 0 | 0 | 0 | 60 |
28 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
29 
30 
31 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
32 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
33 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
34 | 0 | 7.81% | 34.85% | 4.57% | 33.33% | 43.75% | 12.50% | 16.67% | 25.00% | 18.75% | 0.00% | 100.00% | 0.00% | 37.50% | 12.50% | 31.25% | 4.69% | 0.00% | 0.00% | 0.00% | 56.25% |
35 | 1 | 0.78% | 42.42% | 0.00% | 0.00% | 12.50% | 21.25% | 10.42% | 91.67% | 6.25% | 0.00% | 50.00% | 0.00% | 12.50% | 0.00% | 12.50% | 40.62% | 0.00% | 0.00% | 0.00% | 12.50% |
36 | 2 | 0.00% | 30.30% | 0.00% | 0.00% | 0.00% | 5.00% | 4.17% | 33.33% | 3.12% | 0.00% | 25.00% | 0.00% | 0.00% | 0.00% | 0.00% | 20.31% | 0.00% | 0.00% | 0.00% | 6.25% |
37 | 3 | 4.69% | 0.00% | 4.81% | 0.00% | 37.50% | 5.00% | 4.17% | 0.00% | 15.62% | 0.00% | 25.00% | 0.00% | 37.50% | 12.50% | 43.75% | 4.69% | 0.00% | 0.00% | 0.00% | 56.25% |
38 | 4 | 2.34% | 0.00% | 0.00% | 0.00% | 12.50% | 5.00% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 25.00% | 37.50% | 0.00% | 0.00% | 0.00% | 25.00% |
39 | 5 | 3.91% | 13.64% | 0.24% | 0.00% | 12.50% | 5.00% | 4.17% | 8.33% | 18.75% | 0.00% | 25.00% | 0.00% | 12.50% | 0.00% | 18.75% | 4.69% | 0.00% | 0.00% | 0.00% | 18.75% |
40 | 6 | 3.12% | 0.00% | 2.40% | 0.00% | 12.50% | 2.50% | 0.00% | 0.00% | 21.88% | 0.00% | 0.00% | 0.00% | 12.50% | 6.25% | 0.00% | 7.81% | 0.00% | 0.00% | 0.00% | 12.50% |
41 | 7 | 16.41% | 30.30% | 4.33% | 16.67% | 43.75% | 17.50% | 14.58% | 91.67% | 18.75% | 0.00% | 50.00% | 0.00% | 37.50% | 18.75% | 37.50% | 31.25% | 0.00% | 0.00% | 0.00% | 62.50% |
42 | 8 | 5.47% | 0.00% | 9.62% | 0.00% | 25.00% | 7.50% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 25.00% | 6.25% | 37.50% | 17.19% | 0.00% | 0.00% | 0.00% | 43.75% |
43 | 9 | 12.50% | 0.00% | 9.62% | 0.00% | 0.00% | 15.00% | 6.25% | 0.00% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 6.25% | 4.69% | 0.00% | 0.00% | 0.00% | 12.50% |
44 | 10 | 1.56% | 0.00% | 9.62% | 0.00% | 0.00% | 16.25% | 10.42% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 7.81% | 0.00% | 0.00% | 0.00% | 6.25% |
45 | 11 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 25.00% | 12.50% | 0.00% | 0.00% | 0.00% | 25.00% |
46 | 12 | 3.12% | 0.00% | 9.62% | 0.00% | 0.00% | 10.00% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 4.69% | 0.00% | 0.00% | 0.00% | 6.25% |
47 | 13 | 7.03% | 0.00% | 8.65% | 50.00% | 31.25% | 10.00% | 12.50% | 0.00% | 6.25% | 0.00% | 75.00% | 0.00% | 25.00% | 25.00% | 12.50% | 4.69% | 0.00% | 0.00% | 0.00% | 31.25% |
48 | | | | | | | | | | | | | | | | | | | | | |
49 | Average | 5.08% | 10.82% | 4.53% | 7.14% | 16.96% | 9.64% | 6.40% | 17.86% | 11.61% | 0.00% | 30.36% | 0.00% | 16.96% | 7.14% | 17.86% | 14.51% | 0.00% | 0.00% | 0.00% | 26.79% |
50 -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
51 
52 
53 Allocated Resource Usage
54 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
55 | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind |
56 | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result |
57 | | | | | | | | | Bus | | Bus | Bus | Bus |
58 | | | | | | | | | Bytes | | | | |
59 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
60 | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
61 | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
62 | Ingress.filter.ipv6_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
63 | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 |
64 | Ingress.filter.switch_ipv6_addr | 0 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 |
65 | Ingress.ingress_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
66 | Ingress.packet_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
67 | cond-33 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
68 | cond-34 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
69 | cond-35 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
70 | cond-36 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
71 | cond-37 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
72 | tbl_sidecar1064 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
73 | tbl_sidecar1064-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
74 | tbl_sidecar1065 | 0 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
75 | tbl_sidecar1065-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
76 | tbl_sidecar445 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
77 | tbl_sidecar75 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
78 | tbl_sidecar78 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
79 | Ingress.nat_ingress.ingress_ipv4 | 1 | 8 | 0 | 0 | 1 | 10 | 0 | 26 | 2 | 0 | 0 | 1 |
80 | Ingress.nat_ingress.ingress_ipv4$action | 1 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
81 | Ingress.nat_ingress.ingress_ipv6 | 1 | 20 | 0 | 0 | 1 | 12 | 0 | 26 | 2 | 0 | 0 | 1 |
82 | Ingress.nat_ingress.ingress_ipv6$action | 1 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
83 | Ingress.nat_ingress.ipv4_ingress_counter | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
84 | Ingress.nat_ingress.ipv6_ingress_counter | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
85 | cond-38 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
86 | cond-39 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
87 | Ingress.nat_ingress.ingress_ipv6 | 2 | 20 | 0 | 0 | 0 | 8 | 0 | 26 | 2 | 0 | 0 | 0 |
88 | Ingress.nat_ingress.ingress_ipv6$action | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
89 | Ingress.nat_ingress.ipv6_ingress_counter | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
90 | Ingress.nat_ingress.ipv4_set_len | 3 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
91 | Ingress.nat_ingress.nat_only | 3 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 |
92 | Ingress.nat_ingress.nat_only_counter | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
93 | cond-40 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
94 | cond-41 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
95 | cond-42 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
96 | cond-43 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
97 | cond-44 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
98 | cond-47 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
99 | tbl_sidecar456 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
100 | tbl_sidecar457 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
101 | tbl_sidecar460 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
102 | tbl_sidecar461 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
103 | tbl_sidecar464 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
104 | tbl_sidecar465 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
105 | cond-45 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
106 | cond-48 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
107 | tbl_nat_ingress_encap_ipv4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 21 | 1 | 0 | 0 | 1 |
108 | tbl_nat_ingress_encap_ipv4$action | 4 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
109 | tbl_nat_ingress_encap_ipv6 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 1 | 0 | 0 | 1 |
110 | tbl_nat_ingress_encap_ipv6$action | 4 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
111 | tbl_nat_ingress_invert | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
112 | tbl_sidecar250 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
113 | Ingress.services.service | 5 | 9 | 0 | 0 | 1 | 2 | 0 | 6 | 7 | 0 | 0 | 1 |
114 | Ingress.services.service$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
115 | Ingress.services.service_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
116 | cond-46 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
117 | cond-49 | 5 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
118 | tbl_sidecar253 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
119 | tbl_sidecar481 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
120 | Ingress.nat_egress.nat_egress | 6 | 3 | 10 | 0 | 1 | 0 | 0 | 10 | 7 | 1 | 1 | 0 |
121 | Ingress.nat_egress.nat_egress$action | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
122 | cond-50 | 6 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
123 | cond-51 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
124 | Ingress.l3_router.Router4.lookup_idx.index_counter | 7 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
125 | Ingress.l3_router.Router4.lookup_idx.lookup | 7 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 |
126 | Ingress.l3_router.Router4.lookup_idx.lookup$action | 7 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
127 | Ingress.l3_router.Router6.lookup.counter | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
128 | Ingress.l3_router.Router6.lookup.tbl | 7 | 16 | 0 | 0 | 1 | 6 | 0 | 24 | 3 | 0 | 0 | 1 |
129 | Ingress.l3_router.Router6.lookup.tbl$action | 7 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
130 | cond-52 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
131 | cond-53 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
132 | cond-54 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
133 | cond-58 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
134 | cond-59 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
135 | ingresshdr.icmp.hdr_checksum_encode_update_condition_3-gateway | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
136 | ingresshdr.icmp.hdr_checksum_encode_update_condition_3_ingress | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
137 | ingresshdr.udp.checksum_encode_update_condition_2_ingress | 7 | 3 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
138 | tbl_sidecar917 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
139 | tbl_sidecar921 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
140 | tbl_sidecar933 | 7 | 12 | 8 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 0 |
141 | tbl_sidecar933-gateway | 7 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
142 | tbl_sidecar981 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
143 | Ingress.l3_router.Router4.lookup_idx.select_route | 8 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
144 | cond-55 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
145 | cond-56 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
146 | cond-60 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
147 | cond-61 | 8 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
148 | tbl_l3_router_Router6_icmp_error | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
149 | tbl_l3_router_Router6_icmp_error$action | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
150 | tbl_l3_router_Router6_icmp_error_0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
151 | tbl_l3_router_Router6_icmp_error_0$action | 8 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
152 | tbl_sidecar943 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
153 | tbl_sidecar991 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
154 | tbl_sidecar994 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
155 | tbl_sidecar996 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
156 | Ingress.l3_router.Router6.Ndp.counter | 9 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
157 | Ingress.l3_router.Router6.Ndp.tbl | 9 | 16 | 40 | 0 | 8 | 0 | 0 | 6 | 3 | 1 | 1 | 0 |
158 | Ingress.l3_router.Router6.Ndp.tbl$action | 9 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
159 | tbl_sidecar792 | 9 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
160 | Ingress.l3_router.Router4.lookup_idx.forward_counter | 10 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
161 | Ingress.l3_router.Router4.lookup_idx.route | 10 | 2 | 40 | 0 | 4 | 0 | 0 | 10 | 3 | 1 | 1 | 0 |
162 | Ingress.l3_router.Router4.lookup_idx.route$action | 10 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
163 | cond-57 | 11 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
164 | tbl_l3_router_Router4_icmp_error | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
165 | tbl_l3_router_Router4_icmp_error$action | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
166 | tbl_l3_router_Router4_icmp_error_0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
167 | tbl_l3_router_Router4_icmp_error_0$action | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
168 | tbl_sidecar946 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
169 | tbl_sidecar948 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
170 | Ingress.l3_router.Router4.Arp.counter | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
171 | Ingress.l3_router.Router4.Arp.tbl | 12 | 4 | 40 | 0 | 4 | 0 | 0 | 6 | 3 | 1 | 1 | 0 |
172 | Ingress.l3_router.Router4.Arp.tbl$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
173 | Ingress.drop_port_ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
174 | Ingress.drop_reason_ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
175 | Ingress.egress_ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
176 | Ingress.mac_rewrite.mac_rewrite | 13 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 |
177 | Ingress.mac_rewrite.mac_rewrite$action | 13 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
178 | cond-62 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
179 | cond-63 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
180 | cond-64 | 13 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
181 | tbl_sidecar1077 | 13 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
182 | tbl_sidecar1077-gateway | 13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
183 | tbl_sidecar1078 | 13 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
184 | tbl_sidecar1080 | 13 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
185 | tbl_sidecar1080-gateway | 13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
186 | tbl_sidecar1084 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
187 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
188