Max level shown:
1 +---------------------------------------------------------------------+
2 | Log file: mau.resources.log |
3 | Compiler version: 9.13.4 |
4 | Created on: Thu Jul 10 16:50:20 2025 |
5 | Run ID: 6c7dcb3a0098464f |
6 +---------------------------------------------------------------------+
7 
8 
9 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
11 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
12 | 0 | 23 | 6 | 17 | 2 | 15 | 7 | 6 | 2 | 7 | 0 | 3 | 0 | 13 | 4 | 7 | 3 | 0 | 0 | 0 | 16 |
13 | 1 | 39 | 21 | 147 | 2 | 13 | 53 | 10 | 5 | 3 | 0 | 4 | 0 | 11 | 9 | 6 | 92 | 0 | 0 | 0 | 16 |
14 | 2 | 11 | 24 | 39 | 2 | 4 | 20 | 9 | 24 | 8 | 0 | 4 | 0 | 3 | 4 | 1 | 63 | 0 | 0 | 0 | 8 |
15 | 3 | 9 | 27 | 17 | 2 | 4 | 14 | 8 | 11 | 4 | 0 | 4 | 0 | 3 | 2 | 3 | 30 | 0 | 0 | 0 | 6 |
16 | 4 | 17 | 5 | 29 | 1 | 11 | 11 | 8 | 1 | 5 | 0 | 4 | 0 | 11 | 6 | 10 | 11 | 0 | 0 | 0 | 14 |
17 | 5 | 8 | 0 | 9 | 1 | 3 | 4 | 2 | 0 | 3 | 0 | 1 | 0 | 3 | 1 | 7 | 34 | 0 | 0 | 0 | 7 |
18 | 6 | 6 | 10 | 1 | 0 | 2 | 3 | 2 | 2 | 6 | 0 | 1 | 0 | 2 | 0 | 3 | 4 | 0 | 0 | 0 | 3 |
19 | 7 | 40 | 8 | 40 | 0 | 7 | 18 | 5 | 4 | 5 | 0 | 2 | 0 | 8 | 1 | 6 | 4 | 0 | 0 | 0 | 9 |
20 | 8 | 60 | 0 | 66 | 2 | 1 | 15 | 3 | 0 | 2 | 0 | 1 | 0 | 2 | 1 | 1 | 15 | 0 | 0 | 0 | 1 |
21 | 9 | 4 | 7 | 0 | 0 | 2 | 1 | 0 | 2 | 4 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 3 |
22 | 10 | 3 | 0 | 10 | 0 | 1 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | 1 | 1 | 0 | 14 | 0 | 0 | 0 | 1 |
23 | 11 | 23 | 20 | 18 | 1 | 10 | 13 | 7 | 22 | 6 | 0 | 2 | 0 | 10 | 3 | 7 | 29 | 0 | 0 | 0 | 12 |
24 | 12 | 26 | 16 | 120 | 0 | 5 | 26 | 8 | 3 | 9 | 0 | 3 | 0 | 6 | 3 | 9 | 31 | 0 | 0 | 0 | 12 |
25 | 13 | 4 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 2 | 0 | 10 | 26 | 0 | 0 | 0 | 10 |
26 | 14 | 18 | 0 | 80 | 0 | 0 | 25 | 8 | 0 | 3 | 0 | 2 | 0 | 2 | 2 | 0 | 15 | 0 | 0 | 0 | 2 |
27 | 15 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 4 | 9 | 0 | 0 | 0 | 4 |
28 | 16 | 4 | 0 | 40 | 0 | 0 | 8 | 3 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 6 | 0 | 0 | 0 | 1 |
29 | 17 | 9 | 0 | 36 | 3 | 5 | 8 | 6 | 0 | 2 | 0 | 3 | 0 | 4 | 4 | 2 | 6 | 0 | 0 | 0 | 5 |
30 | | | | | | | | | | | | | | | | | | | | | |
31 | Totals | 307 | 144 | 669 | 16 | 86 | 228 | 85 | 76 | 87 | 0 | 35 | 0 | 85 | 42 | 77 | 392 | 0 | 0 | 0 | 130 |
32 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
33 
34 
35 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
36 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
37 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
38 | 0 | 17.97% | 9.09% | 4.09% | 33.33% | 93.75% | 8.75% | 12.50% | 8.33% | 21.88% | 0.00% | 75.00% | 0.00% | 81.25% | 25.00% | 43.75% | 2.34% | 0.00% | 0.00% | 0.00% | 100.00% |
39 | 1 | 30.47% | 31.82% | 35.34% | 33.33% | 81.25% | 66.25% | 20.83% | 20.83% | 9.38% | 0.00% | 100.00% | 0.00% | 68.75% | 56.25% | 37.50% | 71.88% | 0.00% | 0.00% | 0.00% | 100.00% |
40 | 2 | 8.59% | 36.36% | 9.38% | 33.33% | 25.00% | 25.00% | 18.75% | 100.00% | 25.00% | 0.00% | 100.00% | 0.00% | 18.75% | 25.00% | 6.25% | 49.22% | 0.00% | 0.00% | 0.00% | 50.00% |
41 | 3 | 7.03% | 40.91% | 4.09% | 33.33% | 25.00% | 17.50% | 16.67% | 45.83% | 12.50% | 0.00% | 100.00% | 0.00% | 18.75% | 12.50% | 18.75% | 23.44% | 0.00% | 0.00% | 0.00% | 37.50% |
42 | 4 | 13.28% | 7.58% | 6.97% | 16.67% | 68.75% | 13.75% | 16.67% | 4.17% | 15.62% | 0.00% | 100.00% | 0.00% | 68.75% | 37.50% | 62.50% | 8.59% | 0.00% | 0.00% | 0.00% | 87.50% |
43 | 5 | 6.25% | 0.00% | 2.16% | 16.67% | 18.75% | 5.00% | 4.17% | 0.00% | 9.38% | 0.00% | 25.00% | 0.00% | 18.75% | 6.25% | 43.75% | 26.56% | 0.00% | 0.00% | 0.00% | 43.75% |
44 | 6 | 4.69% | 15.15% | 0.24% | 0.00% | 12.50% | 3.75% | 4.17% | 8.33% | 18.75% | 0.00% | 25.00% | 0.00% | 12.50% | 0.00% | 18.75% | 3.12% | 0.00% | 0.00% | 0.00% | 18.75% |
45 | 7 | 31.25% | 12.12% | 9.62% | 0.00% | 43.75% | 22.50% | 10.42% | 16.67% | 15.62% | 0.00% | 50.00% | 0.00% | 50.00% | 6.25% | 37.50% | 3.12% | 0.00% | 0.00% | 0.00% | 56.25% |
46 | 8 | 46.88% | 0.00% | 15.87% | 33.33% | 6.25% | 18.75% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 12.50% | 6.25% | 6.25% | 11.72% | 0.00% | 0.00% | 0.00% | 6.25% |
47 | 9 | 3.12% | 10.61% | 0.00% | 0.00% | 12.50% | 1.25% | 0.00% | 8.33% | 12.50% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 18.75% |
48 | 10 | 2.34% | 0.00% | 2.40% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 21.88% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 10.94% | 0.00% | 0.00% | 0.00% | 6.25% |
49 | 11 | 17.97% | 30.30% | 4.33% | 16.67% | 62.50% | 16.25% | 14.58% | 91.67% | 18.75% | 0.00% | 50.00% | 0.00% | 62.50% | 18.75% | 43.75% | 22.66% | 0.00% | 0.00% | 0.00% | 75.00% |
50 | 12 | 20.31% | 24.24% | 28.85% | 0.00% | 31.25% | 32.50% | 16.67% | 12.50% | 28.12% | 0.00% | 75.00% | 0.00% | 37.50% | 18.75% | 56.25% | 24.22% | 0.00% | 0.00% | 0.00% | 75.00% |
51 | 13 | 3.12% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 25.00% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 62.50% | 20.31% | 0.00% | 0.00% | 0.00% | 62.50% |
52 | 14 | 14.06% | 0.00% | 19.23% | 0.00% | 0.00% | 31.25% | 16.67% | 0.00% | 9.38% | 0.00% | 50.00% | 0.00% | 12.50% | 12.50% | 0.00% | 11.72% | 0.00% | 0.00% | 0.00% | 12.50% |
53 | 15 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 25.00% | 7.03% | 0.00% | 0.00% | 0.00% | 25.00% |
54 | 16 | 3.12% | 0.00% | 9.62% | 0.00% | 0.00% | 10.00% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 4.69% | 0.00% | 0.00% | 0.00% | 6.25% |
55 | 17 | 7.03% | 0.00% | 8.65% | 50.00% | 31.25% | 10.00% | 12.50% | 0.00% | 6.25% | 0.00% | 75.00% | 0.00% | 25.00% | 25.00% | 12.50% | 4.69% | 0.00% | 0.00% | 0.00% | 31.25% |
56 | | | | | | | | | | | | | | | | | | | | | |
57 | Average | 13.32% | 12.12% | 8.93% | 14.81% | 29.86% | 15.83% | 9.84% | 17.59% | 15.10% | 0.00% | 48.61% | 0.00% | 29.51% | 14.58% | 26.74% | 17.01% | 0.00% | 0.00% | 0.00% | 45.14% |
58 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
59 
60 
61 Allocated Resource Usage
62 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
63 | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind |
64 | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result |
65 | | | | | | | | | Bus | | Bus | Bus | Bus |
66 | | | | | | | | | Bytes | | | | |
67 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
68 | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
69 | Ingress.filter.drop_mcast_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
70 | Ingress.filter.drop_reason_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
71 | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
72 | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 |
73 | cond-70 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
74 | cond-71 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
75 | cond-72 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
76 | cond-73 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
77 | cond-74 | 0 | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
78 | cond-75 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
79 | cond-76 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
80 | cond-77 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
81 | cond-78 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
82 | cond-79 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
83 | cond-80 | 0 | 8 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
84 | tbl_filter_drop_mcast | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
85 | tbl_filter_drop_mcast_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
86 | tbl_filter_drop_mcast_with_reason | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
87 | tbl_filter_drop_mcast_with_reason_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
88 | tbl_filter_drop_mcast_with_reason_1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
89 | tbl_filter_drop_with_reason | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
90 | tbl_sidecar186 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
91 | tbl_sidecar186-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
92 | tbl_sidecar225 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
93 | tbl_sidecar225-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
94 | tbl_sidecar241 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
95 | tbl_sidecar241-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
96 | tbl_sidecar256 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
97 | tbl_sidecar256-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
98 | Egress.mcast_egress.asic_id_to_port | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
99 | Egress.mcast_egress.mcast_tag_check | 1 | 19 | 0 | 0 | 1 | 4 | 0 | 0 | 1 | 0 | 0 | 1 |
100 | Egress.mcast_egress.tbl_decap_ports | 1 | 2 | 40 | 0 | 4 | 0 | 0 | 34 | 3 | 1 | 1 | 0 |
101 | Egress.mcast_egress.tbl_decap_ports$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
102 | Ingress.filter.drop_mcast_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
103 | Ingress.filter.drop_reason_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
104 | Ingress.nat_ingress.icmp_dst_port | 1 | 2 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 1 |
105 | Ingress.nat_ingress.ingress_ipv4_mcast | 1 | 4 | 40 | 0 | 4 | 0 | 0 | 26 | 2 | 1 | 1 | 0 |
106 | Ingress.nat_ingress.ingress_ipv4_mcast$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
107 | Ingress.nat_ingress.ingress_ipv6_mcast | 1 | 16 | 40 | 0 | 8 | 0 | 0 | 26 | 2 | 1 | 1 | 0 |
108 | Ingress.nat_ingress.ingress_ipv6_mcast$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
109 | Ingress.nat_ingress.mcast_ipv4_ingress_ctr | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
110 | Ingress.nat_ingress.mcast_ipv6_ingress_ctr | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
111 | cond-125 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
112 | cond-126 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
113 | cond-127 | 1 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
114 | cond-83 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
115 | cond-84 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
116 | cond-85 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
117 | cond-86 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
118 | cond-87 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
119 | tbl_sidecar185 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
120 | tbl_sidecar185-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
121 | tbl_sidecar2065 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
122 | tbl_sidecar2073 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
123 | tbl_sidecar212 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
124 | tbl_sidecar212-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
125 | tbl_sidecar224 | 1 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
126 | tbl_sidecar224-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
127 | tbl_sidecar242 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
128 | tbl_sidecar242-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
129 | tbl_sidecar257 | 1 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
130 | tbl_sidecar257-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
131 | Egress.mac_rewrite.mac_rewrite | 2 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 |
132 | Egress.mac_rewrite.mac_rewrite$action | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
133 | Egress.mcast_egress.port_bitmap_check | 2 | 1 | 10 | 0 | 1 | 0 | 0 | 4 | 9 | 1 | 1 | 0 |
134 | Ingress.ingress_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
135 | Ingress.nat_ingress.ingress_ipv4 | 2 | 8 | 0 | 0 | 0 | 4 | 0 | 26 | 2 | 0 | 0 | 0 |
136 | Ingress.nat_ingress.ingress_ipv4$action | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
137 | Ingress.nat_ingress.ingress_ipv6 | 2 | 20 | 0 | 0 | 0 | 20 | 0 | 26 | 2 | 0 | 0 | 0 |
138 | Ingress.nat_ingress.ingress_ipv6$action | 2 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
139 | Ingress.nat_ingress.ipv4_ingress_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
140 | Ingress.nat_ingress.ipv6_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
141 | Ingress.packet_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
142 | cond-133 | 2 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
143 | cond-81 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
144 | tbl_sidecar1909 | 2 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
145 | tbl_sidecar1909-gateway | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
146 | tbl_sidecar1910 | 2 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
147 | tbl_sidecar1910-gateway | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
148 | tbl_sidecar2081 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
149 | Egress.drop_port_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
150 | Egress.drop_reason_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
151 | Egress.mcast_egress.modify_hdr | 3 | 3 | 0 | 0 | 1 | 1 | 0 | 4 | 5 | 0 | 0 | 1 |
152 | Ingress.filter.ipv6_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
153 | Ingress.filter.switch_ipv6_addr | 3 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 |
154 | Ingress.nat_ingress.ingress_ipv4 | 3 | 8 | 0 | 0 | 0 | 6 | 0 | 26 | 2 | 0 | 0 | 0 |
155 | Ingress.nat_ingress.ingress_ipv4$action | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
156 | Ingress.nat_ingress.ipv4_ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
157 | cond-128 | 3 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
158 | cond-134 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
159 | cond-82 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
160 | tbl_sidecar1878 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
161 | tbl_sidecar2087 | 3 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
162 | tbl_sidecar2087-gateway | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
163 | tbl_sidecar2088 | 3 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
164 | Egress.external_mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
165 | Egress.link_local_mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
166 | Egress.mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
167 | Ingress.nat_ingress.CalculateIPv4Len.ipv4_set_len | 4 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
168 | Ingress.nat_ingress.ingress_hit | 4 | 5 | 0 | 0 | 1 | 1 | 0 | 2 | 4 | 0 | 0 | 1 |
169 | Ingress.nat_ingress.nat_only | 4 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 |
170 | Ingress.nat_ingress.nat_only_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
171 | cond-129 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
172 | cond-130 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
173 | cond-131 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
174 | cond-132 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
175 | cond-135 | 4 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
176 | cond-136 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
177 | cond-137 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
178 | cond-88 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
179 | cond-91 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
180 | cond-92 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
181 | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5-gateway | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
182 | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5_egress | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
183 | tbl_sidecar1434 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
184 | tbl_sidecar1436 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
185 | tbl_sidecar1439 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
186 | tbl_sidecar1449_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
187 | tbl_sidecar1451_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
188 | tbl_sidecar2090 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
189 | tbl_sidecar2093 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
190 | tbl_sidecar2095 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
191 | Egress.underlay_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
192 | cond-138 | 5 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
193 | cond-89 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
194 | cond-93 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
195 | tbl_nat_ingress_CalculateIPv4Len_invert | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
196 | tbl_nat_ingress_encap_ipv4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1 | 0 | 0 | 1 |
197 | tbl_nat_ingress_encap_ipv4$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
198 | tbl_nat_ingress_encap_ipv6 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 1 | 0 | 0 | 1 |
199 | tbl_nat_ingress_encap_ipv6$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
200 | tbl_sidecar1439_0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
201 | tbl_sidecar1454 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
202 | tbl_sidecar2099 | 5 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
203 | tbl_sidecar435 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
204 | Ingress.services.service | 6 | 10 | 0 | 0 | 1 | 2 | 0 | 4 | 7 | 0 | 0 | 1 |
205 | Ingress.services.service_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
206 | cond-90 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
207 | cond-94 | 6 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
208 | tbl_sidecar439 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
209 | tbl_sidecar718 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
210 | Ingress.mcast_ingress.mcast_ipv4_ssm_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
211 | Ingress.mcast_ingress.mcast_ipv6_ssm_ctr | 7 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
212 | Ingress.mcast_ingress.mcast_source_filter_ipv4 | 7 | 8 | 0 | 0 | 1 | 4 | 0 | 1 | 2 | 0 | 0 | 1 |
213 | Ingress.mcast_ingress.mcast_source_filter_ipv6 | 7 | 32 | 40 | 0 | 12 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
214 | cond-100 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
215 | cond-101 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
216 | cond-95 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
217 | cond-96 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
218 | cond-97 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
219 | cond-98 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
220 | cond-99 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
221 | tbl_mcast_ingress_drop_mcastv4_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
222 | tbl_mcast_ingress_drop_mcastv6_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
223 | tbl_sidecar1659 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
224 | tbl_sidecar1668 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
225 | Ingress.mcast_ingress.mcast_ipv6_ctr | 8 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
226 | Ingress.mcast_ingress.mcast_replication_ipv6 | 8 | 58 | 66 | 0 | 8 | 0 | 0 | 15 | 2 | 1 | 1 | 0 |
227 | Ingress.mcast_ingress.mcast_replication_ipv6$action | 8 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
228 | cond-102 | 8 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
229 | mcast_ingress_mcast_replication_ipv6 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
230 | Ingress.mcast_ingress.mcast_tag_check | 9 | 7 | 0 | 0 | 1 | 2 | 0 | 0 | 5 | 0 | 0 | 1 |
231 | cond-103 | 9 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
232 | cond-104 | 9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
233 | Ingress.nat_egress.nat_egress | 10 | 2 | 10 | 0 | 1 | 0 | 0 | 14 | 7 | 1 | 1 | 0 |
234 | Ingress.nat_egress.nat_egress$action | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
235 | cond-105 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
236 | Ingress.l3_router.Router4.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
237 | Ingress.l3_router.Router4.lookup_idx.lookup | 11 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 |
238 | Ingress.l3_router.Router4.lookup_idx.lookup$action | 11 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
239 | Ingress.l3_router.Router6.lookup.ctr | 11 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
240 | Ingress.l3_router.Router6.lookup.tbl | 11 | 16 | 0 | 0 | 1 | 6 | 0 | 20 | 3 | 0 | 0 | 1 |
241 | Ingress.l3_router.Router6.lookup.tbl$action | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
242 | cond-106 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
243 | cond-107 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
244 | cond-108 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
245 | cond-109 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
246 | cond-112 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
247 | cond-116 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
248 | cond-117 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
249 | cond-118 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
250 | ingresshdr.icmp.hdr_checksum_encode_update_condition_4-gateway | 11 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
251 | ingresshdr.icmp.hdr_checksum_encode_update_condition_4_ingress | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
252 | ingresshdr.udp.checksum_encode_update_condition_3_ingress | 11 | 3 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
253 | tbl_sidecar1123 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
254 | tbl_sidecar1135 | 11 | 12 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
255 | tbl_sidecar1135-gateway | 11 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
256 | tbl_sidecar1212 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
257 | tbl_sidecar1221 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
258 | tbl_sidecar1337 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
259 | Ingress.l3_router.MulticastRouter4.ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
260 | Ingress.l3_router.MulticastRouter4.tbl | 12 | 4 | 40 | 0 | 4 | 0 | 0 | 2 | 3 | 1 | 1 | 0 |
261 | Ingress.l3_router.MulticastRouter6.ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
262 | Ingress.l3_router.MulticastRouter6.tbl | 12 | 16 | 40 | 0 | 8 | 0 | 0 | 2 | 3 | 1 | 1 | 0 |
263 | Ingress.l3_router.Router4.lookup_idx.select_route | 12 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
264 | Ingress.l3_router.Router6.lookup.ctr | 12 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
265 | Ingress.l3_router.Router6.lookup.tbl | 12 | 16 | 0 | 0 | 1 | 3 | 0 | 20 | 3 | 0 | 0 | 1 |
266 | Ingress.l3_router.Router6.lookup.tbl$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
267 | cond-110 | 12 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
268 | cond-111 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
269 | cond-113 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
270 | cond-114 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
271 | cond-119 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
272 | tbl_sidecar1146 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
273 | tbl_sidecar1227 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
274 | tbl_sidecar1230 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
275 | tbl_sidecar1233 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
276 | tbl_sidecar1236 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
277 | tbl_sidecar1343 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
278 | tbl_sidecar1346 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
279 | tbl_sidecar1349 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
280 | cond-120 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
281 | cond-121 | 13 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
282 | tbl_l3_router_MulticastRouter4_icmp_error | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
283 | tbl_l3_router_MulticastRouter4_icmp_error_0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
284 | tbl_l3_router_MulticastRouter6_icmp_error | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
285 | tbl_l3_router_MulticastRouter6_icmp_error_0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
286 | tbl_l3_router_Router6_icmp_error | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
287 | tbl_l3_router_Router6_icmp_error_0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
288 | tbl_sidecar1270 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
289 | tbl_sidecar1273 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
290 | tbl_sidecar1275 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
291 | tbl_sidecar999 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
292 | Ingress.l3_router.Router4.lookup_idx.forward_ctr | 14 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
293 | Ingress.l3_router.Router4.lookup_idx.route | 14 | 2 | 40 | 0 | 4 | 0 | 0 | 8 | 3 | 1 | 1 | 0 |
294 | Ingress.l3_router.Router4.lookup_idx.route$action | 14 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
295 | Ingress.l3_router.Router6.Ndp.ctr | 14 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
296 | Ingress.l3_router.Router6.Ndp.tbl | 14 | 16 | 40 | 0 | 8 | 0 | 0 | 7 | 3 | 1 | 1 | 0 |
297 | Ingress.l3_router.Router6.Ndp.tbl$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
298 | cond-115 | 15 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
299 | tbl_l3_router_Router4_icmp_error | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
300 | tbl_l3_router_Router4_icmp_error_0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
301 | tbl_sidecar1149 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
302 | tbl_sidecar1151 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
303 | Ingress.l3_router.Router4.Arp.ctr | 16 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
304 | Ingress.l3_router.Router4.Arp.tbl | 16 | 4 | 40 | 0 | 4 | 0 | 0 | 6 | 3 | 1 | 1 | 0 |
305 | Ingress.l3_router.Router4.Arp.tbl$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
306 | Ingress.drop_port_ctr | 17 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
307 | Ingress.drop_reason_ctr | 17 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
308 | Ingress.egress_ctr | 17 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
309 | Ingress.mac_rewrite.mac_rewrite | 17 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 |
310 | Ingress.mac_rewrite.mac_rewrite$action | 17 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
311 | cond-122 | 17 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
312 | cond-123 | 17 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
313 | cond-124 | 17 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
314 | tbl_sidecar1944 | 17 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
315 | tbl_sidecar1944-gateway | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
316 | tbl_sidecar1945 | 17 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
317 | tbl_sidecar1947 | 17 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
318 | tbl_sidecar1947-gateway | 17 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
319 | tbl_sidecar1951 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
320 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
321