Max level shown:
1 +---------------------------------------------------------------------+
2 | Log file: mau.resources.log |
3 | Compiler version: 9.13.4 |
4 | Created on: Thu Aug 7 15:01:15 2025 |
5 | Run ID: 2ddffe1c217d4cbd |
6 +---------------------------------------------------------------------+
7 
8 
9 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
11 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
12 | 0 | 24 | 6 | 17 | 2 | 15 | 7 | 6 | 2 | 7 | 0 | 3 | 0 | 13 | 4 | 7 | 3 | 0 | 0 | 0 | 16 |
13 | 1 | 39 | 21 | 147 | 2 | 13 | 53 | 10 | 5 | 3 | 0 | 4 | 0 | 11 | 9 | 5 | 91 | 0 | 0 | 0 | 15 |
14 | 2 | 9 | 24 | 30 | 1 | 3 | 20 | 9 | 24 | 8 | 0 | 4 | 0 | 3 | 3 | 2 | 66 | 0 | 0 | 0 | 8 |
15 | 3 | 11 | 27 | 17 | 2 | 4 | 14 | 8 | 11 | 4 | 0 | 4 | 0 | 3 | 2 | 3 | 30 | 0 | 0 | 0 | 6 |
16 | 4 | 18 | 4 | 38 | 2 | 12 | 12 | 8 | 1 | 5 | 0 | 4 | 0 | 11 | 6 | 9 | 17 | 0 | 0 | 0 | 15 |
17 | 5 | 8 | 0 | 9 | 1 | 4 | 10 | 6 | 0 | 2 | 0 | 3 | 0 | 4 | 3 | 8 | 47 | 0 | 0 | 0 | 8 |
18 | 6 | 7 | 11 | 1 | 0 | 2 | 4 | 2 | 2 | 7 | 0 | 1 | 0 | 2 | 0 | 3 | 11 | 0 | 0 | 0 | 3 |
19 | 7 | 40 | 8 | 40 | 0 | 7 | 18 | 5 | 4 | 5 | 0 | 2 | 0 | 8 | 1 | 6 | 4 | 0 | 0 | 0 | 9 |
20 | 8 | 60 | 0 | 66 | 2 | 1 | 15 | 3 | 0 | 2 | 0 | 1 | 0 | 2 | 1 | 1 | 15 | 0 | 0 | 0 | 1 |
21 | 9 | 0 | 7 | 0 | 0 | 0 | 1 | 0 | 2 | 4 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
22 | 10 | 5 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 3 |
23 | 11 | 3 | 0 | 10 | 0 | 1 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | 1 | 1 | 0 | 8 | 0 | 0 | 0 | 1 |
24 | 12 | 20 | 4 | 8 | 1 | 8 | 8 | 5 | 16 | 5 | 0 | 1 | 0 | 7 | 2 | 5 | 9 | 0 | 0 | 0 | 9 |
25 | 13 | 14 | 16 | 90 | 0 | 6 | 17 | 5 | 9 | 7 | 0 | 2 | 0 | 7 | 3 | 6 | 30 | 0 | 0 | 0 | 9 |
26 | 14 | 20 | 0 | 40 | 0 | 3 | 15 | 3 | 0 | 8 | 0 | 1 | 0 | 4 | 1 | 11 | 38 | 0 | 0 | 0 | 12 |
27 | 15 | 18 | 0 | 80 | 0 | 0 | 28 | 8 | 0 | 7 | 0 | 2 | 0 | 2 | 2 | 3 | 33 | 0 | 0 | 0 | 5 |
28 | 16 | 3 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 4 | 17 | 0 | 0 | 0 | 4 |
29 | 17 | 4 | 0 | 40 | 0 | 0 | 9 | 3 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 8 | 0 | 0 | 0 | 1 |
30 | 18 | 9 | 0 | 36 | 3 | 5 | 10 | 8 | 0 | 2 | 0 | 4 | 0 | 4 | 4 | 3 | 6 | 0 | 0 | 0 | 5 |
31 | | | | | | | | | | | | | | | | | | | | | |
32 | Totals | 312 | 128 | 669 | 16 | 88 | 245 | 89 | 76 | 89 | 0 | 37 | 0 | 87 | 43 | 78 | 433 | 0 | 0 | 0 | 131 |
33 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
34 
35 
36 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
37 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
38 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
39 | 0 | 18.75% | 9.09% | 4.09% | 33.33% | 93.75% | 8.75% | 12.50% | 8.33% | 21.88% | 0.00% | 75.00% | 0.00% | 81.25% | 25.00% | 43.75% | 2.34% | 0.00% | 0.00% | 0.00% | 100.00% |
40 | 1 | 30.47% | 31.82% | 35.34% | 33.33% | 81.25% | 66.25% | 20.83% | 20.83% | 9.38% | 0.00% | 100.00% | 0.00% | 68.75% | 56.25% | 31.25% | 71.09% | 0.00% | 0.00% | 0.00% | 93.75% |
41 | 2 | 7.03% | 36.36% | 7.21% | 16.67% | 18.75% | 25.00% | 18.75% | 100.00% | 25.00% | 0.00% | 100.00% | 0.00% | 18.75% | 18.75% | 12.50% | 51.56% | 0.00% | 0.00% | 0.00% | 50.00% |
42 | 3 | 8.59% | 40.91% | 4.09% | 33.33% | 25.00% | 17.50% | 16.67% | 45.83% | 12.50% | 0.00% | 100.00% | 0.00% | 18.75% | 12.50% | 18.75% | 23.44% | 0.00% | 0.00% | 0.00% | 37.50% |
43 | 4 | 14.06% | 6.06% | 9.13% | 33.33% | 75.00% | 15.00% | 16.67% | 4.17% | 15.62% | 0.00% | 100.00% | 0.00% | 68.75% | 37.50% | 56.25% | 13.28% | 0.00% | 0.00% | 0.00% | 93.75% |
44 | 5 | 6.25% | 0.00% | 2.16% | 16.67% | 25.00% | 12.50% | 12.50% | 0.00% | 6.25% | 0.00% | 75.00% | 0.00% | 25.00% | 18.75% | 50.00% | 36.72% | 0.00% | 0.00% | 0.00% | 50.00% |
45 | 6 | 5.47% | 16.67% | 0.24% | 0.00% | 12.50% | 5.00% | 4.17% | 8.33% | 21.88% | 0.00% | 25.00% | 0.00% | 12.50% | 0.00% | 18.75% | 8.59% | 0.00% | 0.00% | 0.00% | 18.75% |
46 | 7 | 31.25% | 12.12% | 9.62% | 0.00% | 43.75% | 22.50% | 10.42% | 16.67% | 15.62% | 0.00% | 50.00% | 0.00% | 50.00% | 6.25% | 37.50% | 3.12% | 0.00% | 0.00% | 0.00% | 56.25% |
47 | 8 | 46.88% | 0.00% | 15.87% | 33.33% | 6.25% | 18.75% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 12.50% | 6.25% | 6.25% | 11.72% | 0.00% | 0.00% | 0.00% | 6.25% |
48 | 9 | 0.00% | 10.61% | 0.00% | 0.00% | 0.00% | 1.25% | 0.00% | 8.33% | 12.50% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 6.25% |
49 | 10 | 3.91% | 0.00% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 18.75% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 18.75% |
50 | 11 | 2.34% | 0.00% | 2.40% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 21.88% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 6.25% |
51 | 12 | 15.62% | 6.06% | 1.92% | 16.67% | 50.00% | 10.00% | 10.42% | 66.67% | 15.62% | 0.00% | 25.00% | 0.00% | 43.75% | 12.50% | 31.25% | 7.03% | 0.00% | 0.00% | 0.00% | 56.25% |
52 | 13 | 10.94% | 24.24% | 21.63% | 0.00% | 37.50% | 21.25% | 10.42% | 37.50% | 21.88% | 0.00% | 50.00% | 0.00% | 43.75% | 18.75% | 37.50% | 23.44% | 0.00% | 0.00% | 0.00% | 56.25% |
53 | 14 | 15.62% | 0.00% | 9.62% | 0.00% | 18.75% | 18.75% | 6.25% | 0.00% | 25.00% | 0.00% | 25.00% | 0.00% | 25.00% | 6.25% | 68.75% | 29.69% | 0.00% | 0.00% | 0.00% | 75.00% |
54 | 15 | 14.06% | 0.00% | 19.23% | 0.00% | 0.00% | 35.00% | 16.67% | 0.00% | 21.88% | 0.00% | 50.00% | 0.00% | 12.50% | 12.50% | 18.75% | 25.78% | 0.00% | 0.00% | 0.00% | 31.25% |
55 | 16 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 25.00% | 13.28% | 0.00% | 0.00% | 0.00% | 25.00% |
56 | 17 | 3.12% | 0.00% | 9.62% | 0.00% | 0.00% | 11.25% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 6.25% |
57 | 18 | 7.03% | 0.00% | 8.65% | 50.00% | 31.25% | 12.50% | 16.67% | 0.00% | 6.25% | 0.00% | 100.00% | 0.00% | 25.00% | 25.00% | 18.75% | 4.69% | 0.00% | 0.00% | 0.00% | 31.25% |
58 | | | | | | | | | | | | | | | | | | | | | |
59 | Average | 12.83% | 10.21% | 8.46% | 14.04% | 28.95% | 16.12% | 9.76% | 16.67% | 14.64% | 0.00% | 48.68% | 0.00% | 28.62% | 14.14% | 25.66% | 17.80% | 0.00% | 0.00% | 0.00% | 43.09% |
60 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
61 
62 
63 Allocated Resource Usage
64 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
65 | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind |
66 | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result |
67 | | | | | | | | | Bus | | Bus | Bus | Bus |
68 | | | | | | | | | Bytes | | | | |
69 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
70 | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
71 | Ingress.filter.drop_mcast_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
72 | Ingress.filter.drop_reason_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
73 | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
74 | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 |
75 | cond-71 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
76 | cond-72 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
77 | cond-73 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
78 | cond-74 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
79 | cond-75 | 0 | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
80 | cond-76 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
81 | cond-77 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
82 | cond-78 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
83 | cond-79 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
84 | cond-80 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
85 | cond-81 | 0 | 8 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
86 | tbl_filter_drop_mcast | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
87 | tbl_filter_drop_mcast_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
88 | tbl_filter_drop_mcast_with_reason | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
89 | tbl_filter_drop_mcast_with_reason_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
90 | tbl_filter_drop_mcast_with_reason_1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
91 | tbl_filter_drop_with_reason | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
92 | tbl_sidecar187 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
93 | tbl_sidecar187-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
94 | tbl_sidecar226 | 0 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
95 | tbl_sidecar226-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
96 | tbl_sidecar242 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
97 | tbl_sidecar242-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
98 | tbl_sidecar257 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
99 | tbl_sidecar257-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
100 | Egress.mcast_egress.asic_id_to_port | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
101 | Egress.mcast_egress.mcast_tag_check | 1 | 19 | 0 | 0 | 1 | 4 | 0 | 0 | 1 | 0 | 0 | 1 |
102 | Egress.mcast_egress.tbl_decap_ports | 1 | 2 | 40 | 0 | 4 | 0 | 0 | 34 | 3 | 1 | 1 | 0 |
103 | Egress.mcast_egress.tbl_decap_ports$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
104 | Ingress.filter.drop_mcast_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
105 | Ingress.filter.drop_reason_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
106 | Ingress.nat_ingress.icmp_dst_port | 1 | 2 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 1 |
107 | Ingress.nat_ingress.ingress_ipv4_mcast | 1 | 4 | 40 | 0 | 4 | 0 | 0 | 26 | 2 | 1 | 1 | 0 |
108 | Ingress.nat_ingress.ingress_ipv4_mcast$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
109 | Ingress.nat_ingress.ingress_ipv6_mcast | 1 | 16 | 40 | 0 | 8 | 0 | 0 | 26 | 2 | 1 | 1 | 0 |
110 | Ingress.nat_ingress.ingress_ipv6_mcast$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
111 | Ingress.nat_ingress.mcast_ipv4_ingress_ctr | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
112 | Ingress.nat_ingress.mcast_ipv6_ingress_ctr | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
113 | cond-127 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
114 | cond-128 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
115 | cond-129 | 1 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
116 | cond-84 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
117 | cond-85 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
118 | cond-86 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
119 | cond-87 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
120 | cond-88 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
121 | tbl_sidecar186 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
122 | tbl_sidecar186-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
123 | tbl_sidecar2122 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
124 | tbl_sidecar213 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
125 | tbl_sidecar213-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
126 | tbl_sidecar225 | 1 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
127 | tbl_sidecar225-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
128 | tbl_sidecar243 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
129 | tbl_sidecar243-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
130 | tbl_sidecar258 | 1 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
131 | tbl_sidecar258-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
132 | Egress.mac_rewrite.ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
133 | Egress.mac_rewrite.mac_rewrite | 2 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 |
134 | Egress.mac_rewrite.mac_rewrite$action | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
135 | Egress.mcast_egress.port_bitmap_check | 2 | 1 | 10 | 0 | 1 | 0 | 0 | 4 | 9 | 1 | 1 | 0 |
136 | Ingress.nat_ingress.ingress_ipv4 | 2 | 8 | 0 | 0 | 0 | 4 | 0 | 26 | 2 | 0 | 0 | 0 |
137 | Ingress.nat_ingress.ingress_ipv4$action | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
138 | Ingress.nat_ingress.ingress_ipv6 | 2 | 20 | 0 | 0 | 0 | 20 | 0 | 26 | 2 | 0 | 0 | 0 |
139 | Ingress.nat_ingress.ingress_ipv6$action | 2 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
140 | Ingress.nat_ingress.ipv4_ingress_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
141 | Ingress.nat_ingress.ipv6_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
142 | Ingress.packet_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
143 | cond-135 | 2 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
144 | cond-82 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
145 | tbl_sidecar1932 | 2 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
146 | tbl_sidecar1932-gateway | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
147 | tbl_sidecar2130 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
148 | tbl_sidecar2139 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
149 | Egress.drop_reason_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
150 | Egress.mcast_egress.modify_hdr | 3 | 3 | 0 | 0 | 1 | 1 | 0 | 4 | 5 | 0 | 0 | 1 |
151 | Ingress.filter.ipv6_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
152 | Ingress.filter.switch_ipv6_addr | 3 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 |
153 | Ingress.ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
154 | Ingress.nat_ingress.ingress_ipv4 | 3 | 8 | 0 | 0 | 0 | 6 | 0 | 26 | 2 | 0 | 0 | 0 |
155 | Ingress.nat_ingress.ingress_ipv4$action | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
156 | Ingress.nat_ingress.ipv4_ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
157 | cond-130 | 3 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
158 | cond-136 | 3 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
159 | cond-83 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
160 | tbl_sidecar1900 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
161 | tbl_sidecar1931 | 3 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
162 | tbl_sidecar1931-gateway | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
163 | tbl_sidecar2146 | 3 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
164 | Egress.drop_port_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
165 | Egress.mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
166 | Egress.unicast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
167 | Ingress.nat_ingress.CalculateIPv4Len.ipv4_set_len | 4 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
168 | Ingress.nat_ingress.ingress_hit | 4 | 4 | 0 | 0 | 1 | 1 | 0 | 8 | 4 | 0 | 0 | 1 |
169 | Ingress.nat_ingress.ingress_hit$action | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
170 | Ingress.nat_ingress.nat_only | 4 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 |
171 | Ingress.nat_ingress.nat_only_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
172 | cond-126 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
173 | cond-131 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
174 | cond-132 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
175 | cond-133 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
176 | cond-134 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
177 | cond-137 | 4 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
178 | cond-89 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
179 | cond-92 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
180 | cond-93 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
181 | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5-gateway | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
182 | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5_egress | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
183 | tbl_sidecar1453 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
184 | tbl_sidecar1455 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
185 | tbl_sidecar1458 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
186 | tbl_sidecar1468_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
187 | tbl_sidecar1470_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
188 | tbl_sidecar2009 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
189 | tbl_sidecar2145 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
190 | tbl_sidecar2145-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
191 | tbl_sidecar2148 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
192 | tbl_sidecar2162 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
193 | tbl_sidecar2162-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
194 | Egress.external_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
195 | Egress.link_local_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
196 | Egress.underlay_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
197 | cond-138 | 5 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
198 | cond-139 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
199 | cond-140 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
200 | cond-90 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
201 | tbl_nat_ingress_CalculateIPv4Len_invert | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
202 | tbl_nat_ingress_encap_ipv4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 1 | 0 | 0 | 1 |
203 | tbl_nat_ingress_encap_ipv4$action | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
204 | tbl_nat_ingress_encap_ipv6 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 23 | 1 | 0 | 0 | 1 |
205 | tbl_nat_ingress_encap_ipv6$action | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
206 | tbl_sidecar1458_0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
207 | tbl_sidecar1473 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
208 | tbl_sidecar2151 | 5 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
209 | tbl_sidecar2153 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
210 | tbl_sidecar2157 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
211 | Ingress.services.service | 6 | 11 | 0 | 0 | 1 | 2 | 0 | 10 | 7 | 0 | 0 | 1 |
212 | Ingress.services.service$action | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
213 | Ingress.services.service_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
214 | cond-94 | 6 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
215 | cond-95 | 6 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
216 | tbl_sidecar443 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
217 | tbl_sidecar447 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
218 | Ingress.mcast_ingress.mcast_ipv4_ssm_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
219 | Ingress.mcast_ingress.mcast_ipv6_ssm_ctr | 7 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
220 | Ingress.mcast_ingress.mcast_source_filter_ipv4 | 7 | 8 | 0 | 0 | 1 | 4 | 0 | 1 | 2 | 0 | 0 | 1 |
221 | Ingress.mcast_ingress.mcast_source_filter_ipv6 | 7 | 32 | 40 | 0 | 12 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
222 | cond-100 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
223 | cond-101 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
224 | cond-102 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
225 | cond-96 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
226 | cond-97 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
227 | cond-98 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
228 | cond-99 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
229 | tbl_mcast_ingress_drop_mcastv4_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
230 | tbl_mcast_ingress_drop_mcastv6_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
231 | tbl_sidecar1678 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
232 | tbl_sidecar1687 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
233 | Ingress.mcast_ingress.mcast_ipv6_ctr | 8 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
234 | Ingress.mcast_ingress.mcast_replication_ipv6 | 8 | 58 | 66 | 0 | 8 | 0 | 0 | 15 | 2 | 1 | 1 | 0 |
235 | Ingress.mcast_ingress.mcast_replication_ipv6$action | 8 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
236 | cond-103 | 8 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
237 | mcast_ingress_mcast_replication_ipv6 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
238 | Ingress.mcast_ingress.mcast_tag_check | 9 | 7 | 0 | 0 | 1 | 2 | 0 | 0 | 5 | 0 | 0 | 1 |
239 | cond-104 | 10 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
240 | cond-105 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
241 | cond-91 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
242 | tbl_sidecar726 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
243 | Ingress.nat_egress.nat_egress | 11 | 2 | 10 | 0 | 1 | 0 | 0 | 8 | 7 | 1 | 1 | 0 |
244 | Ingress.nat_egress.nat_egress$action | 11 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
245 | cond-106 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
246 | Ingress.l3_router.Router4.lookup_idx.index_ctr | 12 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
247 | Ingress.l3_router.Router4.lookup_idx.lookup | 12 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 |
248 | Ingress.l3_router.Router4.lookup_idx.lookup$action | 12 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
249 | cond-107 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
250 | cond-108 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
251 | cond-109 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
252 | cond-110 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
253 | cond-113 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
254 | cond-117 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
255 | ingresshdr.icmp.hdr_checksum_encode_update_condition_4-gateway | 12 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
256 | ingresshdr.icmp.hdr_checksum_encode_update_condition_4_ingress | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
257 | tbl_sidecar1134 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
258 | tbl_sidecar1146 | 12 | 12 | 8 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 0 |
259 | tbl_sidecar1146-gateway | 12 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
260 | tbl_sidecar1223 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
261 | tbl_sidecar1232 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
262 | Ingress.l3_router.MulticastRouter4.ctr | 13 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
263 | Ingress.l3_router.MulticastRouter4.tbl | 13 | 4 | 40 | 0 | 4 | 0 | 0 | 2 | 3 | 1 | 1 | 0 |
264 | Ingress.l3_router.Router4.lookup_idx.select_route | 13 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
265 | Ingress.l3_router.Router6.lookup.ctr | 13 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
266 | Ingress.l3_router.Router6.lookup.tbl | 13 | 16 | 0 | 0 | 1 | 9 | 0 | 22 | 3 | 0 | 0 | 1 |
267 | Ingress.l3_router.Router6.lookup.tbl$action | 13 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
268 | cond-111 | 13 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
269 | cond-112 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
270 | cond-114 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
271 | cond-115 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
272 | cond-118 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
273 | cond-119 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
274 | ingresshdr.udp.checksum_encode_update_condition_3_ingress | 13 | 3 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
275 | tbl_sidecar1157 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
276 | tbl_sidecar1238 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
277 | tbl_sidecar1241 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
278 | tbl_sidecar1247 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
279 | tbl_sidecar1348 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
280 | Ingress.l3_router.MulticastRouter6.ctr | 14 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
281 | Ingress.l3_router.MulticastRouter6.tbl | 14 | 16 | 40 | 0 | 8 | 0 | 0 | 2 | 3 | 1 | 1 | 0 |
282 | cond-120 | 14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
283 | cond-121 | 14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
284 | cond-122 | 14 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
285 | tbl_l3_router_MulticastRouter4_icmp_error | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
286 | tbl_l3_router_MulticastRouter4_icmp_error$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
287 | tbl_l3_router_MulticastRouter4_icmp_error_0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
288 | tbl_l3_router_MulticastRouter4_icmp_error_0$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
289 | tbl_l3_router_Router6_icmp_error | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
290 | tbl_l3_router_Router6_icmp_error$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
291 | tbl_l3_router_Router6_icmp_error_0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
292 | tbl_l3_router_Router6_icmp_error_0$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
293 | tbl_sidecar1010 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
294 | tbl_sidecar1244 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
295 | tbl_sidecar1281 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
296 | tbl_sidecar1284 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
297 | tbl_sidecar1286 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
298 | tbl_sidecar1354 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
299 | tbl_sidecar1357 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
300 | Ingress.l3_router.Router4.lookup_idx.forward_ctr | 15 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
301 | Ingress.l3_router.Router4.lookup_idx.route | 15 | 2 | 40 | 0 | 4 | 0 | 0 | 8 | 3 | 1 | 1 | 0 |
302 | Ingress.l3_router.Router4.lookup_idx.route$action | 15 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
303 | Ingress.l3_router.Router6.Ndp.ctr | 15 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
304 | Ingress.l3_router.Router6.Ndp.tbl | 15 | 16 | 40 | 0 | 8 | 0 | 0 | 9 | 3 | 1 | 1 | 0 |
305 | Ingress.l3_router.Router6.Ndp.tbl$action | 15 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
306 | tbl_l3_router_MulticastRouter6_icmp_error | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
307 | tbl_l3_router_MulticastRouter6_icmp_error$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
308 | tbl_l3_router_MulticastRouter6_icmp_error_0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
309 | tbl_l3_router_MulticastRouter6_icmp_error_0$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
310 | tbl_sidecar1360 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
311 | cond-116 | 16 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
312 | tbl_l3_router_Router4_icmp_error | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
313 | tbl_l3_router_Router4_icmp_error$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
314 | tbl_l3_router_Router4_icmp_error_0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 |
315 | tbl_l3_router_Router4_icmp_error_0$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
316 | tbl_sidecar1160 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
317 | tbl_sidecar1162 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
318 | Ingress.l3_router.Router4.Arp.ctr | 17 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
319 | Ingress.l3_router.Router4.Arp.tbl | 17 | 4 | 40 | 0 | 4 | 0 | 0 | 8 | 3 | 1 | 1 | 0 |
320 | Ingress.l3_router.Router4.Arp.tbl$action | 17 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
321 | Ingress.drop_port_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
322 | Ingress.drop_reason_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
323 | Ingress.egress_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
324 | Ingress.mac_rewrite.ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
325 | Ingress.mac_rewrite.mac_rewrite | 18 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 |
326 | Ingress.mac_rewrite.mac_rewrite$action | 18 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
327 | cond-123 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
328 | cond-124 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
329 | cond-125 | 18 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
330 | tbl_sidecar1966 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
331 | tbl_sidecar1966-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
332 | tbl_sidecar1967 | 18 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
333 | tbl_sidecar1969 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
334 | tbl_sidecar1969-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
335 | tbl_sidecar1973 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
336 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
337