+---------------------------------------------------------------------+ | Log file: mau.resources.log | | Compiler version: 9.13.4 | | Created on: Thu Sep 25 20:30:31 2025 | | Run ID: 50f1101e24804ae4 | +---------------------------------------------------------------------+ --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 22 | 6 | 9 | 1 | 15 | 5 | 4 | 2 | 7 | 0 | 2 | 0 | 13 | 4 | 7 | 3 | 0 | 0 | 0 | 16 | | 1 | 36 | 39 | 139 | 1 | 12 | 54 | 10 | 9 | 4 | 0 | 4 | 0 | 13 | 5 | 8 | 95 | 0 | 0 | 0 | 15 | | 2 | 5 | 24 | 30 | 1 | 1 | 20 | 9 | 24 | 8 | 0 | 4 | 0 | 3 | 3 | 0 | 62 | 0 | 0 | 0 | 5 | | 3 | 12 | 11 | 26 | 3 | 4 | 13 | 8 | 7 | 4 | 0 | 4 | 0 | 3 | 3 | 2 | 30 | 0 | 0 | 0 | 6 | | 4 | 18 | 0 | 29 | 1 | 13 | 10 | 8 | 0 | 5 | 0 | 4 | 0 | 13 | 7 | 11 | 9 | 0 | 0 | 0 | 15 | | 5 | 8 | 0 | 9 | 1 | 4 | 6 | 4 | 0 | 3 | 0 | 2 | 0 | 4 | 2 | 8 | 35 | 0 | 0 | 0 | 8 | | 6 | 5 | 10 | 1 | 0 | 2 | 3 | 2 | 2 | 6 | 0 | 1 | 0 | 2 | 0 | 3 | 4 | 0 | 0 | 0 | 3 | | 7 | 39 | 8 | 40 | 0 | 7 | 18 | 5 | 4 | 5 | 0 | 2 | 0 | 8 | 1 | 6 | 4 | 0 | 0 | 0 | 9 | | 8 | 60 | 0 | 66 | 2 | 1 | 15 | 3 | 0 | 2 | 0 | 1 | 0 | 2 | 1 | 1 | 15 | 0 | 0 | 0 | 1 | | 9 | 3 | 7 | 0 | 0 | 2 | 1 | 0 | 2 | 4 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 3 | | 10 | 3 | 0 | 10 | 0 | 1 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | 1 | 1 | 0 | 14 | 0 | 0 | 0 | 1 | | 11 | 51 | 20 | 26 | 2 | 9 | 12 | 7 | 22 | 6 | 0 | 2 | 0 | 9 | 4 | 7 | 19 | 0 | 0 | 0 | 13 | | 12 | 24 | 16 | 80 | 0 | 5 | 21 | 8 | 3 | 9 | 0 | 3 | 0 | 6 | 2 | 11 | 20 | 0 | 0 | 0 | 14 | | 13 | 5 | 0 | 80 | 0 | 2 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | 2 | 2 | 5 | 21 | 0 | 0 | 0 | 8 | | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 2 | | 15 | 4 | 0 | 80 | 0 | 0 | 24 | 8 | 0 | 4 | 0 | 2 | 0 | 2 | 2 | 0 | 30 | 0 | 0 | 0 | 2 | | 16 | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 2 | 0 | 8 | 18 | 0 | 0 | 0 | 8 | | 17 | 20 | 0 | 80 | 0 | 0 | 20 | 6 | 0 | 4 | 0 | 2 | 0 | 2 | 2 | 0 | 13 | 0 | 0 | 0 | 2 | | 18 | 9 | 0 | 36 | 3 | 5 | 10 | 8 | 0 | 2 | 0 | 4 | 0 | 4 | 4 | 3 | 6 | 0 | 0 | 0 | 5 | | | | | | | | | | | | | | | | | | | | | | | | Totals | 327 | 141 | 741 | 15 | 85 | 242 | 90 | 75 | 94 | 0 | 37 | 0 | 91 | 43 | 83 | 398 | 0 | 0 | 0 | 136 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 17.19% | 9.09% | 2.16% | 16.67% | 93.75% | 6.25% | 8.33% | 8.33% | 21.88% | 0.00% | 50.00% | 0.00% | 81.25% | 25.00% | 43.75% | 2.34% | 0.00% | 0.00% | 0.00% | 100.00% | | 1 | 28.12% | 59.09% | 33.41% | 16.67% | 75.00% | 67.50% | 20.83% | 37.50% | 12.50% | 0.00% | 100.00% | 0.00% | 81.25% | 31.25% | 50.00% | 74.22% | 0.00% | 0.00% | 0.00% | 93.75% | | 2 | 3.91% | 36.36% | 7.21% | 16.67% | 6.25% | 25.00% | 18.75% | 100.00% | 25.00% | 0.00% | 100.00% | 0.00% | 18.75% | 18.75% | 0.00% | 48.44% | 0.00% | 0.00% | 0.00% | 31.25% | | 3 | 9.38% | 16.67% | 6.25% | 50.00% | 25.00% | 16.25% | 16.67% | 29.17% | 12.50% | 0.00% | 100.00% | 0.00% | 18.75% | 18.75% | 12.50% | 23.44% | 0.00% | 0.00% | 0.00% | 37.50% | | 4 | 14.06% | 0.00% | 6.97% | 16.67% | 81.25% | 12.50% | 16.67% | 0.00% | 15.62% | 0.00% | 100.00% | 0.00% | 81.25% | 43.75% | 68.75% | 7.03% | 0.00% | 0.00% | 0.00% | 93.75% | | 5 | 6.25% | 0.00% | 2.16% | 16.67% | 25.00% | 7.50% | 8.33% | 0.00% | 9.38% | 0.00% | 50.00% | 0.00% | 25.00% | 12.50% | 50.00% | 27.34% | 0.00% | 0.00% | 0.00% | 50.00% | | 6 | 3.91% | 15.15% | 0.24% | 0.00% | 12.50% | 3.75% | 4.17% | 8.33% | 18.75% | 0.00% | 25.00% | 0.00% | 12.50% | 0.00% | 18.75% | 3.12% | 0.00% | 0.00% | 0.00% | 18.75% | | 7 | 30.47% | 12.12% | 9.62% | 0.00% | 43.75% | 22.50% | 10.42% | 16.67% | 15.62% | 0.00% | 50.00% | 0.00% | 50.00% | 6.25% | 37.50% | 3.12% | 0.00% | 0.00% | 0.00% | 56.25% | | 8 | 46.88% | 0.00% | 15.87% | 33.33% | 6.25% | 18.75% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 12.50% | 6.25% | 6.25% | 11.72% | 0.00% | 0.00% | 0.00% | 6.25% | | 9 | 2.34% | 10.61% | 0.00% | 0.00% | 12.50% | 1.25% | 0.00% | 8.33% | 12.50% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 18.75% | | 10 | 2.34% | 0.00% | 2.40% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 21.88% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 10.94% | 0.00% | 0.00% | 0.00% | 6.25% | | 11 | 39.84% | 30.30% | 6.25% | 33.33% | 56.25% | 15.00% | 14.58% | 91.67% | 18.75% | 0.00% | 50.00% | 0.00% | 56.25% | 25.00% | 43.75% | 14.84% | 0.00% | 0.00% | 0.00% | 81.25% | | 12 | 18.75% | 24.24% | 19.23% | 0.00% | 31.25% | 26.25% | 16.67% | 12.50% | 28.12% | 0.00% | 75.00% | 0.00% | 37.50% | 12.50% | 68.75% | 15.62% | 0.00% | 0.00% | 0.00% | 87.50% | | 13 | 3.91% | 0.00% | 19.23% | 0.00% | 12.50% | 10.00% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 12.50% | 12.50% | 31.25% | 16.41% | 0.00% | 0.00% | 0.00% | 50.00% | | 14 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | | 15 | 3.12% | 0.00% | 19.23% | 0.00% | 0.00% | 30.00% | 16.67% | 0.00% | 12.50% | 0.00% | 50.00% | 0.00% | 12.50% | 12.50% | 0.00% | 23.44% | 0.00% | 0.00% | 0.00% | 12.50% | | 16 | 2.34% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 50.00% | 14.06% | 0.00% | 0.00% | 0.00% | 50.00% | | 17 | 15.62% | 0.00% | 19.23% | 0.00% | 0.00% | 25.00% | 12.50% | 0.00% | 12.50% | 0.00% | 50.00% | 0.00% | 12.50% | 12.50% | 0.00% | 10.16% | 0.00% | 0.00% | 0.00% | 12.50% | | 18 | 7.03% | 0.00% | 8.65% | 50.00% | 31.25% | 12.50% | 16.67% | 0.00% | 6.25% | 0.00% | 100.00% | 0.00% | 25.00% | 25.00% | 18.75% | 4.69% | 0.00% | 0.00% | 0.00% | 31.25% | | | | | | | | | | | | | | | | | | | | | | | | Average | 13.45% | 11.24% | 9.38% | 13.16% | 27.96% | 15.92% | 9.87% | 16.45% | 15.46% | 0.00% | 48.68% | 0.00% | 29.93% | 14.14% | 27.30% | 16.37% | 0.00% | 0.00% | 0.00% | 44.74% | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Allocated Resource Usage -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind | | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result | | | | | | | | | | Bus | | Bus | Bus | Bus | | | | | | | | | | Bytes | | | | | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.drop_mcast_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 | | cond-72 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-73 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-74 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-75 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-76 | 0 | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-77 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-78 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-79 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-80 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-81 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-82 | 0 | 8 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_filter_drop_mcast | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_filter_drop_mcast_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_filter_drop_mcast_with_reason | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_filter_drop_mcast_with_reason_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_filter_drop_mcast_with_reason_1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_filter_drop_with_reason | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar211 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar211-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar223 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar223-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar239 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar239-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar253 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar253-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Egress.mcast_egress.asic_id_to_port | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | Egress.mcast_egress.mcast_tag_check | 1 | 19 | 0 | 0 | 1 | 4 | 0 | 0 | 1 | 0 | 0 | 1 | | Egress.mcast_egress.tbl_decap_ports | 1 | 2 | 40 | 0 | 4 | 0 | 0 | 34 | 3 | 1 | 1 | 0 | | Egress.mcast_egress.tbl_decap_ports$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.drop_mcast_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.switch_ipv6_addr | 1 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 | | Ingress.nat_ingress.icmp_dst_port | 1 | 2 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4_mcast | 1 | 4 | 40 | 0 | 4 | 0 | 0 | 26 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_ipv4_mcast$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6_mcast | 1 | 16 | 40 | 0 | 8 | 0 | 0 | 26 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_ipv6_mcast$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.mcast_ipv4_ingress_ctr | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.mcast_ipv6_ingress_ctr | 1 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | cond-129 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-130 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-131 | 1 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-137 | 1 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-83 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-84 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-85 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-86 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-87 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-88 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-89 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar185 | 1 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar185-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2183 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar2191 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | tbl_sidecar2200 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | Egress.mac_rewrite.ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.mac_rewrite.mac_rewrite | 2 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 | | Egress.mac_rewrite.mac_rewrite$action | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Egress.mcast_egress.port_bitmap_check | 2 | 1 | 10 | 0 | 1 | 0 | 0 | 4 | 9 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_ipv4 | 2 | 8 | 0 | 0 | 0 | 4 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4$action | 2 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6 | 2 | 20 | 0 | 0 | 0 | 20 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6$action | 2 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv6_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.packet_ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1993 | 2 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1993-gateway | 2 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Egress.drop_port_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.drop_reason_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.mcast_egress.modify_hdr | 3 | 3 | 0 | 0 | 1 | 1 | 0 | 4 | 5 | 0 | 0 | 1 | | Ingress.ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4 | 3 | 8 | 0 | 0 | 0 | 6 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4$action | 3 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-132 | 3 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-138 | 3 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar1961 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1992 | 3 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar1992-gateway | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2206 | 3 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2206-gateway | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2207 | 3 | 2 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | Egress.link_local_mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.unicast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.CalculateIPv4Len.ipv4_set_len | 4 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_hit | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | | Ingress.nat_ingress.nat_only | 4 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.nat_only_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-128 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-133 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-134 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-135 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-136 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-139 | 4 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-140 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-90 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-93 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-94 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5-gateway | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5_egress | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | | nat_ingress_ingress_hit-gateway | 4 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar1514 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | tbl_sidecar1516 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | tbl_sidecar1519 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | tbl_sidecar1529_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1531_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2070 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2209 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2212 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2223 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2223-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Egress.external_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.underlay_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-141 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-142 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-91 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-95 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_nat_ingress_CalculateIPv4Len_invert | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_nat_ingress_encap_ipv6 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 17 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv6$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1519_0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1534 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 | | tbl_sidecar2214 | 5 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2218 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar438 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | Ingress.services.service | 6 | 10 | 0 | 0 | 1 | 2 | 0 | 4 | 7 | 0 | 0 | 1 | | Ingress.services.service_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-92 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-96 | 6 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar442 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar716 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.mcast_ingress.mcast_ipv4_ssm_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_ipv6_ssm_ctr | 7 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_source_filter_ipv4 | 7 | 8 | 0 | 0 | 1 | 4 | 0 | 1 | 2 | 0 | 0 | 1 | | Ingress.mcast_ingress.mcast_source_filter_ipv6 | 7 | 32 | 40 | 0 | 12 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | cond-100 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-101 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-102 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-103 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-97 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-98 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-99 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_mcast_ingress_drop_mcastv4_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_mcast_ingress_drop_mcastv6_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1739 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1748 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.mcast_ingress.mcast_ipv6_ctr | 8 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_replication_ipv6 | 8 | 58 | 66 | 0 | 8 | 0 | 0 | 15 | 2 | 1 | 1 | 0 | | Ingress.mcast_ingress.mcast_replication_ipv6$action | 8 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-104 | 8 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | mcast_ingress_mcast_replication_ipv6 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_tag_check | 9 | 7 | 0 | 0 | 1 | 2 | 0 | 0 | 5 | 0 | 0 | 1 | | cond-105 | 9 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-106 | 9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.nat_egress.nat_egress | 10 | 2 | 10 | 0 | 1 | 0 | 0 | 14 | 7 | 1 | 1 | 0 | | Ingress.nat_egress.nat_egress$action | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-107 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.lookup | 11 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.lookup$action | 11 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 11 | 16 | 0 | 0 | 1 | 6 | 0 | 6 | 2 | 0 | 0 | 1 | | cond-108 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-109 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-110 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-111 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-114 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-118 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-119 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-120 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_4-gateway | 11 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_4_ingress | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | | ingresshdr.udp.checksum_encode_update_condition_3_ingress | 11 | 3 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | tbl_sidecar1174 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1190$precompute | 11 | 12 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | | tbl_sidecar1267 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1276 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1331$precompute | 11 | 36 | 8 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 1 | 0 | | tbl_sidecar1409 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.MulticastRouter4.ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.MulticastRouter4.tbl | 12 | 4 | 40 | 0 | 4 | 0 | 0 | 2 | 3 | 1 | 1 | 0 | | Ingress.l3_router.MulticastRouter6.ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.MulticastRouter6.tbl | 12 | 16 | 40 | 0 | 8 | 0 | 0 | 2 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 12 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 12 | 16 | 0 | 0 | 1 | 3 | 0 | 6 | 2 | 0 | 0 | 1 | | cond-112 | 12 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-113 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-115 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-116 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-121 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1190 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1201 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1282 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1285 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1288 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1291 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1331 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar1415 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1418 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1421 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.select_route | 13 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.select_route | 13 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | cond-122 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-123 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_MulticastRouter4_icmp_error | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_l3_router_MulticastRouter4_icmp_error_0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_l3_router_MulticastRouter6_icmp_error | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_l3_router_MulticastRouter6_icmp_error_0 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar1342 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1050 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar955 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.forward_ctr | 15 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.route | 15 | 2 | 40 | 0 | 4 | 0 | 0 | 8 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router4.lookup_idx.route$action | 15 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.forward_ctr | 15 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.route | 15 | 2 | 40 | 0 | 4 | 0 | 0 | 22 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.route$action | 15 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-117 | 16 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-124 | 16 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_Router4_icmp_error | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error_0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error_0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar1204 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1206 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1345 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1347 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.Arp.ctr | 17 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.Arp.tbl | 17 | 4 | 40 | 0 | 4 | 0 | 0 | 6 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router4.Arp.tbl$action | 17 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.Ndp.ctr | 17 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.Ndp.tbl | 17 | 16 | 40 | 0 | 8 | 0 | 0 | 7 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.Ndp.tbl$action | 17 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.drop_port_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.drop_reason_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.egress_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.mac_rewrite | 18 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 | | Ingress.mac_rewrite.mac_rewrite$action | 18 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-125 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-126 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-127 | 18 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar2027 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2027-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2028 | 18 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2030 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2030-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2034 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 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