| 1 | +---------------------------------------------------------------------+ | ||
| 2 | | Log file: pa.results.log | | ||
| 3 | | Compiler version: 9.13.4 | | ||
| 4 | | Created on: Thu Sep 25 20:30:28 2025 | | ||
| 5 | | Run ID: 50f1101e24804ae4 | | ||
| 6 | +---------------------------------------------------------------------+ | ||
| 7 | |||
| 8 | Allocation state: Final Allocation | ||
| 9 | ------------------------------------------------------------------------------ | ||
| 10 | | PHV Group | Containers Used | Bits Used | Bits Available | | ||
| 11 | | (container bit widths) | (% used) | (% used) | | | ||
| 12 | ------------------------------------------------------------------------------ | ||
| 13 | | 0 (32) | 17 (85.00%) | 521 (81.41%) | 640 | | ||
| 14 | | 1 (32) | 17 (85.00%) | 512 (80.00%) | 640 | | ||
| 15 | | 2 (32) | 15 (75.00%) | 480 (75.00%) | 640 | | ||
| 16 | | 3 (32) | 6 (30.00%) | 192 (30.00%) | 640 | | ||
| 17 | | Total for 32 bit | 55 (68.75%) | 1705 (66.60%) | 2560 | | ||
| 18 | | | | | | | ||
| 19 | | 4 (8) | 16 (80.00%) | 119 (74.38%) | 160 | | ||
| 20 | | 5 (8) | 4 (20.00%) | 25 (15.62%) | 160 | | ||
| 21 | | 6 (8) | 4 (20.00%) | 32 (20.00%) | 160 | | ||
| 22 | | 7 (8) | 5 (25.00%) | 33 (20.62%) | 160 | | ||
| 23 | | Total for 8 bit | 29 (36.25%) | 209 (32.66%) | 640 | | ||
| 24 | | | | | | | ||
| 25 | | 8 (16) | 20 (100.00%) | 311 (97.19%) | 320 | | ||
| 26 | | 9 (16) | 16 (80.00%) | 251 (78.44%) | 320 | | ||
| 27 | | 10 (16) | 19 (95.00%) | 296 (92.50%) | 320 | | ||
| 28 | | 11 (16) | 20 (100.00%) | 299 (93.44%) | 320 | | ||
| 29 | | 12 (16) | 19 (95.00%) | 285 (89.06%) | 320 | | ||
| 30 | | 13 (16) | 20 (100.00%) | 306 (95.62%) | 320 | | ||
| 31 | | Total for 16 bit | 114 (95.00%) | 1748 (91.04%) | 1920 | | ||
| 32 | | | | | | | ||
| 33 | | Overall total | 198 (70.71%) | 3662 (71.52%) | 5120 | | ||
| 34 | ------------------------------------------------------------------------------ | ||
| 35 | |||
| 36 | -------------------------------------------- | ||
| 37 | PHV Allocation | ||
| 38 | -------------------------------------------- | ||
| 39 | |||
| 40 | Allocations in Group 0 32 bits | ||
| 41 | 32-bit PHV 0n (egress): phv0[31:16] = is_link_local_ipv6_mcast_0[15:0] | ||
| 42 | 32-bit PHV 1n (ingress): phv1[31:16] = hdr.geneve_opts.oxg_ext_tag.class[15:0] (deparsed) | ||
| 43 | 32-bit PHV 1n (ingress): phv1[15:15] = hdr.geneve_opts.oxg_ext_tag.crit[0:0] (deparsed) | ||
| 44 | 32-bit PHV 1n (ingress): phv1[14:8] = hdr.geneve_opts.oxg_ext_tag.type[6:0] (deparsed) | ||
| 45 | 32-bit PHV 1n (ingress): phv1[7:5] = hdr.geneve_opts.oxg_ext_tag.reserved[2:0] (deparsed) | ||
| 46 | 32-bit PHV 1n (ingress): phv1[4:0] = hdr.geneve_opts.oxg_ext_tag.opt_len[4:0] (deparsed) | ||
| 47 | 32-bit PHV 2n (egress): phv2[31:16] = hdr.geneve_opts.oxg_ext_tag.class[15:0] (deparsed) | ||
| 48 | 32-bit PHV 2n (egress): phv2[31:30] = hdr.geneve_opts.oxg_mcast.mcast_tag[1:0] (deparsed) | ||
| 49 | 32-bit PHV 2n (egress): phv2[31:0] = hdr.geneve_opts.oxg_mss.mss[31:0] (deparsed) | ||
| 50 | 32-bit PHV 2n (egress): phv2[29:0] = hdr.geneve_opts.oxg_mcast.reserved[29:0] (deparsed) | ||
| 51 | 32-bit PHV 2n (egress): phv2[15:15] = hdr.geneve_opts.oxg_ext_tag.crit[0:0] (deparsed) | ||
| 52 | 32-bit PHV 2n (egress): phv2[14:8] = hdr.geneve_opts.oxg_ext_tag.type[6:0] (deparsed) | ||
| 53 | 32-bit PHV 2n (egress): phv2[7:5] = hdr.geneve_opts.oxg_ext_tag.reserved[2:0] (deparsed) | ||
| 54 | 32-bit PHV 2n (egress): phv2[4:0] = hdr.geneve_opts.oxg_ext_tag.opt_len[4:0] (deparsed) | ||
| 55 | 32-bit PHV 3n (egress): phv3[31:28] = hdr.tcp.data_offset[3:0] (deparsed) | ||
| 56 | 32-bit PHV 3n (egress): phv3[27:24] = hdr.tcp.res[3:0] (deparsed) | ||
| 57 | 32-bit PHV 3n (egress): phv3[23:16] = hdr.tcp.flags[7:0] (deparsed) | ||
| 58 | 32-bit PHV 3n (egress): phv3[15:0] = hdr.tcp.window[15:0] (deparsed) | ||
| 59 | 32-bit PHV 4n (ingress): phv4[31:30] = hdr.geneve.version[1:0] (deparsed) | ||
| 60 | 32-bit PHV 4n (ingress): phv4[29:24] = hdr.geneve.opt_len[5:0] (deparsed) | ||
| 61 | 32-bit PHV 4n (ingress): phv4[23:23] = hdr.geneve.ctrl[0:0] (deparsed) | ||
| 62 | 32-bit PHV 4n (ingress): phv4[22:22] = hdr.geneve.crit[0:0] (deparsed) | ||
| 63 | 32-bit PHV 4n (ingress): phv4[21:16] = hdr.geneve.reserved[5:0] (deparsed) | ||
| 64 | 32-bit PHV 4n (ingress): phv4[15:0] = hdr.geneve.protocol[15:0] (deparsed) | ||
| 65 | 32-bit PHV 5n (ingress): phv5[31:8] = hdr.geneve.vni[23:0] (deparsed) | ||
| 66 | 32-bit PHV 5n (ingress): phv5[7:0] = hdr.geneve.reserved2[7:0] (deparsed) | ||
| 67 | 32-bit PHV 6n (egress): phv6[31:16] = hdr.tcp.checksum[15:0] (deparsed) | ||
| 68 | 32-bit PHV 6n (egress): phv6[15:0] = hdr.tcp.urgent_ptr[15:0] (deparsed) | ||
| 69 | 32-bit PHV 7n (egress): phv7[31:16] = hdr.tcp.src_port[15:0] (deparsed) | ||
| 70 | 32-bit PHV 7n (egress): phv7[15:0] = hdr.tcp.dst_port[15:0] (deparsed) | ||
| 71 | 32-bit PHV 8n (ingress): phv8[31:0] = hdr.ethernet.src_mac[47:16] (deparsed) | ||
| 72 | 32-bit PHV 9n (ingress): phv9[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed) | ||
| 73 | 32-bit PHV 9n (ingress): phv9[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed) | ||
| 74 | 32-bit PHV 9n (ingress): phv9[7:0] = l3_router_Router6_fwd.slots[7:0] | ||
| 75 | 32-bit PHV 10n (egress): phv10[31:0] = hdr.ethernet.src_mac[31:0] (deparsed) | ||
| 76 | 32-bit PHV 11n (egress): phv11[31:0] = hdr.inner_ipv6.dst_addr[95:64] (deparsed) | ||
| 77 | 32-bit PHV 12m (egress): phv12[31:0] = hdr.ipv6.dst_addr[127:96] (deparsed) | ||
| 78 | 32-bit PHV 13m (egress): phv13[31:0] = hdr.ipv6.dst_addr[63:32] (deparsed) | ||
| 79 | 32-bit PHV 14m (egress): phv14[31:0] = hdr.ipv6.dst_addr[95:64] (deparsed) | ||
| 80 | 32-bit PHV 15m (ingress): phv15[31:8] = meta.nat_geneve_vni[23:0] | ||
| 81 | 32-bit PHV 15m (ingress): phv15[0:0] = meta.nat_ingress_hit[0:0] | ||
| 82 | 32-bit PHV 16d (ingress): phv16[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed) | ||
| 83 | >> 7 in ingress and 10 in egress | ||
| 84 | |||
| 85 | Allocations in Group 1 32 bits | ||
| 86 | 32-bit PHV 20n (ingress): phv20[31:16] = hdr.ipv4.identification[15:0] (deparsed) | ||
| 87 | 32-bit PHV 20n (ingress): phv20[31:0] = hdr.ipv6.src_addr[127:96] (deparsed) | ||
| 88 | 32-bit PHV 20n (ingress): phv20[15:13] = hdr.ipv4.flags[2:0] (deparsed) | ||
| 89 | 32-bit PHV 20n (ingress): phv20[12:0] = hdr.ipv4.frag_offset[12:0] (deparsed) | ||
| 90 | 32-bit PHV 21n (ingress): phv21[31:16] = hdr.inner_ipv4.identification[15:0] (deparsed) | ||
| 91 | 32-bit PHV 21n (ingress): phv21[31:28] = hdr.inner_ipv6.version[3:0] (deparsed) | ||
| 92 | 32-bit PHV 21n (ingress): phv21[27:20] = hdr.inner_ipv6.traffic_class[7:0] (deparsed) | ||
| 93 | 32-bit PHV 21n (ingress): phv21[19:0] = hdr.inner_ipv6.flow_label[19:0] (deparsed) | ||
| 94 | 32-bit PHV 21n (ingress): phv21[15:13] = hdr.inner_ipv4.flags[2:0] (deparsed) | ||
| 95 | 32-bit PHV 21n (ingress): phv21[12:0] = hdr.inner_ipv4.frag_offset[12:0] (deparsed) | ||
| 96 | 32-bit PHV 22n (ingress): phv22[31:28] = hdr.ipv6.version[3:0] (deparsed) | ||
| 97 | 32-bit PHV 22n (ingress): phv22[27:20] = hdr.ipv6.traffic_class[7:0] (deparsed) | ||
| 98 | 32-bit PHV 22n (ingress): phv22[19:0] = hdr.ipv6.flow_label[19:0] (deparsed) | ||
| 99 | 32-bit PHV 23n (ingress): phv23[31:16] = hdr.tcp.src_port[15:0] (deparsed) | ||
| 100 | 32-bit PHV 23n (ingress): phv23[31:16] = hdr.inner_tcp.src_port[15:0] (deparsed) | ||
| 101 | 32-bit PHV 23n (ingress): phv23[15:0] = hdr.tcp.dst_port[15:0] (deparsed) | ||
| 102 | 32-bit PHV 23n (ingress): phv23[15:0] = hdr.inner_tcp.dst_port[15:0] (deparsed) | ||
| 103 | 32-bit PHV 24n (ingress): phv24[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed) | ||
| 104 | 32-bit PHV 24n (ingress): phv24[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed) | ||
| 105 | 32-bit PHV 24n (ingress): phv24[0:0] = l3_router_Router6_fwd.is_hit[0:0] | ||
| 106 | 32-bit PHV 25n (ingress): phv25[7:0] = l3_router_Router6_fwd.ecmp_hash[7:0] | ||
| 107 | 32-bit PHV 26n (ingress): phv26[31:0] = meta.nat_inner_mac[31:0] | ||
| 108 | 32-bit PHV 27n (egress): phv27[31:0] = hdr.inner_ipv6.dst_addr[127:96] (deparsed) | ||
| 109 | 32-bit PHV 28n (egress): phv28[31:0] = hdr.tcp.ack_no[31:0] (deparsed) | ||
| 110 | 32-bit PHV 29n (egress): phv29[31:0] = hdr.tcp.seq_no[31:0] (deparsed) | ||
| 111 | 32-bit PHV 30n (ingress): phv30[31:0] = meta.orig_dst_ipv4[31:0] | ||
| 112 | 32-bit PHV 31n (ingress): phv31[31:16] = meta.l4_src_port[15:0] | ||
| 113 | 32-bit PHV 31n (ingress): phv31[7:0] = $tmp14[7:0] | ||
| 114 | 32-bit PHV 32m (ingress): phv32[31:0] = hdr.inner_ipv6.dst_addr[127:96] (deparsed) | ||
| 115 | 32-bit PHV 33m (ingress): phv33[31:0] = hdr.inner_ipv6.src_addr[127:96] (deparsed) | ||
| 116 | 32-bit PHV 34m (ingress): phv34[31:0] = hdr.ipv6.dst_addr[127:96] (deparsed) | ||
| 117 | 32-bit PHV 35m (ingress): phv35[31:0] = meta.nat_ingress_tgt[127:96] | ||
| 118 | 32-bit PHV 36d (ingress): phv36[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed) | ||
| 119 | >> 14 in ingress and 3 in egress | ||
| 120 | |||
| 121 | Allocations in Group 2 32 bits | ||
| 122 | 32-bit PHV 40n (ingress): phv40[31:0] = hdr.ipv6.dst_addr[63:32] (deparsed) | ||
| 123 | 32-bit PHV 41n (ingress): phv41[31:0] = hdr.tcp.ack_no[31:0] (deparsed) | ||
| 124 | 32-bit PHV 41n (ingress): phv41[31:0] = hdr.inner_tcp.ack_no[31:0] (deparsed) | ||
| 125 | 32-bit PHV 42n (egress): phv42[31:0] = meta.decap_ports_0[31:0] | ||
| 126 | 32-bit PHV 43n (egress): phv43[31:0] = meta.decap_ports_1[31:0] | ||
| 127 | 32-bit PHV 44n (egress): phv44[31:0] = meta.decap_ports_2[31:0] | ||
| 128 | 32-bit PHV 45n (egress): phv45[31:0] = meta.decap_ports_3[31:0] | ||
| 129 | 32-bit PHV 46n (egress): phv46[31:0] = meta.decap_ports_4[31:0] | ||
| 130 | 32-bit PHV 47n (egress): phv47[31:0] = meta.decap_ports_5[31:0] | ||
| 131 | 32-bit PHV 48n (egress): phv48[31:0] = meta.decap_ports_6[31:0] | ||
| 132 | 32-bit PHV 49n (egress): phv49[31:0] = meta.decap_ports_7[31:0] | ||
| 133 | 32-bit PHV 50n (egress): phv50[31:0] = meta.bitmap_result[31:0] | ||
| 134 | 32-bit PHV 52m (ingress): phv52[31:0] = hdr.inner_ipv6.dst_addr[63:32] (deparsed) | ||
| 135 | 32-bit PHV 53m (ingress): phv53[31:0] = hdr.inner_ipv6.src_addr[63:32] (deparsed) | ||
| 136 | 32-bit PHV 54m (ingress): phv54[31:0] = hdr.ipv6.src_addr[63:32] (deparsed) | ||
| 137 | 32-bit PHV 55m (ingress): phv55[31:0] = meta.nat_ingress_tgt[63:32] | ||
| 138 | >> 6 in ingress and 9 in egress | ||
| 139 | |||
| 140 | Allocations in Group 3 32 bits | ||
| 141 | 32-bit PHV 60n (ingress): phv60[31:0] = hdr.ipv6.dst_addr[95:64] (deparsed) | ||
| 142 | 32-bit PHV 61n (ingress): phv61[31:0] = hdr.tcp.seq_no[31:0] (deparsed) | ||
| 143 | 32-bit PHV 61n (ingress): phv61[31:0] = hdr.inner_tcp.seq_no[31:0] (deparsed) | ||
| 144 | 32-bit PHV 72m (ingress): phv72[31:0] = hdr.inner_ipv6.dst_addr[95:64] (deparsed) | ||
| 145 | 32-bit PHV 73m (ingress): phv73[31:0] = hdr.inner_ipv6.src_addr[95:64] (deparsed) | ||
| 146 | 32-bit PHV 74m (ingress): phv74[31:0] = hdr.ipv6.src_addr[95:64] (deparsed) | ||
| 147 | 32-bit PHV 75m (ingress): phv75[31:0] = meta.nat_ingress_tgt[95:64] | ||
| 148 | >> 6 in ingress and 0 in egress | ||
| 149 | |||
| 150 | Allocations in Group 4 8 bits | ||
| 151 | 8-bit PHV 80n (ingress): phv80[7:0] = $tmp8[7:0] (deparsed) | ||
| 152 | 8-bit PHV 81n (ingress): phv81[7:7] = hdr.arp.$valid[0:0] (deparsed) | ||
| 153 | 8-bit PHV 81n (ingress): phv81[6:6] = hdr.geneve_opts.oxg_mss.$valid[0:0] | ||
| 154 | 8-bit PHV 81n (ingress): phv81[5:5] = hdr.geneve_opts.oxg_mss_tag.$valid[0:0] (deparsed) | ||
| 155 | 8-bit PHV 81n (ingress): phv81[4:4] = hdr.geneve_opts.oxg_mcast.$valid[0:0] | ||
| 156 | 8-bit PHV 81n (ingress): phv81[3:3] = hdr.geneve_opts.oxg_mcast_tag.$valid[0:0] (deparsed) | ||
| 157 | 8-bit PHV 81n (ingress): phv81[2:2] = hdr.inner_icmp.$valid[0:0] (deparsed) | ||
| 158 | 8-bit PHV 81n (ingress): phv81[1:1] = hdr.inner_udp.$valid[0:0] (deparsed) | ||
| 159 | 8-bit PHV 81n (ingress): phv81[0:0] = hdr.inner_tcp.$valid[0:0] (deparsed) | ||
| 160 | 8-bit PHV 82n (ingress): phv82[7:7] = meta.is_switch_address[0:0] | ||
| 161 | 8-bit PHV 82n (ingress): phv82[6:6] = hdr.inner_ipv6.$valid[0:0] (deparsed) | ||
| 162 | 8-bit PHV 82n (ingress): phv82[5:5] = hdr.ipv6.$valid[0:0] (deparsed) | ||
| 163 | 8-bit PHV 82n (ingress): phv82[4:4] = hdr.inner_ipv4.$valid[0:0] (deparsed) | ||
| 164 | 8-bit PHV 82n (ingress): phv82[3:3] = hdr.inner_eth.$valid[0:0] (deparsed) | ||
| 165 | 8-bit PHV 82n (ingress): phv82[2:2] = hdr.ipv4.$valid[0:0] (deparsed) | ||
| 166 | 8-bit PHV 82n (ingress): phv82[1:1] = hdr.udp.$valid[0:0] (deparsed) | ||
| 167 | 8-bit PHV 82n (ingress): phv82[0:0] = hdr.vlan.$valid[0:0] (deparsed) | ||
| 168 | 8-bit PHV 83n (ingress): phv83[7:7] = meta.nat_egress_hit[0:0] | ||
| 169 | 8-bit PHV 83n (ingress): phv83[6:6] = meta.service_routed[0:0] | ||
| 170 | 8-bit PHV 83n (ingress): phv83[5:5] = filter_hasReturned[0:0] | ||
| 171 | 8-bit PHV 83n (ingress): phv83[4:4] = ig_intr_md_for_tm.bypass_egress[0:0] (deparsed) | ||
| 172 | 8-bit PHV 83n (ingress): phv83[3:3] = hdr.geneve_opts.oxg_ext_tag.$valid[0:0] (deparsed) | ||
| 173 | 8-bit PHV 83n (ingress): phv83[2:2] = hdr.geneve.$valid[0:0] (deparsed) | ||
| 174 | 8-bit PHV 83n (ingress): phv83[1:1] = hdr.icmp.hdr_checksum.$deparse_updated_csum_0[0:0] (deparsed) | ||
| 175 | 8-bit PHV 83n (ingress): phv83[0:0] = hdr.icmp.hdr_checksum.$deparse_original_csum[0:0] (deparsed) | ||
| 176 | 8-bit PHV 84n (egress): phv84[7:7] = eg_intr_md_for_dprsr.mirror_io_select[0:0] (deparsed) | ||
| 177 | 8-bit PHV 84n (egress): phv84[6:6] = hdr.inner_ipv4.hdr_checksum.$deparse_updated_csum_0[0:0] (deparsed) | ||
| 178 | 8-bit PHV 84n (egress): phv84[5:5] = hdr.inner_ipv4.hdr_checksum.$deparse_original_csum[0:0] (deparsed) | ||
| 179 | 8-bit PHV 84n (egress): phv84[4:4] = hdr.tcp.$valid[0:0] (deparsed) | ||
| 180 | 8-bit PHV 84n (egress): phv84[3:3] = hdr.ipv6.$valid[0:0] (deparsed) | ||
| 181 | 8-bit PHV 84n (egress): phv84[2:2] = hdr.geneve_opts.oxg_mss.$valid[0:0] | ||
| 182 | 8-bit PHV 84n (egress): phv84[1:1] = hdr.geneve_opts.oxg_mss_tag.$valid[0:0] (deparsed) | ||
| 183 | 8-bit PHV 84n (egress): phv84[0:0] = hdr.geneve_opts.oxg_mcast.$valid[0:0] | ||
| 184 | 8-bit PHV 85n (egress): phv85[7:0] = hdr.icmp.type[7:0] (deparsed) | ||
| 185 | 8-bit PHV 85n (egress): phv85[7:0] = hdr.inner_ipv4.ttl[7:0] (deparsed) | ||
| 186 | 8-bit PHV 85n (egress): phv85[7:0] = hdr.inner_ipv6.hop_limit[7:0] (deparsed) | ||
| 187 | 8-bit PHV 86n (ingress): phv86[7:0] = $tmp13[7:0] | ||
| 188 | 8-bit PHV 86n (ingress): phv86[7:0] = l3_router_Router6_fwd.nexthop[103:96] | ||
| 189 | 8-bit PHV 87n (ingress): phv87[7:0] = l3_router_Router4_fwd.ecmp_hash[7:0] | ||
| 190 | 8-bit PHV 88n (ingress): phv88[7:7] = meta.icmp_recalc[0:0] | ||
| 191 | 8-bit PHV 88n (ingress): phv88[6:6] = meta.is_link_local_mcastv6[0:0] | ||
| 192 | 8-bit PHV 88n (ingress): phv88[5:5] = meta.is_mcast[0:0] | ||
| 193 | 8-bit PHV 88n (ingress): phv88[4:4] = hdr.udp.checksum.$deparse_updated_csum_3[0:0] (deparsed) | ||
| 194 | 8-bit PHV 88n (ingress): phv88[3:3] = hdr.udp.checksum.$deparse_updated_csum_2[0:0] (deparsed) | ||
| 195 | 8-bit PHV 88n (ingress): phv88[2:2] = hdr.udp.checksum.$deparse_updated_csum_1[0:0] (deparsed) | ||
| 196 | 8-bit PHV 88n (ingress): phv88[1:1] = hdr.udp.checksum.$deparse_updated_csum_0[0:0] (deparsed) | ||
| 197 | 8-bit PHV 88n (ingress): phv88[0:0] = hdr.udp.checksum.$deparse_original_csum[0:0] (deparsed) | ||
| 198 | 8-bit PHV 89n (ingress): phv89[7:0] = hdr.ipv4.ttl[7:0] (deparsed) | ||
| 199 | 8-bit PHV 89n (ingress): phv89[7:0] = hdr.ipv6.hop_limit[7:0] (deparsed) | ||
| 200 | 8-bit PHV 90n (ingress): phv90[7:6] = hdr.geneve_opts.oxg_mcast.mcast_tag[1:0] (deparsed) | ||
| 201 | 8-bit PHV 90n (ingress): phv90[5:0] = hdr.geneve_opts.oxg_mcast.reserved[29:24] (deparsed) | ||
| 202 | 8-bit PHV 92m (ingress): phv92[7:0] = hdr.inner_ipv4.ttl[7:0] (deparsed) | ||
| 203 | 8-bit PHV 92m (ingress): phv92[7:0] = hdr.inner_ipv6.hop_limit[7:0] (deparsed) | ||
| 204 | 8-bit PHV 93m (ingress): phv93[3:0] = ig_intr_md_for_dprsr.mirror_type[3:0] (deparsed) | ||
| 205 | 8-bit PHV 94m (ingress): phv94[2:0] = ig_intr_md_for_dprsr.drop_ctl[2:0] (deparsed) | ||
| 206 | 8-bit PHV 95m (ingress): phv95[7:0] = hdr.sidecar.sc_payload[103:96] (deparsed) | ||
| 207 | 8-bit PHV 96d (ingress): phv96[7:0] = meta.nexthop_ipv6[103:96] | ||
| 208 | >> 14 in ingress and 2 in egress | ||
| 209 | |||
| 210 | Allocations in Group 5 8 bits | ||
| 211 | 8-bit PHV 112m (ingress): phv112[0:0] = meta.is_valid[0:0] | ||
| 212 | 8-bit PHV 113m (egress): phv113[7:0] = meta.port_number[7:0] | ||
| 213 | 8-bit PHV 114m (ingress): phv114[7:0] = hdr.inner_ipv4.protocol[7:0] (deparsed) | ||
| 214 | 8-bit PHV 114m (ingress): phv114[7:0] = hdr.inner_ipv6.next_hdr[7:0] (deparsed) | ||
| 215 | 8-bit PHV 115m (ingress): phv115[7:0] = hdr.ipv4.protocol[7:0] (deparsed) | ||
| 216 | 8-bit PHV 115m (ingress): phv115[7:0] = hdr.ipv6.next_hdr[7:0] (deparsed) | ||
| 217 | >> 3 in ingress and 1 in egress | ||
| 218 | |||
| 219 | Allocations in Group 6 8 bits | ||
| 220 | 8-bit PHV 132m (egress): phv132[7:0] = hdr.geneve.reserved2[7:0] (deparsed) | ||
| 221 | 8-bit PHV 133m (egress): phv133[7:0] = hdr.inner_ipv4.src_addr[31:24] (deparsed) | ||
| 222 | 8-bit PHV 133m (egress): phv133[7:0] = hdr.inner_ipv6.dst_addr[55:48] (deparsed) | ||
| 223 | 8-bit PHV 134m (egress): phv134[7:0] = hdr.inner_ipv6.dst_addr[63:56] (deparsed) | ||
| 224 | 8-bit PHV 135m (egress): phv135[7:0] = hdr.inner_eth.src_mac[7:0] (deparsed) | ||
| 225 | >> 0 in ingress and 4 in egress | ||
| 226 | |||
| 227 | Allocations in Group 7 8 bits | ||
| 228 | 8-bit PHV 140n (ingress): phv140[7:0] = hdr.sidecar.sc_payload[111:104] (deparsed) | ||
| 229 | 8-bit PHV 152m (ingress): phv152[7:0] = l3_router_Router6_fwd.nexthop[111:104] | ||
| 230 | 8-bit PHV 153m (egress): phv153[0:0] = eg_intr_md.egress_rid_first[0:0] | ||
| 231 | 8-bit PHV 154m (ingress): phv154[7:0] = meta.drop_reason[7:0] | ||
| 232 | 8-bit PHV 156d (ingress): phv156[7:0] = meta.nexthop_ipv6[111:104] | ||
| 233 | >> 4 in ingress and 1 in egress | ||
| 234 | |||
| 235 | Allocations in Group 8 16 bits | ||
| 236 | 16-bit PHV 160n (ingress): phv160[15:15] = hdr.tcp.$valid[0:0] (deparsed) | ||
| 237 | 16-bit PHV 160n (ingress): phv160[14:14] = hdr.icmp.$valid[0:0] (deparsed) | ||
| 238 | 16-bit PHV 160n (ingress): phv160[13:13] = hdr.sidecar.$valid[0:0] (deparsed) | ||
| 239 | 16-bit PHV 160n (ingress): phv160[12:12] = hdr.ethernet.$valid[0:0] (deparsed) | ||
| 240 | 16-bit PHV 160n (ingress): phv160[11:11] = meta.bridge_hdr.$valid[0:0] (deparsed) | ||
| 241 | 16-bit PHV 160n (ingress): phv160[10:10] = ig_intr_md_for_tm.bypass_egress.$valid[0:0] (deparsed) | ||
| 242 | 16-bit PHV 160n (ingress): phv160[9:9] = ig_intr_md_for_tm.level2_mcast_hash.$valid[0:0] (deparsed) | ||
| 243 | 16-bit PHV 160n (ingress): phv160[8:8] = ig_intr_md_for_tm.level1_mcast_hash.$valid[0:0] (deparsed) | ||
| 244 | 16-bit PHV 160n (ingress): phv160[7:7] = ig_intr_md_for_tm.level2_exclusion_id.$valid[0:0] (deparsed) | ||
| 245 | 16-bit PHV 160n (ingress): phv160[6:6] = ig_intr_md_for_tm.level1_exclusion_id.$valid[0:0] (deparsed) | ||
| 246 | 16-bit PHV 160n (ingress): phv160[5:5] = ig_intr_md_for_tm.rid.$valid[0:0] (deparsed) | ||
| 247 | 16-bit PHV 160n (ingress): phv160[4:4] = ig_intr_md_for_tm.mcast_grp_b.$valid[0:0] (deparsed) | ||
| 248 | 16-bit PHV 160n (ingress): phv160[3:3] = ig_intr_md_for_tm.mcast_grp_a.$valid[0:0] (deparsed) | ||
| 249 | 16-bit PHV 160n (ingress): phv160[2:2] = ig_intr_md_for_tm.ucast_egress_port.$valid[0:0] (deparsed) | ||
| 250 | 16-bit PHV 160n (ingress): phv160[1:1] = ig_intr_md_for_dprsr.drop_ctl.$valid[0:0] (deparsed) | ||
| 251 | 16-bit PHV 160n (ingress): phv160[0:0] = ig_intr_md_for_dprsr.mirror_type.$valid[0:0] (deparsed) | ||
| 252 | 16-bit PHV 161n (ingress): phv161[13:13] = meta.allow_source_mcast[0:0] | ||
| 253 | 16-bit PHV 161n (ingress): phv161[12:0] = ig_intr_md_for_tm.level1_mcast_hash[12:0] (deparsed) | ||
| 254 | 16-bit PHV 162n (ingress): phv162[12:0] = ig_intr_md_for_tm.level2_mcast_hash[12:0] (deparsed) | ||
| 255 | 16-bit PHV 163n (ingress): phv163[15:0] = hdr.inner_eth.src_mac[15:0] (deparsed) | ||
| 256 | 16-bit PHV 164n (egress): phv164[15:15] = hdr.geneve_opts.oxg_mcast_tag.$valid[0:0] (deparsed) | ||
| 257 | 16-bit PHV 164n (egress): phv164[14:14] = hdr.geneve_opts.oxg_ext_tag.$valid[0:0] (deparsed) | ||
| 258 | 16-bit PHV 164n (egress): phv164[13:13] = hdr.inner_ipv6.$valid[0:0] (deparsed) | ||
| 259 | 16-bit PHV 164n (egress): phv164[12:12] = hdr.inner_udp.$valid[0:0] (deparsed) | ||
| 260 | 16-bit PHV 164n (egress): phv164[11:11] = hdr.inner_tcp.$valid[0:0] (deparsed) | ||
| 261 | 16-bit PHV 164n (egress): phv164[10:10] = hdr.inner_ipv4.$valid[0:0] (deparsed) | ||
| 262 | 16-bit PHV 164n (egress): phv164[9:9] = hdr.inner_eth.$valid[0:0] (deparsed) | ||
| 263 | 16-bit PHV 164n (egress): phv164[8:8] = hdr.geneve.$valid[0:0] (deparsed) | ||
| 264 | 16-bit PHV 164n (egress): phv164[7:7] = hdr.udp.$valid[0:0] (deparsed) | ||
| 265 | 16-bit PHV 164n (egress): phv164[6:6] = hdr.icmp.$valid[0:0] (deparsed) | ||
| 266 | 16-bit PHV 164n (egress): phv164[5:5] = hdr.ipv4.$valid[0:0] (deparsed) | ||
| 267 | 16-bit PHV 164n (egress): phv164[4:4] = hdr.vlan.$valid[0:0] (deparsed) | ||
| 268 | 16-bit PHV 164n (egress): phv164[3:3] = hdr.ethernet.$valid[0:0] (deparsed) | ||
| 269 | 16-bit PHV 164n (egress): phv164[2:2] = eg_intr_md_for_dprsr.drop_ctl.$valid[0:0] (deparsed) | ||
| 270 | 16-bit PHV 164n (egress): phv164[1:1] = eg_intr_md.egress_port.$valid[0:0] (deparsed) | ||
| 271 | 16-bit PHV 164n (egress): phv164[0:0] = eg_intr_md_for_dprsr.mirror_io_select.$valid[0:0] (deparsed) | ||
| 272 | 16-bit PHV 165n (egress): phv165[15:0] = hdr.vlan.ether_type[15:0] (deparsed) | ||
| 273 | 16-bit PHV 166n (egress): phv166[15:13] = hdr.vlan.pcp[2:0] (deparsed) | ||
| 274 | 16-bit PHV 166n (egress): phv166[12:12] = hdr.vlan.dei[0:0] (deparsed) | ||
| 275 | 16-bit PHV 166n (egress): phv166[11:0] = hdr.vlan.vlan_id[11:0] (deparsed) | ||
| 276 | 16-bit PHV 167n (egress): phv167[15:0] = hdr.geneve.vni[15:0] (deparsed) | ||
| 277 | 16-bit PHV 168n (egress): phv168[11:0] = meta.vlan_id[11:0] | ||
| 278 | 16-bit PHV 169n (ingress): phv169[15:0] = hdr.sidecar.sc_payload[31:16] (deparsed) | ||
| 279 | 16-bit PHV 170n (ingress): phv170[15:0] = hdr.sidecar.sc_payload[79:64] (deparsed) | ||
| 280 | 16-bit PHV 171n (ingress): phv171[15:0] = l3_router_Router6_fwd.nexthop[79:64] | ||
| 281 | 16-bit PHV 172m (ingress): phv172[15:0] = meta.icmp_csum[15:0] (deparsed) | ||
| 282 | 16-bit PHV 173m (ingress): phv173[15:0] = meta.body_checksum[15:0] (deparsed) | ||
| 283 | 16-bit PHV 174m (ingress): phv174[15:0] = ig_intr_md_for_tm.mcast_grp_a[15:0] (deparsed) | ||
| 284 | 16-bit PHV 174m (ingress): phv174[15:0] = ig_intr_md_for_tm.mcast_grp_a[15:0] (deparsed) | ||
| 285 | 16-bit PHV 174m (ingress): phv174[15:0] = l3_router_Router4_fwd.nexthop[31:16] | ||
| 286 | 16-bit PHV 175m (ingress): phv175[15:0] = ig_intr_md_for_tm.mcast_grp_b[15:0] (deparsed) | ||
| 287 | 16-bit PHV 175m (ingress): phv175[15:0] = ig_intr_md_for_tm.mcast_grp_b[15:0] (deparsed) | ||
| 288 | 16-bit PHV 175m (ingress): phv175[15:0] = l3_router_Router6_fwd.nexthop[31:16] | ||
| 289 | 16-bit PHV 176d (ingress): phv176[15:0] = meta.nexthop_ipv4[31:16] | ||
| 290 | 16-bit PHV 176d (ingress): phv176[15:0] = meta.nexthop_ipv6[31:16] | ||
| 291 | 16-bit PHV 177d (ingress): phv177[15:0] = ig_intr_md_for_tm.mcast_grp_a[15:0] (deparsed) | ||
| 292 | 16-bit PHV 178d (ingress): phv178[15:0] = ig_intr_md_for_tm.mcast_grp_b[15:0] (deparsed) | ||
| 293 | 16-bit PHV 179d (ingress): phv179[15:0] = meta.nexthop_ipv6[79:64] | ||
| 294 | >> 15 in ingress and 5 in egress | ||
| 295 | |||
| 296 | Allocations in Group 9 16 bits | ||
| 297 | 16-bit PHV 180n (ingress): phv180[15:0] = meta.l4_length[15:0] (deparsed) | ||
| 298 | 16-bit PHV 181n (ingress): phv181[15:0] = hdr.ipv4.dst_addr[15:0] (deparsed) | ||
| 299 | 16-bit PHV 181n (ingress): phv181[15:0] = hdr.ipv6.payload_len[15:0] (deparsed) | ||
| 300 | 16-bit PHV 182n (ingress): phv182[15:0] = hdr.udp.hdr_length[15:0] (deparsed) | ||
| 301 | 16-bit PHV 183n (ingress): phv183[15:0] = hdr.inner_ipv4.dst_addr[15:0] (deparsed) | ||
| 302 | 16-bit PHV 183n (ingress): phv183[15:0] = hdr.inner_ipv6.dst_addr[15:0] (deparsed) | ||
| 303 | 16-bit PHV 184n (ingress): phv184[15:0] = meta.orig_src_mac[15:0] | ||
| 304 | 16-bit PHV 185n (ingress): phv185[15:0] = meta.orig_src_ipv4[15:0] | ||
| 305 | 16-bit PHV 186n (ingress): phv186[15:0] = hdr.inner_ipv4.src_addr[15:0] (deparsed) | ||
| 306 | 16-bit PHV 186n (ingress): phv186[15:0] = hdr.inner_ipv6.src_addr[15:0] (deparsed) | ||
| 307 | 16-bit PHV 187n (ingress): phv187[15:0] = hdr.ethernet.dst_mac[15:0] (deparsed) | ||
| 308 | 16-bit PHV 188n (ingress): phv188[15:0] = meta.nat_ingress_tgt[15:0] | ||
| 309 | 16-bit PHV 189n (ingress): phv189[15:0] = hdr.ipv4.src_addr[15:0] (deparsed) | ||
| 310 | 16-bit PHV 189n (ingress): phv189[15:0] = hdr.ipv6.src_addr[15:0] (deparsed) | ||
| 311 | 16-bit PHV 190n (ingress): phv190[15:0] = hdr.ethernet.src_mac[15:0] (deparsed) | ||
| 312 | 16-bit PHV 191n (ingress): phv191[15:13] = hdr.vlan.pcp[2:0] (deparsed) | ||
| 313 | 16-bit PHV 191n (ingress): phv191[12:12] = hdr.vlan.dei[0:0] (deparsed) | ||
| 314 | 16-bit PHV 191n (ingress): phv191[11:0] = hdr.vlan.vlan_id[11:0] (deparsed) | ||
| 315 | 16-bit PHV 192m (ingress): phv192[10:1] = meta.pkt_type[9:0] | ||
| 316 | 16-bit PHV 192m (ingress): phv192[0:0] = meta.ipv4_checksum_err[0:0] | ||
| 317 | 16-bit PHV 193m (ingress): phv193[15:0] = hdr.inner_ipv4.total_len[15:0] (deparsed) | ||
| 318 | 16-bit PHV 193m (ingress): phv193[15:0] = hdr.inner_ipv6.payload_len[15:0] (deparsed) | ||
| 319 | 16-bit PHV 194m (ingress): phv194[15:0] = hdr.ipv4.total_len[15:0] (deparsed) | ||
| 320 | 16-bit PHV 194m (ingress): phv194[15:0] = hdr.ipv6.dst_addr[15:0] (deparsed) | ||
| 321 | 16-bit PHV 195m (ingress): phv195[15:0] = hdr.icmp.data[15:0] (deparsed) | ||
| 322 | 16-bit PHV 195m (ingress): phv195[15:0] = hdr.tcp.window[15:0] (deparsed) | ||
| 323 | 16-bit PHV 195m (ingress): phv195[15:0] = hdr.inner_tcp.window[15:0] (deparsed) | ||
| 324 | 16-bit PHV 195m (ingress): phv195[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed) | ||
| 325 | 16-bit PHV 195m (ingress): phv195[15:0] = hdr.inner_icmp.data[15:0] (deparsed) | ||
| 326 | >> 16 in ingress and 0 in egress | ||
| 327 | |||
| 328 | Allocations in Group 10 16 bits | ||
| 329 | 16-bit PHV 200n (ingress): phv200[15:0] = l3_router_Router4_fwd.idx[15:0] | ||
| 330 | 16-bit PHV 200n (ingress): phv200[15:0] = l3_router_Router6_fwd.idx[15:0] | ||
| 331 | 16-bit PHV 201n (egress): phv201[15:0] = hdr.ethernet.dst_mac[15:0] (deparsed) | ||
| 332 | 16-bit PHV 202n (egress): phv202[15:0] = hdr.inner_ipv4.dst_addr[31:16] (deparsed) | ||
| 333 | 16-bit PHV 202n (egress): phv202[15:0] = hdr.inner_ipv6.dst_addr[31:16] (deparsed) | ||
| 334 | 16-bit PHV 203n (egress): phv203[15:0] = hdr.ethernet.dst_mac[31:16] (deparsed) | ||
| 335 | 16-bit PHV 204n (egress): phv204[15:0] = mac_rewrite_ip_suffix[15:0] | ||
| 336 | 16-bit PHV 204n (egress): phv204[15:0] = mac_rewrite_ip_suffix_0[31:16] | ||
| 337 | 16-bit PHV 205n (egress): phv205[7:0] = mac_rewrite_ip_suffix[23:16] | ||
| 338 | 16-bit PHV 206n (ingress): phv206[15:0] = hdr.sidecar.sc_payload[15:0] (deparsed) | ||
| 339 | 16-bit PHV 207n (ingress): phv207[15:0] = hdr.sidecar.sc_payload[63:48] (deparsed) | ||
| 340 | 16-bit PHV 208n (ingress): phv208[15:0] = l3_router_Router4_fwd.nexthop[15:0] | ||
| 341 | 16-bit PHV 208n (ingress): phv208[15:0] = l3_router_Router6_fwd.nexthop[15:0] | ||
| 342 | 16-bit PHV 209n (ingress): phv209[15:0] = l3_router_Router6_fwd.nexthop[63:48] | ||
| 343 | 16-bit PHV 210n (egress): phv210[15:0] = hdr.inner_ipv4.hdr_checksum[15:0] (deparsed) | ||
| 344 | 16-bit PHV 210n (egress): phv210[15:0] = hdr.inner_ipv6.dst_addr[47:32] (deparsed) | ||
| 345 | 16-bit PHV 211n (egress): phv211[15:0] = hdr.ethernet.ether_type[15:0] (deparsed) | ||
| 346 | 16-bit PHV 212m (ingress): phv212[15:0] = l3_router_Router4_fwd.slot[15:0] | ||
| 347 | 16-bit PHV 212m (ingress): phv212[15:0] = l3_router_Router6_fwd.slot[15:0] | ||
| 348 | 16-bit PHV 213m (egress): phv213[15:0] = hdr.ipv4.dst_addr[15:0] (deparsed) | ||
| 349 | 16-bit PHV 213m (egress): phv213[15:0] = hdr.ipv6.dst_addr[15:0] (deparsed) | ||
| 350 | 16-bit PHV 214m (egress): phv214[15:8] = hdr.icmp.code[7:0] (deparsed) | ||
| 351 | 16-bit PHV 214m (egress): phv214[15:0] = hdr.inner_ipv4.dst_addr[15:0] (deparsed) | ||
| 352 | 16-bit PHV 214m (egress): phv214[15:0] = hdr.inner_ipv6.dst_addr[15:0] (deparsed) | ||
| 353 | 16-bit PHV 214m (egress): phv214[7:0] = hdr.icmp.hdr_checksum[15:8] (deparsed) | ||
| 354 | 16-bit PHV 215m (egress): phv215[15:0] = hdr.ipv4.dst_addr[31:16] (deparsed) | ||
| 355 | 16-bit PHV 215m (egress): phv215[15:0] = hdr.ipv6.dst_addr[31:16] (deparsed) | ||
| 356 | 16-bit PHV 216d (egress): phv216[15:0] = mac_rewrite_ip_suffix_0[15:0] | ||
| 357 | 16-bit PHV 217d (ingress): phv217[15:0] = meta.nexthop_ipv4[15:0] | ||
| 358 | 16-bit PHV 217d (ingress): phv217[15:0] = meta.nexthop_ipv6[15:0] | ||
| 359 | 16-bit PHV 218d (ingress): phv218[15:0] = meta.nexthop_ipv6[63:48] | ||
| 360 | >> 8 in ingress and 11 in egress | ||
| 361 | |||
| 362 | Allocations in Group 11 16 bits | ||
| 363 | 16-bit PHV 220n (ingress): phv220[15:0] = hdr.sidecar.sc_egress[15:0] (deparsed) | ||
| 364 | 16-bit PHV 221n (ingress): phv221[15:0] = hdr.sidecar.sc_ingress[15:0] (deparsed) | ||
| 365 | 16-bit PHV 222n (ingress): phv222[15:0] = hdr.sidecar.sc_payload[127:112] (deparsed) | ||
| 366 | 16-bit PHV 223n (ingress): phv223[15:8] = hdr.icmp.type[7:0] (deparsed) | ||
| 367 | 16-bit PHV 223n (ingress): phv223[15:0] = hdr.tcp.checksum[15:0] (deparsed) | ||
| 368 | 16-bit PHV 223n (ingress): phv223[15:0] = hdr.inner_tcp.checksum[15:0] (deparsed) | ||
| 369 | 16-bit PHV 223n (ingress): phv223[15:0] = hdr.inner_udp.checksum[15:0] (deparsed) | ||
| 370 | 16-bit PHV 223n (ingress): phv223[15:8] = hdr.inner_icmp.type[7:0] (deparsed) | ||
| 371 | 16-bit PHV 223n (ingress): phv223[7:0] = hdr.icmp.code[7:0] (deparsed) | ||
| 372 | 16-bit PHV 223n (ingress): phv223[7:0] = hdr.inner_icmp.code[7:0] (deparsed) | ||
| 373 | 16-bit PHV 224n (ingress): phv224[15:0] = hdr.sidecar.sc_payload[95:80] (deparsed) | ||
| 374 | 16-bit PHV 225n (ingress): phv225[15:12] = hdr.ipv4.version[3:0] (deparsed) | ||
| 375 | 16-bit PHV 225n (ingress): phv225[11:8] = hdr.ipv4.ihl[3:0] (deparsed) | ||
| 376 | 16-bit PHV 225n (ingress): phv225[7:0] = hdr.ipv4.diffserv[7:0] (deparsed) | ||
| 377 | 16-bit PHV 226n (ingress): phv226[15:0] = hdr.udp.checksum[15:0] (deparsed) | ||
| 378 | 16-bit PHV 227n (ingress): phv227[15:0] = meta.orig_src_mac[47:32] | ||
| 379 | 16-bit PHV 228n (ingress): phv228[15:12] = hdr.inner_ipv4.version[3:0] (deparsed) | ||
| 380 | 16-bit PHV 228n (ingress): phv228[15:12] = hdr.inner_ipv4.version[3:0] (deparsed) | ||
| 381 | 16-bit PHV 228n (ingress): phv228[15:0] = l3_router_Router6_fwd.nexthop[95:80] | ||
| 382 | 16-bit PHV 228n (ingress): phv228[11:8] = hdr.inner_ipv4.ihl[3:0] (deparsed) | ||
| 383 | 16-bit PHV 228n (ingress): phv228[11:8] = hdr.inner_ipv4.ihl[3:0] (deparsed) | ||
| 384 | 16-bit PHV 228n (ingress): phv228[7:0] = hdr.inner_ipv4.diffserv[7:0] (deparsed) | ||
| 385 | 16-bit PHV 228n (ingress): phv228[7:0] = hdr.inner_ipv4.diffserv[7:0] (deparsed) | ||
| 386 | 16-bit PHV 229n (ingress): phv229[15:0] = hdr.ethernet.dst_mac[47:32] (deparsed) | ||
| 387 | 16-bit PHV 230n (ingress): phv230[15:0] = hdr.inner_ipv4.hdr_checksum[15:0] (deparsed) | ||
| 388 | 16-bit PHV 231n (ingress): phv231[15:0] = hdr.ipv4.hdr_checksum[15:0] (deparsed) | ||
| 389 | 16-bit PHV 232m (ingress): phv232[8:0] = ig_intr_md.ingress_port[8:0] | ||
| 390 | 16-bit PHV 233m (ingress): phv233[8:0] = ig_intr_md_for_tm.ucast_egress_port[8:0] (deparsed) | ||
| 391 | 16-bit PHV 234m (ingress): phv234[8:0] = l3_router_Router4_fwd.port[8:0] | ||
| 392 | 16-bit PHV 234m (ingress): phv234[8:0] = l3_router_Router6_fwd.port[8:0] | ||
| 393 | 16-bit PHV 235m (ingress): phv235[15:0] = ig_intr_md_for_tm.level1_exclusion_id[15:0] (deparsed) | ||
| 394 | 16-bit PHV 235m (ingress): phv235[15:0] = ig_intr_md_for_tm.level1_exclusion_id[15:0] (deparsed) | ||
| 395 | 16-bit PHV 235m (ingress): phv235[15:0] = l3_router_Router6_fwd.nexthop[127:112] | ||
| 396 | 16-bit PHV 236d (ingress): phv236[15:0] = meta.nexthop_ipv6[127:112] | ||
| 397 | 16-bit PHV 237d (ingress): phv237[15:0] = ig_intr_md_for_tm.level1_exclusion_id[15:0] (deparsed) | ||
| 398 | 16-bit PHV 238d (ingress): phv238[15:0] = meta.nexthop_ipv6[95:80] | ||
| 399 | 16-bit PHV 239d (ingress): phv239[15:12] = hdr.inner_ipv4.version[3:0] (deparsed) | ||
| 400 | 16-bit PHV 239d (ingress): phv239[11:8] = hdr.inner_ipv4.ihl[3:0] (deparsed) | ||
| 401 | 16-bit PHV 239d (ingress): phv239[7:0] = hdr.inner_ipv4.diffserv[7:0] (deparsed) | ||
| 402 | >> 20 in ingress and 0 in egress | ||
| 403 | |||
| 404 | Allocations in Group 12 16 bits | ||
| 405 | 16-bit PHV 240n (ingress): phv240[15:0] = hdr.icmp.data[31:16] (deparsed) | ||
| 406 | 16-bit PHV 240n (ingress): phv240[15:12] = hdr.tcp.data_offset[3:0] (deparsed) | ||
| 407 | 16-bit PHV 240n (ingress): phv240[15:12] = hdr.inner_tcp.data_offset[3:0] (deparsed) | ||
| 408 | 16-bit PHV 240n (ingress): phv240[15:0] = hdr.inner_udp.dst_port[15:0] (deparsed) | ||
| 409 | 16-bit PHV 240n (ingress): phv240[15:0] = hdr.inner_icmp.data[31:16] (deparsed) | ||
| 410 | 16-bit PHV 240n (ingress): phv240[11:8] = hdr.tcp.res[3:0] (deparsed) | ||
| 411 | 16-bit PHV 240n (ingress): phv240[11:8] = hdr.inner_tcp.res[3:0] (deparsed) | ||
| 412 | 16-bit PHV 240n (ingress): phv240[7:0] = hdr.tcp.flags[7:0] (deparsed) | ||
| 413 | 16-bit PHV 240n (ingress): phv240[7:0] = hdr.inner_tcp.flags[7:0] (deparsed) | ||
| 414 | 16-bit PHV 241n (ingress): phv241[15:0] = hdr.udp.dst_port[15:0] (deparsed) | ||
| 415 | 16-bit PHV 242n (ingress): phv242[15:0] = hdr.icmp.hdr_checksum[15:0] (deparsed) | ||
| 416 | 16-bit PHV 242n (ingress): phv242[15:0] = hdr.tcp.urgent_ptr[15:0] (deparsed) | ||
| 417 | 16-bit PHV 242n (ingress): phv242[15:0] = hdr.inner_tcp.urgent_ptr[15:0] (deparsed) | ||
| 418 | 16-bit PHV 242n (ingress): phv242[15:0] = hdr.inner_udp.src_port[15:0] (deparsed) | ||
| 419 | 16-bit PHV 242n (ingress): phv242[15:0] = hdr.inner_icmp.hdr_checksum[15:0] (deparsed) | ||
| 420 | 16-bit PHV 243n (ingress): phv243[15:0] = hdr.udp.src_port[15:0] (deparsed) | ||
| 421 | 16-bit PHV 244n (ingress): phv244[15:8] = hdr.sidecar.sc_code[7:0] (deparsed) | ||
| 422 | 16-bit PHV 244n (ingress): phv244[7:0] = hdr.sidecar.sc_pad[7:0] (deparsed) | ||
| 423 | 16-bit PHV 245n (ingress): phv245[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed) | ||
| 424 | 16-bit PHV 245n (ingress): phv245[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed) | ||
| 425 | 16-bit PHV 245n (ingress): phv245[7:0] = l3_router_Router4_fwd.slots[7:0] | ||
| 426 | 16-bit PHV 246n (ingress): phv246[15:0] = meta.nat_ingress_csum[15:0] (deparsed) | ||
| 427 | 16-bit PHV 247n (egress): phv247[15:0] = eg_intr_md.egress_rid[15:0] | ||
| 428 | 16-bit PHV 248n (ingress): phv248[15:0] = meta.nat_inner_mac[47:32] | ||
| 429 | 16-bit PHV 249n (egress): phv249[15:0] = hdr.ethernet.src_mac[47:32] (deparsed) | ||
| 430 | 16-bit PHV 249n (egress): phv249[15:0] = hdr.ethernet.src_mac[47:32] (deparsed) | ||
| 431 | 16-bit PHV 249n (egress): phv249[15:0] = mac_rewrite_ip_suffix_0[47:32] | ||
| 432 | 16-bit PHV 250n (egress): phv250[15:0] = hdr.ethernet.dst_mac[47:32] (deparsed) | ||
| 433 | 16-bit PHV 251n (egress): phv251[15:0] = hdr.inner_eth.ether_type[15:0] (deparsed) | ||
| 434 | 16-bit PHV 251n (egress): phv251[15:0] = hdr.inner_eth.ether_type[15:0] (deparsed) | ||
| 435 | 16-bit PHV 251n (egress): phv251[0:0] = meta.ipv4_checksum_recalc[0:0] | ||
| 436 | 16-bit PHV 252m (egress): phv252[8:0] = eg_intr_md.egress_port[8:0] (deparsed) | ||
| 437 | 16-bit PHV 253m (egress): phv253[8:0] = meta.bridge_hdr.ingress_port[8:0] | ||
| 438 | 16-bit PHV 254m (egress): phv254[10:3] = meta.drop_reason[7:0] | ||
| 439 | 16-bit PHV 254m (egress): phv254[2:0] = eg_intr_md_for_dprsr.drop_ctl[2:0] (deparsed) | ||
| 440 | 16-bit PHV 255m (ingress): phv255[15:0] = meta.l4_dst_port[15:0] | ||
| 441 | 16-bit PHV 256d (egress): phv256[15:0] = hdr.ethernet.src_mac[47:32] (tagalong capable) (deparsed) | ||
| 442 | 16-bit PHV 257d (egress): phv257[15:0] = hdr.inner_eth.ether_type[15:0] (tagalong capable) (deparsed) | ||
| 443 | 16-bit PHV 258d (ingress): phv258[15:0] = hdr.inner_eth.dst_mac[47:32] (tagalong capable) (deparsed) | ||
| 444 | >> 10 in ingress and 9 in egress | ||
| 445 | |||
| 446 | Allocations in Group 13 16 bits | ||
| 447 | 16-bit PHV 260n (ingress): phv260[15:0] = hdr.inner_ipv4.dst_addr[31:16] (tagalong capable) (deparsed) | ||
| 448 | 16-bit PHV 260n (ingress): phv260[15:0] = hdr.inner_ipv6.dst_addr[31:16] (tagalong capable) (deparsed) | ||
| 449 | 16-bit PHV 261n (ingress): phv261[15:0] = hdr.inner_ipv4.src_addr[31:16] (tagalong capable) (deparsed) | ||
| 450 | 16-bit PHV 261n (ingress): phv261[15:0] = hdr.inner_ipv6.src_addr[31:16] (tagalong capable) (deparsed) | ||
| 451 | 16-bit PHV 262n (ingress): phv262[15:0] = hdr.ipv4.dst_addr[31:16] (tagalong capable) (deparsed) | ||
| 452 | 16-bit PHV 262n (ingress): phv262[15:0] = hdr.ipv6.dst_addr[31:16] (tagalong capable) (deparsed) | ||
| 453 | 16-bit PHV 263n (ingress): phv263[15:0] = hdr.ethernet.dst_mac[31:16] (tagalong capable) (deparsed) | ||
| 454 | 16-bit PHV 264n (ingress): phv264[15:0] = meta.nat_ingress_tgt[31:16] (tagalong capable) | ||
| 455 | 16-bit PHV 265n (ingress): phv265[15:0] = hdr.ipv4.src_addr[31:16] (tagalong capable) (deparsed) | ||
| 456 | 16-bit PHV 265n (ingress): phv265[15:0] = hdr.ipv6.src_addr[31:16] (tagalong capable) (deparsed) | ||
| 457 | 16-bit PHV 266n (ingress): phv266[15:0] = hdr.vlan.ether_type[15:0] (tagalong capable) (deparsed) | ||
| 458 | 16-bit PHV 267n (ingress): phv267[15:0] = hdr.sidecar.sc_ether_type[15:0] (tagalong capable) (deparsed) | ||
| 459 | 16-bit PHV 268n (ingress): phv268[15:0] = hdr.ethernet.ether_type[15:0] (tagalong capable) (deparsed) | ||
| 460 | 16-bit PHV 269n (ingress): phv269[15:0] = hdr.inner_eth.ether_type[15:0] (tagalong capable) (deparsed) | ||
| 461 | 16-bit PHV 269n (ingress): phv269[15:0] = hdr.inner_eth.ether_type[15:0] (tagalong capable) (deparsed) | ||
| 462 | 16-bit PHV 269n (ingress): phv269[0:0] = l3_router_Router4_fwd.is_hit[0:0] (tagalong capable) | ||
| 463 | 16-bit PHV 270n (ingress): phv270[15:0] = hdr.sidecar.sc_payload[47:32] (tagalong capable) (deparsed) | ||
| 464 | 16-bit PHV 271n (ingress): phv271[15:9] = meta.bridge_hdr.__pad_0[6:0] (tagalong capable) | ||
| 465 | 16-bit PHV 271n (ingress): phv271[8:0] = meta.bridge_hdr.ingress_port[8:0] (tagalong capable) (deparsed) | ||
| 466 | 16-bit PHV 271n (ingress): phv271[8:0] = meta.bridge_hdr.ingress_port[8:0] (tagalong capable) (deparsed) | ||
| 467 | 16-bit PHV 271n (ingress): phv271[0:0] = meta.nat_ingress_port[0:0] (tagalong capable) | ||
| 468 | 16-bit PHV 272m (ingress): phv272[15:0] = ig_intr_md_for_tm.rid[15:0] (tagalong capable) (deparsed) | ||
| 469 | 16-bit PHV 272m (ingress): phv272[15:0] = ig_intr_md_for_tm.rid[15:0] (tagalong capable) (deparsed) | ||
| 470 | 16-bit PHV 272m (ingress): phv272[15:0] = l3_router_Router6_fwd.nexthop[47:32] (tagalong capable) | ||
| 471 | 16-bit PHV 273m (ingress): phv273[8:0] = ig_intr_md_for_tm.level2_exclusion_id[8:0] (tagalong capable) (deparsed) | ||
| 472 | 16-bit PHV 274m (ingress): phv274[15:0] = meta.orig_src_mac[31:16] (tagalong capable) | ||
| 473 | 16-bit PHV 275m (ingress): phv275[15:0] = meta.orig_src_ipv4[31:16] (tagalong capable) | ||
| 474 | 16-bit PHV 276d (ingress): phv276[15:0] = meta.nexthop_ipv6[47:32] (tagalong capable) | ||
| 475 | 16-bit PHV 277d (ingress): phv277[15:0] = ig_intr_md_for_tm.rid[15:0] (tagalong capable) (deparsed) | ||
| 476 | 16-bit PHV 278d (ingress): phv278[8:0] = meta.bridge_hdr.ingress_port[8:0] (tagalong capable) (deparsed) | ||
| 477 | 16-bit PHV 279d (ingress): phv279[15:0] = hdr.inner_eth.ether_type[15:0] (tagalong capable) (deparsed) | ||
| 478 | >> 20 in ingress and 0 in egress | ||
| 479 | |||
| 480 | |||
| 481 | Final POV layout (ingress): | ||
| 482 | |||
| 483 | Final POV layout (egress): | ||