+---------------------------------------------------------------------+ | Log file: mau.resources.log | | Compiler version: 9.13.4 | | Created on: Thu Jan 29 19:29:48 2026 | | Run ID: eee6638cbd7e42c6 | +---------------------------------------------------------------------+ --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 10 | 0 | 29 | 2 | 8 | 5 | 4 | 0 | 2 | 0 | 2 | 0 | 7 | 3 | 1 | 0 | 0 | 0 | 0 | 8 | | 1 | 4 | 27 | 0 | 0 | 3 | 16 | 8 | 14 | 4 | 0 | 4 | 0 | 3 | 0 | 4 | 52 | 0 | 0 | 0 | 4 | | 2 | 2 | 2 | 0 | 0 | 2 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | | 3 | 2 | 28 | 0 | 0 | 2 | 15 | 5 | 24 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 52 | 0 | 0 | 0 | 2 | | 4 | 0 | 8 | 0 | 0 | 0 | 6 | 2 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | 1 | | 5 | 3 | 0 | 20 | 0 | 2 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | 2 | 2 | 1 | 10 | 0 | 0 | 0 | 3 | | 6 | 2 | 0 | 0 | 0 | 2 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | 2 | 0 | 4 | 62 | 0 | 0 | 0 | 4 | | 7 | 6 | 8 | 1 | 0 | 3 | 4 | 2 | 2 | 6 | 0 | 1 | 0 | 3 | 0 | 2 | 18 | 0 | 0 | 0 | 4 | | 8 | 4 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 3 | | 9 | 3 | 0 | 10 | 0 | 1 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | 1 | 1 | 0 | 10 | 0 | 0 | 0 | 1 | | 10 | 40 | 20 | 16 | 2 | 4 | 11 | 7 | 22 | 4 | 0 | 2 | 0 | 4 | 3 | 3 | 10 | 0 | 0 | 0 | 6 | | 11 | 4 | 16 | 10 | 0 | 1 | 4 | 2 | 3 | 3 | 0 | 1 | 0 | 1 | 1 | 4 | 10 | 0 | 0 | 0 | 5 | | 12 | 6 | 0 | 80 | 0 | 3 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | 3 | 2 | 1 | 4 | 0 | 0 | 0 | 3 | | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 2 | | 14 | 4 | 0 | 80 | 0 | 0 | 40 | 8 | 0 | 6 | 0 | 2 | 0 | 2 | 2 | 0 | 48 | 0 | 0 | 0 | 2 | | 15 | 5 | 0 | 0 | 0 | 2 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | 2 | 0 | 8 | 56 | 0 | 0 | 0 | 8 | | 16 | 21 | 0 | 80 | 0 | 2 | 22 | 6 | 0 | 4 | 0 | 2 | 0 | 2 | 2 | 1 | 24 | 0 | 0 | 0 | 3 | | 17 | 3 | 0 | 10 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 4 | 0 | 0 | 0 | 1 | | 18 | 8 | 0 | 36 | 3 | 5 | 10 | 8 | 0 | 2 | 0 | 4 | 0 | 4 | 4 | 3 | 6 | 0 | 0 | 0 | 5 | | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | | | | | | | | | | | | | | | | | | | | | | Totals | 127 | 109 | 372 | 7 | 44 | 158 | 52 | 72 | 60 | 0 | 21 | 0 | 44 | 21 | 38 | 392 | 0 | 0 | 0 | 67 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 7.81% | 0.00% | 6.97% | 33.33% | 50.00% | 6.25% | 8.33% | 0.00% | 6.25% | 0.00% | 50.00% | 0.00% | 43.75% | 18.75% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 50.00% | | 1 | 3.12% | 40.91% | 0.00% | 0.00% | 18.75% | 20.00% | 16.67% | 58.33% | 12.50% | 0.00% | 100.00% | 0.00% | 18.75% | 0.00% | 25.00% | 40.62% | 0.00% | 0.00% | 0.00% | 25.00% | | 2 | 1.56% | 3.03% | 0.00% | 0.00% | 12.50% | 1.25% | 0.00% | 4.17% | 3.12% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | | 3 | 1.56% | 42.42% | 0.00% | 0.00% | 12.50% | 18.75% | 10.42% | 100.00% | 6.25% | 0.00% | 50.00% | 0.00% | 12.50% | 0.00% | 12.50% | 40.62% | 0.00% | 0.00% | 0.00% | 12.50% | | 4 | 0.00% | 12.12% | 0.00% | 0.00% | 0.00% | 7.50% | 4.17% | 25.00% | 3.12% | 0.00% | 25.00% | 0.00% | 0.00% | 0.00% | 0.00% | 20.31% | 0.00% | 0.00% | 0.00% | 6.25% | | 5 | 2.34% | 0.00% | 4.81% | 0.00% | 12.50% | 3.75% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 12.50% | 12.50% | 6.25% | 7.81% | 0.00% | 0.00% | 0.00% | 18.75% | | 6 | 1.56% | 0.00% | 0.00% | 0.00% | 12.50% | 5.00% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 25.00% | 48.44% | 0.00% | 0.00% | 0.00% | 25.00% | | 7 | 4.69% | 12.12% | 0.24% | 0.00% | 18.75% | 5.00% | 4.17% | 8.33% | 18.75% | 0.00% | 25.00% | 0.00% | 18.75% | 0.00% | 12.50% | 14.06% | 0.00% | 0.00% | 0.00% | 25.00% | | 8 | 3.12% | 0.00% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 18.75% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 18.75% | | 9 | 2.34% | 0.00% | 2.40% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 21.88% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 7.81% | 0.00% | 0.00% | 0.00% | 6.25% | | 10 | 31.25% | 30.30% | 3.85% | 33.33% | 25.00% | 13.75% | 14.58% | 91.67% | 12.50% | 0.00% | 50.00% | 0.00% | 25.00% | 18.75% | 18.75% | 7.81% | 0.00% | 0.00% | 0.00% | 37.50% | | 11 | 3.12% | 24.24% | 2.40% | 0.00% | 6.25% | 5.00% | 4.17% | 12.50% | 9.38% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 25.00% | 7.81% | 0.00% | 0.00% | 0.00% | 31.25% | | 12 | 4.69% | 0.00% | 19.23% | 0.00% | 18.75% | 10.00% | 0.00% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 18.75% | 12.50% | 6.25% | 3.12% | 0.00% | 0.00% | 0.00% | 18.75% | | 13 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 0.00% | 12.50% | | 14 | 3.12% | 0.00% | 19.23% | 0.00% | 0.00% | 50.00% | 16.67% | 0.00% | 18.75% | 0.00% | 50.00% | 0.00% | 12.50% | 12.50% | 0.00% | 37.50% | 0.00% | 0.00% | 0.00% | 12.50% | | 15 | 3.91% | 0.00% | 0.00% | 0.00% | 12.50% | 7.50% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 50.00% | 43.75% | 0.00% | 0.00% | 0.00% | 50.00% | | 16 | 16.41% | 0.00% | 19.23% | 0.00% | 12.50% | 27.50% | 12.50% | 0.00% | 12.50% | 0.00% | 50.00% | 0.00% | 12.50% | 12.50% | 6.25% | 18.75% | 0.00% | 0.00% | 0.00% | 18.75% | | 17 | 2.34% | 0.00% | 2.40% | 0.00% | 6.25% | 1.25% | 0.00% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 3.12% | 0.00% | 0.00% | 0.00% | 6.25% | | 18 | 6.25% | 0.00% | 8.65% | 50.00% | 31.25% | 12.50% | 16.67% | 0.00% | 6.25% | 0.00% | 100.00% | 0.00% | 25.00% | 25.00% | 18.75% | 4.69% | 0.00% | 0.00% | 0.00% | 31.25% | | 19 | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | 0.00% | | | | | | | | | | | | | | | | | | | | | | | | Average | 5.22% | 8.69% | 4.71% | 6.14% | 14.47% | 10.39% | 5.70% | 15.79% | 9.87% | 0.00% | 27.63% | 0.00% | 14.47% | 6.91% | 12.50% | 16.12% | 0.00% | 0.00% | 0.00% | 22.04% | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Allocated Resource Usage --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind | | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result | | | | | | | | | | Bus | | Bus | Bus | Bus | | | | | | | | | | Bytes | | | | | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.uplink_ports | 0 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 | | Ingress.ingress_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.packet_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-40 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-41 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-42 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-43 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-44 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-46 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2110 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2110-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2111 | 0 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2111-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2114 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.attached_subnet_ingress.attached_subnets_v4 | 1 | 4 | 0 | 0 | 1 | 2 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.attached_subnet_ingress.attached_subnets_v4$action | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v4_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v6 | 1 | 16 | 0 | 0 | 1 | 6 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.attached_subnet_ingress.attached_subnets_v6$action | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv4_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.switch_ipv4_addr | 1 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 | | Ingress.filter.switch_ipv6_addr | 1 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 | | cond-45 | 1 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-47 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-48 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | Ingress.nat_ingress.icmp_dst_port | 2 | 2 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 1 | | cond-49 | 2 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-50 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4 | 3 | 8 | 0 | 0 | 1 | 4 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4$action | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6 | 3 | 20 | 0 | 0 | 1 | 20 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv6$action | 3 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv6_ingress_ctr | 3 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | cond-51 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-52 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4 | 4 | 8 | 0 | 0 | 0 | 6 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4$action | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.CalculateIPv4Len.ipv4_set_len | 5 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_hit | 5 | 2 | 10 | 0 | 1 | 0 | 0 | 8 | 4 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_hit$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-53 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-78 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2202 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | cond-54 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-56 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_nat_ingress_CalculateIPv4Len_invert | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 29 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4$action | 6 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_nat_ingress_encap_ipv6 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 29 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv6$action | 6 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar756 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | Ingress.services.service | 7 | 8 | 0 | 0 | 1 | 2 | 0 | 18 | 7 | 0 | 0 | 1 | | Ingress.services.service$action | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.services.service_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-57 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-58 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-59 | 7 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar419 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | cond-55 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-60 | 8 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-61 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar746 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.nat_egress.nat_egress | 9 | 2 | 10 | 0 | 1 | 0 | 0 | 10 | 7 | 1 | 1 | 0 | | Ingress.nat_egress.nat_egress$action | 9 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-62 | 9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.index_ctr | 10 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.lookup | 10 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.lookup$action | 10 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 10 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 10 | 16 | 0 | 0 | 1 | 6 | 0 | 3 | 2 | 0 | 0 | 1 | | cond-63 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-64 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-68 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_3-gateway | 10 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_3_ingress | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | | tbl_sidecar1235$precompute | 10 | 12 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | | tbl_sidecar1389$precompute | 10 | 36 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 11 | 16 | 0 | 0 | 1 | 3 | 0 | 3 | 2 | 0 | 0 | 1 | | cond-66 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | ingresshdr.udp.checksum_encode_update_condition_2_ingress | 11 | 3 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | tbl_sidecar1235 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1259 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 | | tbl_sidecar1389 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.select_route | 12 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.select_route | 12 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | cond-65 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-69 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-70 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1400 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1109 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar991 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.forward_ctr | 14 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.route | 14 | 2 | 40 | 0 | 4 | 0 | 0 | 24 | 5 | 1 | 1 | 0 | | Ingress.l3_router.Router4.lookup_idx.route$action | 14 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.forward_ctr | 14 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.route | 14 | 2 | 40 | 0 | 4 | 0 | 0 | 24 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.route$action | 14 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-67 | 15 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-71 | 15 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_Router4_icmp_error | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router4_icmp_error_0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error_0$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router6_icmp_error | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router6_icmp_error_0 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 10 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error_0$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1264 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1266 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 | | tbl_sidecar1266$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1405 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1409 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 1 | 0 | 0 | 1 | | tbl_sidecar1409$action | 15 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Arp.ctr | 16 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Arp.tbl | 16 | 4 | 40 | 0 | 4 | 0 | 0 | 12 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Arp.tbl$action | 16 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Ndp.ctr | 16 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Ndp.tbl | 16 | 16 | 40 | 0 | 8 | 0 | 0 | 12 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Ndp.tbl$action | 16 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-72 | 16 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-73 | 16 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | Ingress.egress_filter.egress_filter | 17 | 2 | 10 | 0 | 1 | 0 | 0 | 4 | 2 | 1 | 1 | 0 | | cond-74 | 17 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.drop_port_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.drop_reason_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.egress_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.mac_rewrite | 18 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 | | Ingress.mac_rewrite.mac_rewrite$action | 18 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-75 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-76 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-77 | 18 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar2158 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2158-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2160 | 18 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2162 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2162-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2166 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------