Max level shown:
1 PHV ALLOCATION SUCCESSFUL
2 PHV Allocation
3 +-----------+-------+-----------------+--------------------------------------------------------+
4 |Container |Gress |Container Slice |Field Slice |
5 +-----------+-------+-----------------+--------------------------------------------------------+
6 |B0 |I | |ingress::$tmp6 |
7 | | | | |
8 |MB0 |E |[0] |egress::hdr.geneve_opts.oxg_mss_tag.$valid |
9 | | |[1] |egress::hdr.geneve_opts.oxg_mss.$valid |
10 | | |[2] |egress::hdr.ipv6.$valid |
11 | | |[3] |egress::eg_intr_md_for_dprsr.mirror_io_select |
12 | | | | |
13 |... | | | |
14 | | | | |
15 |B1 |I |[0] |ingress::hdr.udp.checksum.$deparse_original_csum |
16 | | |[1] |ingress::hdr.udp.checksum.$deparse_updated_csum_0 |
17 | | |[2] |ingress::hdr.udp.checksum.$deparse_updated_csum_1 |
18 | | |[3] |ingress::hdr.udp.checksum.$deparse_updated_csum_2 |
19 | | |[4] |ingress::hdr.udp.checksum.$deparse_updated_csum_3 |
20 | | |[5] |ingress::hdr.icmp.hdr_checksum.$deparse_original_csum |
21 | | |[6] |ingress::hdr.icmp.hdr_checksum.$deparse_updated_csum_0 |
22 | | |[7] |ingress::ig_intr_md_for_tm.bypass_egress |
23 | | | | |
24 |MB1 |I | |ingress::l3_router_Router6_fwd.slots |
25 | | |[0] |ingress::l3_router_Router4_fwd.is_hit |
26 | | | | |
27 |... | | | |
28 | | | | |
29 |MB2 |I |[0] |ingress::l3_router_Router6_fwd.is_hit |
30 | | | | |
31 |... | | | |
32 | | | | |
33 |B4 |I | |$tmp9 |
34 | | | |$tmp10 |
35 | | | | |
36 |B5 |I | |ingress::l3_router_Router4_fwd.ecmp_hash |
37 | | | |ingress::l3_router_Router6_fwd.ecmp_hash |
38 | | | | |
39 |... | | | |
40 | | | | |
41 |MB4 |I | |ingress::hdr.inner_ipv4.ttl |
42 | | | |ingress::hdr.inner_ipv6.hop_limit |
43 | | | | |
44 |... | | | |
45 | | | | |
46 |MB5 |I |[3:0] |ingress::ig_intr_md_for_dprsr.mirror_type |
47 | | | | |
48 |... | | | |
49 | | | | |
50 |MB6 |I |[2:0] |ingress::ig_intr_md_for_dprsr.drop_ctl |
51 | | | | |
52 |... | | | |
53 | | | | |
54 |B12 |I | |ingress::hdr.ipv4.ttl |
55 | | | |ingress::hdr.ipv6.hop_limit |
56 | | | | |
57 |... | | | |
58 | | | | |
59 |MB8 |I | |ingress::hdr.inner_ipv4.protocol |
60 | | | |ingress::hdr.inner_ipv6.next_hdr |
61 | | | | |
62 |... | | | |
63 | | | | |
64 |MB9 |I | |ingress::hdr.ipv4.protocol |
65 | | | |ingress::hdr.ipv6.next_hdr |
66 | | | | |
67 |... | | | |
68 | | | | |
69 |H0 |I |[7:0] |ingress::hdr.inner_ipv4.diffserv |
70 | | |[11:8] |ingress::hdr.inner_ipv4.ihl |
71 | | |[15:12] |ingress::hdr.inner_ipv4.version |
72 | | | | |
73 |MH0 |I | |ingress::meta.icmp_csum |
74 | | | | |
75 |... | | | |
76 | | | | |
77 |H1 |I |[7:0] |ingress::hdr.ipv4.diffserv |
78 | | |[11:8] |ingress::hdr.ipv4.ihl |
79 | | |[15:12] |ingress::hdr.ipv4.version |
80 | | | | |
81 |MH1 |I | |ingress::meta.body_checksum |
82 | | | | |
83 |... | | | |
84 | | | | |
85 |H2 |I | |ingress::hdr.ipv4.hdr_checksum |
86 | | | | |
87 |MH2 |I | |ingress::hdr.ethernet.src_mac[15:0] |
88 | | | | |
89 |... | | | |
90 | | | | |
91 |H3 |I |[7:0] |ingress::hdr.sidecar.sc_pad |
92 | | |[15:8] |ingress::hdr.sidecar.sc_code |
93 | | | | |
94 |MH3 |I | |ingress::hdr.inner_ipv4.hdr_checksum |
95 | | | | |
96 |... | | | |
97 | | | | |
98 |MH4 |I |[0] |ingress::meta.ipv4_checksum_err |
99 | | | | |
100 |DH4 |I | |ingress::hdr.inner_udp.hdr_length ARA |
101 | | | | |
102 |MH5 |E |[0] |egress::eg_intr_md_for_dprsr.mirror_io_select.$valid |
103 | | |[1] |egress::eg_intr_md.egress_port.$valid |
104 | | |[2] |egress::hdr.ethernet.$valid |
105 | | |[3] |egress::hdr.vlan.$valid |
106 | | |[4] |egress::hdr.ipv4.$valid |
107 | | |[5] |egress::hdr.icmp.$valid |
108 | | |[6] |egress::hdr.udp.$valid |
109 | | |[7] |egress::hdr.geneve.$valid |
110 | | |[8] |egress::hdr.inner_eth.$valid |
111 | | |[9] |egress::hdr.inner_ipv4.$valid |
112 | | |[10] |egress::hdr.inner_tcp.$valid |
113 | | |[11] |egress::hdr.inner_udp.$valid |
114 | | |[12] |egress::hdr.inner_ipv6.$valid |
115 | | |[13] |egress::hdr.geneve_opts.oxg_ext_tag.$valid |
116 | | |[14] |egress::hdr.geneve_opts.oxg_mcast_tag.$valid |
117 | | |[15] |egress::hdr.geneve_opts.oxg_mcast.$valid |
118 | | | | |
119 |DH5 |I | |ingress::hdr.inner_eth.src_mac[15:0] ARA |
120 | | | | |
121 |MH6 |I |[7:0] |ingress::l3_router_Router4_fwd.slot[7:0] |
122 | | |[15:8] |ingress::l3_router_Router4_fwd.slot[15:8] |
123 | | |[7:0] |ingress::l3_router_Router6_fwd.slot[7:0] |
124 | | |[15:8] |ingress::l3_router_Router6_fwd.slot[15:8] |
125 | | | | |
126 |... | | | |
127 | | | | |
128 |MH7 |I |[8:0] |ingress::ig_intr_md.ingress_port |
129 | | | | |
130 |... | | | |
131 | | | | |
132 |H12 |I | |ingress::hdr.inner_ipv4.total_len |
133 | | | |ingress::hdr.inner_ipv6.payload_len |
134 | | | | |
135 |H13 |I | |ingress::hdr.ipv4.total_len |
136 | | | |ingress::hdr.ipv6.payload_len |
137 | | | | |
138 |H14 |I | |ingress::meta.l4_length |
139 | | | | |
140 |H15 |I | |ingress::hdr.inner_udp.hdr_length |
141 | | | |ingress::hdr.inner_udp.hdr_length ARA |
142 | | |[8:0] |ingress::l3_router_Router4_fwd.port ARA |
143 | | | | |
144 |H16 |I | |ingress::hdr.udp.hdr_length |
145 | | | | |
146 |H17 |I |[8:0] |ingress::ig_intr_md_for_tm.ucast_egress_port |
147 | | |[9] |ingress::meta.service_routed |
148 | | | | |
149 |H18 |I |[8:0] |ingress::hdr.sidecar.sc_egress[8:0] |
150 | | |[15:9] |ingress::hdr.sidecar.sc_egress[15:9] |
151 | | | | |
152 |H19 |I |[8:0] |ingress::hdr.sidecar.sc_ingress[8:0] |
153 | | |[15:9] |ingress::hdr.sidecar.sc_ingress[15:9] |
154 | | | | |
155 |H20 |I |[7:0] |ingress::l3_router_Router4_fwd.idx[7:0] |
156 | | |[15:8] |ingress::l3_router_Router4_fwd.idx[15:8] |
157 | | |[7:0] |ingress::l3_router_Router6_fwd.idx[7:0] |
158 | | |[15:8] |ingress::l3_router_Router6_fwd.idx[15:8] |
159 | | | | |
160 |H21 |I |[8:0] |ingress::l3_router_Router6_fwd.port ARA |
161 | | | |ingress::hdr.inner_eth.src_mac[15:0] |
162 | | | |ingress::hdr.inner_eth.src_mac[15:0] ARA |
163 | | | | |
164 |H22 |I |[11:0] |ingress::hdr.vlan.vlan_id |
165 | | |[12] |ingress::hdr.vlan.dei |
166 | | |[15:13] |ingress::hdr.vlan.pcp |
167 | | | | |
168 |H23 |I |[7:0] |ingress::hdr.inner_icmp.code |
169 | | |[15:8] |ingress::hdr.inner_icmp.type |
170 | | |[7:0] |ingress::hdr.icmp.code |
171 | | |[15:8] |ingress::hdr.icmp.type |
172 | | | | |
173 |MH8 |E |[8:0] |egress::eg_intr_md.egress_port |
174 | | | | |
175 |DH8 |I | |ingress::hdr.inner_eth.dst_mac[47:32] ARA |
176 | | | | |
177 |MH9 |I | |ingress::meta.nat_inner_mac[47:32] |
178 | | | | |
179 |... | | | |
180 | | | | |
181 |MH10 |I | |ingress::l3_router_Router4_fwd.nexthop6[111:96] |
182 | | | |ingress::l3_router_Router6_fwd.nexthop[111:96] |
183 | | | | |
184 |... | | | |
185 | | | | |
186 |MH11 |I | |ingress::meta.l4_src_port |
187 | | | | |
188 |... | | | |
189 | | | | |
190 |H24 |I | |ingress::hdr.inner_eth.dst_mac[47:32] |
191 | | | |ingress::hdr.inner_eth.dst_mac[47:32] ARA |
192 | | | |ingress::meta.nexthop_ipv6[111:96] ARA |
193 | | | | |
194 |H25 |I | |ingress::hdr.sidecar.sc_payload[111:96] |
195 | | | | |
196 |H26 |I | |ingress::meta.nat_ingress_csum |
197 | | | | |
198 |... | | | |
199 | | | | |
200 |MH12 |I | |ingress::hdr.sidecar.sc_payload[127:112] |
201 | | | | |
202 |... | | | |
203 | | | | |
204 |MH13 |I | |ingress::meta.nexthop_ipv6[127:112] |
205 | | | | |
206 |... | | | |
207 | | | | |
208 |MH14 |I | |ingress::l3_router_Router4_fwd.nexthop6[127:112] |
209 | | | |ingress::l3_router_Router6_fwd.nexthop[127:112] |
210 | | | | |
211 |... | | | |
212 | | | | |
213 |MH15 |I |[8:0] |ingress::meta.bridge_hdr.ingress_port |
214 | | |[15:9] |ingress::meta.bridge_hdr.__pad_0 |
215 | | | | |
216 |... | | | |
217 | | | | |
218 |MH16 |I | |ingress::hdr.sidecar.sc_ether_type |
219 | | | | |
220 |... | | | |
221 | | | | |
222 |MH17 |I | |ingress::hdr.ethernet.ether_type |
223 | | | | |
224 |... | | | |
225 | | | | |
226 |MH18 |I | |ingress::hdr.vlan.ether_type |
227 | | | | |
228 |... | | | |
229 | | | | |
230 |MH19 |I | |ingress::hdr.inner_eth.ether_type |
231 | | | | |
232 |... | | | |
233 | | | | |
234 |MH20 |I |[7:0] |ingress::meta.orig_src_mac[39:32] |
235 | | |[15:8] |ingress::meta.orig_src_mac[47:40] |
236 | | | | |
237 |... | | | |
238 | | | | |
239 |MH21 |I |[7:0] |ingress::hdr.ethernet.dst_mac[39:32] |
240 | | |[15:8] |ingress::hdr.ethernet.dst_mac[47:40] |
241 | | | | |
242 |... | | | |
243 | | | | |
244 |MH22 |I | |ingress::hdr.inner_udp.checksum |
245 | | | |ingress::hdr.inner_icmp.hdr_checksum |
246 | | | |ingress::hdr.icmp.hdr_checksum |
247 | | | | |
248 |... | | | |
249 | | | | |
250 |MH23 |I | |ingress::hdr.udp.checksum |
251 | | | | |
252 |... | | | |
253 | | | | |
254 |W0 |I |[0] |ingress::ig_intr_md_for_dprsr.mirror_type.$valid |
255 | | |[1] |ingress::ig_intr_md_for_tm.ucast_egress_port.$valid |
256 | | |[2] |ingress::ig_intr_md_for_dprsr.drop_ctl.$valid |
257 | | |[3] |ingress::ig_intr_md_for_tm.bypass_egress.$valid |
258 | | |[4] |ingress::meta.bridge_hdr.$valid |
259 | | |[5] |ingress::hdr.ethernet.$valid |
260 | | |[6] |ingress::hdr.sidecar.$valid |
261 | | |[7] |ingress::hdr.vlan.$valid |
262 | | |[8] |ingress::hdr.ipv4.$valid |
263 | | |[9] |ingress::hdr.icmp.$valid |
264 | | |[10] |ingress::hdr.tcp.$valid |
265 | | |[11] |ingress::hdr.udp.$valid |
266 | | |[12] |ingress::hdr.geneve.$valid |
267 | | |[13] |ingress::hdr.inner_eth.$valid |
268 | | |[14] |ingress::hdr.inner_ipv4.$valid |
269 | | |[15] |ingress::hdr.inner_tcp.$valid |
270 | | |[16] |ingress::hdr.inner_udp.$valid |
271 | | |[17] |ingress::hdr.inner_icmp.$valid |
272 | | |[18] |ingress::hdr.inner_ipv6.$valid |
273 | | |[19] |ingress::hdr.geneve_opts.oxg_ext_tag.$valid |
274 | | |[20] |ingress::hdr.geneve_opts.oxg_mcast_tag.$valid |
275 | | |[21] |ingress::hdr.geneve_opts.oxg_mcast.$valid |
276 | | |[22] |ingress::hdr.geneve_opts.oxg_mss_tag.$valid |
277 | | |[23] |ingress::hdr.geneve_opts.oxg_mss.$valid |
278 | | |[24] |ingress::hdr.ipv6.$valid |
279 | | |[25] |ingress::hdr.arp.$valid |
280 | | |[26] |ingress::meta.dropped |
281 | | |[27] |ingress::meta.is_mcast |
282 | | |[28] |ingress::meta.nat_egress_hit |
283 | | |[29] |ingress::meta.encap_needed |
284 | | |[30] |ingress::meta.resolve_nexthop |
285 | | |[31] |ingress::meta.icmp_recalc |
286 | | | | |
287 |MW0 |I | |ingress::meta.orig_src_ipv4 |
288 | | | | |
289 |... | | | |
290 | | | | |
291 |W1 |I |[4:0] |ingress::hdr.geneve_opts.oxg_ext_tag.opt_len |
292 | | |[7:5] |ingress::hdr.geneve_opts.oxg_ext_tag.reserved |
293 | | |[14:8] |ingress::hdr.geneve_opts.oxg_ext_tag.type |
294 | | |[15] |ingress::hdr.geneve_opts.oxg_ext_tag.crit |
295 | | |[31:16] |ingress::hdr.geneve_opts.oxg_ext_tag.class |
296 | | | | |
297 |MW1 |I | |ingress::hdr.inner_ipv4.dst_addr |
298 | | | |ingress::hdr.inner_ipv6.dst_addr[31:0] |
299 | | | | |
300 |... | | | |
301 | | | | |
302 |W2 |I | |ingress::hdr.ipv4.src_addr |
303 | | | |ingress::hdr.ipv6.dst_addr[31:0] |
304 | | | | |
305 |MW2 |I | |ingress::hdr.ipv4.dst_addr |
306 | | | |ingress::hdr.ipv6.src_addr[31:0] |
307 | | | | |
308 |... | | | |
309 | | | | |
310 |W3 |I |[15:0] |ingress::hdr.inner_icmp.data[15:0] |
311 | | |[31:16] |ingress::hdr.inner_icmp.data[31:16] |
312 | | |[15:0] |ingress::hdr.icmp.data[15:0] |
313 | | |[31:16] |ingress::hdr.icmp.data[31:16] |
314 | | |[15:0] |ingress::hdr.inner_tcp.window |
315 | | |[23:16] |ingress::hdr.inner_tcp.flags |
316 | | |[27:24] |ingress::hdr.inner_tcp.res |
317 | | |[31:28] |ingress::hdr.inner_tcp.data_offset |
318 | | |[15:0] |ingress::hdr.tcp.window |
319 | | |[23:16] |ingress::hdr.tcp.flags |
320 | | |[27:24] |ingress::hdr.tcp.res |
321 | | |[31:28] |ingress::hdr.tcp.data_offset |
322 | | |[15:0] |ingress::hdr.inner_udp.dst_port |
323 | | |[31:16] |ingress::hdr.inner_udp.src_port |
324 | | | | |
325 |MW3 |I | |ingress::hdr.inner_ipv4.src_addr |
326 | | | |ingress::hdr.inner_ipv6.src_addr[31:0] |
327 | | | | |
328 |... | | | |
329 | | | | |
330 |W4 |I | |ingress::meta.nat_ingress_tgt[31:0] |
331 | | |[7:0] |ingress::l3_router_Router4_fwd.slots |
332 | | | | |
333 |W5 |I |[15:0] |ingress::meta.l4_dst_port |
334 | | | | |
335 |W6 |I |[15:0] |ingress::hdr.udp.dst_port |
336 | | |[31:16] |ingress::hdr.udp.src_port |
337 | | | | |
338 |W7 |I |[15:0] |ingress::hdr.inner_tcp.urgent_ptr |
339 | | |[31:16] |ingress::hdr.inner_tcp.checksum |
340 | | |[15:0] |ingress::hdr.tcp.urgent_ptr |
341 | | |[31:16] |ingress::hdr.tcp.checksum |
342 | | | | |
343 |W8 |I | |ingress::hdr.inner_tcp.seq_no |
344 | | | |ingress::hdr.tcp.seq_no |
345 | | | | |
346 |W9 |I |[15:0] |ingress::hdr.geneve.protocol |
347 | | |[21:16] |ingress::hdr.geneve.reserved |
348 | | |[22] |ingress::hdr.geneve.crit |
349 | | |[23] |ingress::hdr.geneve.ctrl |
350 | | |[29:24] |ingress::hdr.geneve.opt_len |
351 | | |[31:30] |ingress::hdr.geneve.version |
352 | | | | |
353 |W10 |I | |ingress::hdr.ethernet.src_mac[47:16] |
354 | | | | |
355 |... | | | |
356 | | | | |
357 |MW4 |I | |ingress::hdr.inner_ipv6.dst_addr[63:32] |
358 | | | | |
359 |DW4 |I | |ingress::hdr.inner_eth.src_mac[47:16] ARA |
360 | | | | |
361 |MW5 |I | |ingress::hdr.inner_ipv6.src_addr[63:32] |
362 | | | | |
363 |DW5 |I | |ingress::hdr.inner_eth.dst_mac[31:0] ARA |
364 | | | | |
365 |MW6 |I | |ingress::hdr.ipv6.src_addr[63:32] |
366 | | | | |
367 |... | | | |
368 | | | | |
369 |MW7 |I | |ingress::meta.nat_ingress_tgt[63:32] |
370 | | | | |
371 |... | | | |
372 | | | | |
373 |W12 |I | |ingress::hdr.ipv6.dst_addr[63:32] |
374 | | |[12:0] |ingress::hdr.ipv4.frag_offset |
375 | | |[15:13] |ingress::hdr.ipv4.flags |
376 | | |[31:16] |ingress::hdr.ipv4.identification |
377 | | | | |
378 |W13 |I |[12:0] |ingress::hdr.inner_ipv4.frag_offset |
379 | | |[15:13] |ingress::hdr.inner_ipv4.flags |
380 | | |[31:16] |ingress::hdr.inner_ipv4.identification |
381 | | |[19:0] |ingress::hdr.inner_ipv6.flow_label |
382 | | |[27:20] |ingress::hdr.inner_ipv6.traffic_class |
383 | | |[31:28] |ingress::hdr.inner_ipv6.version |
384 | | | | |
385 |W14 |I |[19:0] |ingress::hdr.ipv6.flow_label |
386 | | |[27:20] |ingress::hdr.ipv6.traffic_class |
387 | | |[31:28] |ingress::hdr.ipv6.version |
388 | | | | |
389 |W15 |I |[15:0] |ingress::hdr.inner_tcp.dst_port |
390 | | |[31:16] |ingress::hdr.inner_tcp.src_port |
391 | | |[15:0] |ingress::hdr.tcp.dst_port |
392 | | |[31:16] |ingress::hdr.tcp.src_port |
393 | | | | |
394 |W16 |I |[7:0] |ingress::hdr.geneve.reserved2 |
395 | | |[31:8] |ingress::hdr.geneve.vni |
396 | | | | |
397 |W17 |I |[7:0] |ingress::hdr.sidecar.sc_payload[7:0] |
398 | | |[31:8] |ingress::hdr.sidecar.sc_payload[31:8] |
399 | | | | |
400 |W18 |I |[31:8] |ingress::meta.nat_geneve_vni |
401 | | |[7:0] |ingress::meta.nexthop_ipv6[7:0] |
402 | | |[15:8] |ingress::l3_router_Router4_fwd.nexthop6[7:0] |
403 | | |[23:16] |ingress::l3_router_Router6_fwd.nexthop[7:0] |
404 | | |[31:24] |ingress::l3_router_Router4_fwd.nexthop[7:0] |
405 | | | | |
406 |W19 |I |[7:0] |ingress::meta.nexthop_ipv4[7:0] |
407 | | |[31:8] |ingress::l3_router_Router4_fwd.nexthop6[31:8] |
408 | | |[31:8] |ingress::l3_router_Router6_fwd.nexthop[31:8] |
409 | | |[17:8] |ingress::meta.pkt_type |
410 | | |[18] |ingress::meta.is_switch_address |
411 | | |[19] |ingress::meta.is_link_local_mcastv6 |
412 | | |[20] |ingress::meta.nat_ingress_hit |
413 | | |[21] |ingress::meta.uplink_ingress |
414 | | | | |
415 |W20 |I |[23:0] |ingress::meta.nexthop_ipv6[31:8] ARA |
416 | | | |ingress::hdr.inner_eth.src_mac[47:16] |
417 | | | |ingress::hdr.inner_eth.src_mac[47:16] ARA |
418 | | | | |
419 |W21 |I |[23:0] |ingress::meta.nexthop_ipv4[31:8] |
420 | | |[31:24] |ingress::meta.drop_reason |
421 | | | | |
422 |W22 |I |[23:0] |ingress::l3_router_Router4_fwd.nexthop[31:8] ARA |
423 | | | |ingress::hdr.inner_eth.dst_mac[31:0] |
424 | | | |ingress::hdr.inner_eth.dst_mac[31:0] ARA |
425 | | | | |
426 |W23 |I | |ingress::meta.nat_inner_mac[31:0] |
427 | | | | |
428 |MW8 |I | |ingress::hdr.inner_ipv6.dst_addr[95:64] |
429 | | | | |
430 |DW8 |I | |ingress::hdr.ipv6.dst_addr[95:64] ARA |
431 | | | | |
432 |MW9 |I | |ingress::hdr.inner_ipv6.src_addr[95:64] |
433 | | | | |
434 |... | | | |
435 | | | | |
436 |MW10 |I | |ingress::hdr.ipv6.src_addr[95:64] |
437 | | | | |
438 |... | | | |
439 | | | | |
440 |MW11 |I | |ingress::meta.nat_ingress_tgt[95:64] |
441 | | | | |
442 |... | | | |
443 | | | | |
444 |W24 |I | |ingress::hdr.ipv6.dst_addr[95:64] |
445 | | | |ingress::hdr.ipv6.dst_addr[95:64] ARA |
446 | | | |ingress::meta.nexthop_ipv6[95:64] ARA |
447 | | | | |
448 |W25 |I |[23:0] |ingress::hdr.ethernet.dst_mac[23:0] |
449 | | |[31:24] |ingress::hdr.ethernet.dst_mac[31:24] |
450 | | | | |
451 |W26 |I |[23:0] |ingress::meta.orig_src_mac[23:0] |
452 | | |[31:24] |ingress::meta.orig_src_mac[31:24] |
453 | | | |ingress::l3_router_Router4_fwd.nexthop6[95:64] |
454 | | | | |
455 |W27 |I | |ingress::hdr.sidecar.sc_payload[95:64] |
456 | | | | |
457 |W28 |I | |ingress::l3_router_Router6_fwd.nexthop[95:64] |
458 | | | |ingress::meta.orig_dst_ipv4 |
459 | | | | |
460 |... | | | |
461 | | | | |
462 |MW12 |I | |ingress::hdr.inner_ipv6.dst_addr[127:96] |
463 | | | | |
464 |DW12 |I | |ingress::hdr.ipv6.dst_addr[127:96] ARA |
465 | | | | |
466 |MW13 |I | |ingress::hdr.inner_ipv6.src_addr[127:96] |
467 | | | | |
468 |... | | | |
469 | | | | |
470 |MW14 |I | |ingress::hdr.ipv6.src_addr[127:96] |
471 | | | | |
472 |... | | | |
473 | | | | |
474 |MW15 |I | |ingress::meta.nat_ingress_tgt[127:96] |
475 | | | | |
476 |... | | | |
477 | | | | |
478 |W36 |I | |ingress::hdr.ipv6.dst_addr[127:96] |
479 | | | |ingress::hdr.ipv6.dst_addr[127:96] ARA |
480 | | | |ingress::meta.nexthop_ipv6[63:32] ARA |
481 | | | | |
482 |W37 |I | |ingress::hdr.inner_tcp.ack_no |
483 | | | |ingress::hdr.tcp.ack_no |
484 | | | | |
485 |W38 |I | |ingress::hdr.sidecar.sc_payload[63:32] |
486 | | | | |
487 |... | | | |
488 | | | | |
489 |W40 |I | |ingress::l3_router_Router4_fwd.nexthop6[63:32] |
490 | | | |ingress::l3_router_Router6_fwd.nexthop[63:32] |
491 | | | | |
492 |... | | | |
493 | | | | |
494 +-----------+-------+-----------------+--------------------------------------------------------+
495 
496 
497 POV Allocation (ingress):
498 +-----------+-----------------+--------------------------------------------------------+
499 |Container |Container Slice |Field Slice |
500 +-----------+-----------------+--------------------------------------------------------+
501 |B1 |[0] |ingress::hdr.udp.checksum.$deparse_original_csum |
502 | |[1] |ingress::hdr.udp.checksum.$deparse_updated_csum_0 |
503 | |[2] |ingress::hdr.udp.checksum.$deparse_updated_csum_1 |
504 | |[3] |ingress::hdr.udp.checksum.$deparse_updated_csum_2 |
505 | |[4] |ingress::hdr.udp.checksum.$deparse_updated_csum_3 |
506 | |[5] |ingress::hdr.icmp.hdr_checksum.$deparse_original_csum |
507 | |[6] |ingress::hdr.icmp.hdr_checksum.$deparse_updated_csum_0 |
508 +-----------+-----------------+--------------------------------------------------------+
509 |W0 |[0] |ingress::ig_intr_md_for_dprsr.mirror_type.$valid |
510 | |[1] |ingress::ig_intr_md_for_tm.ucast_egress_port.$valid |
511 | |[2] |ingress::ig_intr_md_for_dprsr.drop_ctl.$valid |
512 | |[3] |ingress::ig_intr_md_for_tm.bypass_egress.$valid |
513 | |[4] |ingress::meta.bridge_hdr.$valid |
514 | |[5] |ingress::hdr.ethernet.$valid |
515 | |[6] |ingress::hdr.sidecar.$valid |
516 | |[7] |ingress::hdr.vlan.$valid |
517 | |[8] |ingress::hdr.ipv4.$valid |
518 | |[9] |ingress::hdr.icmp.$valid |
519 | |[10] |ingress::hdr.tcp.$valid |
520 | |[11] |ingress::hdr.udp.$valid |
521 | |[12] |ingress::hdr.geneve.$valid |
522 | |[13] |ingress::hdr.inner_eth.$valid |
523 | |[14] |ingress::hdr.inner_ipv4.$valid |
524 | |[15] |ingress::hdr.inner_tcp.$valid |
525 | |[16] |ingress::hdr.inner_udp.$valid |
526 | |[17] |ingress::hdr.inner_icmp.$valid |
527 | |[18] |ingress::hdr.inner_ipv6.$valid |
528 | |[19] |ingress::hdr.geneve_opts.oxg_ext_tag.$valid |
529 | |[20] |ingress::hdr.geneve_opts.oxg_mcast_tag.$valid |
530 | |[21] |ingress::hdr.geneve_opts.oxg_mcast.$valid |
531 | |[22] |ingress::hdr.geneve_opts.oxg_mss_tag.$valid |
532 | |[23] |ingress::hdr.geneve_opts.oxg_mss.$valid |
533 | |[24] |ingress::hdr.ipv6.$valid |
534 | |[25] |ingress::hdr.arp.$valid |
535 +-----------+-----------------+--------------------------------------------------------+
536 | |Total Bits Used |33 / 128 ( 25.8 %) |
537 | |Pack Density |33 / 40 ( 82.5 %) |
538 +-----------+-----------------+--------------------------------------------------------+
539 
540 POV Allocation (egress):
541 +-----------+-----------------+------------------------------------------------------+
542 |Container |Container Slice |Field Slice |
543 +-----------+-----------------+------------------------------------------------------+
544 |MB0 |[0] |egress::hdr.geneve_opts.oxg_mss_tag.$valid |
545 | |[1] |egress::hdr.geneve_opts.oxg_mss.$valid |
546 | |[2] |egress::hdr.ipv6.$valid |
547 +-----------+-----------------+------------------------------------------------------+
548 |MH5 |[0] |egress::eg_intr_md_for_dprsr.mirror_io_select.$valid |
549 | |[1] |egress::eg_intr_md.egress_port.$valid |
550 | |[2] |egress::hdr.ethernet.$valid |
551 | |[3] |egress::hdr.vlan.$valid |
552 | |[4] |egress::hdr.ipv4.$valid |
553 | |[5] |egress::hdr.icmp.$valid |
554 | |[6] |egress::hdr.udp.$valid |
555 | |[7] |egress::hdr.geneve.$valid |
556 | |[8] |egress::hdr.inner_eth.$valid |
557 | |[9] |egress::hdr.inner_ipv4.$valid |
558 | |[10] |egress::hdr.inner_tcp.$valid |
559 | |[11] |egress::hdr.inner_udp.$valid |
560 | |[12] |egress::hdr.inner_ipv6.$valid |
561 | |[13] |egress::hdr.geneve_opts.oxg_ext_tag.$valid |
562 | |[14] |egress::hdr.geneve_opts.oxg_mcast_tag.$valid |
563 | |[15] |egress::hdr.geneve_opts.oxg_mcast.$valid |
564 +-----------+-----------------+------------------------------------------------------+
565 | |Total Bits Used |19 / 128 ( 14.8 %) |
566 | |Pack Density |19 / 24 ( 79.2 %) |
567 +-----------+-----------------+------------------------------------------------------+
568 
569 +--------------------------------------------------------+------------+-----------+----------------+-----------------+
570 |Field Slice |Live Range |Container |Container Type |Container Slice |
571 +--------------------------------------------------------+------------+-----------+----------------+-----------------+
572 |ingress::ig_intr_md_for_dprsr.mirror_type.$valid |[-1r, 16w] |W0 |W |[0] |
573 |ingress::ig_intr_md.ingress_port |[-1r, 16w] |MH7 |MH |[8:0] |
574 |ingress::meta.bridge_hdr.__pad_0 |[-1r, 16w] |MH15 |MH |[15:9] |
575 |ingress::meta.bridge_hdr.ingress_port |[-1r, 16w] |MH15 |MH |[8:0] |
576 |ingress::hdr.ethernet.dst_mac[39:32] |[-1r, 16w] |MH21 |MH |[7:0] |
577 |ingress::hdr.ethernet.dst_mac[47:40] |[-1r, 16w] |MH21 |MH |[15:8] |
578 |ingress::hdr.ethernet.dst_mac[23:0] |[-1r, 16w] |W25 |W |[23:0] |
579 |ingress::hdr.ethernet.dst_mac[31:24] |[-1r, 16w] |W25 |W |[31:24] |
580 |ingress::hdr.ethernet.src_mac[15:0] |[-1r, 16w] |MH2 |MH | |
581 |ingress::hdr.ethernet.src_mac[47:16] |[-1r, 16w] |W10 |W | |
582 |ingress::hdr.ethernet.ether_type |[-1r, 16w] |MH17 |MH | |
583 |ingress::meta.dropped |[-1r, 16w] |W0 |W |[26] |
584 |ingress::meta.ipv4_checksum_err |[-1r, 16w] |MH4 |MH |[0] |
585 |ingress::meta.is_switch_address |[-1r, 16w] |W19 |W |[18] |
586 |ingress::meta.is_mcast |[-1r, 16w] |W0 |W |[27] |
587 |ingress::meta.is_link_local_mcastv6 |[-1r, 16w] |W19 |W |[19] |
588 |ingress::meta.service_routed |[-1r, 16w] |H17 |H |[9] |
589 |ingress::meta.nat_egress_hit |[-1r, 16w] |W0 |W |[28] |
590 |ingress::meta.nat_ingress_hit |[-1r, 16w] |W19 |W |[20] |
591 |ingress::meta.uplink_ingress |[-1r, 16w] |W19 |W |[21] |
592 |ingress::meta.encap_needed |[-1r, 16w] |W0 |W |[29] |
593 |ingress::meta.resolve_nexthop |[-1r, 16w] |W0 |W |[30] |
594 |ingress::meta.nexthop_ipv4[7:0] |[-1r, 16w] |W19 |W |[7:0] |
595 |ingress::meta.nexthop_ipv4[31:8] |[-1r, 16w] |W21 |W |[23:0] |
596 |ingress::meta.nexthop_ipv6[127:112] |[-1r, 16w] |MH13 |MH | |
597 |ingress::meta.nexthop_ipv6[111:96] |[5w, 13r] |H24 |H | |
598 |ingress::meta.nexthop_ipv6[7:0] |[-1r, 16w] |W18 |W |[7:0] |
599 |ingress::meta.nexthop_ipv6[31:8] |[5w, 13r] |W20 |W |[23:0] |
600 |ingress::meta.nexthop_ipv6[95:64] |[7w, 13r] |W24 |W | |
601 |ingress::meta.nexthop_ipv6[63:32] |[7w, 13r] |W36 |W | |
602 |ingress::meta.pkt_type |[-1r, 16w] |W19 |W |[17:8] |
603 |ingress::meta.drop_reason |[-1r, 16w] |W21 |W |[31:24] |
604 |ingress::meta.l4_src_port |[-1r, 16w] |MH11 |MH | |
605 |ingress::meta.l4_dst_port |[-1r, 16w] |W5 |W |[15:0] |
606 |ingress::meta.nat_ingress_tgt[63:32] |[-1r, 16w] |MW7 |MW | |
607 |ingress::meta.nat_ingress_tgt[95:64] |[-1r, 16w] |MW11 |MW | |
608 |ingress::meta.nat_ingress_tgt[127:96] |[-1r, 16w] |MW15 |MW | |
609 |ingress::meta.nat_ingress_tgt[31:0] |[-1r, 16w] |W4 |W | |
610 |ingress::meta.nat_inner_mac[47:32] |[-1r, 16w] |MH9 |MH | |
611 |ingress::meta.nat_inner_mac[31:0] |[-1r, 16w] |W23 |W | |
612 |ingress::meta.nat_geneve_vni |[-1r, 16w] |W18 |W |[31:8] |
613 |ingress::meta.icmp_recalc |[-1r, 16w] |W0 |W |[31] |
614 |ingress::meta.icmp_csum |[-1r, 16w] |MH0 |MH | |
615 |ingress::meta.body_checksum |[-1r, 16w] |MH1 |MH | |
616 |ingress::meta.l4_length |[-1r, 16w] |H14 |H | |
617 |ingress::meta.orig_src_mac[39:32] |[-1r, 16w] |MH20 |MH |[7:0] |
618 |ingress::meta.orig_src_mac[47:40] |[-1r, 16w] |MH20 |MH |[15:8] |
619 |ingress::meta.orig_src_mac[23:0] |[-1r, 16w] |W26 |W |[23:0] |
620 |ingress::meta.orig_src_mac[31:24] |[-1r, 16w] |W26 |W |[31:24] |
621 |ingress::meta.orig_src_ipv4 |[-1r, 16w] |MW0 |MW | |
622 |ingress::meta.orig_dst_ipv4 |[-1r, 16w] |W28 |W | |
623 |ingress::meta.nat_ingress_csum |[-1r, 16w] |H26 |H | |
624 |ingress::hdr.sidecar.sc_code |[-1r, 16w] |H3 |H |[15:8] |
625 |ingress::hdr.sidecar.sc_pad |[-1r, 16w] |H3 |H |[7:0] |
626 |ingress::hdr.sidecar.sc_ingress[8:0] |[-1r, 16w] |H19 |H |[8:0] |
627 |ingress::hdr.sidecar.sc_ingress[15:9] |[-1r, 16w] |H19 |H |[15:9] |
628 |ingress::hdr.sidecar.sc_egress[8:0] |[-1r, 16w] |H18 |H |[8:0] |
629 |ingress::hdr.sidecar.sc_egress[15:9] |[-1r, 16w] |H18 |H |[15:9] |
630 |ingress::hdr.sidecar.sc_ether_type |[-1r, 16w] |MH16 |MH | |
631 |ingress::hdr.sidecar.sc_payload[127:112] |[-1r, 16w] |MH12 |MH | |
632 |ingress::hdr.sidecar.sc_payload[111:96] |[-1r, 16w] |H25 |H | |
633 |ingress::hdr.sidecar.sc_payload[7:0] |[-1r, 16w] |W17 |W |[7:0] |
634 |ingress::hdr.sidecar.sc_payload[31:8] |[-1r, 16w] |W17 |W |[31:8] |
635 |ingress::hdr.sidecar.sc_payload[95:64] |[-1r, 16w] |W27 |W | |
636 |ingress::hdr.sidecar.sc_payload[63:32] |[-1r, 16w] |W38 |W | |
637 |ingress::hdr.vlan.pcp |[-1r, 16w] |H22 |H |[15:13] |
638 |ingress::hdr.vlan.dei |[-1r, 16w] |H22 |H |[12] |
639 |ingress::hdr.vlan.vlan_id |[-1r, 16w] |H22 |H |[11:0] |
640 |ingress::hdr.vlan.ether_type |[-1r, 16w] |MH18 |MH | |
641 |ingress::hdr.ipv4.version |[-1r, 16w] |H1 |H |[15:12] |
642 |ingress::hdr.ipv4.ihl |[-1r, 16w] |H1 |H |[11:8] |
643 |ingress::hdr.ipv4.diffserv |[-1r, 16w] |H1 |H |[7:0] |
644 |ingress::hdr.ipv4.total_len |[-1r, 16w] |H13 |H | |
645 |ingress::hdr.ipv4.identification |[-1r, 16w] |W12 |W |[31:16] |
646 |ingress::hdr.ipv4.flags |[-1r, 16w] |W12 |W |[15:13] |
647 |ingress::hdr.ipv4.frag_offset |[-1r, 16w] |W12 |W |[12:0] |
648 |ingress::hdr.ipv4.ttl |[-1r, 16w] |B12 |B | |
649 |ingress::hdr.ipv4.protocol |[-1r, 16w] |MB9 |MB | |
650 |ingress::hdr.ipv4.hdr_checksum |[-1r, 16w] |H2 |H | |
651 |ingress::hdr.ipv4.src_addr |[-1r, 16w] |W2 |W | |
652 |ingress::hdr.ipv4.dst_addr |[-1r, 16w] |MW2 |MW | |
653 |ingress::hdr.icmp.type |[-1r, 16w] |H23 |H |[15:8] |
654 |ingress::hdr.icmp.code |[-1r, 16w] |H23 |H |[7:0] |
655 |ingress::hdr.icmp.hdr_checksum |[-1r, 16w] |MH22 |MH | |
656 |ingress::hdr.icmp.data[15:0] |[-1r, 16w] |W3 |W |[15:0] |
657 |ingress::hdr.icmp.data[31:16] |[-1r, 16w] |W3 |W |[31:16] |
658 |ingress::hdr.tcp.src_port |[-1r, 16w] |W15 |W |[31:16] |
659 |ingress::hdr.tcp.dst_port |[-1r, 16w] |W15 |W |[15:0] |
660 |ingress::hdr.tcp.seq_no |[-1r, 16w] |W8 |W | |
661 |ingress::hdr.tcp.ack_no |[-1r, 16w] |W37 |W | |
662 |ingress::hdr.tcp.data_offset |[-1r, 16w] |W3 |W |[31:28] |
663 |ingress::hdr.tcp.res |[-1r, 16w] |W3 |W |[27:24] |
664 |ingress::hdr.tcp.flags |[-1r, 16w] |W3 |W |[23:16] |
665 |ingress::hdr.tcp.window |[-1r, 16w] |W3 |W |[15:0] |
666 |ingress::hdr.tcp.checksum |[-1r, 16w] |W7 |W |[31:16] |
667 |ingress::hdr.tcp.urgent_ptr |[-1r, 16w] |W7 |W |[15:0] |
668 |ingress::hdr.udp.src_port |[-1r, 16w] |W6 |W |[31:16] |
669 |ingress::hdr.udp.dst_port |[-1r, 16w] |W6 |W |[15:0] |
670 |ingress::hdr.udp.hdr_length |[-1r, 16w] |H16 |H | |
671 |ingress::hdr.udp.checksum |[-1r, 16w] |MH23 |MH | |
672 |ingress::hdr.geneve.version |[-1r, 16w] |W9 |W |[31:30] |
673 |ingress::hdr.geneve.opt_len |[-1r, 16w] |W9 |W |[29:24] |
674 |ingress::hdr.geneve.ctrl |[-1r, 16w] |W9 |W |[23] |
675 |ingress::hdr.geneve.crit |[-1r, 16w] |W9 |W |[22] |
676 |ingress::hdr.geneve.reserved |[-1r, 16w] |W9 |W |[21:16] |
677 |ingress::hdr.geneve.protocol |[-1r, 16w] |W9 |W |[15:0] |
678 |ingress::hdr.geneve.vni |[-1r, 16w] |W16 |W |[31:8] |
679 |ingress::hdr.geneve.reserved2 |[-1r, 16w] |W16 |W |[7:0] |
680 |ingress::hdr.inner_eth.dst_mac[47:32] |[5w, 13r] |DH8 |DH | |
681 |ingress::hdr.inner_eth.dst_mac[31:0] |[5w, 12r] |DW5 |DW | |
682 |ingress::hdr.inner_eth.dst_mac[47:32] |[-1w, 5r] |H24 |H | |
683 |ingress::hdr.inner_eth.dst_mac[47:32] |[13w, 16r] |H24 |H | |
684 |ingress::hdr.inner_eth.dst_mac[31:0] |[-1w, 5r] |W22 |W | |
685 |ingress::hdr.inner_eth.dst_mac[31:0] |[12w, 16r] |W22 |W | |
686 |ingress::hdr.inner_eth.src_mac[15:0] |[5w, 12r] |DH5 |DH | |
687 |ingress::hdr.inner_eth.src_mac[47:16] |[5w, 13r] |DW4 |DW | |
688 |ingress::hdr.inner_eth.src_mac[15:0] |[-1w, 5r] |H21 |H | |
689 |ingress::hdr.inner_eth.src_mac[15:0] |[12w, 16r] |H21 |H | |
690 |ingress::hdr.inner_eth.src_mac[47:16] |[-1w, 5r] |W20 |W | |
691 |ingress::hdr.inner_eth.src_mac[47:16] |[13w, 16r] |W20 |W | |
692 |ingress::hdr.inner_eth.ether_type |[-1r, 16w] |MH19 |MH | |
693 |ingress::hdr.inner_ipv4.version |[-1r, 16w] |H0 |H |[15:12] |
694 |ingress::hdr.inner_ipv4.ihl |[-1r, 16w] |H0 |H |[11:8] |
695 |ingress::hdr.inner_ipv4.diffserv |[-1r, 16w] |H0 |H |[7:0] |
696 |ingress::hdr.inner_ipv4.total_len |[-1r, 16w] |H12 |H | |
697 |ingress::hdr.inner_ipv4.identification |[-1r, 16w] |W13 |W |[31:16] |
698 |ingress::hdr.inner_ipv4.flags |[-1r, 16w] |W13 |W |[15:13] |
699 |ingress::hdr.inner_ipv4.frag_offset |[-1r, 16w] |W13 |W |[12:0] |
700 |ingress::hdr.inner_ipv4.ttl |[-1r, 16w] |MB4 |MB | |
701 |ingress::hdr.inner_ipv4.protocol |[-1r, 16w] |MB8 |MB | |
702 |ingress::hdr.inner_ipv4.hdr_checksum |[-1r, 16w] |MH3 |MH | |
703 |ingress::hdr.inner_ipv4.src_addr |[-1r, 16w] |MW3 |MW | |
704 |ingress::hdr.inner_ipv4.dst_addr |[-1r, 16w] |MW1 |MW | |
705 |ingress::hdr.inner_tcp.src_port |[-1r, 16w] |W15 |W |[31:16] |
706 |ingress::hdr.inner_tcp.dst_port |[-1r, 16w] |W15 |W |[15:0] |
707 |ingress::hdr.inner_tcp.seq_no |[-1r, 16w] |W8 |W | |
708 |ingress::hdr.inner_tcp.ack_no |[-1r, 16w] |W37 |W | |
709 |ingress::hdr.inner_tcp.data_offset |[-1r, 16w] |W3 |W |[31:28] |
710 |ingress::hdr.inner_tcp.res |[-1r, 16w] |W3 |W |[27:24] |
711 |ingress::hdr.inner_tcp.flags |[-1r, 16w] |W3 |W |[23:16] |
712 |ingress::hdr.inner_tcp.window |[-1r, 16w] |W3 |W |[15:0] |
713 |ingress::hdr.inner_tcp.checksum |[-1r, 16w] |W7 |W |[31:16] |
714 |ingress::hdr.inner_tcp.urgent_ptr |[-1r, 16w] |W7 |W |[15:0] |
715 |ingress::hdr.inner_udp.src_port |[-1r, 16w] |W3 |W |[31:16] |
716 |ingress::hdr.inner_udp.dst_port |[-1r, 16w] |W3 |W |[15:0] |
717 |ingress::hdr.inner_udp.hdr_length |[6w, 12r] |DH4 |DH | |
718 |ingress::hdr.inner_udp.hdr_length |[-1w, 6r] |H15 |H | |
719 |ingress::hdr.inner_udp.hdr_length |[12w, 16r] |H15 |H | |
720 |ingress::hdr.inner_udp.checksum |[-1r, 16w] |MH22 |MH | |
721 |ingress::hdr.inner_icmp.type |[-1r, 16w] |H23 |H |[15:8] |
722 |ingress::hdr.inner_icmp.code |[-1r, 16w] |H23 |H |[7:0] |
723 |ingress::hdr.inner_icmp.hdr_checksum |[-1r, 16w] |MH22 |MH | |
724 |ingress::hdr.inner_icmp.data[15:0] |[-1r, 16w] |W3 |W |[15:0] |
725 |ingress::hdr.inner_icmp.data[31:16] |[-1r, 16w] |W3 |W |[31:16] |
726 |ingress::hdr.inner_ipv6.version |[-1r, 16w] |W13 |W |[31:28] |
727 |ingress::hdr.inner_ipv6.traffic_class |[-1r, 16w] |W13 |W |[27:20] |
728 |ingress::hdr.inner_ipv6.flow_label |[-1r, 16w] |W13 |W |[19:0] |
729 |ingress::hdr.inner_ipv6.payload_len |[-1r, 16w] |H12 |H | |
730 |ingress::hdr.inner_ipv6.next_hdr |[-1r, 16w] |MB8 |MB | |
731 |ingress::hdr.inner_ipv6.hop_limit |[-1r, 16w] |MB4 |MB | |
732 |ingress::hdr.inner_ipv6.src_addr[31:0] |[-1r, 16w] |MW3 |MW | |
733 |ingress::hdr.inner_ipv6.src_addr[63:32] |[-1r, 16w] |MW5 |MW | |
734 |ingress::hdr.inner_ipv6.src_addr[95:64] |[-1r, 16w] |MW9 |MW | |
735 |ingress::hdr.inner_ipv6.src_addr[127:96] |[-1r, 16w] |MW13 |MW | |
736 |ingress::hdr.inner_ipv6.dst_addr[31:0] |[-1r, 16w] |MW1 |MW | |
737 |ingress::hdr.inner_ipv6.dst_addr[63:32] |[-1r, 16w] |MW4 |MW | |
738 |ingress::hdr.inner_ipv6.dst_addr[95:64] |[-1r, 16w] |MW8 |MW | |
739 |ingress::hdr.inner_ipv6.dst_addr[127:96] |[-1r, 16w] |MW12 |MW | |
740 |ingress::hdr.geneve_opts.oxg_ext_tag.class |[-1r, 16w] |W1 |W |[31:16] |
741 |ingress::hdr.geneve_opts.oxg_ext_tag.crit |[-1r, 16w] |W1 |W |[15] |
742 |ingress::hdr.geneve_opts.oxg_ext_tag.type |[-1r, 16w] |W1 |W |[14:8] |
743 |ingress::hdr.geneve_opts.oxg_ext_tag.reserved |[-1r, 16w] |W1 |W |[7:5] |
744 |ingress::hdr.geneve_opts.oxg_ext_tag.opt_len |[-1r, 16w] |W1 |W |[4:0] |
745 |ingress::hdr.ipv6.version |[-1r, 16w] |W14 |W |[31:28] |
746 |ingress::hdr.ipv6.traffic_class |[-1r, 16w] |W14 |W |[27:20] |
747 |ingress::hdr.ipv6.flow_label |[-1r, 16w] |W14 |W |[19:0] |
748 |ingress::hdr.ipv6.payload_len |[-1r, 16w] |H13 |H | |
749 |ingress::hdr.ipv6.next_hdr |[-1r, 16w] |MB9 |MB | |
750 |ingress::hdr.ipv6.hop_limit |[-1r, 16w] |B12 |B | |
751 |ingress::hdr.ipv6.src_addr[31:0] |[-1r, 16w] |MW2 |MW | |
752 |ingress::hdr.ipv6.src_addr[63:32] |[-1r, 16w] |MW6 |MW | |
753 |ingress::hdr.ipv6.src_addr[95:64] |[-1r, 16w] |MW10 |MW | |
754 |ingress::hdr.ipv6.src_addr[127:96] |[-1r, 16w] |MW14 |MW | |
755 |ingress::hdr.ipv6.dst_addr[95:64] |[7w, 13r] |DW8 |DW | |
756 |ingress::hdr.ipv6.dst_addr[127:96] |[7w, 13r] |DW12 |DW | |
757 |ingress::hdr.ipv6.dst_addr[31:0] |[-1r, 16w] |W2 |W | |
758 |ingress::hdr.ipv6.dst_addr[63:32] |[-1r, 16w] |W12 |W | |
759 |ingress::hdr.ipv6.dst_addr[95:64] |[-1w, 7r] |W24 |W | |
760 |ingress::hdr.ipv6.dst_addr[95:64] |[13w, 16r] |W24 |W | |
761 |ingress::hdr.ipv6.dst_addr[127:96] |[-1w, 7r] |W36 |W | |
762 |ingress::hdr.ipv6.dst_addr[127:96] |[13w, 16r] |W36 |W | |
763 |ingress::ig_intr_md_for_tm.ucast_egress_port |[-1r, 16w] |H17 |H |[8:0] |
764 |ingress::ig_intr_md_for_tm.bypass_egress |[-1r, 16w] |B1 |B |[7] |
765 |ingress::ig_intr_md_for_tm.ucast_egress_port.$valid |[-1r, 16w] |W0 |W |[1] |
766 |$tmp9 |[-1r, 16w] |B4 |B | |
767 |ingress::l3_router_Router4_fwd.nexthop[7:0] |[-1r, 16w] |W18 |W |[31:24] |
768 |ingress::l3_router_Router4_fwd.nexthop[31:8] |[5w, 12r] |W22 |W |[23:0] |
769 |ingress::l3_router_Router4_fwd.nexthop6[111:96] |[-1r, 16w] |MH10 |MH | |
770 |ingress::l3_router_Router4_fwd.nexthop6[127:112] |[-1r, 16w] |MH14 |MH | |
771 |ingress::l3_router_Router4_fwd.nexthop6[7:0] |[-1r, 16w] |W18 |W |[15:8] |
772 |ingress::l3_router_Router4_fwd.nexthop6[31:8] |[-1r, 16w] |W19 |W |[31:8] |
773 |ingress::l3_router_Router4_fwd.nexthop6[95:64] |[-1r, 16w] |W26 |W | |
774 |ingress::l3_router_Router4_fwd.nexthop6[63:32] |[-1r, 16w] |W40 |W | |
775 |ingress::l3_router_Router4_fwd.port |[6w, 12r] |H15 |H |[8:0] |
776 |ingress::l3_router_Router4_fwd.is_hit |[-1r, 16w] |MB1 |MB |[0] |
777 |ingress::l3_router_Router4_fwd.ecmp_hash |[-1r, 16w] |B5 |B | |
778 |ingress::l3_router_Router4_fwd.idx[7:0] |[-1r, 16w] |H20 |H |[7:0] |
779 |ingress::l3_router_Router4_fwd.idx[15:8] |[-1r, 16w] |H20 |H |[15:8] |
780 |ingress::l3_router_Router4_fwd.slots |[-1r, 16w] |W4 |W |[7:0] |
781 |ingress::l3_router_Router4_fwd.slot[7:0] |[-1r, 16w] |MH6 |MH |[7:0] |
782 |ingress::l3_router_Router4_fwd.slot[15:8] |[-1r, 16w] |MH6 |MH |[15:8] |
783 |$tmp10 |[-1r, 16w] |B4 |B | |
784 |ingress::l3_router_Router6_fwd.nexthop[111:96] |[-1r, 16w] |MH10 |MH | |
785 |ingress::l3_router_Router6_fwd.nexthop[127:112] |[-1r, 16w] |MH14 |MH | |
786 |ingress::l3_router_Router6_fwd.nexthop[7:0] |[-1r, 16w] |W18 |W |[23:16] |
787 |ingress::l3_router_Router6_fwd.nexthop[31:8] |[-1r, 16w] |W19 |W |[31:8] |
788 |ingress::l3_router_Router6_fwd.nexthop[95:64] |[-1r, 16w] |W28 |W | |
789 |ingress::l3_router_Router6_fwd.nexthop[63:32] |[-1r, 16w] |W40 |W | |
790 |ingress::l3_router_Router6_fwd.port |[5w, 12r] |H21 |H |[8:0] |
791 |ingress::l3_router_Router6_fwd.is_hit |[-1r, 16w] |MB2 |MB |[0] |
792 |ingress::l3_router_Router6_fwd.ecmp_hash |[-1r, 16w] |B5 |B | |
793 |ingress::l3_router_Router6_fwd.idx[7:0] |[-1r, 16w] |H20 |H |[7:0] |
794 |ingress::l3_router_Router6_fwd.idx[15:8] |[-1r, 16w] |H20 |H |[15:8] |
795 |ingress::l3_router_Router6_fwd.slots |[-1r, 16w] |MB1 |MB | |
796 |ingress::l3_router_Router6_fwd.slot[7:0] |[-1r, 16w] |MH6 |MH |[7:0] |
797 |ingress::l3_router_Router6_fwd.slot[15:8] |[-1r, 16w] |MH6 |MH |[15:8] |
798 |ingress::ig_intr_md_for_dprsr.drop_ctl |[-1r, 16w] |MB6 |MB |[2:0] |
799 |ingress::ig_intr_md_for_dprsr.mirror_type |[-1r, 16w] |MB5 |MB |[3:0] |
800 |ingress::ig_intr_md_for_dprsr.drop_ctl.$valid |[-1r, 16w] |W0 |W |[2] |
801 |ingress::ig_intr_md_for_tm.bypass_egress.$valid |[-1r, 16w] |W0 |W |[3] |
802 |ingress::hdr.udp.checksum.$deparse_original_csum |[-1r, 16w] |B1 |B |[0] |
803 |ingress::hdr.udp.checksum.$deparse_updated_csum_0 |[-1r, 16w] |B1 |B |[1] |
804 |ingress::hdr.udp.checksum.$deparse_updated_csum_1 |[-1r, 16w] |B1 |B |[2] |
805 |ingress::hdr.udp.checksum.$deparse_updated_csum_2 |[-1r, 16w] |B1 |B |[3] |
806 |ingress::hdr.udp.checksum.$deparse_updated_csum_3 |[-1r, 16w] |B1 |B |[4] |
807 |ingress::hdr.icmp.hdr_checksum.$deparse_original_csum |[-1r, 16w] |B1 |B |[5] |
808 |ingress::hdr.icmp.hdr_checksum.$deparse_updated_csum_0 |[-1r, 16w] |B1 |B |[6] |
809 |ingress::$tmp6 |[-1r, 16w] |B0 |B | |
810 |egress::eg_intr_md_for_dprsr.mirror_io_select |[-1r, 16w] |MB0 |MB |[3] |
811 |egress::eg_intr_md_for_dprsr.mirror_io_select.$valid |[-1r, 16w] |MH5 |MH |[0] |
812 |egress::eg_intr_md.egress_port |[-1r, 16w] |MH8 |MH |[8:0] |
813 |egress::eg_intr_md.egress_port.$valid |[-1r, 16w] |MH5 |MH |[1] |
814 |ingress::meta.bridge_hdr.$valid |[-1r, 16w] |W0 |W |[4] |
815 |ingress::hdr.ethernet.$valid |[-1r, 16w] |W0 |W |[5] |
816 |ingress::hdr.sidecar.$valid |[-1r, 16w] |W0 |W |[6] |
817 |ingress::hdr.vlan.$valid |[-1r, 16w] |W0 |W |[7] |
818 |ingress::hdr.ipv4.$valid |[-1r, 16w] |W0 |W |[8] |
819 |ingress::hdr.icmp.$valid |[-1r, 16w] |W0 |W |[9] |
820 |ingress::hdr.tcp.$valid |[-1r, 16w] |W0 |W |[10] |
821 |ingress::hdr.udp.$valid |[-1r, 16w] |W0 |W |[11] |
822 |ingress::hdr.geneve.$valid |[-1r, 16w] |W0 |W |[12] |
823 |ingress::hdr.inner_eth.$valid |[-1r, 16w] |W0 |W |[13] |
824 |ingress::hdr.inner_ipv4.$valid |[-1r, 16w] |W0 |W |[14] |
825 |ingress::hdr.inner_tcp.$valid |[-1r, 16w] |W0 |W |[15] |
826 |ingress::hdr.inner_udp.$valid |[-1r, 16w] |W0 |W |[16] |
827 |ingress::hdr.inner_icmp.$valid |[-1r, 16w] |W0 |W |[17] |
828 |ingress::hdr.inner_ipv6.$valid |[-1r, 16w] |W0 |W |[18] |
829 |ingress::hdr.geneve_opts.oxg_ext_tag.$valid |[-1r, 16w] |W0 |W |[19] |
830 |ingress::hdr.geneve_opts.oxg_mcast_tag.$valid |[-1r, 16w] |W0 |W |[20] |
831 |ingress::hdr.geneve_opts.oxg_mcast.$valid |[-1r, 16w] |W0 |W |[21] |
832 |ingress::hdr.geneve_opts.oxg_mss_tag.$valid |[-1r, 16w] |W0 |W |[22] |
833 |ingress::hdr.geneve_opts.oxg_mss.$valid |[-1r, 16w] |W0 |W |[23] |
834 |ingress::hdr.ipv6.$valid |[-1r, 16w] |W0 |W |[24] |
835 |ingress::hdr.arp.$valid |[-1r, 16w] |W0 |W |[25] |
836 |egress::hdr.ethernet.$valid |[-1r, 16w] |MH5 |MH |[2] |
837 |egress::hdr.vlan.$valid |[-1r, 16w] |MH5 |MH |[3] |
838 |egress::hdr.ipv4.$valid |[-1r, 16w] |MH5 |MH |[4] |
839 |egress::hdr.icmp.$valid |[-1r, 16w] |MH5 |MH |[5] |
840 |egress::hdr.udp.$valid |[-1r, 16w] |MH5 |MH |[6] |
841 |egress::hdr.geneve.$valid |[-1r, 16w] |MH5 |MH |[7] |
842 |egress::hdr.inner_eth.$valid |[-1r, 16w] |MH5 |MH |[8] |
843 |egress::hdr.inner_ipv4.$valid |[-1r, 16w] |MH5 |MH |[9] |
844 |egress::hdr.inner_tcp.$valid |[-1r, 16w] |MH5 |MH |[10] |
845 |egress::hdr.inner_udp.$valid |[-1r, 16w] |MH5 |MH |[11] |
846 |egress::hdr.inner_ipv6.$valid |[-1r, 16w] |MH5 |MH |[12] |
847 |egress::hdr.geneve_opts.oxg_ext_tag.$valid |[-1r, 16w] |MH5 |MH |[13] |
848 |egress::hdr.geneve_opts.oxg_mcast_tag.$valid |[-1r, 16w] |MH5 |MH |[14] |
849 |egress::hdr.geneve_opts.oxg_mcast.$valid |[-1r, 16w] |MH5 |MH |[15] |
850 |egress::hdr.geneve_opts.oxg_mss_tag.$valid |[-1r, 16w] |MB0 |MB |[0] |
851 |egress::hdr.geneve_opts.oxg_mss.$valid |[-1r, 16w] |MB0 |MB |[1] |
852 |egress::hdr.ipv6.$valid |[-1r, 16w] |MB0 |MB |[2] |
853 +--------------------------------------------------------+------------+-----------+----------------+-----------------+
854 
855 
856 
857 
858 
859 PHV Allocation State
860 
861 MAU Groups:
862 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
863 | Container Set | Containers Used | Bits Used | Bits Used on Ingress | Bits Used on Egress | Bits Allocated | Bits Allocated on Ingress | Bits Allocated on Egress | Available Bits |
864 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
865 | B0-11 | 4 ( 33.3 %) | 32 ( 33.3 %) | 32 ( 33.3 %) | 0 ( 0 %) | 48 ( 50 %) | 48 ( 50 %) | 0 ( 0 %) | 96 |
866 | MB0-3 | 3 ( 75 %) | 13 ( 40.6 %) | 9 ( 28.1 %) | 4 ( 12.5 %) | 14 ( 43.8 %) | 10 ( 31.2 %) | 4 ( 12.5 %) | 32 |
867 | DB0-3 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 |
868 | | | | | | | | | |
869 | Usage for Group 1 | 7 ( 35 %) | 45 ( 28.1 %) | 41 ( 25.6 %) | 4 ( 2.5 %) | 62 ( 38.8 %) | 58 ( 36.2 %) | 4 ( 2.5 %) | 160 |
870 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
871 | B12-23 | 1 ( 8.33 %) | 8 ( 8.33 %) | 8 ( 8.33 %) | 0 ( 0 %) | 16 ( 16.7 %) | 16 ( 16.7 %) | 0 ( 0 %) | 96 |
872 | MB4-7 | 3 ( 75 %) | 15 ( 46.9 %) | 15 ( 46.9 %) | 0 ( 0 %) | 23 ( 71.9 %) | 23 ( 71.9 %) | 0 ( 0 %) | 32 |
873 | DB4-7 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 |
874 | | | | | | | | | |
875 | Usage for Group 2 | 4 ( 20 %) | 23 ( 14.4 %) | 23 ( 14.4 %) | 0 ( 0 %) | 39 ( 24.4 %) | 39 ( 24.4 %) | 0 ( 0 %) | 160 |
876 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
877 | B24-35 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 96 |
878 | MB8-11 | 2 ( 50 %) | 16 ( 50 %) | 16 ( 50 %) | 0 ( 0 %) | 32 ( 100 %) | 32 ( 100 %) | 0 ( 0 %) | 32 |
879 | DB8-11 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 |
880 | | | | | | | | | |
881 | Usage for Group 3 | 2 ( 10 %) | 16 ( 10 %) | 16 ( 10 %) | 0 ( 0 %) | 32 ( 20 %) | 32 ( 20 %) | 0 ( 0 %) | 160 |
882 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
883 | B36-47 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 96 |
884 | MB12-15 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 |
885 | DB12-15 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 |
886 | | | | | | | | | |
887 | Usage for Group 4 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 160 |
888 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
889 | H0-11 | 4 ( 33.3 %) | 64 ( 33.3 %) | 64 ( 33.3 %) | 0 ( 0 %) | 64 ( 33.3 %) | 64 ( 33.3 %) | 0 ( 0 %) | 192 |
890 | MH0-3 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 |
891 | DH0-3 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 64 |
892 | | | | | | | | | |
893 | Usage for Group 5 | 8 ( 40 %) | 128 ( 40 %) | 128 ( 40 %) | 0 ( 0 %) | 128 ( 40 %) | 128 ( 40 %) | 0 ( 0 %) | 320 |
894 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
895 | H12-23 | 12 ( 100 %) | 186 ( 96.9 %) | 186 ( 96.9 %) | 0 ( 0 %) | 300 ( 156 %) | 300 ( 156 %) | 0 ( 0 %) | 192 |
896 | MH4-7 | 4 ( 100 %) | 42 ( 65.6 %) | 26 ( 40.6 %) | 16 ( 25 %) | 58 ( 90.6 %) | 42 ( 65.6 %) | 16 ( 25 %) | 64 |
897 | DH4-7 | 2 ( 50 %) | 32 ( 50 %) | 32 ( 50 %) | 0 ( 0 %) | 32 ( 50 %) | 32 ( 50 %) | 0 ( 0 %) | 64 |
898 | | | | | | | | | |
899 | Usage for Group 6 | 18 ( 90 %) | 260 ( 81.2 %) | 244 ( 76.2 %) | 16 ( 5 %) | 390 ( 122 %) | 374 ( 117 %) | 16 ( 5 %) | 320 |
900 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
901 | H24-35 | 3 ( 25 %) | 48 ( 25 %) | 48 ( 25 %) | 0 ( 0 %) | 80 ( 41.7 %) | 80 ( 41.7 %) | 0 ( 0 %) | 192 |
902 | MH8-11 | 4 ( 100 %) | 57 ( 89.1 %) | 48 ( 75 %) | 9 ( 14.1 %) | 73 ( 114 %) | 64 ( 100 %) | 9 ( 14.1 %) | 64 |
903 | DH8-11 | 1 ( 25 %) | 16 ( 25 %) | 16 ( 25 %) | 0 ( 0 %) | 16 ( 25 %) | 16 ( 25 %) | 0 ( 0 %) | 64 |
904 | | | | | | | | | |
905 | Usage for Group 7 | 8 ( 40 %) | 121 ( 37.8 %) | 112 ( 35 %) | 9 ( 2.81 %) | 169 ( 52.8 %) | 160 ( 50 %) | 9 ( 2.81 %) | 320 |
906 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
907 | H36-47 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 192 |
908 | MH12-15 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 80 ( 125 %) | 80 ( 125 %) | 0 ( 0 %) | 64 |
909 | DH12-15 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 64 |
910 | | | | | | | | | |
911 | Usage for Group 8 | 4 ( 20 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 80 ( 25 %) | 80 ( 25 %) | 0 ( 0 %) | 320 |
912 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
913 | H48-59 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 192 |
914 | MH16-19 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 |
915 | DH16-19 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 64 |
916 | | | | | | | | | |
917 | Usage for Group 9 | 4 ( 20 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 320 |
918 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
919 | H60-71 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 192 |
920 | MH20-23 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 96 ( 150 %) | 96 ( 150 %) | 0 ( 0 %) | 64 |
921 | DH20-23 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 64 |
922 | | | | | | | | | |
923 | Usage for Group 10 | 4 ( 20 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 96 ( 30 %) | 96 ( 30 %) | 0 ( 0 %) | 320 |
924 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
925 | W0-11 | 11 ( 91.7 %) | 336 ( 87.5 %) | 336 ( 87.5 %) | 0 ( 0 %) | 568 ( 148 %) | 568 ( 148 %) | 0 ( 0 %) | 384 |
926 | MW0-3 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 224 ( 175 %) | 224 ( 175 %) | 0 ( 0 %) | 128 |
927 | DW0-3 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 128 |
928 | | | | | | | | | |
929 | Usage for Group 11 | 15 ( 75 %) | 464 ( 72.5 %) | 464 ( 72.5 %) | 0 ( 0 %) | 792 ( 124 %) | 792 ( 124 %) | 0 ( 0 %) | 640 |
930 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
931 | W12-23 | 12 ( 100 %) | 384 ( 100 %) | 384 ( 100 %) | 0 ( 0 %) | 654 ( 170 %) | 654 ( 170 %) | 0 ( 0 %) | 384 |
932 | MW4-7 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 |
933 | DW4-7 | 2 ( 50 %) | 64 ( 50 %) | 64 ( 50 %) | 0 ( 0 %) | 64 ( 50 %) | 64 ( 50 %) | 0 ( 0 %) | 128 |
934 | | | | | | | | | |
935 | Usage for Group 12 | 18 ( 90 %) | 576 ( 90 %) | 576 ( 90 %) | 0 ( 0 %) | 846 ( 132 %) | 846 ( 132 %) | 0 ( 0 %) | 640 |
936 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
937 | W24-35 | 5 ( 41.7 %) | 160 ( 41.7 %) | 160 ( 41.7 %) | 0 ( 0 %) | 288 ( 75 %) | 288 ( 75 %) | 0 ( 0 %) | 384 |
938 | MW8-11 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 |
939 | DW8-11 | 1 ( 25 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 128 |
940 | | | | | | | | | |
941 | Usage for Group 13 | 10 ( 50 %) | 320 ( 50 %) | 320 ( 50 %) | 0 ( 0 %) | 448 ( 70 %) | 448 ( 70 %) | 0 ( 0 %) | 640 |
942 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
943 | W36-47 | 4 ( 33.3 %) | 128 ( 33.3 %) | 128 ( 33.3 %) | 0 ( 0 %) | 256 ( 66.7 %) | 256 ( 66.7 %) | 0 ( 0 %) | 384 |
944 | MW12-15 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 |
945 | DW12-15 | 1 ( 25 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 128 |
946 | | | | | | | | | |
947 | Usage for Group 14 | 9 ( 45 %) | 288 ( 45 %) | 288 ( 45 %) | 0 ( 0 %) | 416 ( 65 %) | 416 ( 65 %) | 0 ( 0 %) | 640 |
948 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
949 | Usage for 8b | 13 ( 16.2 %) | 84 ( 13.1 %) | 80 ( 12.5 %) | 4 ( 0.625%) | 133 ( 20.8 %) | 129 ( 20.2 %) | 4 ( 0.625%) | 640 |
950 | Usage for 16b | 46 ( 38.3 %) | 701 ( 36.5 %) | 676 ( 35.2 %) | 25 ( 1.3 %) | 927 ( 48.3 %) | 902 ( 47 %) | 25 ( 1.3 %) | 1920 |
951 | Usage for 32b | 52 ( 65 %) | 1648 ( 64.4 %) | 1648 ( 64.4 %) | 0 ( 0 %) | 2502 ( 97.7 %) | 2502 ( 97.7 %) | 0 ( 0 %) | 2560 |
952 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
953 | Usage for dark | 7 ( 12.5 %) | 176 ( 17.2 %) | 176 ( 17.2 %) | 0 ( 0 %) | 176 ( 17.2 %) | 176 ( 17.2 %) | 0 ( 0 %) | 1024 |
954 | Usage for mocha | 48 ( 85.7 %) | 911 ( 89 %) | 882 ( 86.1 %) | 29 ( 2.83 %) | 1112 ( 109 %) | 1083 ( 106 %) | 29 ( 2.83 %) | 1024 |
955 | Usage for normal | 56 ( 33.3 %) | 1346 ( 43.8 %) | 1346 ( 43.8 %) | 0 ( 0 %) | 2274 ( 74 %) | 2274 ( 74 %) | 0 ( 0 %) | 3072 |
956 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
957 | Overall PHV Usage | 111 ( 39.6 %) | 2433 ( 47.5 %) | 2404 ( 47 %) | 29 ( 0.566%) | 3562 ( 69.6 %) | 3533 ( 69 %) | 29 ( 0.566%) | 5120 |
958 +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+
959 
960 
961 
962