March 2, 2026 at 06:51:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1006 0 285 3835 138 5428 46 347 1225 18 7902 10 8 0 82 1 766 0 52 1048 21 2908 16 347 1266 43 6250 4 4 0 91 2 859 0 148 874 18 2396 12 306 1171 23 5369 2 4 0 94 3 767 0 645 1112 419 2279 16 257 1133 40 4362 2 5 0 93 4 935 0 509 887 17 3874 17 371 1099 11 8491 3 5 0 91 5 815 0 46 2567 1618 3220 14 222 1236 26 6982 2 8 0 90 6 998 0 118 1135 15 3490 16 338 1259 36 10531 7 6 0 87 7 1289 0 42 1587 34 4181 19 383 1272 27 4957 3 6 0 91 March 2, 2026 at 06:51:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6062 0 337 2581 101 333 13 68 294 24 5035 6 32 0 62 1 6204 0 59 466 48 424 18 89 431 41 5578 18 8 0 75 2 8318 0 378 420 5 439 6 92 250 49 5013 6 7 0 88 3 7295 0 68 517 108 554 23 99 480 25 4575 21 11 0 67 4 4788 0 296 351 9 455 18 96 473 36 2958 17 4 0 79 5 4650 0 15 312 14 397 12 76 148 35 2904 2 3 0 94 6 7827 0 23 298 0 421 16 87 240 46 5238 16 5 0 79 7 1025 0 35 258 3 386 2 81 92 34 1200 0 1 0 98 March 2, 2026 at 06:51:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 0 2518 101 1018 10 196 1598 0 318 0 13 0 87 1 0 0 11 728 109 1208 7 233 1882 1 552 0 10 0 90 2 0 0 0 271 1 525 8 129 2228 3 300 0 14 0 86 3 31 0 129 1483 982 1381 6 278 1563 13 1330 0 11 0 89 4 0 0 7 295 1 572 10 165 1633 0 0 0 14 0 86 5 0 0 0 290 0 575 7 126 1921 1 0 0 12 0 88 6 0 0 0 589 1 1489 5 256 1598 2 0 0 9 0 91 7 0 0 0 275 4 567 8 138 1676 6 0 0 14 0 86 March 2, 2026 at 06:51:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2115 102 114 2 1 0 0 309 0 1 0 99 1 0 0 11 219 104 12 0 0 0 0 553 0 0 0 100 2 0 0 2 12 1 8 0 0 0 0 308 0 0 0 100 3 26 0 23 313 154 138 0 1 0 0 1312 0 0 0 99 4 0 0 0 20 1 12 0 0 0 0 0 0 0 0 100 5 0 0 7 16 6 4 0 2 1 0 0 0 0 0 100 6 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 24 4 22 0 0 0 0 10 0 0 0 100 March 2, 2026 at 06:51:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 108 0 2 0 0 305 0 0 0 99 1 0 0 10 216 104 10 0 0 3 0 551 0 0 0 100 2 0 0 0 12 2 10 0 1 1 0 300 0 0 0 100 3 0 0 17 312 155 138 0 0 1 0 1313 0 0 0 100 4 0 0 0 16 2 8 0 0 1 0 0 0 0 0 100 5 0 0 0 11 1 4 0 0 1 0 0 0 0 0 100 6 0 0 0 11 2 6 0 1 1 0 0 0 0 0 100 7 7 0 0 14 4 4 0 0 1 0 4 0 0 0 100 March 2, 2026 at 06:51:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 102 104 0 0 0 0 300 0 1 0 99 1 0 0 11 214 104 8 0 0 0 0 553 0 0 0 100 2 0 0 0 10 1 6 0 1 0 0 300 0 0 0 100 3 0 0 16 316 154 146 0 1 1 0 1306 0 0 0 100 4 0 0 0 16 1 10 0 0 0 0 0 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 13 3 8 0 0 0 0 3 0 0 0 100 March 2, 2026 at 06:51:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 51998 0 0 2806 105 4760 661 1544 6806 314 28935 13 22 0 66 1 9936 0 10 916 105 4854 724 1572 8781 304 27410 10 16 0 74 2 16878 0 8 826 2 6783 880 1764 3844 375 35979 10 18 0 72 3 12513 0 412 975 107 6149 866 1907 4020 356 34683 10 17 0 74 4 12220 0 6 871 37 5534 793 1816 4590 322 31219 10 16 0 74 5 10065 0 1 728 9 5645 681 1518 8501 315 29620 10 15 0 75 6 12114 0 8 752 5 5870 817 1765 4522 289 33185 9 16 0 74 7 8723 0 1 690 5 4948 562 1343 7185 264 26687 11 15 0 74 March 2, 2026 at 06:51:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3412 0 0 4270 118 18659 2580 4555 17974 11 103988 43 55 0 2 1 3484 0 10 2758 112 19612 2779 5355 17945 10 115682 40 57 0 3 2 3083 0 2817 1949 19 16635 2304 4567 15182 8 100504 41 56 0 3 3 2835 0 1410 2924 734 16921 2234 4841 22006 32 105052 38 58 0 3 4 3690 0 7 2563 21 20589 2818 5665 19461 15 119302 37 59 0 3 5 3264 0 0 2212 17 18609 2093 5053 24357 16 110032 39 58 0 3 6 2582 0 7 2145 20 17932 2500 4613 22492 21 106915 43 55 0 2 7 3175 0 0 2391 14 18253 2492 5003 20586 16 107119 41 55 0 3 March 2, 2026 at 06:51:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37 0 0 5227 119 21079 3376 4875 12729 23 113237 38 59 0 3 1 2 0 2 3175 113 17861 3066 4317 15187 6 93718 40 57 0 3 2 1 0 5591 2067 10 18297 3025 4321 14413 9 101759 37 60 0 3 3 1 0 1400 3487 814 19072 3032 4345 13243 13 103757 42 55 0 3 4 7 0 0 2897 13 17191 2828 4054 14073 4 94374 42 55 0 3 5 8 0 14 2730 18 16081 2566 3794 14334 5 92382 41 57 0 3 6 1 0 17 3016 23 18968 3190 4285 14896 12 102365 37 59 0 4 7 2 0 4 3076 22 18964 3023 4581 11646 4 107381 38 58 0 4 March 2, 2026 at 06:51:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 0 3912 113 20762 3232 5108 8425 1 118212 41 57 0 2 1 0 0 3 2078 113 18536 2789 4874 9152 0 112434 42 56 0 2 2 0 0 0 2008 13 20717 3118 5182 9021 2 122502 41 57 0 2 3 0 0 1418 2451 860 17837 2829 4306 9993 2 103727 42 56 0 2 4 0 0 133 1882 17 20073 3055 4922 8621 3 118260 43 55 0 2 5 0 0 21 1991 21 21685 3371 5376 9795 3 126583 41 57 0 2 6 1 0 0 2074 23 20359 3185 4892 8614 2 117030 47 50 0 2 7 0 0 0 1976 22 18697 2744 4553 7529 1 106642 46 51 0 3 March 2, 2026 at 06:51:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 4140 119 24353 3595 4807 9839 0 117617 41 57 0 2 1 1 0 3 1956 114 19956 3024 4016 10484 0 106883 43 56 0 2 2 0 0 8 1906 19 20852 3052 4147 8092 0 103646 44 54 0 2 3 0 0 1416 2694 862 20810 3333 4333 8512 4 108561 42 56 0 2 4 0 0 0 1837 22 19297 3072 4151 9776 4 105706 44 54 0 2 5 0 0 172 1864 11 20443 3093 4284 8857 5 110128 42 56 0 2 6 0 0 0 2053 29 21097 3383 4618 9003 6 113568 41 57 0 2 7 0 0 14 2165 25 23249 3522 4845 9547 0 117565 43 55 0 2 March 2, 2026 at 06:51:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 4314 116 24199 3560 4971 8588 24 117589 38 59 0 2 1 0 0 844 2024 122 21162 3036 4135 9803 23 102169 40 58 0 2 2 0 0 0 1973 23 19272 2855 3876 9177 24 97661 44 54 0 2 3 0 0 1424 2602 833 17498 2677 3762 8416 19 92324 41 58 0 2 4 33 0 7 2030 28 20741 3219 4421 10626 25 111910 41 57 0 2 5 0 0 7 1962 12 21805 3013 4426 8242 54 112484 42 55 0 2 6 0 0 0 1952 28 19406 2762 4163 9244 41 102797 41 57 0 2 7 0 0 0 1893 19 18967 2771 4248 8280 40 97269 39 58 0 2 March 2, 2026 at 06:51:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 3863 117 20345 2910 4291 9621 23 105271 41 57 0 2 1 0 0 3 1909 114 17096 2776 3801 7751 3 95611 47 52 0 2 2 0 0 0 1820 17 18869 2794 3969 8875 38 98586 45 53 0 2 3 1 0 1416 2603 833 19631 2962 4321 9365 4 103314 43 54 0 2 4 0 0 0 2336 18 26872 3956 5541 9169 20 133963 41 56 0 3 5 0 0 0 1973 18 21044 3044 4714 8582 13 109053 43 55 0 2 6 0 0 7 1972 37 21817 3199 4802 9049 20 113420 42 56 0 2 7 0 0 14 2006 11 24230 3150 4970 10210 4 122754 40 58 0 3 March 2, 2026 at 06:51:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 3877 126 23194 3207 4816 8998 9 121983 41 57 0 2 1 0 0 3 1853 113 19488 2469 4234 7767 10 101216 44 55 0 2 2 0 0 0 1879 13 21672 3262 4648 8644 5 114107 41 57 0 2 3 0 0 1417 2381 812 20610 2928 4463 7832 7 108596 42 56 0 2 4 0 0 0 1839 21 21273 2987 4557 7537 8 111716 44 54 0 2 5 0 0 0 2063 24 24106 3428 4986 8387 2 121230 43 55 0 2 6 0 0 0 1744 25 19226 2844 3872 7884 8 96250 46 52 0 2 7 0 0 7 1713 20 22429 3100 4522 8020 4 111459 44 54 0 2 March 2, 2026 at 06:51:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 4020 123 18997 3145 4238 9501 3 106260 41 56 0 2 1 1 0 3 2285 122 19649 3195 4943 8871 15 111963 39 59 0 3 2 0 0 0 1876 13 17744 2826 4273 9558 9 101462 39 59 0 2 3 0 0 1416 2751 913 19155 3201 4453 9316 4 100107 42 56 0 2 4 0 0 7 2221 26 20361 3155 4739 9113 16 106809 41 56 0 3 5 0 0 0 2051 24 19901 3161 4672 10331 23 107630 40 58 0 2 6 0 0 0 1927 20 19236 3150 4578 9148 4 102228 41 56 0 3 7 0 0 0 1761 16 17550 2867 4255 9973 19 98371 41 58 0 2 March 2, 2026 at 06:51:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 4062 113 21186 3315 4530 8814 2 112805 44 54 0 2 1 0 0 16 1851 113 18615 2622 4058 8368 1 104179 44 55 0 1 2 0 0 0 1696 13 20095 2818 4177 8392 12 103313 44 54 0 2 3 0 0 1418 2376 819 18400 2906 4075 8851 6 99336 44 54 0 2 4 0 0 7 1967 29 21163 3140 4964 8610 4 116649 40 58 0 2 5 0 0 0 1933 23 21046 3111 4761 9460 1 114778 41 57 0 2 6 0 0 0 1956 28 22452 3277 4885 7810 3 119697 43 55 0 2 7 0 0 0 1983 14 21368 3064 4750 9022 1 113353 40 57 0 3 March 2, 2026 at 06:51:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 4033 124 21775 3074 4489 8449 1 109719 39 57 0 5 1 0 0 3 2163 111 22003 3167 4574 7196 1 109320 39 59 0 2 2 0 0 43 1852 15 22477 3004 4553 8879 1 112305 39 58 0 2 3 0 0 1565 2511 916 20710 3050 4149 7850 1 105784 42 54 0 4 4 0 0 0 1848 16 17793 2531 3751 8905 1 92751 44 54 0 2 5 0 0 49 1932 24 21049 3066 4138 8090 4 108152 43 54 0 2 6 1 0 0 1953 27 21496 3305 4244 9658 1 110417 42 56 0 2 7 0 0 0 1861 16 19867 2964 4241 8931 0 100862 41 56 0 3 March 2, 2026 at 06:51:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 4154 129 21811 3437 4571 7743 1 112290 41 57 0 3 1 0 0 3 2060 119 20160 3125 4570 8229 0 108633 40 58 0 2 2 33 0 0 1955 17 20237 3084 4459 8295 0 112463 41 57 0 2 3 1 0 1417 2471 740 18357 2877 4241 7402 0 100693 43 55 0 2 4 33 0 0 1949 23 19658 3280 4450 8455 2 109972 42 56 0 2 5 0 0 7 1738 14 20692 2999 4471 8106 1 111470 40 58 0 2 6 0 0 0 1862 31 21497 3303 4414 8187 0 113031 44 54 0 2 7 0 0 0 1853 16 17486 2857 4178 7851 0 100766 42 56 0 2 March 2, 2026 at 06:51:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 3976 127 22475 3244 4748 8014 2 115167 40 58 0 2 1 0 0 3 1987 128 22447 3101 4481 9168 9 117024 43 55 0 1 2 0 0 0 1853 12 18443 3002 4312 7847 7 106734 44 54 0 2 3 0 0 1417 2467 704 21533 3350 4576 8285 1 118002 42 56 0 2 4 0 0 0 1750 27 20759 2993 4643 7441 16 113755 43 56 0 2 5 0 0 0 1653 19 21246 2857 4243 8374 2 111123 47 52 0 1 6 0 0 0 1808 28 22108 2965 4457 7648 27 113146 43 55 0 2 7 0 0 8 1739 21 18833 2914 3959 8882 6 102813 45 53 0 2 March 2, 2026 at 06:51:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 3928 116 18701 2753 4123 9842 26 100249 41 57 0 2 1 2 0 17 1966 112 19538 2952 4229 9919 9 107846 41 57 0 1 2 0 0 0 1666 17 19022 2711 4233 9309 6 104681 39 60 0 1 3 0 0 1417 2281 693 17546 2390 3706 8181 2 97028 42 56 0 2 4 0 0 7 1798 22 19338 2869 4100 9164 42 105831 41 57 0 2 5 0 0 0 1773 16 20223 2846 4401 8742 13 107831 41 57 0 2 6 0 0 0 1760 30 19721 2481 4445 9006 24 103854 41 57 0 2 7 0 0 0 1858 20 19217 2995 4085 7896 7 109706 44 54 0 2 March 2, 2026 at 06:51:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 0 2940 116 3017 224 708 3824 0 9983 9 14 0 77 1 1 0 5 1247 109 4437 241 853 4317 0 13621 9 12 0 79 2 0 0 7 939 28 2950 139 591 4125 0 8629 7 12 0 80 3 5 0 269 1517 620 4278 258 831 4115 0 13934 7 14 0 80 4 1 0 0 973 10 4827 228 756 4196 0 12519 8 13 0 79 5 0 0 1 825 4 2501 139 490 4110 0 6342 8 12 0 79 6 6 0 10 902 9 3241 199 641 4500 0 10787 6 13 0 81 7 5 0 0 697 7 2881 172 562 4050 0 9824 10 11 0 79 March 2, 2026 at 06:51:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2155 150 202 0 0 2 0 3 0 1 0 99 1 0 0 4 215 103 8 0 1 0 0 2 0 0 0 100 2 0 0 7 9 2 4 1 0 0 0 559 0 0 0 100 3 0 0 2 211 101 4 0 0 0 0 3 0 0 0 100 4 0 0 0 11 3 6 0 1 0 0 3 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 14 36 11 64 1 1 1 0 1795 0 0 0 99 7 0 0 0 16 3 12 1 1 0 0 308 0 0 0 100 March 2, 2026 at 06:51:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2156 150 204 0 1 0 0 0 0 0 0 100 1 0 0 4 218 102 14 0 0 0 0 0 0 0 0 100 2 0 0 7 9 2 4 1 0 0 0 559 0 0 0 100 3 0 0 2 210 101 4 0 1 0 0 0 0 0 0 100 4 0 0 0 12 4 6 0 0 0 0 1 0 0 0 100 5 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 6 0 0 14 34 10 60 1 0 0 0 1783 0 0 0 99 7 0 0 0 12 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:51:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2162 150 214 1 2 0 0 18 0 1 0 99 1 0 0 3 215 102 10 0 2 1 0 1 0 0 0 100 2 0 0 7 13 2 14 0 1 0 0 558 0 0 0 100 3 0 0 3 208 101 2 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 13 7 0 0 0 0 0 0 0 0 0 100 6 0 0 14 33 11 58 1 0 1 0 1784 0 1 0 99 7 0 0 0 23 5 25 0 3 0 0 326 0 0 0 100 March 2, 2026 at 06:51:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 126 0 10 4029 122 3508 55 295 322 6 9781 18 8 0 73 1 41029 0 3 2064 106 3490 69 309 503 3 9633 19 13 0 69 2 1459 0 20 1663 4 3137 56 234 417 7 9898 19 14 0 68 3 1165 0 913 1842 103 3460 50 258 361 12 10238 18 8 0 74 4 103 0 11 1527 13 2920 42 231 323 14 8187 17 7 0 76 5 95 0 0 1438 5 2701 31 199 432 7 7327 15 6 0 79 6 35 0 14 1516 19 3004 50 231 385 7 9909 15 7 0 78 7 98 0 0 1334 7 2457 34 143 300 4 7972 18 6 0 76 March 2, 2026 at 06:51:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 5278 104 6204 236 781 3114 3 15563 28 21 0 51 1 4 0 4 3370 108 5971 222 792 2926 4 14759 26 19 0 55 2 22 0 7 2837 10 5369 238 646 2992 2 13613 23 17 0 59 3 8 0 1423 3112 482 5793 227 762 3295 4 13856 23 19 0 58 4 15 0 47 2636 9 5136 141 638 3173 5 11784 24 18 0 59 5 5 0 0 2306 11 4527 204 521 3270 4 11553 25 16 0 59 6 15 0 14 2557 17 5175 190 663 3190 0 13634 24 17 0 60 7 9 0 0 2006 16 4109 230 516 3541 6 10533 20 16 0 64 March 2, 2026 at 06:51:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 5120 121 5901 351 866 3189 2 15138 33 18 0 50 1 5 0 4 3241 107 5876 244 874 3344 6 14397 28 18 0 54 2 3 0 0 2577 19 4899 214 752 3068 6 13038 29 16 0 55 3 11 0 1410 3125 616 5380 221 798 3533 0 13003 23 17 0 60 4 9 0 14 2501 8 4719 186 684 3157 1 12017 26 16 0 58 5 5 0 0 2270 10 4433 143 619 3519 4 10626 21 15 0 64 6 13 0 0 2517 11 5084 200 694 3276 5 12815 22 15 0 63 7 6 0 14 2228 8 4416 127 580 3242 1 11144 20 15 0 66 March 2, 2026 at 06:51:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 5255 106 6096 251 882 2767 7 14332 23 18 0 59 1 17 0 3 3180 105 5747 240 833 2489 6 13710 27 17 0 56 2 1 0 0 2762 3 5314 211 693 2621 4 13558 26 17 0 57 3 6 0 1423 3202 610 5578 259 757 2628 3 13746 26 16 0 58 4 8 0 7 2610 20 5116 233 711 2819 4 12912 26 15 0 60 5 5 0 0 2235 9 4276 149 577 2755 6 9949 23 14 0 63 6 4 0 14 2505 8 5060 190 670 2727 1 12356 28 16 0 56 7 1 0 0 2067 13 4013 121 538 2658 4 10485 21 13 0 66 March 2, 2026 at 06:51:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 0 5187 110 5989 338 910 3437 5 14627 28 20 0 52 1 13 0 4 3381 110 6116 305 921 3298 3 13410 25 18 0 56 2 8 0 0 2889 6 5519 213 799 3437 2 12210 23 20 0 58 3 8 0 1402 3274 666 5827 282 862 3497 5 13191 27 19 0 54 4 13 0 7 2595 11 5081 220 773 3483 4 11888 28 18 0 54 5 6 0 0 2397 17 4706 178 667 3542 3 10672 22 18 0 60 6 6 0 14 2416 13 4972 239 777 3727 5 11003 25 17 0 58 7 4 0 0 2095 6 4175 188 641 3413 5 8867 20 16 0 64 March 2, 2026 at 06:51:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 5309 107 6219 336 990 3108 2 16296 32 19 0 49 1 14 0 17 3391 109 6206 269 966 3034 4 15203 27 18 0 55 2 0 0 0 2897 9 5585 300 848 3462 1 13789 27 17 0 56 3 6 0 1403 3469 680 6132 291 902 3138 2 13581 25 17 0 58 4 3 0 7 2751 8 5326 203 797 3261 7 12270 24 17 0 59 5 3 0 125 2371 17 4525 144 641 3132 2 9796 22 16 0 62 6 6 0 0 2643 14 5363 223 784 3278 4 11440 24 16 0 60 7 2 0 0 2245 9 4452 151 636 3206 1 9417 16 14 0 70 March 2, 2026 at 06:51:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 5239 107 6017 259 847 2617 3 15105 25 18 0 57 1 4 0 17 3202 121 5716 263 847 2714 6 14574 26 17 0 57 2 7 0 0 2827 11 5399 267 712 2595 5 14092 27 16 0 56 3 3 0 1401 3252 605 5665 231 802 2778 6 13588 27 17 0 56 4 7 0 7 2664 13 5047 168 663 2816 4 12079 26 16 0 58 5 3 0 0 2471 5 4768 162 582 2785 3 11338 21 15 0 64 6 4 0 0 2500 8 4927 175 662 2555 9 11590 23 15 0 61 7 3 0 114 2106 13 4242 230 521 2679 8 10833 24 13 0 63 March 2, 2026 at 06:51:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 0 5096 106 5722 237 815 3193 4 15346 28 22 0 49 1 1 0 18 3276 130 5832 240 800 3315 3 14928 24 20 0 56 2 0 0 0 2809 10 5349 202 719 3508 4 13864 25 20 0 55 3 7 0 1417 3288 569 5800 207 732 3345 5 14194 26 21 0 53 4 4 0 7 2739 10 5525 256 694 3157 6 14606 26 17 0 57 5 2 0 0 2455 7 4913 144 625 3187 5 10495 15 17 0 68 6 6 0 17 2546 5 5257 224 633 3435 4 11997 24 17 0 59 7 2 0 0 2026 7 4008 195 529 3001 6 10115 24 14 0 61 March 2, 2026 at 06:51:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 5248 105 6244 303 855 3085 3 15013 26 18 0 56 1 5 0 2 3262 111 5930 244 849 3206 4 14559 25 18 0 57 2 3 0 0 2873 10 5406 173 708 3264 3 12714 20 16 0 64 3 6 0 1403 3154 574 5622 243 774 3240 4 13826 29 19 0 53 4 3 0 14 2566 18 4908 194 668 3239 2 12487 28 15 0 57 5 1 0 7 2218 7 4179 127 514 3052 4 12101 26 16 0 58 6 6 0 0 2567 18 5137 204 658 3163 2 11571 23 16 0 61 7 0 0 0 1923 6 3662 107 489 3315 1 8914 21 15 0 65 March 2, 2026 at 06:51:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 1 5052 106 5640 251 744 2305 9 14361 27 18 0 55 1 5 0 3 3193 109 5772 228 752 2277 3 13743 24 17 0 60 2 3 0 0 2645 10 4845 168 572 2333 1 12178 26 16 0 58 3 2 0 1403 3111 463 5603 205 691 2485 1 12572 21 16 0 62 4 2 0 0 2390 8 4579 164 574 2559 9 11996 28 16 0 56 5 3 0 14 2342 23 4529 184 515 2437 2 11893 20 13 0 67 6 12 0 10 2418 15 4751 143 580 2500 7 12025 27 15 0 58 7 4 0 0 2091 8 4186 153 491 2424 7 11616 25 14 0 61 March 2, 2026 at 06:51:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 0 5077 105 5821 272 860 3877 1 14732 27 21 0 52 1 4 0 3 3147 111 5852 268 794 3629 4 14392 27 20 0 53 2 4 0 0 2670 7 4943 200 672 3766 1 12936 26 19 0 56 3 5 0 1417 3007 531 5331 238 735 3656 3 12987 26 19 0 55 4 0 0 0 2476 12 4923 211 634 4008 2 11340 26 18 0 56 5 3 0 14 2182 13 4210 125 547 3944 5 11558 21 19 0 60 6 2 0 0 2411 16 4872 171 642 3927 3 11636 23 19 0 59 7 2 0 7 2137 15 4149 140 537 3723 3 10124 18 17 0 65 March 2, 2026 at 06:51:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 5185 107 5965 274 827 2905 3 15243 27 18 0 55 1 4 0 3 3298 108 5862 248 850 2920 2 14310 29 18 0 54 2 3 0 0 2786 15 5354 249 696 2685 5 13454 24 15 0 61 3 5 0 1418 3110 559 5557 203 747 2932 5 13590 25 18 0 57 4 3 0 0 2496 11 4773 148 692 3049 2 11420 20 16 0 64 5 3 0 0 2320 6 4482 155 570 2769 3 11545 27 15 0 58 6 1 0 14 2451 17 5010 203 676 3033 3 13140 24 14 0 62 7 2 0 7 2282 7 4606 141 536 2831 6 11050 22 14 0 64 March 2, 2026 at 06:51:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 4936 110 5424 240 644 2758 2 14868 27 19 0 54 1 1 0 3 3169 115 5655 208 675 2716 1 13759 21 19 0 60 2 2 0 0 2561 8 4740 184 525 2705 5 13207 31 18 0 51 3 0 0 1416 2726 393 4935 243 607 2714 2 13098 28 18 0 54 4 2 0 0 2389 13 4518 151 581 2841 4 10933 25 17 0 58 5 1 0 0 2122 10 4032 131 406 2910 2 10174 22 15 0 62 6 3 0 7 2348 15 4711 197 509 2940 3 13620 28 16 0 55 7 3 0 14 2014 14 3870 97 417 2553 2 9265 16 15 0 69 March 2, 2026 at 06:51:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 14 5112 108 5701 253 804 3444 3 15420 29 20 0 52 1 0 0 3 3282 111 6187 314 884 3269 3 14940 26 17 0 57 2 0 0 54 2883 9 5539 257 724 3516 6 13824 27 18 0 55 3 1 0 1417 3135 553 5377 217 760 3149 4 12894 24 18 0 58 4 3 0 0 2588 8 5285 263 727 3652 4 12295 24 16 0 60 5 2 0 0 2373 9 4486 162 613 3351 3 10456 22 16 0 62 6 1 0 7 2442 14 5017 181 699 3368 5 12797 22 15 0 63 7 1 0 0 2128 10 4139 163 566 3332 7 10929 23 16 0 60 March 2, 2026 at 06:51:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 21 5174 108 5868 244 783 2631 1 16183 26 19 0 54 1 0 0 2 3339 108 6135 246 828 2967 3 14625 27 18 0 54 2 0 0 0 2803 10 5220 220 685 2742 1 12926 24 16 0 60 3 4 0 1418 3248 603 5721 245 728 2715 1 13592 28 17 0 56 4 1 0 0 2603 15 4956 158 663 2611 2 11664 25 16 0 59 5 2 0 0 2451 20 4805 258 550 2538 3 11240 23 14 0 63 6 0 0 0 2559 9 4993 163 645 2780 1 10978 20 15 0 65 7 1 0 0 2214 7 4404 130 551 2620 1 11031 22 15 0 63 March 2, 2026 at 06:51:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 4958 109 5507 256 679 2775 5 15365 28 20 0 53 1 2 0 10 3260 113 5965 237 741 2908 6 14292 27 20 0 53 2 0 0 0 2617 11 4937 196 572 3011 9 13674 29 18 0 53 3 1 0 1403 2981 450 5352 196 622 2564 2 12956 23 19 0 58 4 8 0 14 2379 13 4500 145 556 2924 3 11471 25 19 0 56 5 8 0 0 2084 11 4172 233 498 3301 11 10213 25 14 0 61 6 1 0 0 2265 5 4393 142 506 2851 2 10552 22 17 0 61 7 1 0 0 1951 14 3721 108 416 2560 5 9785 18 15 0 67 March 2, 2026 at 06:51:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 5008 107 5385 260 809 3396 5 13995 32 20 0 48 1 1 0 11 3221 107 5902 307 856 3533 1 14335 26 18 0 55 2 3 0 0 2653 9 4924 199 651 3231 1 11945 25 17 0 58 3 6 0 1416 3170 553 5805 207 792 3535 2 14113 19 17 0 64 4 1 0 14 2664 10 5187 179 708 3514 2 11815 24 16 0 60 5 4 0 0 2248 17 4396 198 595 3220 8 10948 23 16 0 61 6 0 0 0 2452 16 5025 220 728 3523 4 11554 24 15 0 61 7 6 0 0 2065 19 3997 137 557 3379 3 10335 25 15 0 60 March 2, 2026 at 06:51:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 4945 107 5393 218 753 2631 4 14895 28 19 0 53 1 4 0 9 3192 108 5872 224 765 2745 4 14501 25 16 0 59 2 0 0 0 2589 13 4759 169 557 2650 4 12234 26 16 0 58 3 6 0 1418 2914 490 5096 180 632 2625 5 13042 25 17 0 58 4 3 0 14 2540 10 4956 148 585 2899 1 12836 28 16 0 55 5 1 0 0 2144 11 4300 172 513 2815 0 11963 22 13 0 64 6 6 0 0 2507 15 5015 172 606 2902 2 12153 23 15 0 62 7 1 0 0 2196 10 4340 156 485 2698 3 10957 22 14 0 64 March 2, 2026 at 06:51:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 0 5138 111 5850 239 806 3334 1 14680 24 20 0 56 1 5 0 4 3312 114 6173 293 827 3190 2 14997 23 19 0 58 2 4 0 0 2606 7 4948 276 615 3296 9 13596 29 18 0 53 3 5 0 1416 3160 473 5792 231 730 2908 3 13417 24 20 0 57 4 5 0 14 2571 11 5056 163 647 3355 1 12824 26 19 0 55 5 4 0 0 2323 8 4547 185 556 3284 3 12422 26 17 0 56 6 2 0 7 2335 5 4588 135 559 3392 4 12618 23 18 0 58 7 7 0 0 2038 12 4109 147 492 3002 5 10050 20 15 0 65 March 2, 2026 at 06:51:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 4819 109 5086 228 782 3371 0 14468 31 19 0 50 1 4 0 4 3025 114 5358 223 735 3208 5 13703 26 18 0 56 2 5 0 63 2479 10 4835 172 627 3606 3 12681 22 17 0 60 3 1 0 1402 2877 523 5067 249 704 3498 4 12172 28 17 0 56 4 0 0 0 2514 13 4821 166 653 3310 3 10251 23 15 0 62 5 1 0 0 2171 12 4166 127 541 3139 4 9836 21 14 0 65 6 5 0 14 2419 14 4911 227 692 3337 2 11564 25 14 0 61 7 4 0 7 2102 5 4118 152 506 3291 5 9873 25 15 0 60 March 2, 2026 at 06:51:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 5222 112 5946 240 766 2375 3 14647 26 18 0 56 1 4 0 7 3329 115 6009 222 748 2333 3 13378 21 16 0 62 2 2 0 0 2618 9 4818 145 559 2493 1 12645 27 17 0 56 3 5 0 1393 2956 477 5153 157 627 2472 3 13437 26 17 0 57 4 6 0 0 2336 14 4454 149 571 2500 4 13215 29 17 0 55 5 8 0 0 2234 7 4262 120 463 2342 0 10821 24 14 0 61 6 4 0 14 2632 14 5274 163 595 2471 5 12359 21 14 0 65 7 2 0 7 2035 18 4173 197 459 2547 2 10850 23 13 0 64 March 2, 2026 at 06:51:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 3068 107 1950 59 316 2237 1 4123 7 10 0 84 1 0 0 3 1180 103 2005 53 324 1962 2 4154 5 9 0 86 2 2 0 0 964 8 1939 74 302 1921 2 4061 7 9 0 84 3 5 0 437 1352 394 2172 102 303 1970 1 4313 9 8 0 84 4 4 0 0 814 7 1631 39 277 2254 0 4591 6 9 0 85 5 0 0 0 793 7 1586 61 266 2059 0 2869 6 6 0 88 6 1 0 14 749 3 1522 42 268 2292 1 3372 6 8 0 86 7 2 0 7 570 9 1064 28 179 1867 1 2549 7 7 0 86 March 2, 2026 at 06:51:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 0 0 0 0 0 1 0 99 1 0 0 4 217 105 10 0 0 0 0 2 0 0 0 100 2 0 0 0 21 8 14 0 0 0 0 7 0 0 0 100 3 0 0 2 314 154 106 1 0 0 0 601 0 0 0 100 4 0 0 0 13 3 36 1 0 0 0 1516 0 1 0 99 5 0 0 0 11 1 6 0 1 0 0 1 0 0 0 100 6 0 0 14 9 2 6 0 1 0 0 267 0 0 0 100 7 0 0 7 18 3 18 0 1 0 0 259 0 0 0 100 March 2, 2026 at 06:51:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 114 0 0 0 0 1 0 1 0 99 1 0 0 4 211 103 4 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 5 0 0 0 100 3 0 0 2 314 155 108 0 0 0 0 601 0 0 0 100 4 0 0 0 12 3 36 1 0 1 0 1512 0 0 0 99 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 7 0 0 7 22 4 20 1 0 0 0 259 0 0 0 100 March 2, 2026 at 06:51:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 112 0 0 0 0 0 0 1 0 99 1 0 0 4 215 104 10 0 0 0 0 1 0 0 0 100 2 0 0 0 17 6 12 0 0 0 0 6 0 0 0 100 3 0 0 2 312 154 106 0 0 0 0 600 0 0 0 100 4 0 0 0 22 5 50 1 1 2 0 1527 0 1 0 99 5 0 0 0 15 7 4 0 0 0 0 1 0 0 0 100 6 0 0 14 8 1 6 0 0 0 0 273 0 0 0 100 7 0 0 7 18 3 16 0 2 0 0 264 0 0 0 100 March 2, 2026 at 06:51:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5584 0 37 2312 100 341 0 56 287 14 1413 1 7 0 92 1 5476 0 124 406 111 403 7 48 4730 4 12534 2 15 0 83 2 7710 0 43 161 4 214 0 46 5067 4 2316 2 7 0 91 3 7300 0 204 460 127 231 10 48 368 13 10786 2 20 0 79 4 5252 0 49 182 20 504 5 41 332 5 5298 1 4 0 95 5 4830 0 39 326 22 209 1 42 261 10 1372 1 3 0 96 6 2437 0 107 79 6 124 2 28 145 7 2703 1 4 0 95 7 2310 0 32 125 4 171 1 24 4749 4 1354 1 4 0 95 March 2, 2026 at 06:51:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5192 0 211 3161 100 868 4 173 1125 57 2787 1 7 0 92 1 2380 0 3580 589 103 514 11 125 1753 23 855 0 9 0 91 2 3843 0 263 1027 1 547 2 132 878 44 1686 1 5 0 94 3 1361 0 178 1172 270 580 3 136 787 38 1726 1 5 0 95 4 1970 0 6 740 11 591 4 129 973 47 4436 2 6 0 92 5 7258 0 131 819 57 770 3 111 848 48 3873 2 6 0 92 6 1691 0 142 1481 3 928 2 173 1264 51 3480 2 4 0 94 7 1851 0 33 738 5 809 1 150 1001 49 1918 1 4 0 95 March 2, 2026 at 06:51:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 433 0 7 2120 101 137 1 4 23 0 3232 1 1 0 98 1 6 0 4 229 102 16 0 3 0 0 350 0 0 0 100 2 452 0 0 28 0 13 0 1 22 1 2365 1 0 0 99 3 495 0 65 222 104 20 0 3 22 0 1775 0 2 0 98 4 64 0 7 34 2 30 0 3 7 0 316 0 0 0 99 5 5 0 0 34 1 35 0 3 0 0 87 0 0 0 100 6 4 0 14 24 2 12 0 2 0 0 573 0 0 0 100 7 38 0 7 131 53 120 1 1 0 0 265 0 0 0 100 March 2, 2026 at 06:51:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2157 101 136 1 0 0 0 1052 0 1 0 99 1 0 0 3 265 103 8 0 1 0 0 300 0 0 0 100 2 0 0 0 69 0 18 0 1 0 0 0 0 0 0 100 3 0 0 24 259 102 6 0 1 3 0 0 0 1 0 99 4 0 0 336 13 2 4 0 0 3 0 294 0 1 0 99 5 0 0 0 60 1 4 0 0 0 0 0 0 0 0 100 6 0 0 14 60 3 6 0 0 0 0 567 0 0 0 100 7 0 0 7 163 53 108 0 0 0 0 258 0 0 0 100 March 2, 2026 at 06:51:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2157 101 134 1 4 0 0 1060 0 1 0 99 1 0 0 3 272 103 16 0 2 0 0 300 0 0 0 100 2 0 0 0 69 0 20 0 0 0 0 0 0 0 0 100 3 0 0 3 267 103 18 0 0 0 0 14 0 0 0 100 4 0 0 336 10 2 6 0 0 1 0 294 0 0 0 99 5 0 0 0 64 8 4 0 0 0 0 0 0 0 0 100 6 0 0 14 62 3 10 1 0 0 0 572 0 0 0 100 7 0 0 7 163 53 110 0 0 0 0 258 0 0 0 100 March 2, 2026 at 06:52:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 141 1 1 1 0 1052 0 1 0 99 1 0 0 3 216 103 6 1 1 1 0 300 0 0 0 100 2 0 0 0 18 1 8 0 1 1 0 0 0 0 0 100 3 0 0 24 211 102 6 0 0 1 0 0 0 0 0 100 4 0 0 0 13 3 4 0 1 0 0 294 0 0 0 100 5 0 0 0 18 4 4 0 0 1 0 0 0 0 0 100 6 0 0 14 12 3 4 0 0 1 0 567 0 0 0 100 7 0 0 7 116 54 106 0 0 1 0 258 0 0 0 100 March 2, 2026 at 06:52:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 2231 102 392 1 76 16645 3 1136 0 12 0 88 1 3296 0 12 323 106 234 4 40 29063 11 1202 1 16 0 83 2 176 0 9 218 41 404 1 70 16661 15 259 0 8 0 92 3 402 0 4 459 227 266 2 59 15724 10 228 0 6 0 93 4 41 0 0 120 3 220 1 36 24006 7 415 0 10 0 90 5 0 0 0 135 1 310 1 55 10210 4 83 0 5 0 95 6 20 0 14 174 3 353 0 50 22043 2 663 0 9 0 91 7 26 0 10 150 10 427 1 92 16127 5 282 0 11 0 89 March 2, 2026 at 06:52:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10931 0 0 7274 116 14276 1500 4209 7820 66 41708 26 56 0 17 1 8549 0 3 5500 125 13641 1433 4078 8129 72 41368 22 60 0 18 2 6099 0 7 5510 21 14204 1412 4261 7531 59 45365 24 57 0 20 3 13469 0 1382 5701 785 13624 1313 3975 8310 65 41013 25 57 0 18 4 6311 0 0 5166 17 13687 1255 4132 8410 61 41695 24 56 0 20 5 7464 0 0 5199 17 14373 1481 4119 8376 53 43564 24 55 0 21 6 6403 0 0 5004 26 13294 1310 3937 8056 64 42246 24 55 0 21 7 7833 0 14 4901 24 13000 1423 3664 8194 44 40173 25 53 0 22 March 2, 2026 at 06:52:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 7741 122 14272 902 4191 9563 3 41318 25 58 0 18 1 0 0 3 5826 132 14707 884 4342 10285 11 42371 25 57 0 18 2 2 0 14 5730 26 14697 883 4218 10716 6 41353 24 57 0 19 3 0 0 1417 6298 1065 14702 1004 4296 10048 1 42314 24 57 0 19 4 1 0 7 5615 23 14687 909 4129 10453 0 43514 23 56 0 21 5 0 0 0 5256 25 13730 835 3830 10124 3 39350 24 57 0 20 6 1 0 0 5527 31 14868 955 4149 10172 7 44139 23 55 0 22 7 0 0 0 5087 18 13465 801 3802 10149 2 39564 23 56 0 21 March 2, 2026 at 06:52:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 7605 118 14287 824 4357 10768 10 40110 23 60 0 17 1 0 0 3 5754 119 15039 929 4480 11042 19 42936 24 58 0 18 2 0 0 0 5540 21 14623 914 4361 11496 9 42525 23 58 0 18 3 1 0 1417 6350 1209 14554 941 4317 9878 3 41154 24 58 0 18 4 0 0 7 5510 23 15206 984 4311 11287 3 44052 25 55 0 20 5 0 0 7 5214 28 13877 871 4104 10781 15 40382 24 57 0 19 6 0 0 14 5339 27 15114 993 4226 11467 16 43467 24 55 0 20 7 0 0 0 5212 28 14364 855 4098 10738 5 40941 24 55 0 21 March 2, 2026 at 06:52:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 7793 130 14823 886 4387 10379 31 42672 25 58 0 17 1 120 0 8 5962 121 15298 1008 4575 11350 35 44193 25 57 0 18 2 105 0 0 5548 19 14655 809 4276 9493 40 42405 23 58 0 19 3 32 0 1416 6202 1001 14550 984 4179 9807 22 41915 24 58 0 18 4 0 0 0 5542 25 15235 998 4289 9746 28 43220 24 56 0 20 5 0 0 0 5289 22 13788 751 3936 11094 32 39244 23 56 0 20 6 0 0 2 5335 35 14607 891 4149 10697 34 43609 24 54 0 21 7 0 0 14 4952 13 13749 801 3911 10170 38 40727 24 55 0 22 March 2, 2026 at 06:52:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 7726 123 14638 818 4305 10260 38 40349 24 58 0 17 1 0 0 3 5994 126 15395 869 4618 10713 28 44221 25 57 0 18 2 0 0 2 5505 24 14559 835 4232 10886 21 42070 25 57 0 19 3 0 0 1496 6140 1077 14023 825 4214 11566 55 40160 23 58 0 19 4 0 0 0 5441 29 14412 802 4214 10669 28 40560 24 57 0 20 5 0 0 0 5326 22 14536 811 4138 10735 16 41455 23 56 0 21 6 0 0 0 5384 32 15205 839 4327 11127 22 45145 24 55 0 21 7 0 0 14 5289 24 14187 775 3988 11297 30 40226 24 54 0 22 March 2, 2026 at 06:52:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 7377 126 14040 921 4014 10876 31 41011 23 61 0 17 1 0 0 3 5651 133 14173 845 4067 10940 42 41068 23 59 0 17 2 0 0 0 5429 27 14469 890 4084 10253 19 41698 25 57 0 18 3 0 0 1417 5713 930 13108 822 3901 9909 16 40079 23 60 0 18 4 0 0 7 5221 23 14179 928 3970 11320 49 42526 25 57 0 19 5 0 0 0 5120 17 13733 827 3882 10404 24 40826 23 58 0 20 6 0 0 0 5123 28 14499 883 4033 11055 45 42097 24 57 0 20 7 2 0 14 4972 27 12829 730 3570 10351 38 38340 22 57 0 21 March 2, 2026 at 06:52:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 7360 121 13728 781 4177 10213 3 40473 24 59 0 16 1 0 0 115 5725 136 14895 947 4292 11235 7 42865 26 56 0 18 2 0 0 0 5521 29 14322 769 4212 10622 15 42787 24 58 0 18 3 1 0 1431 5866 883 13808 852 4088 10178 7 41756 24 58 0 18 4 0 0 7 5402 28 14420 807 4044 10843 6 43674 25 56 0 20 5 0 0 0 5089 21 13330 731 3840 10992 12 40059 24 57 0 20 6 0 0 0 5285 27 15087 939 4067 11054 8 44467 25 54 0 20 7 0 0 0 5071 29 13632 725 3835 10144 12 41545 23 56 0 21 March 2, 2026 at 06:52:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 7695 118 14325 972 4316 9907 34 42047 23 59 0 17 1 0 0 17 5776 123 14327 964 4296 11280 21 41947 24 58 0 17 2 0 0 7 5336 19 13884 822 4119 10560 36 40720 24 58 0 18 3 0 0 1417 6259 1128 14443 944 4284 11381 34 41393 23 59 0 18 4 0 0 0 5381 20 14196 850 4083 11348 42 40470 24 57 0 20 5 0 0 0 5272 32 13882 802 4010 11466 25 40194 22 58 0 20 6 0 0 7 5263 27 14514 929 4132 10547 32 42029 26 54 0 20 7 0 0 0 5240 28 14192 920 3996 11045 68 40960 24 56 0 21 March 2, 2026 at 06:52:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 0 6572 128 11919 719 3383 9470 11 32442 20 50 0 30 1 18 0 3 4841 117 11985 732 3494 9102 9 32577 20 50 0 30 2 10 0 14 4652 23 12052 645 3388 9245 25 32874 19 47 0 34 3 6 0 1152 5268 1009 11655 756 3398 9872 20 31415 18 50 0 31 4 8 0 7 4496 18 12168 741 3358 10237 18 34386 20 46 0 34 5 0 0 0 4390 19 11449 663 3238 9270 2 31191 18 48 0 34 6 1 0 0 4285 20 11389 650 3260 10393 16 31983 18 48 0 34 7 0 0 26 4352 22 11778 796 3151 9658 18 33144 19 44 0 36 March 2, 2026 at 06:52:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2289 132 431 2 97 1987 0 0 0 3 0 97 1 0 0 3 400 110 390 3 110 2085 0 0 0 3 0 97 2 6 0 14 237 8 486 3 96 1918 0 888 0 3 0 97 3 0 0 3 604 288 580 2 89 1909 0 32 0 3 0 97 4 0 0 7 181 6 387 3 108 1915 0 560 0 3 0 97 5 0 0 0 150 0 345 3 78 2185 0 0 0 2 0 98 6 0 0 0 175 2 415 3 89 2008 0 1141 0 3 0 97 7 0 0 0 171 2 356 2 76 1891 0 0 0 2 0 98 March 2, 2026 at 06:52:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2154 147 109 0 7 0 0 1 0 1 0 99 1 0 0 3 306 105 100 0 6 0 0 3 0 0 0 100 2 0 0 14 12 3 10 0 1 0 0 568 0 0 0 100 3 0 0 3 227 109 22 0 1 0 0 312 0 0 0 100 4 0 0 7 27 7 24 0 1 0 0 567 0 0 0 100 5 0 0 0 12 1 10 0 2 0 0 1 0 0 0 100 6 0 0 0 11 2 36 1 1 1 0 1143 0 0 0 100 7 0 0 0 9 0 4 0 2 0 0 0 0 0 0 100 March 2, 2026 at 06:52:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2138 133 99 0 10 0 0 0 0 1 0 99 1 0 0 4 282 110 71 0 8 0 0 0 0 0 0 100 2 0 0 14 44 11 38 0 4 0 0 566 0 0 0 100 3 0 0 2 226 110 20 0 0 0 0 304 0 0 0 100 4 0 0 7 22 5 16 0 0 0 0 560 0 0 0 100 5 0 0 0 11 2 6 0 1 1 0 1 0 0 0 100 6 0 0 0 15 2 44 1 1 0 0 1140 0 0 0 100 7 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:52:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 210 0 8 3220 123 2632 121 643 179 11 15262 3 9 0 88 1 231 0 18 1286 108 2606 113 676 146 6 16400 3 5 0 91 2 2662 0 22 1025 12 2352 106 548 171 17 16383 3 5 0 91 3 187 0 242 1191 118 2462 102 592 248 15 16688 3 5 0 91 4 5303 0 11 914 9 2216 86 527 227 6 16386 4 6 0 90 5 277 0 9 916 8 2212 69 478 126 12 14914 3 4 0 93 6 154 0 4 845 2 2230 86 534 185 8 16805 3 5 0 92 7 132 0 2 834 0 2052 80 470 229 9 15308 3 4 0 92 March 2, 2026 at 06:52:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 124 0 0 7941 106 14774 733 4280 3849 9 96489 20 38 0 42 1 137 0 117 5867 116 15548 765 4517 4097 5 102031 20 36 0 45 2 129 0 21 5412 8 14657 691 3997 4233 10 99123 19 35 0 46 3 106 0 1416 5399 512 14264 657 4135 4058 9 99813 19 36 0 45 4 103 0 7 5096 16 14561 652 4054 4130 5 98649 19 34 0 48 5 139 0 0 4792 12 13617 584 3645 3980 9 93419 18 33 0 49 6 83 0 0 4830 11 13458 626 3864 4189 6 98825 19 35 0 47 7 121 0 0 4571 10 12545 546 3391 4113 7 91239 17 32 0 50 March 2, 2026 at 06:52:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 68 0 16 7588 112 15908 565 4890 4955 4 94732 19 37 0 44 1 102 0 4 5465 110 16491 597 5080 5194 4 102069 21 36 0 43 2 46 0 39 4950 11 15562 539 4584 5273 10 97774 20 35 0 45 3 53 0 1413 5215 624 15306 484 4693 4819 1 95685 19 36 0 45 4 44 0 0 4864 14 15508 450 4780 5236 7 97799 18 35 0 47 5 35 0 7 4494 9 14406 478 4295 5217 10 94159 20 35 0 46 6 55 0 7 4562 9 15211 495 4681 5237 8 96663 20 34 0 46 7 41 0 0 4342 12 14009 425 4193 4841 4 91858 17 33 0 50 March 2, 2026 at 06:52:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 51 0 14 7623 111 15997 599 5065 5195 4 95382 20 38 0 42 1 29 0 4 5569 108 16508 559 5200 4828 7 102428 20 37 0 43 2 31 0 0 4975 14 15522 564 4731 4903 7 98321 20 36 0 44 3 28 0 1415 5287 654 15467 532 4925 4774 5 98353 19 36 0 45 4 20 0 0 4856 11 15776 477 4930 5253 4 99233 18 35 0 46 5 33 0 0 4581 11 14578 434 4469 4708 11 93948 18 34 0 48 6 36 0 0 4663 7 15357 501 4762 5141 12 95468 19 34 0 47 7 41 0 14 4385 8 14764 500 4303 4952 8 96382 20 33 0 48 March 2, 2026 at 06:52:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 34 0 0 7472 110 17027 515 5279 4807 1 94293 20 38 0 42 1 58 0 3 5533 111 16818 479 5388 4819 6 101770 20 37 0 43 2 35 0 0 4968 9 15584 422 4866 4909 12 95164 18 35 0 47 3 27 0 1418 5284 747 16158 491 5140 4907 6 97238 20 36 0 44 4 16 0 171 4602 15 15482 423 5020 4794 2 98146 20 36 0 45 5 40 0 14 4541 13 15066 449 4679 4828 2 93957 19 34 0 48 6 33 0 7 4642 11 15900 451 5065 4771 8 101682 20 35 0 45 7 56 0 0 4335 9 15128 399 4622 4968 4 94045 19 34 0 48 March 2, 2026 at 06:52:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 24 0 64 7663 113 16307 540 5126 4647 6 91682 20 38 0 43 1 37 0 4 5574 118 16408 642 5168 4990 8 99171 22 37 0 42 2 22 0 0 5061 11 15013 491 4668 4784 9 94461 19 35 0 47 3 19 0 1415 5463 838 15780 523 4982 4584 11 95956 19 36 0 44 4 18 0 0 4750 8 15429 455 4817 4893 9 94698 19 35 0 46 5 15 0 0 4583 20 15541 532 4491 4888 13 93333 20 33 0 47 6 29 0 0 4747 16 15565 444 4746 4864 10 93047 18 34 0 48 7 19 0 7 4386 9 15184 401 4395 5093 6 93095 18 32 0 49 March 2, 2026 at 06:52:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 0 7648 105 16283 626 4944 4954 7 92555 20 38 0 43 1 37 0 3 5534 112 16387 575 5040 5165 8 102681 20 37 0 43 2 26 0 0 5113 13 15712 510 4623 5097 12 98155 20 35 0 45 3 25 0 1417 5402 873 15117 528 4667 4935 8 99043 19 37 0 44 4 16 0 0 4953 12 16112 508 4781 5243 6 97152 19 36 0 45 5 16 0 14 4603 11 14801 487 4216 5323 8 93934 19 34 0 47 6 23 0 0 4711 14 15011 490 4504 5262 5 95273 18 35 0 47 7 28 0 7 4466 10 14215 419 4108 4903 8 92069 18 35 0 47 March 2, 2026 at 06:52:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 30 0 0 7762 112 15751 669 4784 4709 6 92964 21 39 0 41 1 21 0 3 5825 110 15863 687 4876 4749 9 97802 19 37 0 44 2 18 0 0 5205 11 14936 579 4468 4449 7 93649 19 35 0 46 3 23 0 1417 5701 900 15855 608 4679 4818 8 95238 18 36 0 46 4 48 0 0 4977 10 15003 580 4568 5224 9 96196 20 34 0 46 5 18 0 0 4788 8 13867 446 4122 4660 4 90344 16 34 0 50 6 22 0 14 4759 13 15542 592 4436 4674 4 99689 19 34 0 47 7 19 0 7 4635 7 14041 537 3974 4584 4 92434 20 33 0 46 March 2, 2026 at 06:52:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 36 0 0 7954 111 15840 669 4603 4442 7 94602 21 37 0 42 1 13 0 4 5730 111 15549 583 4722 4686 9 99390 20 38 0 43 2 23 0 0 5179 12 15764 735 4248 4759 10 96707 19 35 0 46 3 24 0 1416 5573 878 14418 560 4373 4340 10 96356 18 37 0 45 4 25 0 21 4926 13 14499 558 4435 4658 7 96020 19 36 0 45 5 12 0 0 4815 15 14524 525 3991 4442 18 92419 19 33 0 48 6 31 0 0 4825 10 15110 657 4299 4690 16 96036 19 34 0 46 7 25 0 7 4500 7 13011 468 3726 4410 9 89659 18 34 0 49 March 2, 2026 at 06:52:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 0 7670 115 15763 559 4967 4177 11 97310 22 37 0 42 1 26 0 3 5651 113 16208 546 5082 4402 11 100590 19 36 0 45 2 19 0 0 5147 9 14883 477 4513 4265 12 97213 20 34 0 46 3 39 0 1418 5656 932 16580 579 4794 4018 7 100455 19 34 0 47 4 33 0 21 4916 13 15270 456 4731 4316 8 97341 19 34 0 47 5 16 0 0 4853 8 14414 414 4228 4302 12 93997 18 31 0 51 6 22 0 0 4663 16 14900 441 4535 4710 8 96132 19 34 0 47 7 16 0 0 4532 10 14644 480 4222 4316 10 95232 19 31 0 50 March 2, 2026 at 06:52:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35 0 0 7812 119 16076 633 5059 5036 9 94686 21 38 0 41 1 29 0 4 5742 111 16157 580 5165 4900 9 100411 19 36 0 44 2 12 0 0 5293 6 15516 537 4709 5027 10 96469 19 35 0 47 3 12 0 1415 5622 859 15399 592 4852 5004 10 96460 19 35 0 46 4 20 0 0 4951 15 15673 609 4784 5157 5 99094 19 33 0 48 5 16 0 7 4882 15 14885 546 4425 4943 6 92935 19 34 0 47 6 23 0 14 4930 11 16400 691 4747 4960 8 101649 20 33 0 47 7 16 0 0 4552 12 14268 425 4199 5100 6 92866 18 33 0 49 March 2, 2026 at 06:52:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 0 7600 114 15253 632 4779 5079 8 91164 20 39 0 42 1 8 0 11 5624 114 16713 714 4904 5189 5 100246 20 37 0 43 2 20 0 0 5119 6 14626 583 4358 4986 6 91272 19 37 0 44 3 10 0 1417 5470 861 15531 631 4596 4744 6 98763 20 36 0 45 4 58 0 0 4872 11 15310 575 4564 5163 7 96048 19 35 0 46 5 10 0 110 4670 8 14560 497 4107 5160 8 88965 18 34 0 47 6 34 0 14 4610 10 14556 620 4395 5317 10 92931 19 36 0 46 7 27 0 0 4442 14 13427 431 3851 5121 6 89513 18 35 0 48 March 2, 2026 at 06:52:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 38 0 0 7708 108 17668 758 4821 4513 7 100455 22 37 0 41 1 14 0 4 5724 116 15916 683 4925 4717 8 100629 20 37 0 42 2 17 0 0 5113 3 14601 608 4408 4879 10 94346 20 36 0 44 3 36 0 1415 5591 850 14904 581 4478 4618 7 95342 17 37 0 46 4 17 0 0 4856 11 14651 552 4426 4564 5 95157 17 35 0 48 5 40 0 7 4796 7 14497 604 4144 4748 6 90988 18 34 0 48 6 42 0 14 4655 14 14269 555 4286 4929 10 96050 19 36 0 45 7 30 0 0 4397 11 13381 564 3979 4372 8 92443 18 35 0 47 March 2, 2026 at 06:52:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2514 103 1073 3 271 2145 2 898 0 5 0 95 1 4 0 3 628 109 1010 8 265 2293 1 1212 0 5 0 95 2 0 0 0 420 1 975 2 263 2172 0 1012 0 4 0 96 3 0 0 45 980 500 1017 2 280 2391 0 1043 0 5 0 95 4 3 0 0 478 48 1074 7 281 2384 1 2063 0 4 0 95 5 0 0 7 389 7 959 3 240 2256 1 1156 0 4 0 96 6 0 0 14 659 6 1487 7 278 2215 1 1323 0 4 0 96 7 0 0 0 441 2 1036 4 236 2260 0 1247 0 4 0 96 March 2, 2026 at 06:52:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 1 0 0 0 0 0 0 100 1 0 0 4 213 103 6 0 0 0 0 294 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 2 213 104 6 0 0 0 0 4 0 0 0 100 4 0 0 0 109 52 133 1 1 0 0 1141 0 0 0 100 5 0 0 7 25 8 20 0 0 0 0 270 0 0 0 100 6 0 0 14 12 3 10 0 2 1 0 567 0 0 0 100 7 0 0 0 15 1 14 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:52:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 100 117 1 1 0 0 7 0 1 0 99 1 0 0 3 217 104 12 0 0 0 0 299 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 3 207 101 2 0 1 0 0 1 0 0 0 100 4 0 0 0 111 52 134 1 0 0 0 1143 0 0 0 100 5 0 0 7 42 18 34 0 1 0 0 284 0 0 0 100 6 0 0 14 14 4 14 0 1 0 0 575 0 0 0 100 7 0 0 0 15 1 15 0 2 0 0 312 0 0 0 100 March 2, 2026 at 06:52:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 100 120 0 2 0 0 0 0 1 0 99 1 0 0 7 216 103 8 0 0 1 0 294 0 0 0 100 2 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 3 0 0 7 208 101 2 0 0 1 0 0 0 0 0 100 4 0 0 0 110 52 132 1 0 1 0 1142 0 0 0 100 5 0 0 7 25 8 18 1 0 1 0 267 0 0 0 100 6 0 0 14 14 5 8 0 0 1 0 566 0 0 0 100 7 0 0 0 13 2 4 0 1 1 0 300 0 0 0 100 March 2, 2026 at 06:52:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4918 0 102 2464 103 463 1 79 477 8 3215 1 5 0 94 1 2426 0 47 376 104 266 3 62 1523 3 1286 1 3 0 96 2 1837 0 9 153 1 208 3 52 1505 11 503 1 3 0 96 3 2250 0 75 374 151 200 4 56 1486 3 4304 1 6 0 94 4 2410 0 56 231 10 403 2 62 535 15 3998 1 6 0 93 5 8674 0 50 356 29 457 2 86 855 7 4053 2 8 0 90 6 9370 0 231 237 7 738 6 85 737 14 17602 2 14 0 84 7 8737 0 66 207 4 330 5 85 686 16 3163 2 6 0 93 March 2, 2026 at 06:52:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 42 2196 100 304 0 34 227 4 26 0 2 0 98 1 18 0 3 322 103 218 0 42 256 5 306 0 1 0 99 2 2 0 0 113 1 200 0 30 229 2 19 0 1 0 99 3 1 0 3 509 256 490 0 47 210 2 33 0 1 0 99 4 138 0 0 121 3 246 1 42 280 2 823 0 1 0 99 5 363 0 14 140 10 208 0 32 240 2 405 0 1 0 99 6 25 0 14 108 3 195 0 34 237 4 667 0 1 0 99 7 7 0 14 94 4 157 0 32 173 1 346 0 1 0 99 March 2, 2026 at 06:52:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 49 2156 100 114 0 1 1 0 0 0 2 0 98 1 0 0 346 228 104 14 1 1 1 0 296 0 0 0 100 2 0 0 0 67 0 12 0 2 0 0 0 0 0 0 100 3 0 0 3 401 170 142 0 0 0 0 20 0 0 0 100 4 0 0 0 67 3 34 1 0 0 0 754 0 0 0 100 5 0 0 7 66 2 6 0 0 0 0 258 0 0 0 100 6 0 0 14 67 4 8 0 0 0 0 567 0 0 0 100 7 0 0 0 69 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 100 114 0 0 0 0 0 0 0 0 100 1 0 0 4 215 103 10 0 1 0 0 294 0 0 0 100 2 0 0 0 10 0 6 0 0 0 0 3 0 0 0 100 3 0 0 2 359 173 162 0 1 0 0 28 0 0 0 100 4 0 0 0 12 3 36 1 1 0 0 759 0 0 0 100 5 0 0 7 17 9 6 1 0 0 0 258 0 0 0 100 6 0 0 14 17 4 18 1 0 0 0 579 0 0 0 100 7 0 0 0 15 2 12 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:52:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 108 0 0 0 0 0 0 1 0 99 1 0 0 4 217 104 10 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 347 171 144 0 0 0 0 21 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 11 2 8 0 1 0 0 258 0 0 0 100 6 0 0 14 12 4 8 1 0 0 0 567 0 0 0 100 7 0 0 0 12 2 6 1 1 0 0 300 0 0 0 100 March 2, 2026 at 06:52:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 109 0 0 0 0 0 0 0 0 100 1 0 0 4 216 104 8 0 0 0 0 295 0 0 0 100 2 0 0 0 10 1 6 0 0 1 0 0 0 0 0 100 3 0 0 2 347 170 144 0 0 3 0 20 0 0 0 100 4 0 0 0 17 3 46 1 1 1 0 753 0 0 0 100 5 0 0 7 12 2 12 0 0 4 0 258 0 0 0 100 6 0 0 14 10 3 8 0 1 0 0 566 0 0 0 100 7 0 0 0 13 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 0 0 1 0 99 1 0 0 4 217 104 10 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 346 170 142 0 0 0 0 25 0 0 0 100 4 0 0 0 16 3 40 1 2 0 0 756 0 0 0 100 5 0 0 7 19 5 18 0 1 0 0 258 0 0 0 100 6 0 0 14 11 3 10 0 0 0 0 571 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 0 0 1 0 99 1 0 0 4 215 103 8 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 345 170 142 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 10 2 6 1 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 1 0 0 0 0 1 0 99 1 0 0 4 216 104 10 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 349 170 150 0 0 0 0 32 0 0 0 100 4 0 0 0 13 3 38 1 0 0 0 762 0 0 0 100 5 0 0 7 19 8 8 0 0 1 0 258 0 0 0 100 6 0 0 14 21 4 22 1 1 0 0 572 0 0 0 100 7 0 0 0 15 2 8 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 1 0 0 0 0 0 0 100 1 0 0 3 213 103 6 0 0 1 0 294 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 3 342 169 140 0 0 1 0 20 0 0 0 100 4 0 0 0 12 4 34 0 0 1 0 753 0 0 0 100 5 0 0 7 11 3 6 0 0 1 0 258 0 0 0 100 6 0 0 14 13 4 8 0 0 2 0 566 0 0 0 100 7 0 0 0 17 3 14 0 1 1 0 300 0 0 0 100 March 2, 2026 at 06:52:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 110 0 1 0 0 0 0 1 0 99 1 0 0 4 217 104 8 0 0 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 1 0 0 0 0 0 100 3 0 0 2 346 170 144 0 1 3 0 20 0 0 0 100 4 0 0 0 12 3 36 1 0 2 0 754 0 0 0 100 5 0 0 7 12 2 12 0 0 2 0 258 0 0 0 100 6 0 0 14 11 3 8 1 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 100 118 0 1 0 0 0 0 1 0 99 1 0 0 4 213 103 6 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 344 170 140 0 0 0 0 20 0 0 0 100 4 0 0 0 19 6 204 1 2 1 0 1088 0 0 0 100 5 3 0 7 11 2 10 1 2 0 0 265 0 0 0 100 6 0 0 14 10 3 8 0 1 0 0 569 0 0 0 100 7 0 0 0 13 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 110 0 0 0 0 0 0 1 0 99 1 0 0 4 221 104 18 1 2 0 0 296 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 4 0 0 0 100 3 0 0 2 349 171 148 0 1 0 0 23 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 14 12 4 8 1 0 0 0 567 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 100 110 0 0 0 0 0 0 1 0 99 1 0 0 4 214 103 8 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 355 173 156 0 0 0 0 36 0 0 0 100 4 0 0 0 13 3 38 1 0 0 0 763 0 0 0 100 5 0 0 7 19 8 10 0 1 0 0 258 0 0 0 100 6 0 0 14 15 4 12 0 0 0 0 573 0 0 0 100 7 0 0 0 16 3 10 0 1 0 0 321 0 0 0 100 March 2, 2026 at 06:52:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 0 0 0 0 100 1 0 0 4 217 104 10 0 0 0 0 296 0 0 0 100 2 0 0 0 13 0 14 0 1 0 0 0 0 0 0 100 3 0 0 2 334 165 128 0 0 0 0 21 0 0 0 100 4 0 0 0 24 9 48 1 1 0 0 755 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 0 0 0 0 565 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 111 0 0 0 0 0 0 1 0 99 1 0 0 4 216 104 8 0 0 0 0 295 0 0 0 100 2 0 0 0 12 1 8 0 0 0 0 0 0 0 0 100 3 0 0 2 252 121 52 0 1 0 0 20 0 0 0 100 4 0 0 0 110 53 134 0 0 0 0 754 0 0 0 100 5 0 0 7 12 2 10 1 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 566 0 0 0 100 7 0 0 0 13 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 0 0 1 0 99 1 0 0 4 215 104 8 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 246 121 42 0 0 0 0 21 0 0 0 100 4 0 0 0 112 53 134 2 0 0 0 755 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 566 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 0 0 1 0 99 1 0 0 4 213 103 6 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 248 121 42 0 1 0 0 20 0 0 0 100 4 0 0 0 115 53 144 0 1 1 0 755 0 0 0 100 5 0 0 7 11 4 6 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 114 0 0 0 0 0 0 1 0 99 1 0 0 4 216 104 10 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 252 123 48 0 0 0 0 24 0 0 0 100 4 0 0 0 115 53 140 1 0 1 0 763 0 0 0 100 5 0 0 7 21 8 16 0 1 0 0 258 0 0 0 100 6 0 0 14 15 3 14 0 1 0 0 579 0 0 0 100 7 0 0 0 15 2 12 0 2 0 0 301 0 0 0 100 March 2, 2026 at 06:52:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 1 0 0 0 1 0 99 1 0 0 3 213 103 6 0 0 1 0 294 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 1 0 20 0 0 0 100 4 0 0 0 110 53 135 0 1 0 0 754 0 0 0 100 5 0 0 7 12 3 6 1 0 1 0 258 0 0 0 100 6 0 0 14 12 4 6 1 0 1 0 566 0 0 0 100 7 0 0 0 12 3 4 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:52:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 108 0 0 0 0 0 0 0 0 100 1 0 0 4 215 104 8 0 0 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 2 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 111 53 134 1 0 0 0 756 0 0 0 100 5 0 0 7 13 2 12 0 0 0 0 258 0 0 0 100 6 0 0 14 15 3 16 1 1 0 0 566 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 4 213 103 6 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 61 27 84 1 1 0 0 755 0 0 0 100 5 0 0 7 66 29 64 0 1 0 0 258 0 0 0 100 6 0 0 14 13 4 10 0 0 0 0 567 0 0 0 100 7 0 0 0 16 2 14 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:52:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 0 0 1 0 99 1 0 0 3 215 104 8 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 257 0 0 0 100 6 0 0 14 11 4 8 0 0 0 0 567 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 100 122 0 2 0 0 0 0 1 0 99 1 0 0 3 217 103 9 1 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 1 14 3 38 1 0 1 0 762 0 0 0 100 5 0 0 7 115 57 106 1 0 0 0 258 0 0 0 100 6 0 0 14 19 6 20 0 0 0 0 580 0 0 0 100 7 0 0 0 19 2 16 0 1 0 0 305 0 0 0 100 March 2, 2026 at 06:52:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 112 0 0 0 0 0 0 1 0 99 1 0 0 3 218 104 16 0 1 0 0 296 0 0 0 100 2 0 0 0 11 1 8 0 0 0 0 9 0 0 0 100 3 0 0 3 250 122 46 0 1 0 0 39 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 756 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 567 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 111 0 0 0 0 0 0 1 0 99 1 0 0 3 214 104 6 0 0 0 0 295 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 12 3 34 1 0 0 0 754 0 0 0 100 5 0 0 7 113 52 112 0 0 0 0 258 0 0 0 100 6 0 0 14 11 4 8 0 0 0 0 566 0 0 0 100 7 0 0 0 13 2 8 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:52:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 110 0 0 0 0 0 0 0 0 100 1 0 0 3 215 104 8 0 1 1 0 296 0 0 0 100 2 0 0 0 12 0 14 0 1 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 755 0 0 0 100 5 0 0 7 13 4 10 0 1 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 107 50 102 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:52:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 208 0 1 0 0 0 0 0 0 100 1 0 0 3 211 103 4 0 0 0 0 294 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 3 251 121 50 0 1 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 10 2 6 1 0 0 0 257 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 14 4 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:52:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 160 0 0 0 0 0 0 1 0 99 1 0 0 4 214 104 8 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 299 147 94 0 1 0 0 20 0 0 0 100 4 0 0 0 13 3 38 1 0 0 0 763 0 0 0 100 5 0 0 7 14 7 6 0 0 0 0 258 0 0 0 100 6 1 0 14 18 5 18 1 0 0 0 579 0 0 0 100 7 0 0 0 17 2 14 1 0 0 0 305 0 0 0 100 March 2, 2026 at 06:53:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 1 1 0 0 0 1 0 99 1 0 0 7 212 103 4 0 0 1 0 294 0 0 0 100 2 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 3 0 0 7 352 170 151 0 1 0 0 20 0 0 0 100 4 0 0 0 14 4 34 1 0 1 0 754 0 0 0 100 5 0 0 7 21 10 6 0 0 1 0 258 0 0 0 100 6 0 0 14 20 6 10 1 0 1 0 573 0 0 0 100 7 0 0 0 13 3 4 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:53:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 346 170 142 0 0 0 0 20 0 0 0 100 4 0 0 0 16 3 44 1 1 0 0 755 0 0 0 100 5 0 0 7 12 2 10 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 4 211 103 4 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 326 161 122 0 0 0 0 20 0 0 0 100 4 0 0 0 29 12 54 0 1 0 0 756 0 0 0 100 5 0 0 7 10 2 6 1 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 565 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 4 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 113 53 136 1 0 0 0 755 0 0 0 100 5 0 0 7 17 2 20 0 1 0 0 258 0 0 0 100 6 0 0 14 12 4 8 1 0 0 0 568 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 113 1 1 0 0 0 0 1 0 99 1 0 0 4 213 103 6 1 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 0 113 53 138 1 0 0 0 764 0 0 0 100 5 0 0 7 17 8 8 0 0 0 0 258 0 0 0 100 6 0 0 14 25 6 26 1 1 0 0 573 0 0 0 100 7 0 0 0 20 3 19 0 2 0 0 331 0 0 0 100 March 2, 2026 at 06:53:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 0 0 100 1 0 0 4 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 2 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 0 111 53 134 1 0 0 0 754 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 113 0 0 0 0 0 0 1 0 99 1 0 0 4 214 104 6 0 0 0 0 295 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 2 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 60 28 82 0 0 0 0 754 0 0 0 100 5 0 0 7 63 27 62 1 1 0 0 258 0 0 0 100 6 0 0 14 11 3 8 0 0 0 0 566 0 0 0 100 7 0 0 0 18 2 20 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 100 122 0 1 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 247 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 13 3 36 1 0 0 0 757 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 579 0 0 0 100 7 0 0 0 14 2 8 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 211 103 4 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 754 0 0 0 100 5 0 0 7 111 52 108 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 13 3 8 0 0 0 0 301 0 0 0 100 March 2, 2026 at 06:53:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 116 0 0 0 0 0 0 1 0 99 1 0 0 3 223 104 26 0 2 0 0 307 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 244 120 40 0 0 0 0 20 0 0 0 100 4 0 0 0 14 4 40 0 0 0 0 785 0 0 0 100 5 0 0 7 116 59 106 0 0 1 0 258 0 0 0 100 6 0 0 14 13 3 10 0 0 0 0 571 0 0 0 100 7 0 0 0 20 4 18 0 0 0 0 304 0 0 0 100 March 2, 2026 at 06:53:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 1 0 0 0 0 1 0 99 1 0 0 7 214 103 6 0 0 1 0 294 0 0 0 100 2 0 0 0 15 1 12 0 1 1 0 0 0 0 0 100 3 0 0 7 247 121 40 0 0 1 0 20 0 0 0 100 4 0 0 0 14 4 34 1 0 2 0 755 0 0 0 100 5 0 0 7 111 52 106 1 0 1 0 258 0 0 0 100 6 0 0 14 13 4 6 1 0 1 0 566 0 0 0 100 7 0 0 0 13 3 4 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:53:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 755 0 0 0 100 5 0 0 7 111 52 110 0 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 566 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 215 105 8 0 0 0 0 296 0 0 0 100 2 0 0 0 9 0 4 0 0 1 0 0 0 0 0 100 3 0 0 3 251 121 52 0 1 0 0 20 0 0 0 100 4 0 0 0 12 4 36 0 0 0 0 756 0 0 0 100 5 0 0 7 109 52 108 0 1 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 120 42 0 1 0 0 20 0 0 0 100 4 0 0 0 17 3 46 1 1 0 0 755 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 11 4 8 0 0 0 0 567 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 114 0 0 0 0 0 0 1 0 99 1 0 0 3 221 105 18 0 0 0 0 307 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 1 13 3 38 1 0 1 0 762 0 0 0 100 5 0 0 7 117 57 108 1 0 0 0 258 0 0 0 100 6 0 0 14 16 4 12 1 0 0 0 573 0 0 0 100 7 0 0 0 14 2 10 0 1 1 0 300 0 0 0 100 March 2, 2026 at 06:53:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 0 13 3 36 1 0 0 0 755 0 0 0 100 5 0 0 7 115 52 119 0 2 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 565 0 0 0 100 7 0 0 0 12 2 4 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 111 0 0 0 0 0 0 0 0 100 1 0 0 3 216 105 8 0 0 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 1 0 755 0 0 0 100 5 0 0 7 114 52 112 0 0 0 0 258 0 0 0 100 6 0 0 14 14 3 16 0 1 0 0 567 0 0 0 100 7 0 0 0 13 2 8 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 214 104 6 1 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 244 120 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 1 0 755 0 0 0 100 5 0 0 7 109 52 108 0 1 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 565 0 0 0 100 7 0 0 0 11 2 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 211 103 4 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 244 120 40 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 756 0 0 0 100 5 0 0 7 110 52 108 1 1 0 0 258 0 0 0 100 6 0 0 14 11 3 8 0 0 0 0 565 0 0 0 100 7 0 0 0 16 2 14 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 100 124 0 1 0 0 0 0 1 0 99 1 0 0 3 220 105 18 0 0 0 0 308 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 1 0 0 16 3 38 1 0 0 0 763 0 0 0 100 5 0 0 10 118 57 110 0 1 0 0 259 0 0 0 100 6 0 0 14 14 3 10 1 0 0 0 571 0 0 0 100 7 0 0 0 17 2 12 1 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 112 0 0 1 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 1 0 295 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 1 0 20 0 0 0 100 4 0 0 0 13 4 34 1 0 1 0 755 0 0 0 100 5 0 0 7 109 52 107 0 1 0 0 258 0 0 0 100 6 0 0 14 11 4 6 0 0 1 0 567 0 0 0 100 7 0 0 0 12 3 4 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:53:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 112 0 0 1 0 0 0 1 0 99 1 0 0 3 219 104 18 0 1 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 756 0 0 0 100 5 0 0 7 112 52 110 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 112 0 0 0 0 0 0 1 0 99 1 0 0 3 215 104 8 0 0 1 0 294 0 0 0 100 2 0 0 0 15 1 16 0 1 1 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 15 4 38 1 0 1 0 754 0 0 0 100 5 0 0 7 117 53 118 1 3 0 0 259 0 0 0 100 6 0 0 14 13 4 10 1 1 0 0 566 0 0 0 100 7 0 0 0 12 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 1 0 755 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 12 4 8 1 0 0 0 567 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 0 0 0 0 0 0 0 100 1 0 0 3 222 105 22 0 0 0 0 310 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 3 253 122 52 0 1 0 0 21 0 0 0 100 4 0 0 0 12 3 38 0 0 0 0 762 0 0 0 100 5 0 0 7 121 60 108 0 0 0 0 258 0 0 0 100 6 0 0 14 16 4 12 0 0 0 0 572 0 0 0 100 7 0 0 0 16 3 12 0 1 0 0 321 0 0 0 100 March 2, 2026 at 06:53:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 11 1 8 0 0 0 0 9 0 0 0 100 3 0 0 3 252 122 48 0 0 1 0 39 0 0 0 100 4 0 0 0 16 3 44 1 1 4 0 756 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 111 0 0 0 0 0 0 1 0 99 1 0 0 3 214 104 6 0 0 0 0 295 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 1 0 755 0 0 0 100 5 0 0 7 113 52 110 1 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 7 0 0 0 13 2 8 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 112 0 0 0 0 0 0 0 0 100 1 0 0 3 214 104 6 1 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 12 3 36 0 0 0 0 754 0 0 0 100 5 0 0 7 114 52 116 0 1 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 566 0 0 0 100 7 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 295 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 756 0 0 0 100 5 0 0 7 111 52 109 0 1 0 0 258 0 0 0 100 6 0 0 14 14 3 16 0 1 0 0 566 0 0 0 100 7 0 0 0 11 2 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 0 0 0 0 0 1 0 99 1 0 0 3 223 106 22 0 0 0 0 312 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 13 3 38 1 0 0 0 762 0 0 0 100 5 0 0 7 119 58 109 0 1 0 0 258 0 0 0 100 6 0 0 14 13 3 10 0 0 0 0 572 0 0 0 100 7 0 0 0 14 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 110 0 0 1 0 0 0 1 0 99 1 0 0 7 212 103 4 0 0 1 0 294 0 0 0 100 2 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 3 0 0 7 247 121 40 0 0 1 0 20 0 0 0 100 4 0 0 0 14 4 34 1 0 1 0 754 0 0 0 100 5 0 0 7 111 52 106 1 0 1 0 258 0 0 0 100 6 0 0 14 14 4 10 0 1 0 0 565 0 0 0 100 7 0 0 0 18 3 14 0 1 2 0 300 0 0 0 100 March 2, 2026 at 06:53:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 100 122 0 1 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 3 0 0 3 244 120 40 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 111 52 111 0 1 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 566 0 0 0 100 7 0 0 0 14 2 6 1 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 211 103 4 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 12 3 34 2 0 2 0 756 0 0 0 100 5 0 0 7 111 53 108 0 0 0 0 259 0 0 0 100 6 0 0 14 10 3 6 0 0 0 0 567 0 0 0 100 7 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 112 0 0 0 0 0 0 1 0 99 1 0 0 3 220 105 18 0 1 0 0 297 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 246 121 40 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 755 0 0 0 100 5 0 0 7 109 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 13 4 8 1 0 0 0 566 0 0 0 100 7 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 116 0 0 0 0 0 0 0 0 100 1 0 0 3 222 105 22 0 0 0 0 309 0 0 0 100 2 0 0 0 12 0 12 0 1 0 0 0 0 0 0 100 3 0 0 3 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 0 13 3 38 1 0 1 0 761 0 0 0 100 5 0 0 7 116 58 106 1 0 1 0 258 0 0 0 100 6 0 0 14 16 4 12 0 0 0 0 572 0 0 0 100 7 0 0 0 15 2 12 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 3 213 104 6 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 248 122 42 0 0 0 0 21 0 0 0 100 4 0 0 0 11 3 34 1 0 1 0 755 0 0 0 100 5 0 0 7 110 52 106 0 0 0 0 258 0 0 0 100 6 0 0 14 10 3 6 1 0 0 0 565 0 0 0 100 7 0 0 0 12 2 6 1 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 111 0 0 0 0 0 0 1 0 99 1 0 0 3 214 104 6 0 0 0 0 295 0 0 0 100 2 0 0 0 12 1 8 0 0 0 0 0 0 0 0 100 3 0 0 3 251 121 50 0 1 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 756 0 0 0 100 5 0 0 7 111 52 110 0 0 0 0 258 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 567 0 0 0 100 7 0 0 0 13 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2243 101 399 4 1 3 0 25 0 1 0 99 1 645 0 4 234 105 36 0 2 0 0 357 0 0 0 100 2 0 0 0 8 0 5 0 2 0 0 51 0 0 0 100 3 0 0 3 224 109 18 0 0 0 0 14 0 0 0 100 4 7 0 1 43 3 80 3 3 11 1 875 0 0 0 99 5 19 0 12 397 330 132 3 4 35 0 394 0 1 0 99 6 1289 0 18 36 7 46 0 2 6 0 762 0 0 0 99 7 1 0 0 155 2 289 1 3 11 0 333 0 0 0 100 March 2, 2026 at 06:53:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 0 0 100 1 0 0 3 212 103 6 0 0 0 0 294 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 4 0 0 0 11 3 36 0 0 1 0 758 0 0 0 100 5 0 0 8 131 69 114 1 1 0 0 269 0 0 0 100 6 1 0 14 19 3 21 0 1 0 0 594 0 0 0 100 7 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 101 124 0 0 0 0 0 0 1 0 99 1 0 0 3 214 104 8 0 0 0 0 296 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 4 0 0 0 18 3 46 1 0 0 0 767 0 0 0 100 5 14 0 7 126 75 102 0 2 1 0 306 0 0 0 99 6 1 0 14 32 8 35 1 1 0 0 603 0 0 0 100 7 0 0 0 62 22 62 1 1 2 0 300 0 0 0 100