March 2, 2026 at 06:52:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 946 0 48 4374 138 5932 96 373 1506 20 6848 12 9 0 79 1 975 0 104 1217 21 4143 27 419 1588 21 8498 10 7 0 83 2 1025 0 275 1016 19 3462 21 324 1552 11 6839 10 9 0 81 3 921 0 116 1450 511 2894 23 381 1640 24 8904 5 9 0 86 4 863 0 279 1157 18 2983 18 332 1520 22 6747 4 7 0 89 5 796 0 709 3267 2385 3401 22 394 1651 14 7465 4 8 0 88 6 729 0 181 1110 21 3397 22 413 1600 25 7574 3 7 0 90 7 1041 0 65 2253 19 5765 48 436 1532 11 5461 3 8 0 89 March 2, 2026 at 06:52:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4468 0 116 2538 136 887 25 179 648 72 3538 10 12 0 77 1 7148 0 43 609 18 1203 15 208 814 58 2447 7 6 0 86 2 5880 0 16 258 3 488 18 152 663 21 2563 12 5 0 83 3 6849 0 59 844 370 676 11 170 667 55 3653 3 35 0 62 4 3281 0 12 398 17 831 23 142 798 52 1565 10 7 0 83 5 4486 0 18 450 13 952 9 230 874 78 2490 5 4 0 92 6 5203 0 71 482 45 864 14 208 747 65 1963 5 10 0 85 7 5126 0 58 359 6 898 18 217 772 64 2072 9 6 0 85 March 2, 2026 at 06:52:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 17 2398 203 270 0 85 498 0 871 0 2 0 98 1 0 0 0 525 13 986 1 84 417 0 10 0 1 0 99 2 0 0 0 175 37 326 1 93 575 0 0 0 1 0 99 3 31 0 0 439 333 284 3 89 606 0 1016 0 2 0 98 4 0 0 0 114 4 258 2 100 521 0 7 0 1 0 99 5 0 0 0 113 10 246 2 81 438 0 300 0 1 0 99 6 0 0 11 305 103 263 0 85 524 0 267 0 1 0 99 7 0 0 0 102 0 252 1 82 560 0 0 0 1 0 99 March 2, 2026 at 06:52:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2403 204 275 0 88 678 0 859 0 2 0 98 1 0 0 0 442 0 941 0 99 692 0 0 0 1 0 99 2 0 0 0 227 12 389 0 99 787 0 0 0 1 0 99 3 23 0 0 441 339 301 0 94 720 0 998 0 2 0 98 4 0 0 0 151 23 316 1 106 737 0 0 0 1 0 99 5 0 0 0 151 21 328 0 99 676 0 302 0 1 0 99 6 0 0 10 320 103 288 0 108 741 0 259 0 1 0 99 7 0 0 0 110 0 271 0 104 646 0 0 0 1 0 99 March 2, 2026 at 06:52:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2359 203 186 0 18 123 0 561 0 1 0 99 1 0 0 0 151 1 289 0 21 93 0 0 0 0 0 100 2 0 0 0 89 1 145 0 17 128 0 0 0 0 0 100 3 0 0 0 161 99 119 1 23 126 0 848 0 1 0 99 4 0 0 0 63 3 147 0 28 102 0 148 0 0 0 100 5 0 0 0 159 54 195 1 18 92 0 301 0 0 0 100 6 0 0 14 277 103 137 0 24 114 0 559 0 0 0 100 7 0 0 0 50 1 89 0 14 110 0 0 0 0 0 100 March 2, 2026 at 06:52:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2357 202 194 1 27 313 0 559 0 2 0 98 1 0 0 0 63 1 123 3 35 429 0 1 0 2 0 98 2 0 0 0 67 0 131 2 29 278 0 0 0 2 0 98 3 0 0 0 197 124 141 2 32 264 0 0 0 2 0 98 4 0 0 0 89 12 176 2 31 291 0 996 0 2 0 98 5 0 0 0 302 47 490 0 45 169 0 302 0 0 0 100 6 0 0 11 283 104 175 1 46 217 0 558 0 1 0 99 7 0 0 0 79 1 146 1 31 291 0 0 0 2 0 98 March 2, 2026 at 06:52:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2314 202 116 0 3 0 0 561 0 1 0 99 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 996 0 0 0 100 5 0 0 0 115 53 110 0 0 0 0 300 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 560 0 0 0 100 7 0 0 0 20 1 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:52:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2305 202 112 0 2 0 0 559 0 0 0 99 1 0 0 0 15 2 16 0 0 0 0 14 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 4 0 0 0 15 3 38 1 0 0 0 1004 0 0 0 100 5 0 0 0 129 60 116 0 2 0 0 303 0 0 0 100 6 0 0 11 214 104 10 0 0 0 0 565 0 0 0 100 7 0 0 0 12 1 9 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2308 203 110 0 0 0 0 561 0 0 0 100 1 0 0 0 11 0 12 0 1 0 0 0 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 996 0 0 0 100 5 0 0 0 123 53 118 0 1 0 0 301 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 558 0 0 0 100 7 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2307 203 108 0 0 0 0 560 0 0 0 99 1 0 0 0 10 1 6 0 0 0 0 1 0 0 0 100 2 0 0 0 10 0 10 0 1 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 995 0 0 0 100 5 0 0 0 123 53 118 0 0 0 0 302 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 559 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2308 203 106 0 0 0 0 560 0 0 0 100 1 0 0 0 7 0 4 0 0 2 0 0 0 0 0 100 2 0 0 0 8 0 4 0 0 1 0 0 0 0 0 100 3 0 0 0 10 1 8 0 1 0 0 0 0 0 0 100 4 0 0 0 14 4 38 1 0 1 0 997 0 0 0 100 5 0 0 0 121 52 116 0 0 0 0 300 0 0 0 100 6 0 0 10 217 105 12 0 1 1 0 560 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2306 203 106 0 0 0 0 559 0 0 0 99 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 997 0 0 0 100 5 0 0 0 123 53 118 0 0 0 0 302 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 560 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2308 203 110 0 0 0 0 560 0 0 0 100 1 0 0 0 14 2 10 0 0 0 0 7 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 21 3 54 2 1 1 0 1010 0 0 0 100 5 0 0 0 127 58 116 0 0 0 0 300 0 0 0 100 6 0 0 11 214 104 10 0 0 0 0 566 0 0 0 100 7 0 0 0 13 1 11 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2308 203 108 0 0 0 0 561 0 1 0 99 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 12 4 36 0 0 0 0 996 0 0 0 100 5 0 0 0 123 53 118 0 0 0 0 302 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 559 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2304 203 106 0 0 1 0 559 0 1 0 99 1 0 0 0 8 1 2 0 0 1 0 0 0 0 0 100 2 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 3 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 4 0 0 0 15 4 36 1 0 2 0 995 0 0 0 100 5 0 0 0 127 53 124 0 1 1 0 300 0 0 0 100 6 0 0 11 212 104 6 0 0 1 0 559 0 0 0 100 7 0 0 0 11 2 6 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:52:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2311 205 114 0 0 0 0 560 0 0 0 100 1 0 0 0 11 0 12 0 4 3 0 0 0 0 0 100 2 0 0 0 9 0 10 0 4 2 0 0 0 0 0 100 3 0 0 0 10 1 8 0 0 0 0 0 0 0 0 100 4 0 0 0 16 5 40 1 0 0 0 998 0 0 0 100 5 0 0 0 125 53 120 0 0 0 0 302 0 0 0 100 6 0 0 11 218 104 18 0 1 1 0 560 0 0 0 100 7 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2307 203 106 0 0 1 0 560 0 0 0 100 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 1 0 0 0 100 4 2 0 0 11 3 34 1 0 0 0 1009 0 0 0 100 5 0 0 0 121 52 116 0 0 0 0 300 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 558 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2310 203 110 0 0 0 0 561 0 1 0 99 1 0 0 0 10 0 6 0 0 0 0 5 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 4 0 0 0 18 5 48 1 0 1 0 1022 0 0 0 100 5 0 0 0 132 61 120 0 0 0 0 304 0 0 0 100 6 0 0 11 216 104 12 0 0 0 0 566 0 0 0 100 7 0 0 0 18 1 21 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:52:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2312 203 118 0 1 1 0 560 0 0 0 100 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 13 4 36 1 0 0 0 1029 0 0 0 100 5 0 0 0 123 53 118 0 1 0 0 301 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 559 0 0 0 100 7 0 0 0 13 1 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2310 204 114 0 0 0 0 569 0 0 0 100 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 6 0 0 0 0 18 0 0 0 100 4 0 0 0 11 3 34 1 0 1 0 1009 0 0 0 100 5 0 0 0 123 53 118 0 0 0 0 302 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 560 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2308 203 110 1 1 2 0 560 0 0 0 99 1 0 0 0 10 0 16 0 1 1 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 6 0 0 0 0 0 0 0 0 100 4 0 0 0 13 4 38 0 0 2 0 1007 0 0 0 100 5 0 0 0 123 54 114 0 0 0 0 300 0 0 0 100 6 0 0 11 216 105 10 0 0 0 0 559 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:52:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 767 0 59 2392 205 277 10 30 64 7 1037 2 1 0 97 1 861 0 0 105 1 210 5 40 55 8 434 2 1 0 97 2 3623 0 7 125 1 215 9 27 182 14 1046 5 6 0 88 3 669 0 1 143 25 239 2 25 107 10 662 2 1 0 97 4 864 0 0 114 4 247 11 32 107 15 1717 2 1 0 96 5 914 0 0 143 28 242 11 30 92 5 843 1 1 0 98 6 728 0 11 301 106 188 6 23 87 1 1127 3 1 0 96 7 768 0 0 108 3 204 11 34 107 6 483 1 1 0 98 March 2, 2026 at 06:52:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 31 2313 203 118 1 1 5 0 597 0 1 0 99 1 18 0 0 15 1 10 0 0 1 0 13 0 0 0 100 2 0 0 0 8 0 2 0 1 0 0 1 0 0 0 100 3 1 0 0 113 51 110 1 2 0 0 7 0 0 0 100 4 15 0 0 39 10 64 2 3 0 0 1118 0 0 0 99 5 1 0 0 26 8 16 0 2 0 0 307 0 0 0 100 6 17 0 11 220 104 14 0 2 0 0 623 0 0 0 100 7 1 0 0 16 1 10 0 1 0 0 3 0 0 0 100 March 2, 2026 at 06:52:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2303 202 112 0 0 0 0 559 0 0 0 99 1 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 112 51 112 0 1 0 0 0 0 0 0 100 4 7 0 0 23 9 46 1 0 1 0 1093 0 0 0 100 5 0 0 0 16 3 10 0 0 0 0 302 0 0 0 100 6 0 0 11 212 104 6 0 0 0 0 560 0 0 0 100 7 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:52:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2305 202 116 1 0 1 0 560 0 0 0 99 1 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 2 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 3 0 0 0 112 52 104 0 0 1 0 0 0 0 0 100 4 0 0 0 31 10 56 1 1 1 0 1093 0 0 0 100 5 0 0 0 15 3 6 0 0 1 0 300 0 0 0 100 6 0 0 14 213 104 8 0 1 0 0 560 0 0 0 100 7 0 0 0 13 2 6 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:52:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19377 0 77 2678 205 680 19 110 121 33 3286 7 19 0 74 1 1617 0 216 412 18 722 13 141 166 47 2139 2 3 0 95 2 1966 0 136 311 1 546 10 117 182 41 2431 3 3 0 94 3 6911 0 11 533 98 756 14 130 177 38 3050 3 3 0 94 4 7822 0 20 451 12 677 15 113 216 44 4711 5 3 0 91 5 1695 0 6 413 5 739 15 110 182 53 1833 3 2 0 96 6 8666 0 206 600 104 639 17 122 107 54 2262 4 7 0 89 7 498 0 10 332 3 571 6 102 165 34 1761 1 1 0 98 March 2, 2026 at 06:52:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 241 0 59 2537 204 568 31 80 44 5 2377 3 2 0 95 1 581 0 0 304 8 524 19 80 77 6 1591 2 1 0 97 2 671 0 56 254 2 475 18 49 19 1 1569 2 2 0 96 3 1090 0 0 229 3 419 15 69 36 2 1185 3 1 0 96 4 100 0 0 216 4 411 24 63 26 1 2118 3 1 0 96 5 517 0 0 277 48 408 13 51 61 1 1601 2 1 0 97 6 548 0 4 429 104 418 12 49 20 3 1367 2 1 0 97 7 452 0 14 238 5 445 10 41 23 3 1348 2 1 0 97 March 2, 2026 at 06:52:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 252 2309 201 116 0 1 2 0 266 0 1 0 99 1 0 0 0 63 6 26 0 0 0 0 14 0 0 0 100 2 0 0 7 46 2 8 0 1 2 0 294 0 1 0 99 3 0 0 0 44 2 4 0 0 0 0 1 0 0 0 100 4 12 0 0 46 3 34 1 0 0 0 1088 0 0 0 100 5 0 0 0 163 60 122 0 0 1 0 318 0 0 0 100 6 0 0 7 255 103 20 0 1 0 0 307 0 0 0 100 7 0 0 7 54 3 19 0 0 0 0 307 0 0 0 100 March 2, 2026 at 06:52:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 136 2310 202 108 1 0 1 0 268 0 1 0 99 1 0 0 0 43 5 20 0 0 0 0 8 0 0 0 100 2 0 0 14 28 2 6 0 0 0 0 294 0 0 0 100 3 0 0 0 28 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 30 3 34 1 0 0 0 1086 0 0 0 100 5 0 0 0 130 52 106 0 1 0 0 301 0 0 0 100 6 0 0 4 233 103 8 0 0 0 0 301 0 0 0 100 7 0 0 7 32 3 10 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:52:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2305 201 102 0 0 0 0 266 0 0 0 100 1 0 0 0 28 6 22 0 0 0 0 9 0 0 0 100 2 0 0 14 11 2 6 0 0 0 0 294 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 13 3 34 1 0 0 0 1086 0 0 0 100 5 0 0 0 115 53 106 0 0 0 0 303 0 0 0 100 6 0 0 4 218 103 10 0 1 0 0 300 0 0 0 100 7 0 0 7 19 3 18 0 1 0 0 260 0 0 0 100 March 2, 2026 at 06:52:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35686 0 128 2943 202 1082 32 205 169 55 4679 13 9 0 78 1 3482 0 148 631 7 1130 38 218 203 74 4271 6 4 0 91 2 1812 0 10 573 3 985 21 161 176 56 3150 3 2 0 95 3 3306 0 20 631 63 995 35 199 231 49 3732 4 4 0 92 4 9991 0 396 529 5 1041 24 194 253 65 4913 7 5 0 88 5 6163 0 17 693 26 974 16 137 162 57 3287 6 3 0 91 6 990 0 20 806 127 1110 19 189 187 81 3491 3 2 0 94 7 2031 0 132 512 4 985 23 135 180 71 5308 4 2 0 93 March 2, 2026 at 06:52:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 45 2313 202 65 0 4 4 0 280 0 1 0 99 1 0 0 7 69 0 54 0 3 0 0 0 0 0 0 100 2 0 0 0 21 2 4 0 0 0 0 294 0 0 0 100 3 40 0 0 34 7 16 0 0 0 0 9 0 0 0 100 4 0 0 42 19 2 38 1 0 5 0 1098 0 1 0 99 5 0 0 0 122 52 106 0 0 0 0 302 0 0 0 100 6 0 0 4 226 104 8 0 0 0 0 300 0 0 0 100 7 0 0 7 31 4 14 0 0 0 0 308 0 0 0 100 March 2, 2026 at 06:52:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 59 2373 201 116 1 0 3 0 266 0 1 0 99 1 0 0 462 25 0 22 0 2 2 0 4 0 1 0 99 2 0 0 0 82 2 6 0 1 0 0 294 0 0 0 100 3 0 0 0 92 7 16 0 1 0 0 12 0 0 0 100 4 0 0 0 81 2 32 1 0 0 0 1087 0 0 0 100 5 0 0 0 195 59 116 0 0 0 0 314 0 0 0 100 6 0 0 4 289 104 12 0 0 0 0 307 0 0 0 100 7 0 0 7 87 3 13 0 1 0 0 260 0 0 0 100 March 2, 2026 at 06:52:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2304 201 112 0 0 0 0 266 0 0 0 100 1 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 2 0 0 0 14 2 16 0 1 0 0 294 0 0 0 100 3 0 0 0 19 7 14 0 0 0 0 9 0 0 0 100 4 0 0 0 8 2 32 0 0 1 0 1085 0 0 0 100 5 0 0 0 113 53 108 0 0 0 0 303 0 0 0 100 6 0 0 4 216 104 10 0 0 0 0 300 0 0 0 100 7 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:52:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1529 0 299 2897 208 1168 26 207 78 64 4600 4 4 0 92 1 2196 0 222 620 3 1110 35 210 110 50 4327 4 3 0 93 2 34498 0 17 552 3 924 40 155 101 44 4088 11 8 0 81 3 2581 0 123 524 13 901 30 169 173 59 5059 5 4 0 91 4 12072 0 153 561 4 941 29 188 191 59 5019 6 5 0 88 5 8501 0 26 618 32 881 28 156 156 54 3769 7 3 0 90 6 478 0 17 766 107 1024 38 177 92 69 3793 5 2 0 93 7 1513 0 14 487 8 800 28 142 118 51 3664 4 2 0 94 March 2, 2026 at 06:52:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 31 2366 204 186 0 18 75 0 310 0 1 0 99 1 13 0 70 51 3 71 0 18 63 0 15 0 1 0 99 2 0 0 0 60 1 66 0 10 68 0 311 0 0 0 99 3 0 0 9 235 108 219 0 23 82 0 9 0 0 0 100 4 0 0 0 71 2 130 1 14 72 0 1115 0 0 0 99 5 12 0 0 122 3 204 0 12 74 0 328 0 0 0 100 6 41 0 4 296 107 136 1 15 80 0 319 0 0 0 100 7 26 0 7 77 3 90 0 10 72 0 268 0 0 0 100 March 2, 2026 at 06:52:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2357 203 120 1 1 1 0 266 0 1 0 99 1 0 0 28 57 0 4 0 0 4 0 0 0 1 0 99 2 0 0 343 14 1 6 0 0 3 0 294 0 1 0 99 3 0 0 0 168 53 110 0 1 0 0 1 0 0 0 100 4 0 0 0 68 2 42 1 1 2 0 1085 0 0 0 100 5 0 0 0 63 1 6 0 1 0 0 300 0 0 0 100 6 0 0 4 278 109 18 0 0 0 0 309 0 0 0 100 7 0 0 7 64 2 8 0 1 0 0 263 0 0 0 100 March 2, 2026 at 06:52:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 136 2309 204 119 1 1 1 0 266 0 1 0 99 1 0 0 0 27 1 6 0 0 0 0 0 0 0 0 100 2 0 0 0 24 1 2 0 0 0 0 294 0 0 0 100 3 0 0 0 129 53 108 0 0 0 0 2 0 0 0 100 4 0 0 0 25 2 32 0 0 1 0 1087 0 0 0 100 5 0 0 0 44 11 16 0 0 0 0 310 0 0 0 100 6 0 0 4 244 109 22 0 0 0 0 317 0 0 0 100 7 0 0 7 31 2 14 0 1 0 0 269 0 0 0 100 March 2, 2026 at 06:52:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2423 0 163 2450 203 243 4 12 43 36 2115 2 2 0 97 1 2251 0 32 121 0 155 3 34 53 31 709 0 1 0 98 2 2159 0 17 118 1 189 0 39 43 26 1030 0 1 0 98 3 952 0 189 199 51 293 0 49 59 40 613 0 1 0 99 4 2402 0 11 137 3 227 3 39 57 30 1852 1 2 0 97 5 369 0 7 124 2 152 1 22 25 25 809 1 0 0 99 6 54 0 10 346 111 188 1 36 18 27 998 0 0 0 99 7 39 0 20 106 2 127 1 20 13 11 528 0 0 0 99 March 2, 2026 at 06:52:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2576 0 225 2717 206 844 21 135 88 39 3376 4 3 0 92 1 39151 0 81 442 2 775 33 137 102 35 4076 12 10 0 78 2 3880 0 12 343 3 580 15 98 105 25 4141 3 3 0 94 3 1231 0 3 434 2 762 23 128 96 30 3260 4 2 0 94 4 1260 0 186 331 6 618 13 118 61 32 3273 5 2 0 93 5 3638 0 16 390 3 496 11 85 63 27 1918 6 2 0 92 6 1006 0 25 723 148 879 23 136 61 30 2976 3 1 0 96 7 598 0 16 293 6 470 13 86 68 25 2039 2 2 0 96 March 2, 2026 at 06:52:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 514 2361 203 220 1 10 78 0 24 0 2 0 98 1 1 0 7 123 1 86 0 22 60 0 258 0 1 0 99 2 0 0 0 135 1 108 0 16 66 0 294 0 0 0 100 3 40 0 0 225 79 133 0 20 94 0 9 0 1 0 99 4 0 0 0 135 2 140 1 19 60 0 1093 0 1 0 99 5 0 0 0 189 0 221 0 14 47 0 0 0 0 0 100 6 0 0 4 442 155 215 0 14 89 0 602 0 0 0 100 7 0 0 7 116 2 76 0 9 40 0 263 0 0 0 100 March 2, 2026 at 06:52:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 106 0 2 0 0 0 0 0 0 100 1 0 0 14 15 1 10 0 1 0 0 266 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 9 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 1087 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 6 0 0 4 317 154 110 0 0 0 0 599 0 0 0 100 7 0 0 7 15 2 16 0 1 0 0 260 0 0 0 100 March 2, 2026 at 06:52:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 202 131 1 2 0 0 0 0 0 0 100 1 0 0 14 6 1 6 0 1 0 0 266 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 9 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 1085 0 0 0 100 5 0 0 0 16 5 4 0 0 0 0 5 0 0 0 100 6 0 0 4 317 154 112 0 0 0 0 607 0 0 0 100 7 0 0 7 23 4 27 0 1 0 0 273 0 0 0 100 March 2, 2026 at 06:52:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1125 0 84 2881 202 1107 30 175 133 44 3011 4 4 0 92 1 3520 0 28 621 16 1033 30 164 137 54 6497 6 4 0 90 2 43561 0 497 487 16 921 33 159 142 64 5196 14 12 0 74 3 8211 0 34 576 7 893 27 159 144 60 3533 6 4 0 91 4 2143 0 120 475 3 952 22 173 149 66 4367 3 2 0 94 5 2884 0 26 452 1 668 14 126 122 61 1978 3 2 0 96 6 1459 0 31 710 124 851 23 149 87 57 4276 5 3 0 92 7 728 0 22 398 4 646 22 100 70 29 3039 3 2 0 95 March 2, 2026 at 06:52:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 98 2313 204 126 0 4 5 0 10 0 2 0 98 1 18 0 14 38 3 30 1 5 7 0 286 0 0 0 99 2 40 0 0 137 56 118 0 2 1 0 306 0 0 0 100 3 22 0 0 28 3 6 0 2 3 0 10 0 0 0 100 4 20 0 0 30 4 36 1 1 3 0 1106 0 0 0 99 5 2 0 0 27 2 2 0 1 3 0 9 0 0 0 100 6 0 0 7 230 104 10 0 2 1 0 613 0 0 0 100 7 0 0 7 32 4 12 0 1 1 0 263 0 0 0 100 March 2, 2026 at 06:52:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2416 202 192 0 20 74 0 0 0 2 0 98 1 0 0 476 52 1 88 0 18 76 0 266 0 1 0 99 2 0 0 0 235 57 207 0 14 70 0 303 0 0 0 99 3 0 0 0 201 72 107 0 16 86 0 0 0 0 0 100 4 1 0 0 156 4 170 0 23 96 0 1087 0 1 0 99 5 0 0 0 188 4 199 0 13 63 0 3 0 0 0 100 6 0 0 4 353 104 142 0 22 81 0 599 0 0 0 100 7 8 0 7 122 2 87 0 16 62 0 306 0 0 0 100 March 2, 2026 at 06:52:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 202 116 0 0 0 0 0 0 0 0 100 1 0 0 14 7 1 4 0 0 0 0 266 0 0 0 100 2 0 0 0 119 57 115 0 1 0 0 303 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 1 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 1085 0 0 0 100 5 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 6 0 0 4 215 104 8 0 0 0 0 601 0 0 0 100 7 0 0 7 13 3 8 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:52:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1029 0 176 2560 203 516 13 91 51 41 2094 1 2 0 97 1 880 0 23 247 2 369 8 74 61 34 2414 2 2 0 96 2 8287 0 300 321 43 513 11 84 102 64 3134 3 3 0 94 3 5231 0 39 358 11 498 7 110 101 46 2128 3 2 0 95 4 636 0 15 301 10 544 11 117 55 71 3609 1 1 0 97 5 233 0 11 247 7 381 2 87 44 35 1567 1 1 0 98 6 28241 0 14 470 104 374 10 69 31 38 2084 8 4 0 88 7 173 0 39 219 4 307 6 66 34 30 1485 1 2 0 97 March 2, 2026 at 06:52:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1528 0 102 2565 204 550 22 78 50 4 1877 3 3 0 94 1 1536 0 191 341 3 608 21 94 52 17 2399 2 3 0 95 2 3004 0 9 247 2 440 12 71 58 17 1582 2 2 0 96 3 4414 0 3 327 1 439 23 64 78 14 2350 4 2 0 94 4 471 0 3 284 8 537 14 82 43 21 2586 3 1 0 95 5 613 0 0 200 2 309 8 57 35 13 956 1 1 0 98 6 5276 0 9 478 106 537 17 76 26 8 1644 5 4 0 92 7 1790 0 18 259 44 383 9 42 30 10 1963 4 1 0 96 March 2, 2026 at 06:52:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2393 218 154 0 2 2 0 9 0 1 0 99 1 0 0 476 15 1 10 0 1 2 0 266 0 1 0 99 2 0 0 0 85 2 6 0 1 0 0 294 0 0 0 100 3 0 0 0 83 1 8 0 1 0 0 18 0 0 0 100 4 40 0 0 95 9 44 1 0 0 0 1095 0 0 0 99 5 0 0 0 83 2 6 0 1 0 0 3 0 0 0 100 6 0 0 4 286 103 6 0 1 0 0 0 0 0 0 100 7 0 0 7 154 38 78 0 1 0 0 864 0 0 0 100 March 2, 2026 at 06:52:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2403 252 301 0 12 76 0 1 0 1 0 99 1 0 0 14 39 1 69 0 19 61 0 266 0 0 0 100 2 0 0 0 43 2 67 0 17 53 0 294 0 0 0 100 3 0 0 0 111 54 105 0 17 82 0 0 0 0 0 100 4 0 0 0 55 8 110 0 14 66 0 1094 0 0 0 99 5 0 0 0 106 0 203 0 15 52 0 0 0 0 0 100 6 0 0 4 258 104 98 0 17 91 0 1 0 0 0 100 7 0 0 7 53 4 87 0 13 70 0 860 0 0 0 100 March 2, 2026 at 06:52:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 251 210 0 0 0 0 0 0 0 0 100 1 0 0 14 6 1 4 0 0 0 0 266 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 21 8 44 1 0 1 0 1096 0 0 0 100 5 0 0 0 11 1 6 0 0 0 0 2 0 0 0 100 6 0 0 4 218 103 16 0 1 0 0 0 0 0 0 100 7 0 0 7 14 4 10 0 1 0 0 860 0 0 0 100 March 2, 2026 at 06:52:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2206 0 197 2815 215 1050 32 176 93 57 4640 4 4 0 92 1 3773 0 219 566 4 1040 39 207 97 61 6208 9 4 0 87 2 1071 0 32 533 21 912 42 183 75 60 3346 4 3 0 93 3 41210 0 320 533 5 1024 42 195 163 63 4933 16 10 0 73 4 6528 0 37 609 8 999 37 161 158 65 4402 4 4 0 92 5 2980 0 4 451 7 713 16 124 94 58 2799 4 2 0 94 6 4615 0 10 799 114 923 26 185 137 40 3224 4 3 0 94 7 1332 0 18 423 10 676 11 116 103 48 3097 2 2 0 96 March 2, 2026 at 06:52:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2316 200 112 0 0 0 0 17 0 0 0 100 1 2 0 14 23 2 6 0 0 0 0 283 0 0 0 100 2 26 0 70 84 36 76 0 0 7 0 303 0 1 0 99 3 13 0 0 66 20 50 1 3 6 0 15 0 0 0 100 4 6 0 0 29 3 42 1 2 2 0 1108 0 0 0 100 5 40 0 7 36 6 24 0 3 0 0 18 0 0 0 100 6 19 0 4 227 103 10 0 1 0 0 10 0 0 0 100 7 9 0 7 32 4 25 0 3 0 0 887 0 0 0 100 March 2, 2026 at 06:52:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2380 200 120 0 1 1 0 0 0 1 0 99 1 0 0 14 83 4 6 0 0 1 0 267 0 0 0 100 2 0 0 42 81 3 8 0 0 3 0 294 0 1 0 99 3 0 0 462 117 52 108 0 1 2 0 0 0 1 0 99 4 0 0 0 83 3 32 1 0 2 0 1086 0 0 0 100 5 0 0 0 92 6 12 0 1 1 0 8 0 0 0 100 6 0 0 3 284 103 6 0 1 1 0 0 0 0 0 100 7 0 0 7 88 5 10 0 0 1 0 860 0 0 0 100 March 2, 2026 at 06:52:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2353 200 188 1 15 66 0 0 0 1 0 99 1 0 0 14 43 2 73 1 18 56 0 266 0 0 0 100 2 0 0 0 55 2 91 1 14 66 0 294 0 0 0 100 3 0 0 0 239 121 225 1 21 95 0 0 0 0 0 100 4 0 0 0 61 2 135 1 21 88 0 1086 0 0 0 100 5 0 0 0 142 9 245 0 21 58 0 12 0 0 0 100 6 0 0 4 267 103 120 1 23 95 0 0 0 0 0 100 7 0 0 7 60 4 104 0 12 85 0 859 0 0 0 100 March 2, 2026 at 06:52:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3539 0 386 2808 200 1034 36 175 120 71 3167 6 4 0 91 1 1138 0 143 588 10 1077 34 197 87 63 3725 3 2 0 95 2 35440 0 14 556 4 869 32 136 89 62 4713 11 8 0 81 3 5849 0 18 560 37 873 26 142 113 33 4093 5 4 0 92 4 4304 0 197 459 3 817 25 138 123 51 4546 4 4 0 92 5 6348 0 28 498 10 729 25 129 153 60 3073 3 4 0 93 6 2811 0 33 779 107 880 18 141 100 51 4207 5 2 0 93 7 414 0 23 402 4 680 16 107 85 43 3351 2 2 0 96 March 2, 2026 at 06:52:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 494 0 45 2381 201 242 7 36 18 3 641 2 1 0 97 1 206 0 14 104 6 147 8 27 9 3 718 3 0 0 97 2 429 0 0 160 32 209 13 27 34 1 530 1 0 0 99 3 69 0 1 105 21 125 8 22 10 1 571 1 0 0 98 4 677 0 70 73 3 146 16 27 21 1 1452 1 2 0 98 5 225 0 0 89 11 106 10 21 14 4 428 1 1 0 98 6 903 0 4 283 106 119 9 22 45 6 555 1 0 0 99 7 586 0 14 85 5 113 6 18 11 1 1114 1 0 0 99 March 2, 2026 at 06:52:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2340 200 106 0 1 0 0 0 0 1 0 99 1 0 0 14 43 2 4 0 0 0 0 266 0 0 0 100 2 0 0 0 49 3 8 0 0 0 0 4 0 0 0 100 3 0 0 0 151 53 108 0 0 0 0 294 0 0 0 100 4 0 0 14 54 3 42 2 1 6 0 1109 0 1 0 99 5 0 0 238 23 6 16 0 0 4 0 9 0 1 0 99 6 0 0 3 251 104 8 0 2 0 0 300 0 0 0 100 7 0 0 7 48 3 10 0 1 0 0 563 0 0 0 100 March 2, 2026 at 06:53:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2335 200 102 0 0 0 0 0 0 1 0 99 1 0 0 14 41 2 4 0 0 0 0 266 0 0 0 100 2 0 0 0 43 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 151 53 118 0 1 0 0 294 0 0 0 100 4 0 0 14 45 3 36 1 0 0 0 1089 0 1 0 99 5 0 0 224 28 9 22 0 0 1 0 13 0 0 0 100 6 0 0 4 253 103 12 0 0 0 0 300 0 0 0 100 7 0 0 7 44 3 6 0 0 0 0 560 0 0 0 100 March 2, 2026 at 06:53:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2351 200 157 0 13 64 0 0 0 1 0 99 1 0 0 14 52 2 86 1 18 70 0 266 0 0 0 100 2 0 0 0 55 0 95 0 11 91 0 0 0 0 0 100 3 0 0 0 203 104 178 0 14 56 0 294 0 0 0 100 4 0 0 14 55 3 123 1 14 101 0 1089 0 1 0 99 5 0 0 0 98 6 169 0 10 60 0 8 0 0 0 100 6 0 0 4 300 104 138 0 13 81 0 301 0 0 0 100 7 0 0 7 56 3 94 0 8 77 0 560 0 0 0 100 March 2, 2026 at 06:53:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 34800 0 97 2986 229 1246 49 214 90 54 4369 12 9 0 79 1 3959 0 171 661 3 1107 31 210 114 61 5531 6 3 0 91 2 2638 0 365 496 2 913 18 192 97 54 3212 3 3 0 94 3 1343 0 9 638 26 1132 42 218 139 86 3807 5 3 0 92 4 9128 0 23 517 3 832 44 163 176 48 5054 7 4 0 89 5 9442 0 131 523 7 852 21 144 162 62 5230 7 5 0 88 6 1240 0 20 805 105 1079 29 195 100 66 4032 3 3 0 94 7 1430 0 39 463 4 840 21 143 94 61 3935 3 3 0 94 March 2, 2026 at 06:53:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 3 2380 257 151 0 2 0 0 303 0 0 0 99 1 2 0 21 21 3 38 0 1 1 0 1361 0 0 0 100 2 0 0 0 26 2 10 0 0 0 0 7 0 0 0 100 3 0 0 0 104 2 88 0 0 0 0 8 0 0 0 100 4 0 0 0 28 2 14 0 0 1 0 12 0 0 0 100 5 0 0 0 33 6 18 0 2 7 0 0 0 0 0 100 6 0 0 4 223 103 4 0 0 0 0 300 0 0 0 100 7 0 0 77 18 3 15 0 1 6 0 563 0 1 0 99 March 2, 2026 at 06:53:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2439 257 217 0 0 0 0 303 0 1 0 99 1 0 0 14 86 3 38 2 0 1 0 1352 0 0 0 99 2 0 0 0 80 0 4 0 1 0 0 0 0 0 0 100 3 0 0 0 90 2 14 0 1 0 0 0 0 0 0 100 4 0 0 0 80 2 2 0 0 0 0 0 0 0 0 100 5 0 0 462 18 1 8 0 0 2 0 2 0 1 0 99 6 0 0 3 288 103 14 0 1 0 0 300 0 0 0 100 7 0 0 49 78 3 8 0 0 2 0 560 0 1 0 99 March 2, 2026 at 06:53:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2369 257 217 0 0 1 0 303 0 1 0 99 1 0 0 14 14 4 36 1 0 2 0 1351 0 0 0 100 2 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 21 3 14 0 0 1 0 0 0 0 0 100 4 0 0 0 11 3 2 0 0 1 0 0 0 0 0 100 5 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 6 0 0 7 212 103 6 0 1 0 0 300 0 0 0 100 7 0 0 7 13 4 6 0 0 1 0 559 0 0 0 100 March 2, 2026 at 06:53:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3506 0 255 2950 234 1250 37 216 223 69 5349 8 5 0 87 1 4700 0 146 576 5 1040 33 195 185 50 5759 6 6 0 88 2 1313 0 22 577 8 981 24 175 223 54 2462 3 2 0 95 3 30499 0 4 643 72 976 40 173 156 37 3671 11 6 0 83 4 10815 0 308 505 8 966 21 192 244 52 4514 4 5 0 90 5 9635 0 38 630 3 885 28 145 249 57 3890 9 4 0 87 6 1734 0 28 867 112 1240 27 207 212 77 3771 3 3 0 94 7 1540 0 11 516 7 888 18 154 150 58 3371 3 2 0 96 March 2, 2026 at 06:53:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 87 2314 200 124 0 1 6 0 16 0 2 0 98 1 4 0 14 33 4 54 1 2 6 0 1661 0 1 0 99 2 25 0 0 27 1 8 0 0 0 0 10 0 0 0 100 3 3 0 7 31 3 16 0 2 0 0 9 0 0 0 100 4 0 0 0 35 4 20 0 4 0 0 20 0 0 0 100 5 1 0 0 27 1 7 0 3 0 0 17 0 0 0 100 6 53 0 11 346 162 130 0 1 1 0 585 0 0 0 100 7 9 0 0 26 1 7 1 2 0 0 324 0 0 0 100 March 2, 2026 at 06:53:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 38 2357 201 89 0 3 3 0 23 0 1 0 98 1 0 0 364 46 4 68 2 2 3 0 1646 0 1 0 99 2 0 0 0 68 0 8 0 0 0 0 5 0 0 0 100 3 0 0 0 69 2 12 0 0 0 0 8 0 0 0 100 4 0 0 0 79 3 24 0 1 0 0 14 0 0 0 100 5 0 0 0 71 7 6 0 0 0 0 0 0 0 0 100 6 0 0 11 387 164 126 0 0 0 0 574 0 0 0 100 7 0 0 0 66 1 9 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2303 200 105 0 0 0 0 0 0 1 0 99 1 0 0 14 34 4 48 1 1 0 0 1648 0 0 0 99 2 0 0 0 25 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 24 1 6 0 1 0 0 0 0 0 0 100 4 0 0 0 30 1 8 0 0 0 0 0 0 0 0 100 5 0 0 0 27 2 4 0 0 0 0 1 0 0 0 100 6 7 0 11 345 162 122 1 0 0 0 569 0 0 0 100 7 0 0 0 23 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1794 0 126 2455 200 377 5 59 28 38 1676 2 2 0 96 1 305 0 18 186 4 315 6 60 47 36 2991 1 1 0 98 2 179 0 22 175 0 298 3 64 38 30 1710 1 2 0 98 3 381 0 14 157 1 249 5 54 34 20 939 1 1 0 98 4 4650 0 16 143 1 223 10 50 92 25 1281 1 2 0 96 5 2307 0 24 137 1 217 2 42 42 25 896 1 1 0 98 6 2808 0 25 529 164 318 6 37 40 17 1331 2 1 0 97 7 1017 0 181 128 2 227 0 47 55 27 780 1 1 0 98 March 2, 2026 at 06:53:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 891 0 90 2831 204 1059 22 139 166 40 2861 4 4 0 93 1 1484 0 132 552 7 1026 39 156 153 26 5586 6 3 0 91 2 1478 0 190 395 1 700 20 129 127 22 3633 4 3 0 93 3 990 0 4 566 65 915 17 140 165 39 2464 3 2 0 94 4 37704 0 17 482 6 861 26 132 188 30 3463 12 10 0 79 5 6169 0 91 452 9 676 12 86 138 29 2236 4 4 0 92 6 658 0 23 735 112 986 21 139 178 28 3082 3 2 0 95 7 1124 0 4 478 35 779 8 96 137 28 2292 4 2 0 95 March 2, 2026 at 06:53:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 46 2387 217 138 0 2 2 0 0 0 1 0 99 1 2 0 476 18 3 12 1 1 2 0 568 0 1 0 99 2 0 0 0 84 1 36 1 1 1 0 1098 0 0 0 99 3 0 0 0 81 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 84 1 8 0 1 0 0 0 0 0 0 100 5 0 0 0 89 0 10 0 0 0 0 0 0 0 0 100 6 0 0 11 297 109 18 0 1 0 0 859 0 0 0 100 7 40 0 0 159 39 80 0 1 0 0 8 0 0 0 100 March 2, 2026 at 06:53:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2356 250 205 0 0 0 0 0 0 0 0 100 1 0 0 14 9 3 8 0 1 0 0 566 0 0 0 100 2 0 0 0 14 1 38 1 0 1 0 1103 0 0 0 100 3 0 0 0 11 1 8 0 0 0 0 7 0 0 0 100 4 0 0 0 17 3 16 0 1 0 0 14 0 0 0 100 5 0 0 0 27 7 18 0 2 1 0 0 0 0 0 100 6 0 0 11 221 108 14 0 0 0 0 853 0 0 0 100 7 0 0 0 23 6 21 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:53:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2353 250 202 0 0 0 0 0 0 0 0 100 1 0 0 14 9 3 6 0 0 0 0 566 0 0 0 100 2 0 0 0 10 1 34 1 0 1 0 1099 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 15 0 10 0 0 0 0 0 0 0 0 100 6 0 0 11 223 109 18 0 0 0 0 856 0 0 0 100 7 0 0 0 19 6 14 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:53:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3136 0 242 2882 223 1163 40 208 117 60 4148 6 4 0 90 1 1365 0 24 561 5 932 32 186 96 56 3747 4 3 0 94 2 1043 0 15 535 12 916 30 160 71 52 3646 3 2 0 95 3 1187 0 19 528 3 912 37 193 88 41 3839 3 3 0 94 4 9223 0 313 494 6 901 30 168 151 64 4119 6 5 0 89 5 42735 0 55 555 4 676 33 117 169 37 5073 17 10 0 74 6 3678 0 144 776 123 1076 31 195 110 93 5906 4 3 0 93 7 1118 0 30 499 7 870 19 152 107 65 3005 3 2 0 95 March 2, 2026 at 06:53:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 24 2355 203 176 0 11 71 0 15 0 1 0 99 1 24 0 14 89 6 134 2 24 87 0 583 0 1 0 99 2 8 0 0 69 3 118 1 19 69 0 1114 0 0 0 99 3 0 0 0 130 60 96 0 19 72 0 25 0 0 0 100 4 1 0 0 78 1 115 0 21 83 0 15 0 0 0 100 5 1 0 0 71 3 87 0 17 55 0 7 0 0 0 100 6 75 0 11 443 164 321 0 19 70 0 875 0 0 0 99 7 1 0 70 62 1 101 0 12 62 0 14 0 1 0 99 March 2, 2026 at 06:53:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2375 200 104 0 0 0 0 0 0 1 0 99 1 0 0 476 16 2 8 0 1 2 0 566 0 1 0 99 2 0 0 0 80 1 32 1 0 0 0 1092 0 0 0 100 3 0 0 0 84 2 8 0 0 0 0 1 0 0 0 100 4 0 0 0 78 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 87 0 10 0 1 0 0 0 0 0 0 100 6 0 0 11 404 164 126 0 0 0 0 864 0 0 0 100 7 0 0 42 75 0 4 0 0 2 0 0 0 1 0 99 March 2, 2026 at 06:53:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 118 0 1 0 0 0 0 0 0 100 1 0 0 14 7 2 4 0 0 0 0 567 0 0 0 100 2 0 0 0 11 1 36 0 0 1 0 1097 0 0 0 100 3 0 0 0 85 38 84 0 1 0 0 8 0 0 0 100 4 0 0 0 15 3 14 0 0 0 0 14 0 0 0 100 5 0 0 0 21 6 10 0 0 1 0 0 0 0 0 100 6 0 0 11 266 131 58 0 0 0 0 867 0 0 0 100 7 0 0 0 14 0 13 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 29046 0 190 2654 200 600 12 84 96 52 2808 10 6 0 84 1 941 0 37 307 8 532 8 121 59 57 3481 2 1 0 96 2 350 0 9 295 1 486 8 92 31 47 2559 1 1 0 98 3 1079 0 192 331 45 530 7 100 62 51 1568 1 1 0 97 4 1287 0 136 221 4 378 8 101 44 44 1912 2 3 0 96 5 222 0 4 220 3 308 5 66 33 29 1017 1 1 0 99 6 683 0 24 479 116 474 5 86 76 51 3625 2 2 0 97 7 4739 0 15 211 0 347 6 69 117 48 2037 2 3 0 95 March 2, 2026 at 06:53:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16415 0 298 2566 202 570 18 70 75 14 2091 8 7 0 85 1 3742 0 16 362 10 644 21 85 59 20 3259 4 2 0 94 2 2337 0 8 394 4 597 10 69 55 13 3048 2 2 0 96 3 670 0 3 303 2 553 16 75 34 23 1808 2 1 0 96 4 731 0 0 243 2 415 7 58 50 9 1642 2 1 0 97 5 340 0 0 260 24 415 7 46 19 4 1464 3 1 0 96 6 688 0 9 446 110 452 14 62 42 6 2201 4 1 0 95 7 642 0 0 239 17 398 3 34 59 5 952 2 1 0 97 March 2, 2026 at 06:53:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 46 2418 200 187 0 16 110 0 0 0 2 0 98 1 42 0 476 145 8 230 0 15 67 0 575 0 1 0 99 2 1 0 0 123 1 120 1 17 73 0 1089 0 1 0 99 3 0 0 0 187 56 109 0 18 81 0 0 0 0 0 100 4 0 0 0 120 1 84 0 14 65 0 0 0 0 0 100 5 0 0 0 114 0 60 0 14 41 0 0 0 0 0 100 6 0 0 10 337 109 101 0 13 87 0 857 0 0 0 100 7 0 0 0 222 51 189 1 16 78 0 1 0 0 0 100 March 2, 2026 at 06:53:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 106 0 1 0 0 0 0 0 0 100 1 0 0 14 19 8 16 0 0 0 0 576 0 0 0 100 2 0 0 0 10 1 34 1 1 1 0 1089 0 0 0 100 3 0 0 0 13 1 14 0 1 0 0 0 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 17 2 8 0 0 0 0 0 0 0 0 100 6 0 0 11 224 110 18 0 0 0 0 856 0 0 0 100 7 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 112 0 0 0 0 0 0 0 0 100 1 0 0 14 19 8 16 0 0 0 0 575 0 0 0 100 2 0 0 0 13 1 36 1 0 0 0 1094 0 0 0 100 3 0 0 0 10 1 8 0 0 0 0 7 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 22 7 16 0 1 0 0 12 0 0 0 100 6 0 0 11 223 109 16 1 0 0 0 854 0 0 0 100 7 0 0 0 108 50 105 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:53:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1405 0 210 2793 201 960 23 181 79 68 2802 5 3 0 92 1 5507 0 59 645 17 1053 35 194 115 68 4179 5 4 0 91 2 2036 0 128 433 3 789 19 139 120 56 3676 3 3 0 95 3 3860 0 194 466 4 810 27 151 123 51 3554 3 3 0 94 4 43007 0 32 531 5 791 24 133 170 60 4339 13 9 0 78 5 3468 0 24 387 3 617 16 128 109 37 4503 3 2 0 95 6 1850 0 16 676 130 804 10 155 84 57 4295 4 2 0 94 7 2623 0 191 400 15 694 22 106 92 58 3641 5 3 0 92 March 2, 2026 at 06:53:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 42 0 21 2330 205 126 0 2 0 0 45 0 1 0 99 1 2 0 21 29 4 12 0 2 9 0 577 0 0 0 99 2 23 0 0 29 3 36 1 1 2 0 1107 0 0 0 100 3 0 0 0 25 2 5 0 1 1 0 14 0 0 0 100 4 0 0 0 26 2 4 0 1 1 0 2 0 0 0 100 5 11 0 70 22 3 10 0 0 8 0 27 0 1 0 99 6 13 0 14 352 161 132 0 1 1 0 865 0 0 0 100 7 2 0 0 33 2 17 0 2 1 0 22 0 0 0 100 March 2, 2026 at 06:53:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2431 207 209 0 15 88 0 9 0 1 0 99 1 0 0 476 107 3 181 0 16 67 0 565 0 1 0 99 2 0 0 0 130 1 132 1 16 77 0 1087 0 1 0 99 3 0 0 0 172 55 86 0 12 55 0 0 0 0 0 100 4 5 0 0 121 2 244 0 15 62 0 331 0 0 0 100 5 0 0 42 110 1 67 0 11 40 0 1 0 1 0 99 6 0 0 11 429 159 187 0 9 56 0 856 0 0 0 100 7 0 0 0 116 0 79 0 11 62 0 0 0 0 0 100 March 2, 2026 at 06:53:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 208 136 0 1 0 0 13 0 0 0 99 1 0 0 14 12 4 10 0 0 0 0 568 0 0 0 100 2 0 0 0 10 1 34 1 0 0 0 1086 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 4 3 0 0 7 1 4 0 1 0 0 7 0 0 0 100 5 0 0 0 12 1 8 0 1 0 0 5 0 0 0 100 6 0 0 11 322 158 116 1 0 0 0 855 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2528 0 88 2872 210 1086 38 162 88 81 5190 5 4 0 91 1 1237 0 25 572 6 998 24 179 102 54 3351 3 2 0 95 2 1539 0 126 495 2 843 31 138 66 51 3956 3 2 0 95 3 1856 0 207 429 2 819 26 134 106 51 3384 3 3 0 94 4 36999 0 133 415 2 701 20 118 101 49 3658 12 9 0 79 5 5695 0 186 422 21 717 18 123 92 58 3526 3 3 0 94 6 7474 0 38 786 144 824 28 121 118 55 4840 6 3 0 91 7 6062 0 24 405 1 572 15 93 113 65 2265 5 3 0 92 March 2, 2026 at 06:53:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 101 2308 201 106 0 2 6 0 4 0 1 0 99 1 9 0 0 80 21 73 1 5 8 0 338 2 0 0 98 2 54 0 0 34 1 46 1 3 1 0 1131 0 0 0 99 3 10 0 21 29 2 11 2 1 1 0 279 2 0 0 98 4 40 0 0 97 36 78 0 2 0 0 21 0 0 0 100 5 0 0 0 27 1 4 0 1 0 0 2 0 0 0 100 6 9 0 11 239 108 20 0 1 1 0 862 0 0 0 100 7 13 0 0 30 3 10 0 0 1 0 15 0 0 0 100 March 2, 2026 at 06:53:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2337 200 105 0 1 2 0 0 0 1 0 99 1 0 0 238 126 52 122 0 1 3 0 300 0 0 0 100 2 0 0 0 52 2 46 0 1 0 0 1089 0 0 0 100 3 0 0 14 44 1 6 0 0 0 0 266 0 0 0 100 4 0 0 0 55 7 14 0 1 0 0 9 0 0 0 100 5 0 0 0 43 0 2 0 0 0 0 0 0 0 0 100 6 0 0 11 258 109 16 0 0 0 0 859 0 0 0 100 7 0 0 0 43 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 241 2361 201 182 0 22 89 0 0 0 1 0 99 1 0 0 0 299 52 370 0 20 87 0 300 0 0 0 100 2 0 0 0 92 2 127 1 16 86 0 1090 0 0 0 99 3 0 0 14 162 67 115 0 16 77 0 266 0 1 0 99 4 0 0 0 114 7 141 0 18 64 0 10 0 0 0 100 5 0 0 0 85 0 86 0 12 67 0 0 0 0 0 100 6 0 0 11 301 108 105 1 20 63 0 854 0 0 0 100 7 0 0 0 76 1 71 0 11 54 0 1 0 0 0 100 March 2, 2026 at 06:53:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2304 200 94 0 2 0 0 0 0 1 0 99 1 0 0 0 129 52 120 0 2 0 0 300 0 0 0 100 2 0 0 0 14 2 36 1 0 0 0 1090 0 0 0 100 3 0 0 14 10 1 6 1 0 0 0 266 0 0 0 100 4 0 0 0 20 7 12 0 0 0 0 9 0 0 0 100 5 0 0 0 11 1 4 0 0 0 0 1 0 0 0 100 6 0 0 11 224 109 16 0 0 0 0 855 0 0 0 100 7 0 0 0 9 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3097 0 412 2840 203 1061 25 181 101 58 3971 5 4 0 91 1 1015 0 16 699 22 1171 39 185 96 60 4677 4 3 0 92 2 41879 0 198 585 32 924 29 142 151 51 4321 12 10 0 78 3 12870 0 168 653 2 991 31 171 186 69 6982 7 5 0 88 4 1118 0 14 591 7 1068 30 203 103 64 4365 3 2 0 95 5 575 0 13 477 8 815 24 153 104 65 2771 5 2 0 94 6 1511 0 27 745 110 999 30 190 108 73 4503 4 2 0 94 7 1796 0 33 404 2 695 21 121 131 28 3124 5 3 0 91 March 2, 2026 at 06:53:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 73 2307 200 75 0 4 5 0 0 0 2 0 98 1 0 0 0 60 2 42 0 4 6 0 300 0 0 0 100 2 0 0 0 122 50 104 0 0 0 0 0 0 0 0 100 3 2 0 14 19 2 6 0 0 0 0 266 0 0 0 100 4 0 0 0 22 2 34 1 0 0 0 1091 0 0 0 100 5 0 0 7 20 0 4 0 1 0 0 0 0 0 0 100 6 0 0 11 237 109 18 0 0 0 0 859 0 0 0 100 7 40 0 0 35 6 24 0 2 0 0 9 0 0 0 100 March 2, 2026 at 06:53:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 49 2370 200 112 0 1 2 0 0 0 1 0 99 1 0 0 462 21 3 10 0 1 3 0 300 0 1 0 99 2 0 0 0 182 51 102 0 1 1 0 0 0 0 0 100 3 0 0 14 83 3 6 0 0 1 0 266 0 0 0 100 4 0 0 0 83 3 32 0 0 1 0 1089 0 0 0 99 5 0 0 0 83 1 2 0 0 1 0 0 0 0 0 100 6 0 0 14 296 109 18 0 1 1 0 856 0 0 0 100 7 0 0 0 94 7 14 0 0 1 0 9 0 0 0 100 March 2, 2026 at 06:53:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2345 200 191 0 14 65 0 0 0 0 0 100 1 0 0 0 101 2 191 0 16 87 0 300 0 0 0 100 2 0 0 0 144 51 174 0 11 63 0 1 0 0 0 100 3 0 0 14 110 57 95 1 15 74 0 266 0 0 0 100 4 0 0 0 50 2 115 1 15 72 0 1090 0 0 0 100 5 0 0 0 44 1 77 0 12 81 0 1 0 0 0 100 6 0 0 11 272 110 114 1 17 72 0 855 0 0 0 100 7 0 0 0 66 6 107 0 16 60 0 9 0 0 0 100 March 2, 2026 at 06:53:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2479 0 206 2896 201 1163 51 208 129 59 4612 6 4 0 90 1 3107 0 21 678 3 1052 34 208 102 48 4117 7 3 0 90 2 44939 0 374 668 38 1135 64 186 176 75 6288 16 12 0 72 3 6958 0 42 670 4 1006 34 209 153 58 4859 5 4 0 91 4 1106 0 20 555 7 1005 41 193 131 69 5823 4 3 0 94 5 2759 0 35 498 9 847 23 155 108 55 4104 4 2 0 93 6 1330 0 150 706 107 919 48 167 72 50 3192 3 3 0 94 7 617 0 14 443 5 742 22 123 86 39 2632 3 2 0 95 March 2, 2026 at 06:53:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 17 2321 202 119 0 1 1 0 23 0 0 0 100 1 1 0 0 29 2 12 1 0 0 0 305 0 0 0 100 2 22 0 0 137 54 128 0 1 1 0 43 0 0 0 100 3 43 0 15 40 7 28 0 2 0 0 295 0 0 0 100 4 0 0 7 35 5 44 1 1 1 0 1375 0 0 0 100 5 25 0 70 25 9 4 0 1 4 0 10 0 1 0 99 6 0 0 4 239 108 20 0 2 5 0 616 0 0 0 100 7 6 0 7 31 1 23 0 5 0 0 27 0 0 0 100 March 2, 2026 at 06:53:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2357 200 114 0 1 0 0 0 0 1 0 99 1 0 0 0 70 2 16 0 2 0 0 300 0 0 0 100 2 0 0 0 162 50 102 0 0 0 0 0 0 0 0 100 3 0 0 14 75 8 18 0 0 0 0 275 0 0 0 100 4 0 0 7 69 5 38 1 0 1 0 1374 0 0 0 100 5 0 0 35 61 1 7 0 2 3 0 1 0 1 0 99 6 0 0 353 225 106 14 0 0 3 0 593 0 1 0 99 7 0 0 0 64 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2319 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 27 2 6 0 0 0 0 300 0 0 0 100 2 0 0 0 130 51 114 0 1 1 0 1 0 0 0 100 3 0 0 14 36 8 18 1 0 0 0 275 0 0 0 100 4 0 0 7 28 4 36 1 0 0 0 1350 0 0 0 100 5 0 0 112 9 0 5 0 0 0 0 0 0 0 0 100 6 0 0 3 237 107 12 1 0 0 0 597 0 0 0 100 7 0 0 0 23 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1130 0 244 2548 200 541 15 92 104 29 1259 1 2 0 96 1 651 0 6 328 4 576 10 102 147 29 1549 1 2 0 97 2 7491 0 135 328 38 504 12 79 190 41 3932 2 3 0 94 3 2361 0 33 360 65 516 4 108 172 45 2090 1 2 0 97 4 2184 0 38 277 4 485 2 84 135 35 2580 3 2 0 96 5 896 0 28 250 0 419 5 83 124 30 1764 2 2 0 96 6 758 0 14 529 114 479 7 101 157 27 1963 1 2 0 97 7 194 0 1 192 6 273 5 54 79 18 965 1 1 0 99 March 2, 2026 at 06:53:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 668 0 36 2648 202 731 26 139 59 24 2165 4 2 0 94 1 636 0 8 332 2 563 21 110 41 18 2391 4 2 0 95 2 3545 0 2 320 3 514 23 96 89 16 2239 2 2 0 95 3 4986 0 29 421 3 605 25 121 88 15 2755 6 2 0 92 4 861 0 7 348 6 640 27 100 40 33 4318 3 2 0 96 5 1385 0 185 312 2 575 28 103 41 28 2010 2 2 0 96 6 34502 0 197 546 131 593 24 105 55 28 2647 10 8 0 82 7 1108 0 4 355 24 592 19 74 62 28 2377 3 1 0 96 March 2, 2026 at 06:53:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 3 2407 222 158 0 1 0 0 10 0 1 0 99 1 0 0 0 85 2 6 0 0 0 0 300 0 0 0 100 2 0 0 0 89 2 18 0 1 0 0 14 0 0 0 100 3 2 0 14 86 2 12 0 0 0 0 273 0 0 0 100 4 0 0 7 95 4 50 1 1 0 0 1355 0 0 0 100 5 0 0 0 87 7 2 0 0 0 0 0 0 0 0 100 6 0 0 46 285 105 10 0 0 2 0 300 0 1 0 99 7 0 0 462 89 36 81 0 1 2 0 295 0 1 0 99 March 2, 2026 at 06:53:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2363 256 148 0 2 0 0 9 0 0 0 99 1 0 0 0 85 2 78 0 1 0 0 300 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 3 0 0 14 9 2 6 1 0 0 0 266 0 0 0 100 4 0 0 7 12 4 36 1 0 1 0 1347 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 4 217 106 10 0 0 0 0 302 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 294 0 0 0 100 March 2, 2026 at 06:53:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2366 256 222 0 0 1 0 9 0 0 0 99 1 0 0 0 12 3 6 0 0 1 0 300 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 14 10 3 6 0 0 1 0 266 0 0 0 100 4 0 0 7 16 5 38 1 1 2 0 1347 0 0 0 100 5 0 0 0 13 1 10 0 1 1 0 0 0 0 0 100 6 0 0 4 215 105 8 0 0 1 0 300 0 0 0 100 7 0 0 0 11 2 6 0 1 0 0 294 0 0 0 100 March 2, 2026 at 06:53:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37472 0 96 3013 222 1095 39 187 193 40 3651 14 9 0 77 1 2770 0 129 651 9 1122 40 224 190 42 4156 6 3 0 91 2 4292 0 126 535 1 931 21 156 204 69 3190 4 4 0 93 3 8282 0 22 659 72 1069 44 221 220 63 4678 7 4 0 89 4 6757 0 61 652 7 1052 24 175 245 60 5789 5 5 0 91 5 2154 0 380 486 12 931 19 167 176 58 4097 3 4 0 93 6 965 0 16 774 110 1041 26 187 158 53 3794 4 2 0 94 7 941 0 2 518 3 953 25 159 177 60 4602 3 2 0 95 March 2, 2026 at 06:53:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 17 2319 203 116 0 3 0 0 14 0 0 0 99 1 41 0 0 33 4 22 0 3 0 0 324 0 0 0 100 2 0 0 0 23 1 5 0 1 1 0 13 0 0 0 100 3 0 0 7 129 50 116 0 3 0 0 13 0 0 0 100 4 12 0 21 30 6 16 0 2 0 0 547 0 0 0 100 5 1 0 70 17 1 42 0 4 4 0 1104 0 1 0 99 6 3 0 4 235 106 14 0 1 2 0 316 0 0 0 100 7 25 0 0 25 1 11 0 1 5 0 310 0 0 0 100 March 2, 2026 at 06:53:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2379 200 120 0 2 0 0 0 0 1 0 99 1 0 0 0 92 7 16 0 0 0 0 308 0 0 0 100 2 0 0 0 85 2 8 0 0 0 0 7 0 0 0 100 3 0 0 0 187 51 110 1 0 0 0 9 0 0 0 100 4 1 0 21 86 4 16 1 0 0 0 538 0 0 0 100 5 0 0 42 84 7 36 1 0 4 0 1087 0 1 0 99 6 0 0 4 300 108 24 0 0 0 0 303 0 0 0 100 7 0 0 462 20 1 13 0 1 2 0 294 0 1 0 99 March 2, 2026 at 06:53:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 21 8 16 0 0 0 0 309 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 106 50 102 0 0 0 0 0 0 0 0 100 4 0 0 21 9 4 6 0 0 0 0 526 0 0 0 100 5 0 0 0 12 2 36 1 1 0 0 1088 0 0 0 100 6 0 0 4 219 106 12 0 0 0 0 300 0 0 0 100 7 0 0 0 15 1 14 0 1 1 0 294 0 0 0 100 March 2, 2026 at 06:53:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5821 0 266 2586 202 588 9 91 73 50 2484 2 4 0 94 1 3008 0 11 318 17 445 8 79 83 50 3960 2 2 0 97 2 288 0 15 244 1 372 6 90 61 43 1446 1 1 0 98 3 7535 0 429 339 39 594 13 92 136 68 4291 4 4 0 92 4 4722 0 46 367 7 476 5 103 94 59 3135 3 2 0 95 5 666 0 10 332 2 535 5 102 51 49 2681 1 2 0 97 6 34769 0 37 566 108 431 11 88 57 39 2483 10 7 0 83 7 304 0 9 247 2 349 6 63 52 37 1526 1 1 0 98 March 2, 2026 at 06:53:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 801 0 101 2570 201 610 24 100 90 3 1555 2 2 0 96 1 1038 0 0 275 3 502 25 97 126 2 1848 2 2 0 96 2 403 0 0 334 8 597 22 70 75 5 1168 2 1 0 97 3 930 0 7 453 120 637 18 95 119 4 1124 2 1 0 96 4 1452 0 21 257 6 449 16 81 108 0 1973 4 1 0 95 5 352 0 0 219 2 415 13 65 86 8 2176 3 1 0 96 6 970 0 4 474 105 522 28 90 98 2 1363 3 1 0 96 7 519 0 0 196 3 390 18 77 110 2 1708 2 1 0 98 March 2, 2026 at 06:53:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2369 200 117 0 1 2 0 0 0 2 0 98 1 0 0 462 29 2 32 0 1 2 0 300 0 1 0 99 2 0 0 0 77 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 180 50 104 0 0 0 0 0 0 0 0 100 4 0 0 21 84 5 10 1 1 0 0 531 0 0 0 100 5 40 0 0 91 6 44 0 0 0 0 1100 0 0 0 99 6 0 0 4 287 105 8 0 0 0 0 2 0 0 0 100 7 0 0 0 85 3 8 0 0 0 0 593 0 0 0 100 March 2, 2026 at 06:53:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 114 0 0 0 0 23 0 0 0 99 1 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 5 0 0 0 100 3 0 0 0 108 50 106 0 0 0 0 7 0 0 0 100 4 0 0 21 21 7 24 0 1 0 0 543 0 0 0 100 5 0 0 0 29 12 44 1 0 0 0 1098 0 0 0 100 6 0 0 4 213 104 6 0 0 0 0 0 0 0 0 100 7 0 0 0 16 3 13 0 0 0 0 595 0 0 0 100 March 2, 2026 at 06:53:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 2 0 0 0 10 0 10 0 1 0 0 0 0 0 0 100 3 0 0 0 106 50 102 0 0 0 0 0 0 0 0 100 4 0 0 21 21 10 18 0 0 0 0 535 0 0 0 100 5 0 0 0 10 1 34 1 0 0 0 1090 0 0 0 100 6 0 0 4 215 105 8 0 0 0 0 2 0 0 0 100 7 0 0 0 13 3 8 0 0 0 0 593 0 0 0 100 March 2, 2026 at 06:53:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11298 0 239 2917 202 1131 38 191 239 65 5179 8 6 0 86 1 31036 0 45 711 4 1088 29 181 333 69 4852 14 10 0 76 2 2352 0 198 570 5 1036 26 171 95 80 4286 5 3 0 92 3 1403 0 20 648 18 1178 20 192 255 57 3962 3 3 0 94 4 3435 0 401 529 13 1025 19 157 97 66 5165 8 3 0 89 5 13693 0 8 544 25 743 26 129 273 46 3208 8 3 0 88 6 21134 0 18 725 105 981 29 163 285 54 3819 8 5 0 87 7 5463 0 9 449 12 715 21 100 184 47 4787 4 3 0 92 March 2, 2026 at 06:53:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 88 2344 200 164 0 14 79 0 8 0 2 0 98 1 0 0 0 90 2 118 0 19 71 0 323 0 0 0 99 2 2 0 0 208 43 288 0 17 73 0 7 0 0 0 100 3 13 0 0 117 56 90 0 14 64 0 14 0 0 0 100 4 11 0 21 77 6 140 1 13 65 0 1642 0 0 0 99 5 0 0 7 75 8 91 0 9 62 0 18 0 0 0 100 6 0 0 2 268 104 90 0 14 75 0 12 0 0 0 100 7 65 0 0 77 8 102 0 12 78 0 617 0 0 0 100 March 2, 2026 at 06:53:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2369 200 106 0 1 2 0 0 0 1 0 99 1 0 0 462 21 2 16 0 0 2 0 300 0 1 0 99 2 0 0 0 185 50 106 0 0 0 0 0 0 0 0 100 3 0 0 0 80 1 4 0 0 0 0 1 0 0 0 100 4 0 0 21 88 6 42 1 1 1 0 1612 0 0 0 99 5 0 0 0 86 0 16 0 1 0 0 0 0 0 0 100 6 0 0 3 284 103 6 0 1 0 0 0 0 0 0 100 7 0 0 0 99 10 22 0 0 0 0 602 0 0 0 100 March 2, 2026 at 06:53:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 116 0 0 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 110 50 106 0 0 0 0 5 0 0 0 100 3 0 0 0 10 1 8 0 0 0 0 8 0 0 0 100 4 0 0 21 21 7 52 1 0 0 0 1629 0 0 0 100 5 0 0 0 14 5 4 0 1 1 0 0 0 0 0 100 6 0 0 4 220 105 18 0 1 0 0 3 0 0 0 100 7 0 0 0 33 11 31 0 0 0 0 605 0 0 0 100 March 2, 2026 at 06:53:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10633 0 131 2946 204 1070 39 186 170 53 4378 7 5 0 88 1 25367 0 397 660 4 1263 40 217 473 58 5123 10 10 0 80 2 1350 0 10 686 41 1173 28 189 106 79 3927 4 2 0 94 3 29809 0 19 569 0 1050 51 205 563 72 6333 12 7 0 80 4 1409 0 26 610 12 1093 34 180 189 54 5283 4 5 0 91 5 772 0 30 441 2 727 25 150 71 38 2996 3 2 0 96 6 5103 0 211 719 105 796 29 150 130 45 3847 8 4 0 89 7 14941 0 123 437 12 605 25 106 242 43 3977 7 4 0 89 March 2, 2026 at 06:54:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2346 234 167 0 6 6 0 9 0 1 0 99 1 7 0 7 65 18 54 1 7 5 0 30 2 0 0 98 2 0 0 0 23 1 4 0 0 0 0 301 0 0 0 100 3 13 0 0 34 2 16 1 1 0 0 10 0 0 0 100 4 0 0 7 39 6 50 1 1 0 0 1388 0 0 0 100 5 6 0 14 26 2 4 1 1 6 0 277 0 0 0 100 6 18 0 4 236 104 23 1 6 2 0 35 0 0 0 100 7 93 0 0 42 7 30 1 3 0 0 631 0 0 0 100 March 2, 2026 at 06:54:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2378 200 160 0 8 83 0 0 0 1 0 99 1 0 0 231 140 31 168 0 14 66 0 0 0 1 0 99 2 0 0 0 177 22 222 0 9 75 0 300 0 0 0 100 3 0 0 0 156 55 120 0 15 99 0 0 0 0 0 100 4 0 0 7 97 4 137 1 11 70 0 1353 0 0 0 99 5 0 0 14 83 1 80 0 12 69 0 266 0 0 0 100 6 0 0 4 284 102 82 0 9 78 0 0 0 0 0 100 7 0 0 0 92 11 81 0 11 48 0 604 0 0 0 100 March 2, 2026 at 06:54:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2337 200 104 0 0 0 0 0 0 1 0 99 1 0 0 231 14 2 8 0 1 1 0 0 0 0 0 100 2 0 0 0 142 51 104 0 1 0 0 300 0 0 0 100 3 0 0 0 50 0 12 0 0 0 0 0 0 0 0 100 4 0 0 7 46 4 38 1 1 0 0 1349 0 0 0 100 5 1 0 14 42 1 2 1 0 0 0 302 0 0 0 100 6 0 0 4 245 103 4 0 0 0 0 2 0 0 0 100 7 0 0 0 59 10 20 0 0 0 0 604 0 0 0 100 March 2, 2026 at 06:54:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 25 2303 200 110 0 0 0 0 0 0 1 0 99 1 0 0 0 17 1 14 0 2 0 0 0 0 0 0 100 2 0 0 0 116 52 108 0 0 0 0 305 0 0 0 100 3 0 0 0 19 0 14 0 0 0 0 7 0 0 0 100 4 0 0 7 23 6 48 1 0 0 0 1364 0 0 0 100 5 0 0 14 15 6 4 0 1 0 0 266 0 0 0 100 6 0 0 2 212 102 2 0 0 0 0 0 0 0 0 100 7 0 0 0 32 10 25 0 1 0 0 600 0 0 0 100 March 2, 2026 at 06:54:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8511 0 396 2826 203 1016 26 182 180 58 4349 5 5 0 90 1 31974 0 56 633 3 1013 50 200 194 50 6163 13 10 0 77 2 1308 0 12 542 5 965 24 173 111 89 4535 4 2 0 94 3 1867 0 211 569 3 1018 26 168 108 58 3643 3 3 0 94 4 1978 0 18 524 21 897 23 158 124 65 4849 5 3 0 92 5 2992 0 39 553 35 726 28 128 66 37 2313 4 2 0 94 6 1891 0 23 710 105 915 16 161 86 45 3796 6 3 0 91 7 5847 0 123 360 6 616 20 114 133 55 3355 5 3 0 92 March 2, 2026 at 06:54:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 7 2325 205 114 0 1 0 0 8 0 0 0 99 1 0 0 70 15 2 6 0 0 7 0 0 0 1 0 99 2 0 0 0 31 3 12 0 1 7 0 300 0 0 0 100 3 0 0 0 23 1 6 0 1 1 0 0 0 0 0 100 4 0 0 14 27 5 38 0 1 2 0 1354 0 0 0 100 5 2 0 14 125 53 104 1 0 1 0 267 0 0 0 100 6 0 0 7 225 103 2 0 0 1 0 0 0 0 0 100 7 0 0 0 27 5 8 0 0 1 0 594 0 0 0 100 March 2, 2026 at 06:54:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2420 206 173 0 8 49 0 9 0 1 0 99 1 0 0 42 123 1 101 0 14 85 0 0 0 1 0 99 2 0 0 462 118 1 203 0 13 66 0 300 0 1 0 99 3 0 0 0 194 59 120 0 19 63 0 0 0 1 0 99 4 0 0 7 133 4 131 1 15 73 0 1350 0 1 0 99 5 0 0 14 220 52 180 1 14 45 0 267 0 0 0 100 6 0 0 4 316 103 68 0 15 59 0 2 0 0 0 100 7 0 0 0 122 4 85 0 13 58 0 594 0 0 0 100 March 2, 2026 at 06:54:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2317 206 116 0 0 0 0 9 0 0 0 99 1 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 16 1 10 0 0 0 0 300 0 0 0 100 3 0 0 0 10 1 6 0 1 0 0 0 0 0 0 100 4 0 0 7 19 5 48 1 1 1 0 1351 0 0 0 100 5 0 0 14 107 51 104 0 0 0 0 266 0 0 0 100 6 0 0 4 209 102 2 0 0 0 0 0 0 0 0 100 7 0 0 0 13 4 8 0 0 0 0 594 0 0 0 100 March 2, 2026 at 06:54:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10236 0 97 2856 208 1024 43 204 195 67 4425 6 6 0 89 1 7681 0 44 575 2 855 31 173 145 44 5080 6 4 0 90 2 1303 0 14 555 16 915 33 175 104 56 3210 3 2 0 95 3 2992 0 231 509 4 982 36 178 131 73 3409 5 3 0 92 4 2623 0 205 575 11 911 29 172 62 71 3364 5 5 0 90 5 33766 0 24 491 34 745 35 125 64 48 3005 11 8 0 82 6 2480 0 54 628 104 751 21 138 71 43 4194 4 3 0 93 7 2438 0 185 391 4 690 19 113 132 50 4945 4 3 0 92 March 2, 2026 at 06:54:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2307 202 111 0 2 5 0 9 0 1 0 99 1 0 0 0 34 2 24 0 2 5 0 16 0 1 0 99 2 0 0 0 129 51 110 1 2 1 0 316 0 0 0 100 3 1 0 0 25 1 10 0 1 0 0 7 0 0 0 100 4 13 0 7 36 6 22 0 2 0 0 279 0 0 0 100 5 0 0 0 33 2 19 0 3 0 0 6 0 0 0 100 6 53 0 25 234 106 48 1 3 1 0 1385 0 0 0 99 7 12 0 0 27 3 11 0 3 1 0 615 0 0 0 100 March 2, 2026 at 06:54:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 38 2354 201 57 0 2 4 0 0 0 1 0 99 1 0 0 350 78 1 72 0 3 3 0 0 0 1 0 99 2 0 0 0 109 24 46 0 0 0 0 300 0 0 0 100 3 0 0 0 63 1 4 0 0 0 0 0 0 0 0 100 4 0 0 7 66 3 6 0 0 0 0 263 0 0 0 100 5 0 0 0 64 0 4 0 0 0 0 0 0 0 0 100 6 0 0 18 287 111 64 1 1 0 0 1366 0 0 0 99 7 0 0 0 123 30 64 1 2 0 0 593 0 0 0 100 March 2, 2026 at 06:54:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2369 201 113 0 11 68 0 0 0 1 0 99 1 0 0 112 142 1 181 0 15 83 0 0 0 0 0 100 2 0 0 0 130 13 190 0 15 49 0 300 0 0 0 100 3 0 0 0 122 55 90 0 15 72 0 0 0 0 0 100 4 0 0 7 75 3 99 0 18 76 0 260 0 0 0 100 5 0 0 0 68 0 92 0 8 67 0 0 0 0 0 100 6 0 0 18 270 111 108 1 16 62 0 1365 0 1 0 99 7 0 0 0 156 42 189 0 16 84 0 595 0 0 0 100 March 2, 2026 at 06:54:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4005 0 181 2571 201 534 13 88 91 43 2727 3 4 0 93 1 5980 0 325 232 1 415 4 85 108 49 3750 2 4 0 94 2 3344 0 14 342 49 470 4 86 78 45 2222 1 2 0 97 3 1783 0 9 262 2 419 3 77 64 51 1730 3 1 0 95 4 4238 0 24 331 3 437 8 86 45 42 1757 2 2 0 97 5 240 0 3 245 2 378 6 76 39 33 1106 1 1 0 98 6 143 0 32 480 113 473 11 87 33 46 2828 1 1 0 97 7 326 0 32 235 3 366 7 69 65 39 2695 1 2 0 97 March 2, 2026 at 06:54:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5764 0 55 2667 202 622 31 88 80 12 2335 5 3 0 92 1 1191 0 247 283 5 497 22 95 49 13 1973 2 2 0 95 2 1710 0 0 318 11 555 23 84 74 22 2342 3 2 0 95 3 787 0 1 294 4 516 23 90 53 7 1830 4 1 0 95 4 30591 0 16 285 4 509 22 65 42 9 2144 10 7 0 83 5 855 0 0 302 12 482 19 70 41 8 1707 4 1 0 95 6 403 0 21 568 142 633 23 92 37 4 2952 2 2 0 96 7 2455 0 2 212 3 339 14 59 62 4 2142 2 1 0 97 March 2, 2026 at 06:54:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2377 201 104 0 0 0 0 0 0 1 0 99 1 40 0 42 98 7 26 0 1 2 0 9 0 1 0 99 2 0 0 462 14 1 4 0 1 2 0 300 0 1 0 99 3 0 0 0 83 1 6 0 1 0 0 0 0 0 0 100 4 0 0 7 83 3 6 0 1 0 0 263 0 0 0 100 5 0 0 0 81 1 2 0 0 0 0 0 0 0 0 100 6 2 0 18 387 155 138 2 0 1 0 1359 0 0 0 99 7 0 0 0 83 3 6 0 0 0 0 594 0 0 0 100 March 2, 2026 at 06:54:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2306 201 104 0 0 1 0 0 0 0 0 100 1 0 0 0 35 7 32 0 1 1 0 10 0 0 0 100 2 0 0 0 10 2 2 0 0 1 0 300 0 0 0 100 3 0 0 0 13 3 6 0 0 1 0 0 0 0 0 100 4 0 0 7 14 4 6 0 0 1 0 260 0 0 0 100 5 0 0 0 9 1 0 0 0 1 0 0 0 0 0 100 6 0 0 21 313 154 138 1 1 1 0 1355 0 0 0 100 7 0 0 0 14 4 6 0 0 1 0 594 0 0 0 100 March 2, 2026 at 06:54:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2353 202 197 0 12 69 0 0 0 1 0 99 1 0 0 0 80 8 126 0 12 90 0 9 0 0 0 100 2 0 0 0 103 2 195 0 15 64 0 300 0 0 0 100 3 0 0 0 112 61 96 0 15 74 0 0 0 0 0 100 4 0 0 7 51 4 86 0 12 77 0 260 0 0 0 100 5 0 0 0 36 2 52 0 11 52 0 1 0 0 0 100 6 0 0 18 311 131 179 1 23 73 0 1359 0 0 0 99 7 0 0 0 115 29 166 0 18 64 0 594 0 0 0 100 March 2, 2026 at 06:54:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9362 0 312 2979 212 1155 48 227 164 66 5471 10 6 0 83 1 6704 0 152 765 21 1240 39 230 143 64 4993 7 4 0 89 2 2272 0 203 602 4 1135 30 191 129 81 3933 4 3 0 94 3 1172 0 10 645 5 1196 42 212 106 72 4014 4 2 0 94 4 636 0 17 551 4 992 25 195 98 54 3656 3 2 0 95 5 662 0 15 471 2 781 24 136 58 42 3274 3 2 0 95 6 34466 0 29 751 105 947 33 168 106 37 5434 13 9 0 79 7 8119 0 130 426 23 735 22 118 126 46 5185 6 5 0 89 March 2, 2026 at 06:54:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 87 2313 202 114 1 0 6 0 8 0 1 0 99 1 0 0 0 124 50 108 1 3 6 0 19 0 1 0 99 2 25 0 7 31 3 18 0 3 3 0 316 0 0 0 100 3 53 0 0 46 8 40 0 1 1 0 42 0 0 0 100 4 10 0 7 31 5 13 0 3 3 0 283 0 0 0 100 5 2 0 0 44 7 30 0 3 0 0 26 0 0 0 100 6 7 0 18 232 105 10 2 2 3 0 281 0 0 0 100 7 0 0 0 33 5 48 0 1 0 0 1714 0 0 0 100 March 2, 2026 at 06:54:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2371 200 96 0 3 3 0 0 0 2 0 98 1 0 0 462 48 16 40 0 0 3 0 0 0 1 0 99 2 0 0 0 155 36 78 0 1 0 0 300 0 0 0 100 3 0 0 0 95 7 20 0 1 0 0 9 0 0 0 100 4 0 0 7 96 4 22 0 1 0 0 284 0 0 0 100 5 0 0 0 83 2 4 0 0 0 0 1 0 0 0 100 6 0 0 17 279 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 99 5 52 1 3 0 0 1682 0 0 0 100 March 2, 2026 at 06:54:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 108 0 0 0 0 0 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 111 52 106 0 0 0 0 300 0 0 0 100 3 0 0 0 24 8 22 0 0 0 0 18 0 0 0 100 4 0 0 7 13 3 10 0 0 0 0 278 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 6 0 0 18 209 103 4 0 0 0 0 268 0 0 0 100 7 0 0 0 16 5 40 1 0 0 0 1682 0 0 0 100 March 2, 2026 at 06:54:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37773 0 73 2611 201 550 18 106 157 35 3040 10 8 0 82 1 2705 0 12 313 1 517 5 105 151 38 1834 1 2 0 97 2 2534 0 307 375 40 652 6 95 136 62 2778 3 3 0 94 3 3266 0 157 430 66 514 12 102 110 50 1875 3 2 0 95 4 710 0 20 328 7 514 10 95 145 53 3099 1 1 0 97 5 344 0 14 297 8 501 2 86 126 40 1268 1 1 0 98 6 141 0 30 465 102 422 7 92 129 39 1824 1 1 0 98 7 2328 0 11 277 7 472 6 81 156 23 3311 1 2 0 96 March 2, 2026 at 06:54:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5447 0 133 2673 213 652 32 101 89 10 2315 5 5 0 90 1 1182 0 0 380 1 637 26 103 79 14 2327 2 2 0 96 2 1540 0 0 331 15 536 15 84 55 6 2729 3 2 0 95 3 1213 0 0 289 2 523 29 86 64 14 1626 2 1 0 96 4 802 0 190 247 4 448 8 76 25 11 1728 2 1 0 96 5 707 0 0 263 6 433 13 69 46 19 1220 3 1 0 96 6 337 0 23 426 105 361 14 67 41 7 1692 3 1 0 95 7 2584 0 2 301 27 506 15 52 67 10 2855 2 2 0 96 March 2, 2026 at 06:54:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2370 200 106 0 0 2 0 0 0 1 0 99 1 0 0 462 22 0 16 0 1 2 0 0 0 1 0 99 2 40 0 0 201 59 124 0 0 0 0 315 0 0 0 100 3 0 0 0 82 1 8 0 0 0 0 5 0 0 0 100 4 0 0 7 83 3 6 0 1 0 0 263 0 0 0 100 5 0 0 0 95 9 14 0 1 0 0 12 0 0 0 100 6 0 0 17 279 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 93 5 45 1 1 0 0 1681 0 0 0 100 March 2, 2026 at 06:54:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 200 104 0 1 0 0 0 0 0 0 100 1 0 0 0 13 0 8 0 0 0 0 0 0 0 0 100 2 0 0 0 123 58 118 0 1 0 0 309 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 4 0 0 7 9 3 4 0 0 0 0 260 0 0 0 100 5 0 0 0 11 3 4 0 0 0 0 0 0 0 0 100 6 0 0 18 211 103 6 0 0 0 0 268 0 0 0 100 7 0 0 0 21 5 48 1 1 0 0 1681 0 0 0 100 March 2, 2026 at 06:54:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2308 201 118 0 2 0 0 0 0 0 0 100 1 0 0 0 16 1 8 0 0 1 0 0 0 0 0 100 2 0 0 0 128 60 120 0 0 1 0 310 0 0 0 100 3 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 4 0 0 7 13 4 6 0 1 1 0 260 0 0 0 100 5 0 0 0 13 3 2 0 0 1 0 1 0 0 0 100 6 0 0 21 208 102 2 0 0 1 0 266 0 0 0 100 7 0 0 0 19 5 40 1 1 2 0 1681 0 0 0 100 March 2, 2026 at 06:54:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7757 0 117 2913 202 1033 18 165 232 66 3487 5 5 0 90 1 36886 0 313 641 2 1088 52 206 215 65 4964 14 10 0 76 2 1865 0 9 595 19 936 29 146 136 70 3175 5 2 0 92 3 1771 0 12 637 63 1043 28 182 166 78 3958 5 3 0 92 4 1094 0 21 512 15 864 19 172 175 46 2916 3 2 0 95 5 2228 0 27 475 26 788 14 119 184 41 3483 4 2 0 94 6 1104 0 23 700 107 888 18 141 182 40 2928 3 2 0 95 7 10517 0 316 393 5 746 12 116 251 50 6277 4 5 0 91 March 2, 2026 at 06:54:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2312 203 114 1 1 6 0 14 0 1 0 99 1 8 0 0 34 1 22 0 3 6 0 12 0 0 0 100 2 41 0 0 45 8 31 0 3 0 0 324 0 0 0 100 3 9 0 0 22 1 6 0 1 0 0 10 0 0 0 100 4 0 0 7 35 4 16 0 2 2 0 279 0 0 0 100 5 1 0 0 126 51 111 0 4 0 0 7 0 0 0 100 6 11 0 25 224 102 9 0 2 0 0 289 0 0 0 100 7 14 0 0 38 6 49 2 1 3 0 1690 0 0 0 100 March 2, 2026 at 06:54:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2373 201 88 0 2 2 0 0 0 1 0 99 1 0 0 462 19 0 12 0 0 2 0 0 0 1 0 99 2 0 0 0 133 8 62 0 2 0 0 313 0 0 0 100 3 0 0 0 84 2 10 0 1 0 0 7 0 0 0 100 4 0 0 7 82 3 6 0 0 0 0 260 0 0 0 100 5 0 0 0 193 57 114 0 0 0 0 14 0 0 0 100 6 0 0 18 285 104 8 0 1 0 0 269 0 0 0 100 7 0 0 0 92 4 48 1 2 1 0 1681 0 0 0 100 March 2, 2026 at 06:54:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 112 0 0 0 0 0 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 13 3 8 0 0 0 0 300 0 0 0 100 3 0 0 0 17 6 12 0 0 0 0 8 0 0 0 100 4 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 5 0 0 0 115 54 110 0 1 0 0 4 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 14 4 38 1 0 0 0 1681 0 0 0 100 March 2, 2026 at 06:54:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8181 0 219 2865 205 1104 44 194 163 57 4804 5 5 0 90 1 40995 0 37 654 2 1047 43 198 175 73 5606 15 10 0 75 2 2686 0 363 490 5 869 31 154 126 68 5286 5 4 0 91 3 1645 0 8 595 8 1064 22 177 91 85 4010 4 2 0 94 4 2801 0 24 641 4 1039 28 166 98 52 4176 6 3 0 91 5 2547 0 37 534 35 876 31 137 101 55 2106 3 2 0 94 6 595 0 33 696 114 867 19 162 86 36 3076 3 3 0 94 7 3892 0 125 494 6 945 34 154 128 49 5256 3 3 0 93 March 2, 2026 at 06:54:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 94 2357 202 164 0 19 84 0 9 0 2 0 98 1 11 0 14 92 3 135 0 24 110 0 284 0 0 0 100 2 2 0 0 182 51 213 0 18 80 0 310 0 1 0 99 3 1 0 0 157 75 120 0 20 71 0 5 0 0 0 100 4 42 0 7 101 8 145 0 14 92 0 274 0 1 0 99 5 25 0 0 113 2 137 0 14 64 0 11 0 0 0 100 6 0 0 3 342 102 236 0 13 86 0 17 0 0 0 100 7 13 0 0 73 7 123 1 13 62 0 1714 0 0 0 99 March 2, 2026 at 06:54:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2337 201 108 0 0 3 0 0 0 1 0 99 1 0 0 14 44 2 9 0 2 0 0 266 0 0 0 100 2 0 0 231 76 31 68 0 0 4 0 300 0 1 0 99 3 0 0 0 57 7 18 0 1 0 0 1 0 0 0 100 4 0 0 7 89 25 52 0 1 0 0 272 0 0 0 100 5 0 0 0 41 0 2 0 0 0 0 0 0 0 0 100 6 0 0 4 243 102 2 0 0 0 0 2 0 0 0 100 7 0 0 0 48 4 38 1 0 0 0 1683 0 0 0 100 March 2, 2026 at 06:54:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2340 201 110 0 0 0 0 0 0 1 0 99 1 0 0 14 49 2 10 0 1 0 0 266 0 0 0 100 2 0 0 231 16 1 16 0 1 1 0 310 0 0 0 100 3 0 0 0 48 2 10 0 0 0 0 8 0 0 0 100 4 0 0 7 159 59 120 0 0 0 0 269 0 0 0 100 5 0 0 0 60 7 20 0 1 0 0 7 0 0 0 100 6 0 0 4 242 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 52 4 43 1 0 0 0 1679 0 0 0 100 March 2, 2026 at 06:54:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 30 2322 201 140 2 11 14 4 59 0 1 0 99 1 1220 0 21 30 1 31 3 6 26 6 563 0 1 0 99 2 4 0 0 31 2 28 0 3 1 1 347 0 0 0 100 3 13 0 7 35 2 30 0 4 3 2 63 0 1 0 99 4 17 0 25 146 60 162 4 8 5 7 309 0 0 0 99 5 20 0 0 23 0 26 0 10 7 4 28 0 0 0 100 6 30 0 9 232 102 33 1 6 2 3 25 0 0 0 100 7 10 0 0 29 4 49 1 0 0 1 1700 0 0 0 99 March 2, 2026 at 06:54:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35737 0 271 2764 203 777 40 173 95 44 5228 15 11 0 74 1 2217 0 20 576 4 972 23 185 102 46 3744 4 3 0 93 2 9106 0 424 511 4 942 28 137 149 56 4227 5 6 0 90 3 10963 0 44 701 5 1030 32 169 209 63 5281 9 4 0 87 4 1139 0 77 646 11 1063 22 172 124 79 4982 3 3 0 93 5 1556 0 12 487 6 758 15 138 119 47 2814 3 2 0 95 6 640 0 19 767 131 931 34 153 96 42 2959 5 2 0 93 7 479 0 16 448 16 795 25 115 65 41 4068 2 2 0 96 March 2, 2026 at 06:54:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2353 201 183 0 14 78 0 0 0 1 0 99 1 2 0 14 54 1 84 0 9 46 0 266 0 0 0 100 2 0 0 0 36 2 48 0 13 40 0 300 0 0 0 100 3 0 0 0 112 56 101 0 12 79 0 0 0 0 0 100 4 0 0 14 54 4 89 0 15 81 0 263 0 0 0 100 5 40 0 0 65 8 106 0 11 77 0 303 0 0 0 100 6 0 0 4 399 152 276 0 17 71 0 2 0 0 0 100 7 0 0 0 69 3 141 1 13 58 0 1387 0 0 0 100 March 2, 2026 at 06:54:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2383 201 114 0 1 0 0 0 0 1 0 99 1 0 0 14 184 50 110 0 1 0 0 266 0 0 0 100 2 0 0 462 18 3 8 0 0 2 0 301 0 1 0 99 3 0 0 0 83 2 6 0 0 0 0 0 0 0 0 100 4 0 0 49 78 4 9 0 0 2 0 261 0 1 0 99 5 0 0 0 93 7 16 0 0 0 0 303 0 0 0 100 6 0 0 4 281 102 0 0 0 0 0 0 0 0 0 100 7 0 0 0 87 3 38 2 0 3 0 1388 0 1 0 99 March 2, 2026 at 06:54:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 110 0 0 0 0 23 0 0 0 99 1 0 0 14 114 51 111 1 1 0 0 266 0 0 0 100 2 0 0 0 20 4 20 0 0 0 0 315 0 0 0 100 3 0 0 0 15 3 10 0 0 0 0 8 0 0 0 100 4 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 5 0 0 0 31 13 20 0 0 0 0 308 0 0 0 100 6 0 0 3 211 103 4 0 0 0 0 3 0 0 0 100 7 0 0 0 15 3 41 1 1 0 0 1387 0 0 0 100 March 2, 2026 at 06:54:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8922 0 197 2988 208 1095 40 212 209 63 4989 7 5 0 88 1 2103 0 22 739 31 1337 49 258 125 71 6196 7 3 0 90 2 1935 0 14 596 4 1013 36 187 119 52 4279 5 3 0 92 3 3619 0 194 582 2 1099 42 191 134 64 3602 4 3 0 93 4 1165 0 19 581 11 972 37 191 116 53 3257 3 2 0 94 5 1429 0 22 518 11 868 35 171 94 55 2938 3 3 0 94 6 812 0 21 740 103 921 35 162 111 53 4568 4 3 0 93 7 43432 0 331 460 5 864 31 137 189 53 6583 16 11 0 73 March 2, 2026 at 06:54:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 17 2368 251 212 0 3 0 0 21 0 0 0 99 1 6 0 14 32 2 14 0 2 2 0 275 0 0 0 100 2 3 0 0 34 2 26 0 2 7 0 310 0 0 0 99 3 0 0 0 25 1 10 0 1 0 0 26 0 0 0 100 4 10 0 14 32 5 16 0 2 0 0 274 0 0 0 100 5 53 0 0 39 6 23 1 0 0 0 312 0 0 0 100 6 1 0 74 218 102 12 0 3 7 0 17 0 1 0 99 7 0 0 0 30 4 40 1 1 0 0 1403 0 0 0 100 March 2, 2026 at 06:54:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2455 251 284 0 7 67 0 0 0 1 0 99 1 0 0 14 117 2 112 0 20 85 0 266 0 0 0 99 2 0 0 350 52 3 76 0 14 66 0 301 0 1 0 99 3 0 0 0 152 54 75 0 16 81 0 0 0 0 0 100 4 0 0 7 103 4 79 0 14 79 0 263 0 0 0 100 5 0 0 0 111 7 87 0 12 56 0 303 0 0 0 100 6 0 0 39 352 101 193 0 21 70 0 0 0 1 0 99 7 0 0 0 111 4 121 1 11 54 0 1392 0 0 0 99 March 2, 2026 at 06:54:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2368 251 204 0 0 0 0 0 0 1 0 99 1 0 0 14 30 1 10 1 0 0 0 266 0 0 0 100 2 0 0 0 29 2 8 0 0 0 0 300 0 0 0 100 3 0 0 0 28 1 12 0 1 0 0 0 0 0 0 100 4 3 0 7 29 4 8 0 0 0 0 262 0 0 0 100 5 0 0 0 41 8 20 1 0 0 0 304 0 0 0 100 6 0 0 116 211 102 5 0 0 0 0 2 0 0 0 100 7 0 0 0 29 3 36 1 0 0 0 1391 0 0 0 100 March 2, 2026 at 06:54:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5516 0 163 2613 245 672 9 91 117 54 2057 2 3 0 95 1 5179 0 46 326 3 427 4 89 81 42 2900 3 2 0 95 2 1762 0 297 251 4 460 6 82 68 55 2929 2 2 0 96 3 952 0 12 286 2 469 12 102 65 44 2915 2 2 0 96 4 7786 0 22 293 6 502 7 109 50 51 2064 2 2 0 96 5 2311 0 21 279 18 405 2 79 52 23 1847 1 1 0 97 6 263 0 27 437 101 361 6 76 31 23 1260 1 2 0 97 7 489 0 27 217 3 354 10 76 65 37 3141 1 2 0 97 March 2, 2026 at 06:54:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1000 0 50 2576 202 555 12 79 60 17 1811 2 2 0 96 1 1771 0 192 273 3 496 24 90 36 7 3097 4 2 0 94 2 1238 0 0 323 3 579 16 73 55 23 1604 2 1 0 97 3 388 0 0 285 2 511 16 74 32 9 1866 3 1 0 96 4 26332 0 14 283 6 450 32 74 47 13 2107 8 6 0 86 5 698 0 3 245 12 391 21 59 57 10 1459 3 1 0 96 6 2438 0 16 426 105 375 15 68 36 9 1452 4 1 0 95 7 5200 0 84 335 40 415 12 46 69 7 2808 4 3 0 94 March 2, 2026 at 06:54:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 507 2323 217 132 0 4 2 0 294 0 2 0 98 1 2 0 14 95 8 16 0 1 1 0 266 0 0 0 100 2 0 0 0 85 4 6 0 0 1 0 301 0 0 0 100 3 0 0 0 89 2 10 0 0 1 0 0 0 0 0 100 4 0 0 7 89 5 10 0 0 2 0 263 0 0 0 100 5 0 0 0 95 1 18 0 2 1 0 0 0 0 0 100 6 40 0 3 296 107 14 0 0 1 0 9 0 0 0 100 7 0 0 0 148 33 100 0 3 1 0 1387 0 0 0 99 March 2, 2026 at 06:54:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2358 202 203 0 11 61 0 294 0 0 0 99 1 0 0 14 165 51 225 1 20 78 0 266 0 0 0 100 2 0 0 0 45 2 80 0 18 77 0 300 0 0 0 100 3 0 0 0 136 71 115 0 20 94 0 0 0 0 0 100 4 0 0 7 62 4 111 0 12 88 0 260 0 0 0 100 5 0 0 0 34 1 53 0 10 56 0 1 0 0 0 100 6 0 0 4 337 108 245 0 17 60 0 11 0 0 0 100 7 0 0 0 61 3 135 1 15 52 0 1387 0 0 0 100 March 2, 2026 at 06:54:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 107 0 0 0 0 294 0 0 0 100 1 0 0 14 106 51 102 0 0 0 0 266 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 3 0 0 0 17 1 12 0 0 0 0 0 0 0 0 100 4 0 0 7 15 5 10 0 0 0 0 261 0 0 0 100 5 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 6 0 0 3 219 107 12 0 0 0 0 9 0 0 0 100 7 0 0 0 12 3 36 1 0 0 0 1387 0 0 0 100 March 2, 2026 at 06:54:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5221 0 174 2890 204 1147 38 220 142 72 5410 7 5 0 88 1 3684 0 39 745 24 1207 51 216 119 64 6693 5 3 0 91 2 33793 0 36 605 5 1040 57 208 89 61 4035 11 9 0 79 3 2166 0 202 600 4 1110 39 199 96 62 5676 4 3 0 92 4 1110 0 2 553 9 931 26 194 78 56 3152 4 2 0 94 5 4840 0 23 603 25 1005 39 166 101 45 3716 4 4 0 92 6 9737 0 324 805 113 999 25 173 192 68 4349 7 4 0 88 7 2767 0 14 487 5 868 22 144 118 68 3269 5 2 0 93 March 2, 2026 at 06:54:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2322 202 120 0 3 6 0 296 0 1 0 99 1 2 0 21 26 3 41 1 3 0 0 1377 0 0 0 100 2 2 0 0 24 1 6 0 1 2 0 310 0 0 0 100 3 9 0 42 24 1 13 0 3 7 0 15 0 1 0 99 4 0 0 0 23 2 6 0 1 1 0 21 0 0 0 100 5 65 0 0 92 33 73 0 3 0 0 20 0 0 0 100 6 13 0 11 277 126 60 0 2 0 0 285 0 0 0 100 7 7 0 0 34 3 19 0 5 0 0 310 0 0 0 100 March 2, 2026 at 06:54:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2374 202 105 0 0 2 0 294 0 1 0 99 1 0 0 476 21 2 42 2 1 2 0 1353 0 1 0 99 2 0 0 0 82 2 6 0 1 0 0 301 0 0 0 100 3 0 0 0 85 3 10 0 0 0 0 9 0 0 0 100 4 0 0 0 82 2 6 0 0 0 0 18 0 0 0 100 5 0 0 0 94 6 18 0 0 0 0 9 0 0 0 100 6 0 0 11 384 153 106 0 0 0 0 260 0 0 0 100 7 0 0 0 91 3 14 0 0 0 0 302 0 0 0 100 March 2, 2026 at 06:54:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2385 202 260 0 24 88 0 294 0 1 0 99 1 0 0 14 97 2 214 1 27 118 0 1352 0 1 0 99 2 0 0 0 52 2 94 0 23 84 0 300 0 0 0 100 3 0 0 0 208 127 154 0 27 110 0 0 0 0 0 100 4 0 0 0 87 2 158 0 17 123 0 0 0 0 0 100 5 0 0 0 76 6 125 0 18 73 0 9 0 0 0 99 6 0 0 10 468 145 433 0 26 83 0 260 0 0 0 100 7 0 0 0 117 11 193 0 23 100 0 301 0 0 0 100 March 2, 2026 at 06:54:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4674 0 75 2708 207 585 11 96 89 54 3240 3 3 0 94 1 1677 0 135 356 2 656 10 121 66 70 4023 2 2 0 96 2 1303 0 33 324 2 541 12 110 83 65 2904 3 2 0 94 3 394 0 9 298 3 496 9 106 75 46 2206 1 1 0 98 4 475 0 8 254 3 383 5 93 69 45 2754 1 2 0 97 5 33761 0 126 246 9 337 10 71 68 47 1584 9 8 0 83 6 7523 0 209 479 111 467 13 110 128 57 2753 2 3 0 94 7 7524 0 203 375 40 490 10 65 116 48 2284 5 3 0 92 March 2, 2026 at 06:54:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1307 0 105 2574 203 638 30 100 41 5 2341 4 3 0 93 1 817 0 14 437 17 832 31 101 57 9 3569 4 2 0 94 2 838 0 0 317 29 512 20 74 42 3 1503 5 1 0 94 3 929 0 7 330 9 663 22 97 50 4 2437 3 1 0 96 4 1231 0 7 254 7 442 14 63 39 5 2149 2 1 0 96 5 248 0 0 232 7 413 21 60 19 2 1308 2 1 0 97 6 719 0 7 506 104 590 11 65 40 3 1498 2 1 0 97 7 432 0 0 215 2 375 14 48 42 4 1724 2 1 0 97 March 2, 2026 at 06:54:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 46 2370 201 104 0 0 2 0 0 0 1 0 99 1 40 0 476 133 59 158 1 0 3 0 1364 0 1 0 99 2 0 0 0 79 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 89 4 12 0 1 0 0 595 0 0 0 100 4 0 0 7 91 4 18 0 2 1 0 263 0 0 0 100 5 0 0 0 82 1 6 0 0 0 0 1 0 0 0 100 6 0 0 2 281 101 2 0 1 0 0 0 0 0 0 100 7 0 0 0 92 3 14 0 0 0 0 302 0 0 0 100 March 2, 2026 at 06:54:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 102 0 0 1 0 0 0 0 0 100 1 0 0 14 122 59 148 1 1 0 0 1361 0 0 0 99 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 16 5 8 1 0 1 0 593 0 0 0 100 4 0 0 7 15 5 8 0 1 2 0 260 0 0 0 100 5 0 0 0 14 1 12 0 1 1 0 0 0 0 0 100 6 0 0 4 209 101 2 0 0 1 0 0 0 0 0 100 7 0 0 0 19 3 12 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:54:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2348 201 190 0 11 81 0 0 0 1 0 99 1 0 0 14 118 39 182 1 16 80 0 1361 0 0 0 99 2 0 0 0 54 3 86 0 17 54 0 0 0 0 0 100 3 0 0 0 134 74 111 0 12 44 0 594 0 0 0 100 4 0 0 7 53 4 94 0 16 77 0 260 0 0 0 100 5 0 0 0 48 1 83 0 14 62 0 1 0 0 0 100 6 0 0 4 305 101 200 0 22 84 0 0 0 0 0 100 7 0 0 0 60 3 95 0 13 66 0 302 0 0 0 100 March 2, 2026 at 06:54:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6499 0 123 2887 203 974 29 185 175 50 3569 4 5 0 91 1 2335 0 310 567 9 1055 21 192 87 77 5144 4 3 0 93 2 3764 0 27 573 0 869 18 153 105 59 3000 4 2 0 94 3 1907 0 9 561 15 1022 33 175 103 66 4659 6 3 0 91 4 2453 0 53 509 30 884 21 163 119 55 4074 5 3 0 92 5 34930 0 132 405 3 700 30 120 84 59 4322 11 8 0 81 6 1368 0 19 721 113 916 19 148 91 44 2916 5 3 0 92 7 10411 0 185 341 2 644 14 123 178 48 4872 4 4 0 92 March 2, 2026 at 06:54:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2326 201 122 0 2 0 0 7 0 0 0 100 1 57 0 14 37 8 55 2 1 6 0 1382 0 1 0 99 2 0 0 0 27 1 8 0 1 0 0 9 0 0 0 100 3 1 0 0 36 5 22 0 1 0 0 610 0 0 0 100 4 22 0 77 119 54 114 0 2 7 0 273 0 1 0 99 5 12 0 7 37 8 21 0 3 3 0 30 0 0 0 100 6 0 0 4 231 104 12 0 2 0 0 10 0 0 0 100 7 0 0 0 41 4 25 0 1 3 0 319 0 0 0 100 March 2, 2026 at 06:54:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2374 201 102 0 0 0 0 0 0 1 0 99 1 0 0 476 28 8 48 1 0 2 0 1369 0 1 0 99 2 0 0 0 79 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 85 4 8 0 0 0 0 593 0 0 0 100 4 0 0 49 99 14 26 0 0 2 0 281 0 1 0 99 5 0 0 0 167 42 92 0 3 0 0 1 0 0 0 100 6 0 0 3 282 101 4 0 1 0 0 0 0 0 0 100 7 0 0 0 89 2 12 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:55:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 104 0 0 0 0 0 0 0 0 100 1 0 0 14 23 7 54 1 1 0 0 1368 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 14 4 8 1 0 0 0 594 0 0 0 100 4 0 0 7 11 4 6 0 0 0 0 260 0 0 0 100 5 0 0 0 108 50 104 0 0 0 0 0 0 0 0 100 6 0 0 4 209 101 2 0 0 0 0 0 0 0 0 100 7 0 0 0 19 3 14 0 0 0 0 302 0 0 0 100 March 2, 2026 at 06:55:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 34401 0 111 2891 202 993 54 181 219 51 5140 14 10 0 75 1 2445 0 149 645 9 1209 31 201 193 77 5615 6 4 0 90 2 3626 0 22 616 1 1011 21 157 204 63 3130 5 3 0 93 3 9764 0 243 700 61 1216 25 185 189 65 5351 5 4 0 92 4 1315 0 26 568 6 877 19 178 159 48 3275 4 3 0 94 5 835 0 10 543 41 839 12 138 155 41 2971 3 2 0 96 6 570 0 21 733 106 915 17 148 163 32 2958 4 2 0 94 7 10490 0 305 368 5 644 19 107 228 38 3559 4 5 0 91 March 2, 2026 at 06:55:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 87 2313 203 97 1 6 6 0 21 0 1 0 98 1 6 0 14 54 3 70 1 5 7 0 1440 0 1 0 99 2 1 0 0 26 1 8 0 3 0 0 7 0 0 0 100 3 0 0 0 39 4 24 0 3 0 0 600 0 0 0 100 4 0 0 7 28 5 8 0 1 0 0 271 0 0 0 100 5 2 0 0 24 1 10 0 1 3 0 13 0 0 0 100 6 65 0 4 237 106 23 0 1 0 0 23 0 0 0 100 7 9 0 7 124 53 109 0 3 0 0 325 0 0 0 100 March 2, 2026 at 06:55:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 31 2356 201 110 0 1 4 0 0 0 1 0 99 1 0 0 357 18 3 45 1 1 5 0 1360 0 1 0 99 2 0 0 0 64 0 8 0 0 0 0 5 0 0 0 100 3 0 0 0 81 3 30 0 2 0 0 600 0 0 0 100 4 0 0 7 64 4 4 0 0 0 0 263 0 0 0 100 5 1 0 0 78 9 18 0 0 1 0 16 0 0 0 100 6 0 0 4 276 108 14 0 0 0 0 9 0 0 0 100 7 0 0 0 168 52 113 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:55:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 122 2309 202 73 0 3 0 0 2 0 1 0 99 1 0 0 14 67 2 74 2 2 1 0 1360 0 0 0 99 2 0 0 0 24 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 39 4 14 1 0 0 0 595 0 0 0 100 4 0 0 7 31 3 14 0 1 0 0 260 0 0 0 100 5 0 0 0 25 0 4 0 0 0 0 0 0 0 0 100 6 0 0 4 240 108 17 0 1 0 0 9 0 0 0 100 7 0 0 0 126 52 104 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:55:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2366 0 34 2348 201 133 1 22 36 15 498 0 2 0 98 1 40 0 17 106 3 141 1 18 13 11 1534 0 1 0 99 2 28 0 0 56 2 60 1 17 9 15 84 0 0 0 100 3 9 0 0 50 5 41 1 8 5 2 712 0 0 0 100 4 140 0 9 63 5 84 0 16 9 19 927 0 0 0 100 5 36 0 5 58 1 68 0 13 9 15 186 0 0 0 100 6 724 0 121 266 109 89 1 15 11 17 247 0 1 0 99 7 45 0 1 164 53 171 0 15 17 10 536 0 0 0 99 March 2, 2026 at 06:55:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3822 0 166 2804 203 967 23 172 228 39 3991 4 5 0 90 1 8953 0 327 525 5 1039 35 197 235 65 6442 5 6 0 90 2 41889 0 45 642 4 959 33 172 195 59 4251 17 11 0 72 3 1721 0 193 669 76 1140 29 214 204 76 4153 3 3 0 94 4 2023 0 16 575 7 1058 20 200 197 55 4327 6 2 0 92 5 579 0 14 432 3 728 19 132 142 46 1921 4 2 0 94 6 539 0 10 667 118 732 15 124 108 30 2566 3 2 0 96 7 472 0 4 397 16 657 18 112 169 38 3007 2 2 0 96 March 2, 2026 at 06:55:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2374 202 58 0 3 1 0 300 0 2 0 98 1 2 0 476 86 2 110 1 1 3 0 1353 0 1 0 99 2 0 0 0 85 0 14 0 2 0 0 0 0 0 0 100 3 0 0 0 87 4 8 0 0 1 0 594 0 0 0 100 4 40 0 7 93 9 16 0 0 0 0 272 0 0 0 100 5 0 0 0 84 2 6 0 0 0 0 1 0 0 0 100 6 0 0 4 281 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 183 52 104 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 203 116 0 0 0 0 302 0 0 0 99 1 0 0 14 13 2 38 2 0 0 0 1353 0 0 0 100 2 0 0 0 11 0 6 0 0 0 0 5 0 0 0 100 3 0 0 0 17 5 14 0 0 0 0 601 0 0 0 100 4 0 0 7 21 9 16 0 0 0 0 269 0 0 0 100 5 0 0 0 21 7 16 0 0 0 0 13 0 0 0 100 6 0 0 4 210 102 2 1 0 0 0 1 0 0 0 100 7 0 0 0 112 52 109 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 202 112 0 0 0 0 300 0 0 0 100 1 0 0 14 10 2 36 1 0 1 0 1353 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 19 4 18 1 1 0 0 594 0 0 0 100 4 0 0 7 22 9 16 1 0 0 0 269 0 0 0 100 5 0 0 0 10 1 6 0 1 0 0 1 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 110 52 104 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4232 0 130 2957 204 1159 48 189 111 51 5058 9 5 0 86 1 6237 0 48 691 13 1189 43 215 201 76 7100 6 6 0 88 2 9139 0 254 551 2 1024 37 177 144 67 5646 6 5 0 89 3 7016 0 210 676 5 1109 31 208 167 73 4804 7 4 0 89 4 1131 0 15 573 10 978 34 188 100 59 2989 3 2 0 95 5 344 0 6 459 11 736 12 119 91 51 2725 3 2 0 96 6 34173 0 197 653 101 787 29 150 73 48 3665 11 8 0 80 7 1023 0 8 539 29 923 26 122 88 42 2582 5 2 0 94 March 2, 2026 at 06:55:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 87 2352 201 86 0 13 88 0 331 0 2 0 98 1 5 0 14 179 3 239 1 27 79 0 1372 0 1 0 99 2 0 0 0 70 2 85 0 17 83 0 5 0 0 0 100 3 49 0 7 147 69 119 0 16 83 0 617 0 1 0 99 4 2 0 7 71 4 94 0 13 65 0 268 0 0 0 100 5 13 0 0 163 52 184 0 11 72 0 20 0 0 0 99 6 9 0 4 318 102 190 0 17 65 0 33 0 0 0 100 7 0 0 0 70 4 94 1 15 76 0 3 0 0 0 100 March 2, 2026 at 06:55:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 38 2359 202 6 0 0 1 0 302 0 1 0 99 1 0 0 14 172 2 144 1 0 0 0 1353 0 0 0 99 2 0 0 0 64 1 4 0 1 0 0 0 0 0 0 100 3 0 0 350 39 10 36 0 0 2 0 603 0 1 0 99 4 0 0 7 67 3 8 0 2 0 0 263 0 0 0 100 5 0 0 0 168 50 114 0 1 0 0 0 0 0 0 100 6 0 0 4 262 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 64 2 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2307 201 105 0 3 0 0 300 0 1 0 99 1 0 0 0 45 3 48 1 1 0 0 1088 0 0 0 100 2 0 0 14 28 1 10 0 1 0 0 271 0 0 0 100 3 0 0 0 44 10 24 0 0 0 0 611 0 0 0 100 4 0 0 7 25 3 4 0 0 0 0 260 0 0 0 100 5 0 0 0 144 59 122 0 0 0 0 17 0 0 0 100 6 0 0 4 228 101 10 0 1 0 0 0 0 0 0 100 7 0 0 0 29 2 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4420 0 353 2517 202 510 12 91 97 50 2981 3 4 0 94 1 2369 0 37 336 1 450 9 99 53 53 3098 3 3 0 95 2 460 0 36 295 2 490 4 96 45 34 1759 1 2 0 97 3 4967 0 19 275 11 423 8 76 93 42 2845 2 2 0 96 4 3185 0 137 252 3 471 11 96 71 56 2013 2 2 0 97 5 549 0 10 361 48 522 4 91 55 53 2400 1 1 0 98 6 640 0 32 451 102 458 7 92 47 41 2896 1 1 0 97 7 2031 0 9 220 4 299 4 67 36 37 1210 1 1 0 98 March 2, 2026 at 06:55:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 451 0 31 2549 212 426 12 73 59 5 1841 2 2 0 96 1 2910 0 2 286 5 526 20 63 85 8 3643 3 2 0 95 2 5405 0 98 272 5 358 18 46 82 11 1571 5 3 0 92 3 734 0 0 262 2 477 21 63 70 17 1546 2 1 0 97 4 1327 0 8 352 44 558 9 69 71 21 1794 2 1 0 97 5 1583 0 184 230 2 405 14 56 25 12 1729 4 1 0 94 6 570 0 6 500 103 479 16 63 33 13 1426 2 1 0 97 7 32410 0 7 202 6 335 8 44 35 10 1991 10 7 0 84 March 2, 2026 at 06:55:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 507 2371 209 217 0 14 74 0 597 0 2 0 98 1 1 0 0 135 4 130 1 17 78 0 1412 0 1 0 99 2 2 0 14 119 5 75 1 13 67 0 266 0 0 0 100 3 0 0 0 196 63 107 0 15 75 0 0 0 0 0 100 4 0 0 7 225 50 197 0 18 81 0 263 0 0 0 100 5 0 0 0 125 2 88 0 11 68 0 1 0 0 0 100 6 0 0 4 374 103 183 0 17 68 0 0 0 0 0 100 7 0 0 0 125 1 88 0 11 61 0 0 0 0 0 100 March 2, 2026 at 06:55:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 207 114 0 0 0 0 309 0 0 0 99 1 0 0 0 15 3 38 2 0 1 0 1695 0 0 0 100 2 0 0 14 11 3 6 0 0 0 0 266 0 0 0 100 3 0 0 0 109 51 105 0 1 0 0 0 0 0 0 100 4 0 0 7 11 4 6 0 0 0 0 260 0 0 0 100 5 0 0 0 10 1 6 0 0 0 0 1 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 15 1 10 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 208 122 0 0 1 0 311 0 0 0 99 1 0 0 0 19 3 48 1 1 1 0 1691 0 0 0 100 2 0 0 14 15 3 13 0 2 0 0 271 0 0 0 100 3 0 0 0 80 36 76 0 1 0 0 8 0 0 0 100 4 0 0 7 11 4 6 0 0 0 0 260 0 0 0 100 5 0 0 0 54 23 50 0 1 0 0 13 0 0 0 100 6 0 0 4 209 102 2 0 0 0 0 1 0 0 0 100 7 0 0 0 16 1 11 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2881 0 454 2867 207 1098 44 229 100 48 4560 7 4 0 88 1 9119 0 137 662 4 1084 38 217 161 51 7093 8 5 0 87 2 43591 0 153 628 4 1035 42 200 160 77 5185 14 11 0 75 3 3785 0 11 680 3 1216 38 230 126 55 4876 4 3 0 93 4 1182 0 15 630 10 1093 31 196 93 52 6149 4 3 0 93 5 791 0 10 569 26 988 28 178 104 58 3138 5 2 0 93 6 1385 0 29 742 103 984 35 183 89 54 3657 3 3 0 94 7 513 0 22 443 19 723 25 130 50 23 2117 3 2 0 95 March 2, 2026 at 06:55:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 66 0 94 2320 205 123 0 2 6 0 326 0 2 0 98 1 0 0 0 33 4 48 1 1 6 0 1706 0 1 0 99 2 19 0 14 27 2 13 4 3 0 0 279 0 0 0 100 3 9 0 0 30 4 15 0 1 0 0 39 0 0 0 100 4 0 0 0 26 2 12 0 2 0 0 31 0 0 0 100 5 13 0 0 31 3 16 0 2 0 0 28 0 0 0 100 6 3 0 11 231 104 14 0 5 0 0 283 0 0 0 100 7 7 0 0 135 51 119 0 3 0 0 7 0 0 0 100 March 2, 2026 at 06:55:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2439 223 193 0 15 76 0 309 0 2 0 98 1 0 0 462 67 3 129 1 15 77 0 1693 0 1 0 98 2 0 0 14 146 1 94 0 10 70 0 266 0 0 0 100 3 0 0 0 192 61 109 0 17 91 0 0 0 0 0 100 4 0 0 0 132 2 110 0 14 75 0 0 0 0 0 100 5 0 0 0 124 0 97 0 12 92 0 0 0 0 0 100 6 0 0 11 376 103 195 0 19 53 0 260 0 0 0 100 7 0 0 0 189 36 140 0 12 55 0 1 0 0 0 100 March 2, 2026 at 06:55:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2368 258 224 0 0 0 0 311 0 0 0 99 1 0 0 0 12 3 36 1 0 0 0 1693 0 0 0 100 2 0 0 14 7 1 4 0 0 0 0 266 0 0 0 100 3 0 0 0 13 3 8 0 1 0 0 0 0 0 0 100 4 0 0 0 14 2 14 0 1 0 0 0 0 0 0 100 5 0 0 0 10 1 6 0 0 0 0 1 0 0 0 100 6 0 0 11 210 103 4 0 0 0 0 260 0 0 0 100 7 0 0 0 10 1 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:55:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1979 0 242 2605 247 586 14 84 41 43 2607 4 2 0 94 1 362 0 10 274 4 454 6 85 73 49 3299 1 2 0 97 2 8526 0 156 243 2 440 11 88 148 55 2789 2 4 0 94 3 37432 0 41 335 4 420 17 87 137 47 2499 10 9 0 81 4 672 0 15 271 3 437 4 72 62 46 2781 1 2 0 97 5 1760 0 119 291 10 468 6 76 48 47 1794 2 2 0 96 6 378 0 23 456 110 407 8 84 49 35 1848 1 1 0 97 7 252 0 7 198 2 307 7 74 43 35 1472 1 1 0 98 March 2, 2026 at 06:55:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1543 0 102 2705 203 663 24 114 49 5 2650 3 3 0 94 1 2381 0 12 408 6 735 23 104 44 7 3629 7 2 0 91 2 1690 0 21 382 4 629 21 85 75 13 2153 3 2 0 96 3 3067 0 0 354 6 608 23 83 62 7 2374 3 2 0 95 4 653 0 0 371 46 595 11 80 54 7 2006 3 1 0 96 5 1183 0 176 252 1 445 15 56 45 13 1454 2 1 0 96 6 1356 0 10 559 105 646 28 101 56 19 3172 5 2 0 93 7 248 0 2 272 1 478 26 73 19 11 1210 2 1 0 98 March 2, 2026 at 06:55:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2373 201 112 0 0 4 0 300 0 1 0 99 1 0 0 462 24 4 42 1 0 5 0 1681 0 1 0 99 2 0 0 14 83 2 6 0 1 1 0 266 0 0 0 100 3 40 0 0 127 24 50 0 2 1 0 11 0 0 0 100 4 0 0 0 156 40 76 0 1 0 0 0 0 0 0 100 5 0 0 0 87 3 4 0 0 1 0 0 0 0 0 100 6 0 0 11 289 104 16 0 1 1 0 263 0 0 0 100 7 0 0 0 83 2 4 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:55:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2351 203 217 2 21 60 0 1108 0 1 0 99 1 0 0 0 65 3 117 1 25 89 0 874 0 0 0 100 2 0 0 14 51 1 85 0 15 55 0 266 0 0 0 100 3 0 0 0 219 111 213 1 16 88 0 8 0 0 0 100 4 0 0 0 54 3 252 1 17 84 0 331 0 0 0 100 5 0 0 0 49 2 80 0 13 56 0 2 0 0 0 100 6 0 0 11 297 104 178 0 19 76 0 260 0 0 0 100 7 0 0 0 49 1 86 0 15 75 0 0 0 0 0 100 March 2, 2026 at 06:55:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 204 146 1 0 0 0 1391 0 1 0 99 1 0 0 0 11 2 6 1 0 0 0 595 0 0 0 100 2 0 0 14 7 1 4 0 0 0 0 266 0 0 0 100 3 0 0 0 125 60 120 0 0 0 0 9 0 0 0 100 4 0 0 0 9 2 6 0 2 0 0 2 0 0 0 100 5 0 0 0 12 2 8 0 0 0 0 3 0 0 0 100 6 0 0 11 213 103 8 0 1 0 0 261 0 0 0 100 7 0 0 0 14 1 14 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:55:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4274 0 106 2901 220 1032 33 171 120 66 6698 6 4 0 90 1 35763 0 260 529 4 953 33 170 100 51 4580 13 10 0 77 2 3985 0 22 577 2 987 35 151 119 67 4537 4 4 0 92 3 9480 0 387 529 23 932 32 153 180 60 5684 6 5 0 89 4 5411 0 24 530 3 948 24 185 154 75 3460 5 4 0 91 5 803 0 8 492 8 856 20 155 100 72 2664 3 2 0 95 6 3033 0 33 766 120 846 20 163 92 53 2975 6 2 0 92 7 837 0 14 447 7 694 12 107 65 44 2119 2 1 0 97 March 2, 2026 at 06:55:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 87 2323 212 106 1 4 6 0 1399 0 2 0 98 1 0 0 0 172 42 158 0 5 6 0 596 0 1 0 99 2 6 0 14 24 1 8 0 2 0 0 279 0 0 0 100 3 0 0 0 26 2 8 0 1 0 0 9 0 0 0 100 4 62 0 7 39 9 21 0 2 0 0 32 0 0 0 100 5 1 0 0 30 2 12 0 3 0 0 18 0 0 0 100 6 0 0 11 230 105 9 0 0 0 0 274 0 0 0 100 7 25 0 0 24 1 6 1 1 0 0 10 0 0 0 100 March 2, 2026 at 06:55:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2376 203 136 0 2 3 0 1395 0 2 0 98 1 0 0 462 141 52 138 0 3 3 0 594 0 1 0 99 2 0 0 14 79 1 4 0 0 0 0 266 0 0 0 100 3 0 0 0 81 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 92 7 14 0 0 0 0 8 0 0 0 100 5 0 0 0 81 0 6 0 1 0 0 0 0 0 0 100 6 0 0 10 284 104 6 0 0 0 0 260 0 0 0 100 7 0 0 0 81 1 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:55:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2345 202 218 1 13 55 0 1393 0 1 0 99 1 0 0 0 165 52 218 0 20 90 0 593 0 0 0 100 2 0 0 14 53 2 95 0 17 64 0 266 0 0 0 100 3 0 0 0 122 72 88 0 13 69 0 0 0 0 0 100 4 0 0 0 76 8 130 0 18 74 0 9 0 0 0 100 5 0 0 0 55 1 96 0 9 83 0 1 0 0 0 100 6 0 0 10 320 104 221 0 16 60 0 260 0 0 0 100 7 0 0 0 64 2 109 0 17 89 0 1 0 0 0 100 March 2, 2026 at 06:55:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3614 0 89 2852 203 1114 29 206 120 65 5926 4 4 0 91 1 2763 0 131 648 34 1128 38 209 149 65 5056 5 4 0 92 2 34444 0 12 529 6 893 24 147 94 62 3678 11 8 0 81 3 2314 0 186 533 10 911 28 167 107 44 3788 5 3 0 92 4 756 0 3 515 14 837 24 138 104 52 2766 3 2 0 95 5 8509 0 308 446 0 815 30 126 115 54 3859 6 4 0 90 6 10216 0 58 804 105 886 30 154 132 60 3925 7 5 0 89 7 809 0 33 435 2 791 15 121 95 72 4360 3 2 0 95 March 2, 2026 at 06:55:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2314 203 118 1 8 5 0 1703 0 2 0 98 1 9 0 0 108 20 99 0 7 6 0 320 0 1 0 99 2 93 0 0 38 5 24 0 1 0 0 42 0 0 0 100 3 31 0 0 40 3 28 0 3 0 0 41 1 0 0 99 4 0 0 0 84 32 62 0 1 0 0 14 0 0 0 100 5 1 0 0 40 7 26 0 3 0 0 28 0 0 0 100 6 14 0 18 236 107 18 1 2 0 0 267 0 0 0 100 7 8 0 14 26 2 11 0 1 1 0 277 0 0 0 100 March 2, 2026 at 06:55:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2342 203 146 0 0 3 0 1392 0 1 0 99 1 0 0 231 82 36 76 1 0 4 0 595 0 1 0 99 2 0 0 0 84 21 46 0 1 0 0 8 0 0 0 100 3 0 0 0 45 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 45 1 10 0 1 0 0 0 0 0 0 100 5 0 0 0 42 0 4 0 0 0 0 0 0 0 0 100 6 0 0 11 248 104 8 0 0 1 0 262 0 0 0 100 7 0 0 14 42 2 6 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:55:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 42 2341 202 126 1 3 1 0 1390 0 2 0 98 1 0 0 231 43 3 30 0 2 3 0 594 0 0 0 100 2 0 0 0 160 57 114 0 0 1 0 9 0 0 0 100 3 0 0 0 50 3 4 0 0 1 0 0 0 0 0 100 4 0 0 0 47 2 0 0 0 1 0 0 0 0 0 100 5 0 0 0 50 2 4 0 0 1 0 1 0 0 0 100 6 0 0 14 258 105 18 0 0 4 0 260 0 1 0 99 7 0 0 14 48 3 4 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:55:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2356 203 222 1 13 65 0 1393 0 1 0 99 1 0 0 0 50 2 86 0 18 76 0 593 0 0 0 100 2 0 0 0 155 56 187 0 17 61 0 6 0 0 0 100 3 0 0 0 108 58 94 0 18 84 0 0 0 0 0 100 4 0 0 0 59 1 105 0 20 75 0 0 0 0 0 100 5 0 0 0 50 2 84 0 11 70 0 1 0 0 0 100 6 0 0 11 305 105 192 0 14 68 0 260 0 0 0 100 7 0 0 14 58 2 110 1 16 87 0 266 0 0 0 100 March 2, 2026 at 06:55:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1184 0 107 2956 209 1315 50 244 95 49 5721 4 4 0 92 1 1893 0 118 645 6 1159 57 241 56 52 4966 5 3 0 92 2 726 0 8 660 9 1068 40 188 85 38 3631 4 2 0 94 3 2799 0 193 604 6 1076 51 217 85 51 3943 5 4 0 91 4 1998 0 20 623 5 1074 32 207 128 46 5212 7 3 0 90 5 11146 0 309 489 2 921 34 156 167 71 5238 8 6 0 87 6 9999 0 64 953 108 1135 35 191 179 67 5804 6 5 0 89 7 33550 0 35 605 31 1040 36 167 100 66 3866 12 8 0 80 March 2, 2026 at 06:55:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 73 2310 203 138 1 2 6 0 1388 0 2 0 98 1 40 0 0 52 8 36 1 2 6 0 604 0 1 0 99 2 0 0 0 22 0 6 0 0 0 0 5 0 0 0 100 3 1 0 0 26 3 10 0 0 0 0 8 0 0 0 100 4 0 0 0 23 3 4 0 0 0 0 1 0 0 0 100 5 0 0 7 34 8 20 0 1 0 0 14 0 0 0 100 6 0 0 11 229 106 10 0 0 0 0 264 0 0 0 100 7 2 0 14 122 52 111 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2375 202 144 0 0 2 0 1387 0 2 0 98 1 0 0 462 34 8 28 0 1 2 0 602 0 1 0 99 2 0 0 0 79 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 81 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 80 2 2 0 0 0 0 21 0 0 0 100 5 0 0 0 86 2 8 0 0 0 0 2 0 0 0 100 6 0 0 10 289 105 12 0 2 0 0 260 0 0 0 100 7 0 0 14 184 52 118 0 2 0 0 266 0 0 0 100 March 2, 2026 at 06:55:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 203 144 1 0 0 0 1389 0 1 0 99 1 0 0 0 28 8 28 0 1 0 0 604 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 6 0 0 11 214 105 8 0 0 0 0 260 0 0 0 100 7 0 0 14 110 52 106 1 1 1 0 266 0 0 0 100 March 2, 2026 at 06:55:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4226 0 85 2901 210 1137 31 180 173 55 4250 4 4 0 93 1 33794 0 15 573 12 936 41 185 110 65 4918 13 8 0 78 2 4320 0 142 510 1 773 33 162 173 37 3458 6 3 0 91 3 1224 0 15 599 54 966 25 185 216 49 3912 3 2 0 94 4 2504 0 364 481 8 936 26 175 209 74 3908 3 3 0 94 5 8074 0 14 486 2 854 26 140 227 62 4196 5 4 0 90 6 6492 0 47 802 106 988 20 168 241 71 4495 7 4 0 89 7 3064 0 168 521 29 919 23 152 190 52 3524 5 2 0 93 March 2, 2026 at 06:55:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2320 203 130 2 3 0 0 1400 0 1 0 99 1 13 0 0 32 4 18 0 1 6 0 613 0 0 0 100 2 3 0 0 31 1 20 1 3 1 0 12 0 0 0 100 3 0 0 0 26 2 8 0 1 0 0 15 0 0 0 100 4 40 0 0 110 44 91 0 3 1 0 24 0 0 0 100 5 8 0 0 70 12 50 0 2 0 0 10 0 0 0 100 6 1 0 11 230 104 12 0 1 0 0 264 0 0 0 100 7 12 0 84 20 4 14 0 1 6 0 284 0 1 0 99 March 2, 2026 at 06:55:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2365 202 148 0 0 0 0 1388 0 1 0 99 1 0 0 350 19 2 10 1 1 3 0 594 0 1 0 99 2 0 0 0 70 0 10 0 0 0 0 5 0 0 0 100 3 0 0 0 71 2 18 0 1 1 0 7 0 0 0 100 4 0 0 0 71 6 10 0 0 0 0 8 0 0 0 100 5 0 0 0 176 57 116 0 1 1 0 17 0 0 0 100 6 0 0 10 267 104 6 0 0 0 0 263 0 0 0 100 7 0 0 49 66 3 16 0 1 3 0 266 0 1 0 99 March 2, 2026 at 06:55:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2323 203 144 1 0 0 0 1388 0 1 0 99 1 0 0 0 27 2 6 0 1 0 0 594 0 0 0 100 2 0 0 0 26 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 25 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 34 7 12 0 0 0 0 9 0 0 0 100 5 0 0 0 124 50 104 0 0 0 0 0 0 0 0 100 6 0 0 11 228 104 6 0 0 0 0 260 0 0 0 100 7 0 0 126 11 3 9 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1527 0 56 2523 204 510 11 77 64 36 2821 3 2 0 94 1 891 0 189 225 6 355 8 78 38 32 2285 1 1 0 97 2 2347 0 41 279 1 373 9 72 50 33 1988 3 2 0 95 3 413 0 13 240 3 388 4 78 39 35 1556 1 1 0 98 4 2500 0 11 223 9 333 6 67 41 28 1281 1 1 0 98 5 2577 0 18 292 46 421 3 65 59 29 1226 1 2 0 97 6 227 0 32 387 104 305 3 65 56 26 1279 1 1 0 98 7 3224 0 139 182 5 302 13 46 75 38 3267 2 2 0 96 March 2, 2026 at 06:55:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 722 0 46 2833 203 1070 46 172 155 30 3474 3 3 0 94 1 1671 0 182 484 15 871 29 147 158 28 3174 3 2 0 95 2 779 0 2 501 21 815 26 124 142 26 2155 2 2 0 96 3 33949 0 14 532 80 899 30 142 143 20 3388 12 8 0 80 4 3269 0 117 378 3 654 15 122 131 31 2357 4 2 0 93 5 2359 0 9 365 3 653 20 97 133 20 1997 2 2 0 96 6 5505 0 98 663 106 708 24 116 188 25 3863 6 3 0 91 7 1743 0 19 411 4 704 14 85 114 29 2887 3 2 0 94 March 2, 2026 at 06:55:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2378 202 116 0 2 0 0 1090 0 1 0 99 1 40 0 0 117 8 37 0 2 0 0 590 0 0 0 100 2 0 0 0 106 12 27 0 2 0 0 17 0 0 0 100 3 0 0 0 156 36 79 0 3 0 0 0 0 0 0 100 4 0 0 0 88 5 10 0 1 0 0 0 0 0 0 100 5 0 0 0 85 2 10 0 1 0 0 2 0 0 0 100 6 0 0 52 282 105 10 0 1 2 0 563 0 1 0 99 7 4 0 476 18 2 6 0 0 2 0 268 0 1 0 99 March 2, 2026 at 06:55:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 203 142 1 2 0 0 1092 0 1 0 99 1 0 0 0 44 17 40 0 2 0 0 310 0 0 0 100 2 0 0 0 13 1 8 0 0 0 0 299 0 0 0 100 3 0 0 0 20 3 14 0 0 0 0 6 0 0 0 100 4 0 0 0 86 41 78 0 0 0 0 0 0 0 0 100 5 0 0 0 24 7 18 0 0 1 0 15 0 0 0 100 6 0 0 11 221 106 20 0 1 0 0 562 0 0 0 100 7 0 0 14 10 2 9 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 142 1 0 0 0 1090 0 1 0 99 1 0 0 0 121 58 116 0 0 0 0 309 0 0 0 100 2 0 0 0 9 1 4 0 1 0 0 294 0 0 0 100 3 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 10 1 6 0 1 0 0 1 0 0 0 100 6 0 0 11 216 105 10 0 0 1 0 559 0 0 0 100 7 0 0 14 13 2 14 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:55:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 868 0 92 2851 204 1109 37 190 83 58 4541 4 3 0 93 1 3025 0 314 625 31 1139 36 196 95 45 4934 6 4 0 90 2 34235 0 26 556 5 980 27 166 107 37 4194 12 8 0 80 3 1216 0 9 505 13 886 27 164 87 45 3488 3 3 0 94 4 1617 0 5 470 14 757 16 155 108 43 2990 3 2 0 95 5 10463 0 309 407 1 740 11 132 190 57 3854 6 5 0 89 6 10418 0 49 845 104 965 29 152 164 65 5588 7 4 0 89 7 1711 0 26 446 4 848 16 149 121 77 4283 4 3 0 93 March 2, 2026 at 06:55:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2359 202 167 1 14 87 0 1094 0 2 0 98 1 11 0 0 153 2 197 0 26 97 0 310 0 1 0 99 2 53 0 0 78 8 104 0 14 44 0 321 0 0 0 100 3 0 0 0 126 55 205 0 26 82 0 18 0 0 0 100 4 3 0 0 102 19 126 1 24 82 0 15 0 0 0 100 5 0 0 0 123 34 138 0 14 36 0 14 0 0 0 100 6 5 0 25 263 103 79 0 13 79 0 577 0 0 0 100 7 6 0 7 54 4 66 0 10 60 0 270 0 0 0 100 March 2, 2026 at 06:55:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2375 203 80 1 1 4 0 1089 0 2 0 98 1 0 0 462 94 1 92 0 1 3 0 300 0 1 0 99 2 0 0 0 81 2 4 0 0 0 0 294 0 0 0 100 3 0 0 0 95 8 18 0 0 0 0 9 0 0 0 100 4 0 0 0 78 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 180 50 104 0 0 0 0 0 0 0 0 100 6 0 0 18 284 103 6 1 0 0 0 566 0 0 0 100 7 2 0 7 83 3 8 0 1 0 0 263 0 0 0 100 March 2, 2026 at 06:55:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 124 0 0 0 0 1087 0 1 0 99 1 0 0 0 28 1 23 0 3 0 0 312 0 0 0 100 2 0 0 0 13 2 9 0 1 0 0 282 0 0 0 100 3 0 0 0 25 8 22 0 0 0 0 14 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 1 0 0 122 57 116 0 0 0 0 14 0 0 0 100 6 0 0 18 209 103 4 0 0 0 0 566 0 0 0 100 7 0 0 7 13 3 11 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:55:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4567 0 61 2659 204 562 5 101 99 34 4041 2 3 0 95 1 1096 0 251 298 9 489 11 109 55 49 2407 1 2 0 97 2 2812 0 26 308 2 370 7 79 50 40 1336 3 1 0 96 3 33706 0 22 280 10 435 19 89 62 52 2302 10 6 0 84 4 253 0 32 251 2 382 10 90 44 32 1284 1 2 0 97 5 3374 0 116 288 40 434 5 63 80 44 2940 2 2 0 97 6 1291 0 150 421 107 386 5 88 65 33 2412 2 2 0 96 7 2683 0 18 224 3 357 10 63 102 41 2440 1 1 0 97 March 2, 2026 at 06:55:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 972 0 49 2604 202 658 16 91 60 8 2741 4 2 0 94 1 2307 0 177 319 7 482 13 68 51 8 2942 4 2 0 94 2 2481 0 9 279 4 463 23 74 72 21 2283 3 2 0 96 3 5605 0 14 344 5 457 23 82 86 11 1815 5 4 0 91 4 734 0 73 267 4 497 18 76 52 25 1500 2 2 0 96 5 250 0 0 227 3 389 12 59 45 10 1061 1 1 0 98 6 790 0 21 524 148 492 16 57 71 8 2057 2 1 0 97 7 524 0 7 205 6 342 10 41 28 7 1296 2 1 0 98 March 2, 2026 at 06:55:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2426 203 226 1 15 73 0 1089 0 1 0 99 1 0 0 0 137 3 114 1 18 83 0 593 0 0 0 99 2 0 0 0 129 1 98 0 18 70 0 0 0 0 0 100 3 0 0 0 200 70 235 0 24 87 0 0 0 0 0 100 4 0 0 42 126 1 106 0 18 67 0 0 0 1 0 99 5 0 0 462 53 1 85 0 10 66 0 1 0 1 0 99 6 0 0 18 434 153 210 1 14 99 0 566 0 0 0 100 7 40 0 7 118 8 65 0 11 47 0 271 0 0 0 100 March 2, 2026 at 06:55:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 146 0 1 0 0 1088 0 1 0 99 1 0 0 0 11 2 6 0 1 0 0 595 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 11 1 10 0 1 1 0 0 0 0 0 100 5 0 0 0 10 1 6 0 0 0 0 1 0 0 0 100 6 0 0 18 309 153 104 0 0 0 0 567 0 0 0 100 7 0 0 7 22 9 18 0 0 0 0 269 0 0 0 100 March 2, 2026 at 06:55:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 203 134 1 1 0 0 1089 0 1 0 99 1 0 0 0 27 2 21 0 1 0 0 581 0 0 0 100 2 0 0 0 12 1 7 0 1 0 0 22 0 0 0 100 3 0 0 0 14 3 10 1 0 0 0 6 0 0 0 100 4 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 5 0 0 0 26 8 24 0 1 0 0 17 0 0 0 100 6 0 0 18 311 154 106 0 0 0 0 566 0 0 0 100 7 0 0 7 28 10 27 0 0 0 0 270 0 0 0 100 March 2, 2026 at 06:55:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37094 0 78 3065 204 1282 64 230 133 71 6585 16 11 0 72 1 1618 0 18 685 4 1238 57 250 143 55 6438 6 4 0 90 2 1508 0 25 656 23 1142 49 208 100 56 3795 4 3 0 93 3 4987 0 487 612 8 1235 42 239 119 80 4523 5 4 0 91 4 629 0 17 583 4 1020 46 212 96 57 3414 4 3 0 94 5 1393 0 14 536 5 893 31 172 106 37 3788 4 3 0 93 6 9575 0 166 728 112 963 34 170 177 67 4398 6 5 0 88 7 6602 0 18 627 17 944 26 148 128 58 4551 5 3 0 91 March 2, 2026 at 06:56:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 17 2338 218 188 2 3 1 0 1105 0 1 0 99 1 9 0 0 27 2 10 0 0 0 0 323 0 0 0 100 2 3 0 70 33 10 30 0 2 5 0 316 0 1 0 99 3 0 0 0 26 2 10 0 2 5 0 15 0 0 0 100 4 22 0 7 74 27 58 0 3 0 0 8 0 0 0 100 5 3 0 0 28 1 10 0 1 3 0 10 0 0 0 100 6 42 0 18 245 107 37 1 4 0 0 593 0 0 0 100 7 13 0 7 30 5 12 0 1 2 0 282 0 0 0 100 March 2, 2026 at 06:56:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2475 251 327 1 11 84 0 1089 0 1 0 99 1 0 0 0 133 2 110 0 14 84 0 300 0 0 0 100 2 0 0 42 117 2 88 0 8 80 0 294 0 1 0 99 3 0 0 462 115 59 207 0 12 89 0 0 0 1 0 99 4 0 0 0 125 2 88 0 15 78 0 0 0 0 0 100 5 0 0 0 123 0 86 0 11 54 0 0 0 0 0 100 6 0 0 17 344 109 111 0 14 86 0 575 0 0 0 100 7 0 0 7 130 4 103 0 16 70 0 261 0 0 0 100 March 2, 2026 at 06:56:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2359 252 242 1 2 0 0 1093 0 1 0 99 1 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 3 0 0 0 14 2 8 0 1 0 0 0 0 0 0 100 4 0 0 0 10 2 4 0 0 0 0 0 0 0 0 100 5 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 6 2 0 17 222 109 16 1 0 0 0 644 1 0 0 99 7 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3476 0 117 2930 235 1125 31 169 117 89 4839 5 4 0 92 1 3231 0 121 551 7 960 35 185 97 59 6344 6 3 0 91 2 1400 0 36 481 2 831 13 139 116 55 3266 3 3 0 94 3 2403 0 188 609 3 1127 34 164 101 53 3651 3 3 0 93 4 1140 0 4 489 16 781 9 131 80 48 2673 3 2 0 96 5 510 0 15 440 9 733 13 112 105 40 3149 2 2 0 96 6 10825 0 319 682 111 900 37 144 199 62 4955 5 5 0 89 7 40531 0 37 424 3 570 19 110 123 55 3286 12 9 0 79 March 2, 2026 at 06:56:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37 0 101 2316 206 137 2 5 4 0 1399 2 2 0 96 1 53 0 0 54 2 50 0 6 5 0 327 0 1 0 99 2 2 0 0 21 0 2 0 0 0 0 9 0 0 0 100 3 1 0 0 31 3 13 0 3 0 0 310 0 0 0 100 4 40 0 0 42 7 24 0 2 0 0 25 0 0 0 100 5 13 0 0 129 52 116 0 2 0 0 18 0 0 0 100 6 2 0 11 228 102 11 1 2 0 0 10 1 0 0 99 7 8 0 7 28 3 10 0 1 0 0 580 0 0 0 100 March 2, 2026 at 06:56:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2342 203 86 1 3 5 0 1356 0 2 0 98 1 0 0 238 86 3 78 0 3 5 0 300 0 1 0 99 2 0 0 0 45 1 0 0 0 1 0 0 0 0 0 100 3 0 0 0 51 4 6 0 0 1 0 294 0 0 0 100 4 0 0 0 62 9 16 0 1 1 0 9 0 0 0 100 5 0 0 0 147 51 102 0 0 1 0 0 0 0 0 100 6 0 0 4 247 101 2 0 0 1 0 0 0 0 0 100 7 0 0 7 51 4 8 0 1 1 0 562 0 0 0 100 March 2, 2026 at 06:56:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2383 204 223 1 20 69 0 1358 0 1 0 99 1 0 0 224 64 2 106 0 14 81 0 300 0 0 0 99 2 0 0 0 71 0 72 0 17 56 0 0 0 0 0 100 3 0 0 0 171 78 226 0 12 64 0 294 0 0 0 100 4 0 0 0 100 7 98 0 10 70 0 6 0 0 0 100 5 0 0 0 147 34 146 0 10 50 0 1 0 0 0 100 6 0 0 4 285 102 88 0 14 104 0 0 0 0 0 100 7 0 0 7 78 3 82 0 13 54 0 561 0 0 0 100 March 2, 2026 at 06:56:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 31 2309 204 142 1 0 0 0 1356 0 1 0 99 1 0 0 0 13 2 6 0 1 0 0 300 0 0 0 100 2 0 0 0 11 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 125 52 122 1 2 0 0 294 0 0 0 100 4 0 0 0 25 8 16 1 0 0 0 9 0 0 0 100 5 0 0 0 12 1 6 0 0 0 0 1 0 0 0 100 6 0 0 4 209 101 0 0 0 0 0 0 0 0 0 100 7 0 0 7 12 3 6 0 0 0 0 559 0 0 0 100 March 2, 2026 at 06:56:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35550 0 317 2853 208 1076 38 197 134 62 6493 15 11 0 74 1 3171 0 237 619 3 1150 33 220 135 73 6232 5 4 0 92 2 1686 0 202 570 4 1037 38 205 91 70 3908 4 3 0 93 3 834 0 31 650 9 1208 35 225 69 72 4243 4 3 0 93 4 1321 0 14 568 8 976 24 207 80 45 3129 4 3 0 94 5 870 0 7 489 11 780 26 141 120 38 2846 3 3 0 94 6 11129 0 21 740 133 936 24 190 189 38 4515 7 4 0 88 7 8667 0 35 583 13 767 17 127 141 48 3972 6 3 0 91 March 2, 2026 at 06:56:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 94 2310 204 138 1 4 4 0 1356 0 2 0 98 1 40 0 0 48 8 32 0 2 5 0 309 0 0 0 99 2 0 0 0 18 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 28 2 10 0 0 0 0 294 0 0 0 100 4 0 0 0 26 2 14 0 2 0 0 0 0 0 0 100 5 0 0 0 21 1 4 0 1 0 0 0 0 0 0 100 6 0 0 4 322 152 102 0 0 0 0 1 0 0 0 100 7 0 0 7 23 3 8 0 0 0 0 562 0 0 0 100 March 2, 2026 at 06:56:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 59 2377 205 121 1 0 2 0 667 0 2 0 98 1 0 0 462 37 8 64 0 4 2 0 1001 0 1 0 99 2 0 0 0 77 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 81 2 4 0 0 0 0 294 0 0 0 100 4 0 0 0 84 2 6 0 0 0 0 0 0 0 0 100 5 0 0 0 85 0 14 0 1 0 0 0 0 0 0 100 6 0 0 4 381 152 102 0 0 0 0 1 0 0 0 100 7 0 0 7 82 3 6 0 0 0 0 561 0 0 0 100 March 2, 2026 at 06:56:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2341 202 188 1 11 90 0 266 0 1 0 99 1 0 0 0 62 10 125 1 12 66 0 1399 0 0 0 99 2 0 0 0 44 0 74 0 10 51 0 0 0 0 0 100 3 0 0 0 94 53 173 0 17 54 0 294 0 0 0 100 4 0 0 0 59 2 106 0 19 82 0 0 0 0 0 100 5 0 0 0 48 1 85 0 16 70 0 1 0 0 0 100 6 0 0 3 353 152 192 0 14 84 0 0 0 0 0 100 7 0 0 7 46 4 75 0 8 61 0 560 0 0 0 100 March 2, 2026 at 06:56:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3510 0 237 2889 211 1155 34 221 108 74 6898 6 5 0 89 1 37219 0 155 696 10 1088 50 235 132 77 5636 15 10 0 75 2 627 0 15 591 4 1009 40 195 104 55 3503 3 2 0 94 3 6056 0 9 548 4 997 31 190 139 48 5036 5 4 0 91 4 4001 0 193 570 11 992 23 185 110 57 3134 4 4 0 93 5 872 0 10 481 1 838 27 165 105 62 3054 3 2 0 95 6 7066 0 205 778 128 1047 54 194 177 57 4603 6 5 0 89 7 4558 0 32 514 4 831 19 136 137 56 3912 6 3 0 91 March 2, 2026 at 06:56:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 101 2309 202 152 1 0 6 0 1373 0 2 0 98 1 40 0 0 44 6 39 0 3 7 0 321 0 1 0 99 2 0 0 7 23 1 8 0 1 0 0 22 0 0 0 100 3 32 0 0 29 4 12 0 2 1 0 313 0 0 0 100 4 3 0 0 94 36 76 0 0 1 0 16 0 0 0 100 5 8 0 0 74 26 58 0 2 0 0 28 0 0 0 100 6 1 0 4 235 103 20 0 2 0 0 17 0 0 0 100 7 22 0 7 33 3 25 0 3 1 0 568 0 0 0 100 March 2, 2026 at 06:56:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 52 2356 202 88 1 1 2 0 1353 0 2 0 98 1 0 0 350 91 9 88 0 1 3 0 311 0 1 0 99 2 0 0 0 66 1 6 0 3 0 0 0 0 0 0 100 3 0 0 0 65 2 4 0 0 0 0 294 0 0 0 100 4 0 0 0 67 2 6 0 2 0 0 0 0 0 0 100 5 0 0 0 163 50 104 0 0 0 0 0 0 0 0 100 6 0 0 4 264 102 2 0 0 0 0 0 0 0 0 100 7 0 0 7 65 3 6 0 0 0 0 562 0 0 0 100 March 2, 2026 at 06:56:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2352 228 110 2 6 0 0 1353 0 1 0 99 1 0 0 0 135 9 108 0 0 1 0 309 0 0 0 100 2 0 0 0 33 1 8 0 0 1 0 0 0 0 0 100 3 0 0 0 28 3 4 0 0 1 0 294 0 0 0 100 4 0 0 0 29 3 4 0 0 1 0 0 0 0 0 100 5 0 0 112 61 26 53 0 2 1 0 0 0 0 0 100 6 0 0 7 226 102 2 0 0 1 0 0 0 0 0 100 7 2 0 7 31 4 8 0 0 1 0 563 0 0 0 100 March 2, 2026 at 06:56:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 639 0 46 2586 251 579 4 89 110 30 2180 1 2 0 97 1 541 0 9 318 16 500 3 97 126 27 1049 1 2 0 97 2 835 0 23 227 2 356 9 74 130 16 1184 2 2 0 96 3 3498 0 113 277 58 519 7 78 130 28 2206 1 2 0 97 4 3042 0 210 219 3 411 12 75 135 44 2478 1 2 0 97 5 3107 0 15 210 3 346 1 66 141 38 1535 1 2 0 97 6 326 0 10 407 103 370 5 75 105 33 1170 1 1 0 98 7 1512 0 23 256 4 288 1 50 66 19 1316 2 1 0 97 March 2, 2026 at 06:56:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2517 0 81 2779 204 832 22 132 64 28 4333 4 3 0 93 1 1768 0 185 437 2 788 19 127 84 30 2921 3 3 0 95 2 33965 0 88 358 2 582 22 85 98 27 2611 12 9 0 79 3 849 0 8 477 41 813 28 118 88 27 3222 3 2 0 95 4 4800 0 9 335 4 555 13 104 80 37 2919 4 2 0 94 5 4559 0 24 256 4 409 13 68 101 19 2258 3 2 0 95 6 1251 0 119 515 104 606 17 104 78 32 1924 2 1 0 96 7 593 0 10 281 15 446 11 65 49 27 1569 2 1 0 97 March 2, 2026 at 06:56:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 17 2379 203 140 1 0 0 0 1357 0 1 0 99 1 0 0 0 87 3 10 0 1 0 0 302 0 0 0 100 2 0 0 42 75 0 4 0 1 2 0 0 0 1 0 99 3 0 0 0 195 52 122 0 1 0 0 1 0 0 0 100 4 40 0 0 96 8 20 0 0 0 0 16 0 0 0 100 5 0 0 462 39 12 24 0 0 5 0 609 0 1 0 99 6 0 0 4 290 103 10 0 1 0 0 6 0 0 0 100 7 0 0 7 86 2 11 0 0 0 0 263 0 0 0 100 March 2, 2026 at 06:56:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2306 203 140 1 1 1 0 1350 0 1 0 99 1 4 0 0 15 3 12 0 1 1 0 309 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 33 0 0 0 100 3 0 0 0 116 52 110 0 1 1 0 21 0 0 0 100 4 0 0 0 27 8 26 0 1 0 0 9 0 0 0 100 5 0 0 0 12 2 8 0 1 0 0 594 0 0 0 100 6 0 0 4 212 103 6 0 0 1 0 1 0 0 0 100 7 0 0 7 9 2 6 0 1 2 0 260 0 0 0 100 March 2, 2026 at 06:56:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2305 202 142 1 0 0 0 1347 0 1 0 99 1 0 0 0 15 4 10 0 0 0 0 302 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 111 52 108 0 0 0 0 9 0 0 0 100 4 0 0 0 24 8 20 0 0 0 0 27 0 0 0 100 5 0 0 0 15 3 10 1 0 0 0 595 0 0 0 100 6 0 0 4 209 102 2 0 0 0 0 0 0 0 0 100 7 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2104 0 229 2901 203 1204 34 213 222 63 6479 5 4 0 90 1 2567 0 212 693 4 1140 39 237 161 76 4804 5 4 0 91 2 896 0 17 545 1 923 35 187 182 50 2860 3 3 0 95 3 36705 0 127 662 79 1183 38 214 182 52 4728 13 10 0 77 4 3487 0 30 573 11 991 35 205 207 64 3528 4 3 0 93 5 3394 0 6 513 3 869 20 144 188 57 4078 3 3 0 94 6 10008 0 200 781 113 941 44 180 240 52 3669 7 4 0 89 7 4126 0 17 446 19 731 24 124 195 54 2917 3 3 0 94 March 2, 2026 at 06:56:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 38 2321 204 140 2 2 0 0 1631 0 1 0 99 1 1 0 70 38 3 32 1 3 6 0 316 0 1 0 99 2 54 0 7 33 6 20 0 2 0 0 16 0 0 0 100 3 0 0 0 29 2 12 0 3 0 0 15 0 0 0 100 4 20 0 0 26 4 6 0 1 0 0 9 0 0 0 100 5 0 0 0 31 2 14 0 1 5 0 595 0 1 0 99 6 0 0 4 228 102 16 0 2 0 0 16 0 0 0 100 7 9 0 0 119 50 102 0 0 3 0 10 0 0 0 100 March 2, 2026 at 06:56:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2381 204 146 2 2 0 0 1613 0 1 0 99 1 0 0 42 79 2 8 0 0 2 0 300 0 1 0 99 2 0 0 462 26 6 16 0 1 2 0 9 0 1 0 99 3 0 0 0 85 1 8 0 2 0 0 0 0 0 0 100 4 1 0 0 84 3 8 0 0 0 0 7 0 0 0 100 5 0 0 0 102 11 24 0 0 0 0 611 0 0 0 100 6 0 0 4 285 102 6 0 0 0 0 5 0 0 0 100 7 0 0 0 180 50 105 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2311 205 140 1 0 0 0 1612 0 1 0 99 1 0 0 0 13 3 8 0 0 0 0 302 0 0 0 100 2 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 3 0 0 0 15 0 10 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 15 3 10 1 0 0 0 594 0 0 0 100 6 0 0 4 211 102 4 0 0 0 0 0 0 0 0 100 7 0 0 0 111 50 112 0 1 1 0 0 0 0 0 100 March 2, 2026 at 06:56:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 300 0 86 2587 215 597 6 101 50 53 3253 1 2 0 97 1 33962 0 22 301 4 450 14 87 60 47 2474 10 6 0 84 2 307 0 14 277 9 373 4 89 38 35 1887 1 1 0 97 3 1842 0 326 259 2 497 9 92 27 55 1977 2 2 0 97 4 1917 0 26 262 4 400 10 82 62 31 2020 2 1 0 96 5 5392 0 139 248 4 418 9 89 112 64 3720 2 4 0 94 6 2373 0 8 442 102 410 4 93 95 52 1811 1 1 0 97 7 3607 0 16 360 41 424 7 73 87 44 1738 2 2 0 96 March 2, 2026 at 06:56:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1903 0 312 2651 209 782 38 128 114 22 4054 4 4 0 93 1 1961 0 0 382 4 699 28 120 156 29 2043 4 4 0 92 2 774 0 0 358 2 635 26 105 112 13 2427 2 1 0 96 3 365 0 2 456 90 757 24 105 97 13 2144 2 1 0 97 4 334 0 7 375 9 615 22 101 131 5 1377 2 1 0 97 5 2778 0 2 323 2 521 18 71 141 7 1582 2 2 0 96 6 4838 0 18 580 115 513 15 80 164 5 1991 5 2 0 93 7 751 0 1 278 1 503 17 73 86 24 1216 2 1 0 97 March 2, 2026 at 06:56:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 66 2381 207 130 1 2 3 0 1617 0 2 0 98 1 40 0 462 50 7 42 0 4 3 0 14 0 1 0 99 2 0 0 0 89 4 10 0 0 1 0 602 0 0 0 100 3 0 0 0 99 2 28 0 2 1 0 295 0 0 0 100 4 0 0 0 86 3 8 0 1 0 0 9 0 0 0 100 5 0 0 0 88 4 8 0 0 0 0 16 0 0 0 100 6 0 0 11 381 151 104 0 1 0 0 1 0 0 0 100 7 0 0 0 78 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2312 205 120 1 2 0 0 1610 0 1 0 99 1 0 0 0 52 9 44 0 0 0 0 11 0 0 0 100 2 0 0 0 10 2 4 0 0 0 0 600 0 0 0 100 3 0 0 0 21 2 16 0 0 0 0 295 0 0 0 100 4 0 0 0 17 3 18 0 1 1 0 7 0 0 0 100 5 0 0 0 22 8 16 0 0 1 0 14 0 0 0 100 6 0 0 4 315 152 108 0 1 0 0 6 0 0 0 100 7 0 0 0 12 0 12 0 2 0 0 0 0 0 0 100 March 2, 2026 at 06:56:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2311 206 142 1 0 0 0 1610 0 1 0 99 1 0 0 0 25 9 20 0 1 0 0 10 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 599 0 0 0 100 3 0 0 0 18 1 12 1 0 0 0 294 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 6 0 0 4 309 152 102 0 0 0 0 1 0 0 0 100 7 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1459 0 104 2890 207 1228 36 221 143 97 5170 4 3 0 93 1 1415 0 132 549 7 991 31 187 100 60 3408 3 3 0 94 2 2027 0 144 511 16 877 27 167 103 61 5418 4 4 0 92 3 972 0 9 500 4 880 29 174 150 44 3668 5 2 0 93 4 35153 0 204 435 5 716 32 138 111 55 4055 14 9 0 77 5 7655 0 20 507 22 839 8 127 126 57 3456 4 5 0 92 6 8698 0 208 699 114 754 27 142 124 59 3567 6 4 0 90 7 6173 0 28 486 2 728 23 128 198 55 3585 5 3 0 93 March 2, 2026 at 06:56:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 45 2361 205 226 2 17 80 0 1622 0 1 0 99 1 2 0 0 68 2 94 0 11 82 0 9 0 1 0 99 2 0 0 0 64 2 89 0 16 52 0 619 0 0 0 100 3 1 0 0 142 59 234 0 19 67 0 327 0 0 0 100 4 9 0 70 65 3 112 0 23 69 0 31 0 1 0 99 5 25 0 0 174 51 209 0 14 68 0 10 0 0 0 99 6 53 0 4 293 109 124 0 18 80 0 29 0 0 0 100 7 0 0 0 51 2 57 0 13 47 0 3 0 0 0 100 March 2, 2026 at 06:56:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2381 205 142 1 0 0 0 1607 0 1 0 99 1 0 0 0 86 3 10 0 1 0 0 2 0 0 0 100 2 0 0 0 81 2 4 0 0 0 0 600 0 0 0 100 3 0 0 0 92 1 14 0 0 0 0 294 0 0 0 100 4 0 0 7 82 2 4 0 1 2 0 0 0 1 0 99 5 0 0 497 34 12 29 0 2 2 0 1 0 1 0 99 6 0 0 4 370 146 92 0 1 0 0 8 0 0 0 100 7 0 0 0 77 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2309 205 134 0 0 0 0 1607 0 1 0 99 1 0 0 0 18 2 14 0 1 0 0 0 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 600 0 0 0 100 3 0 0 0 18 1 12 1 0 0 0 294 0 0 0 100 4 0 0 0 10 2 6 0 0 0 0 7 0 0 0 100 5 0 0 0 25 8 20 0 0 0 0 15 0 0 0 100 6 0 0 3 323 157 118 0 0 0 0 14 0 0 0 100 7 0 0 0 14 0 17 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:56:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8773 0 126 2956 215 1113 37 185 179 72 4038 7 5 0 89 1 4480 0 240 668 9 1108 34 211 150 72 4534 8 3 0 88 2 1443 0 17 578 3 987 33 167 90 60 4280 4 3 0 93 3 2491 0 133 570 4 1065 30 182 109 55 4556 5 4 0 91 4 985 0 7 476 4 791 29 162 92 44 3091 3 2 0 95 5 788 0 15 456 2 728 25 129 85 37 3501 2 2 0 96 6 3465 0 190 722 139 868 10 142 141 50 4659 4 3 0 93 7 41243 0 138 451 2 801 28 137 126 75 5296 12 10 0 78 March 2, 2026 at 06:56:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 54 0 91 2312 201 121 0 5 7 0 30 0 1 0 98 1 8 0 14 44 5 35 1 2 7 0 286 0 0 0 99 2 14 0 7 34 5 16 0 3 2 0 608 0 0 0 100 3 6 0 0 30 2 12 1 3 1 0 331 2 0 0 98 4 49 0 0 136 57 114 0 1 1 0 21 0 0 0 100 5 26 0 7 33 5 10 0 0 1 0 269 0 0 0 100 6 0 0 7 228 103 36 1 1 5 0 1092 0 0 0 100 7 0 0 0 34 3 10 0 2 1 0 13 0 0 0 100 March 2, 2026 at 06:56:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2385 200 185 0 15 94 0 0 0 1 0 99 1 0 0 245 89 5 131 0 20 86 0 268 0 1 0 99 2 0 0 0 91 3 102 0 17 73 0 600 0 0 0 100 3 0 0 0 129 58 175 0 21 80 0 294 0 0 0 100 4 0 0 0 167 42 168 0 17 75 0 9 0 0 0 100 5 0 0 7 82 5 77 0 10 55 0 265 0 0 0 100 6 0 0 4 331 118 168 1 17 80 0 1078 0 0 0 99 7 0 0 0 74 0 66 0 11 54 0 0 0 0 0 100 March 2, 2026 at 06:56:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2340 200 112 0 0 0 0 0 0 1 0 99 1 0 0 245 18 4 16 0 2 1 0 266 0 0 0 100 2 0 0 0 45 2 6 0 1 0 0 600 0 0 0 100 3 0 0 0 47 1 14 0 1 0 0 294 0 0 0 100 4 0 0 0 55 8 14 1 0 0 0 9 0 0 0 100 5 0 0 7 49 4 12 0 0 0 0 261 0 0 0 100 6 0 0 4 344 152 132 1 0 0 0 1077 0 0 0 100 7 0 0 0 39 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2304 200 72 0 1 0 0 0 0 1 0 99 1 0 0 14 60 5 54 0 1 0 0 268 0 0 0 100 2 0 0 0 12 2 4 0 0 0 0 599 0 0 0 100 3 0 0 0 12 2 4 0 0 0 0 295 0 0 0 100 4 0 0 0 25 8 18 0 0 0 0 13 0 0 0 100 5 1 0 7 31 10 24 0 0 0 0 275 0 0 0 100 6 0 0 4 319 153 138 1 0 0 0 1084 0 0 0 100 7 0 0 0 11 0 5 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10672 0 296 2853 205 1019 33 199 240 55 5756 8 7 0 85 1 10308 0 56 763 13 1126 38 199 164 48 4429 8 4 0 88 2 1837 0 9 550 10 925 25 190 95 72 4230 4 2 0 93 3 2752 0 317 553 4 1036 40 200 115 62 4132 4 3 0 93 4 1718 0 114 487 4 888 21 177 125 67 3723 4 2 0 94 5 1074 0 32 511 33 819 19 155 80 39 3407 3 3 0 95 6 34286 0 36 727 107 935 32 159 77 50 5596 12 10 0 78 7 1093 0 10 462 4 761 16 127 97 46 2469 4 2 0 94 March 2, 2026 at 06:56:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 73 2314 204 122 0 0 6 0 7 0 1 0 98 1 2 0 14 28 5 16 0 2 6 0 268 0 0 0 99 2 0 0 0 22 2 6 0 0 0 0 599 0 0 0 100 3 0 0 0 26 1 16 0 2 0 0 294 0 0 0 100 4 0 0 7 23 3 4 0 1 0 0 0 0 0 0 100 5 0 0 7 126 54 112 0 0 0 0 264 0 0 0 100 6 0 0 4 223 102 32 1 0 1 0 1084 0 0 0 100 7 0 0 0 20 1 2 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:56:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2434 208 122 0 18 72 0 9 0 2 0 98 1 0 0 476 175 5 225 0 14 81 0 266 0 1 0 99 2 0 0 0 128 2 88 0 11 51 0 600 0 0 0 100 3 0 0 0 172 58 190 0 14 66 0 294 0 0 0 100 4 0 0 0 152 16 118 0 18 61 0 0 0 0 0 100 5 0 0 7 182 37 131 0 14 62 0 260 0 0 0 100 6 0 0 4 322 102 114 1 16 71 0 1084 0 0 0 99 7 0 0 0 114 1 76 0 11 50 0 1 0 0 0 100 March 2, 2026 at 06:56:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 206 80 0 1 0 0 9 0 0 0 100 1 0 0 14 59 5 54 0 0 0 0 268 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 600 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 294 0 0 0 100 4 0 0 0 113 52 114 0 1 0 0 0 0 0 0 100 5 0 0 7 15 3 12 0 0 0 0 260 0 0 0 100 6 0 0 4 210 102 32 1 0 0 0 1085 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 36774 0 118 2853 206 1015 40 177 142 56 4877 12 12 0 76 1 4368 0 143 607 7 1060 33 199 147 56 4648 6 4 0 90 2 8107 0 197 512 4 856 21 140 138 52 5292 6 5 0 89 3 6821 0 199 603 5 1013 33 170 155 74 5390 6 4 0 91 4 3908 0 26 607 30 894 13 148 121 72 3775 6 3 0 91 5 1651 0 30 475 12 833 19 142 106 68 2948 2 2 0 96 6 1154 0 128 711 121 966 29 152 79 53 4168 3 2 0 95 7 579 0 13 478 0 869 25 108 90 52 2444 3 2 0 94 March 2, 2026 at 06:56:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 87 2308 201 82 0 2 8 0 9 0 1 0 99 1 44 0 14 70 7 58 0 4 6 0 289 0 0 0 99 2 13 0 0 35 6 20 0 1 0 0 620 0 0 0 100 3 9 0 0 27 2 9 1 3 0 0 310 0 0 0 100 4 20 0 0 23 2 2 0 1 0 0 9 0 0 0 100 5 0 0 7 36 5 20 0 2 0 0 262 0 0 0 100 6 0 0 11 325 152 136 0 1 0 0 1098 0 0 0 100 7 0 0 0 24 1 4 0 0 0 0 15 0 0 0 100 March 2, 2026 at 06:56:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 42 2354 200 103 0 1 4 0 0 0 1 0 99 1 0 0 364 42 10 34 0 1 4 0 276 0 1 0 99 2 0 0 0 73 5 10 0 1 1 0 601 0 0 0 100 3 0 0 0 65 2 2 0 0 1 0 294 0 0 0 100 4 0 0 0 64 2 0 0 0 1 0 0 0 0 0 100 5 0 0 7 74 4 12 0 0 1 0 263 0 0 0 100 6 0 0 7 373 152 144 1 3 1 0 1088 0 0 0 100 7 0 0 0 65 1 4 0 2 1 0 0 0 0 0 100 March 2, 2026 at 06:56:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2343 200 166 0 14 58 0 0 0 1 0 99 1 0 0 14 89 10 106 0 14 80 0 277 0 0 0 100 2 0 0 0 63 5 79 0 13 57 0 600 0 0 0 100 3 0 0 0 115 57 190 0 17 74 0 294 0 0 0 100 4 0 0 0 71 1 95 0 19 65 0 0 0 0 0 100 5 0 0 7 72 4 96 0 15 83 0 261 0 0 0 100 6 0 0 4 267 102 114 1 13 79 0 1087 0 0 0 99 7 0 0 0 160 50 177 0 16 53 0 0 0 0 0 100 March 2, 2026 at 06:56:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 539 0 40 2518 200 429 6 66 28 34 1201 1 2 0 97 1 252 0 41 233 10 350 9 73 34 34 1565 1 1 0 98 2 2446 0 8 186 4 281 8 64 53 18 1593 1 1 0 97 3 290 0 5 164 1 238 3 56 27 15 2911 1 1 0 98 4 2323 0 3 153 1 248 5 68 55 20 1660 1 1 0 98 5 5600 0 144 217 4 286 6 48 42 36 1430 4 2 0 94 6 1074 0 20 363 103 312 8 58 54 37 2809 2 2 0 96 7 922 0 188 252 50 345 3 48 48 23 1236 1 1 0 98 March 2, 2026 at 06:56:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1372 0 184 2747 201 897 31 158 82 42 2502 3 3 0 94 1 1074 0 91 484 5 843 39 152 78 39 3065 3 3 0 94 2 33754 0 8 402 5 652 23 130 59 29 2553 10 8 0 81 3 866 0 4 407 11 707 34 118 63 24 3824 3 2 0 94 4 6201 0 182 452 38 788 27 121 138 39 3425 5 3 0 92 5 5184 0 31 442 16 613 21 90 89 34 3250 6 2 0 92 6 1177 0 18 637 108 839 42 145 70 44 3557 4 3 0 93 7 645 0 8 326 2 565 17 103 51 23 2014 4 1 0 95 March 2, 2026 at 06:56:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2377 200 108 0 0 0 0 0 0 1 0 99 1 2 0 63 86 4 24 0 3 2 0 268 0 1 0 99 2 0 0 462 26 1 14 0 0 2 0 0 0 1 0 99 3 0 0 0 82 1 4 0 1 0 0 300 0 0 0 100 4 0 0 0 185 53 104 0 0 0 0 595 0 0 0 100 5 0 0 7 88 3 10 0 1 0 0 263 0 0 0 100 6 0 0 4 285 103 34 1 0 0 0 1082 0 0 0 100 7 40 0 0 90 6 12 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:56:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 100 0 0 0 0 0 0 0 0 100 1 0 0 14 15 5 12 0 0 0 0 268 0 0 0 100 2 0 0 0 18 1 14 0 1 0 0 0 0 0 0 100 3 0 0 0 11 2 8 0 0 0 0 309 0 0 0 100 4 0 0 0 112 53 108 0 0 0 0 612 0 0 0 100 5 0 0 7 15 3 12 0 0 0 0 260 0 0 0 100 6 0 0 4 209 102 1 0 0 1 0 259 0 0 0 100 7 0 0 0 19 7 14 0 0 0 0 11 0 0 0 100 March 2, 2026 at 06:56:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2350 200 185 0 13 81 0 0 0 1 0 99 1 0 0 14 62 4 96 1 19 66 0 266 0 0 0 100 2 0 0 0 64 1 104 0 12 69 0 0 0 0 0 100 3 0 0 0 113 59 212 0 18 78 0 300 0 0 0 100 4 0 0 0 165 53 213 1 17 93 0 566 0 0 0 100 5 0 0 7 65 3 122 0 10 90 0 260 0 0 0 100 6 0 0 4 256 102 126 1 19 80 0 859 0 0 0 100 7 0 0 0 49 7 72 0 9 54 0 10 0 0 0 100 March 2, 2026 at 06:56:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2142 0 244 2817 211 1006 17 176 89 67 4143 4 4 0 93 1 814 0 31 495 5 846 29 176 90 51 4680 3 2 0 95 2 870 0 14 458 2 738 29 149 71 38 2573 2 2 0 96 3 1683 0 6 525 2 916 21 165 74 56 4099 6 2 0 92 4 8776 0 249 498 23 887 29 162 145 44 4346 6 5 0 89 5 8656 0 233 567 19 877 28 138 160 67 3469 6 5 0 89 6 5791 0 23 725 107 862 22 147 143 70 4689 7 3 0 90 7 34659 0 10 492 6 845 22 130 77 80 4582 12 9 0 79 March 2, 2026 at 06:56:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 17 2321 203 89 0 3 1 0 14 0 0 0 99 1 5 0 84 23 5 19 0 4 6 0 275 0 1 0 99 2 0 0 0 40 2 24 0 2 5 0 16 0 0 0 100 3 1 0 7 24 1 8 0 3 1 0 312 0 0 0 100 4 48 0 0 33 6 19 0 3 1 0 345 0 0 0 100 5 2 0 7 138 46 123 1 2 0 0 302 0 0 0 100 6 6 0 4 260 119 72 0 1 0 0 1404 0 0 0 100 7 0 0 0 27 1 15 0 2 0 0 21 0 0 0 100 March 2, 2026 at 06:56:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2376 200 100 0 0 0 0 0 0 1 0 99 1 0 0 56 88 5 18 0 0 2 0 268 0 1 0 99 2 0 0 462 17 1 8 0 1 2 0 0 0 1 0 99 3 0 0 0 83 1 6 0 0 0 0 300 0 0 0 100 4 0 0 0 98 8 26 0 2 0 0 309 0 0 0 100 5 0 0 7 87 3 12 0 1 0 0 263 0 0 0 100 6 0 0 4 384 153 134 1 0 1 0 1375 0 0 0 100 7 0 0 0 77 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 104 0 1 1 0 0 0 0 0 100 1 0 0 14 18 4 10 1 0 1 0 266 0 0 0 100 2 0 0 0 13 3 6 0 1 1 0 0 0 0 0 100 3 0 0 0 9 2 4 0 1 0 0 300 0 0 0 100 4 0 0 0 24 9 16 0 0 1 0 309 0 0 0 100 5 0 0 7 22 4 22 0 1 1 0 260 0 0 0 100 6 0 0 4 313 153 134 2 0 1 0 1375 0 0 0 100 7 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:56:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 664 0 72 2624 200 605 6 104 118 38 1618 1 2 0 97 1 353 0 20 297 5 467 7 100 145 34 1799 1 1 0 98 2 1263 0 122 305 4 531 8 86 135 44 2843 2 2 0 96 3 502 0 11 363 81 591 4 91 122 33 1962 1 1 0 98 4 1023 0 129 315 10 535 10 102 137 34 1707 1 2 0 97 5 2752 0 21 291 6 497 6 90 198 46 3734 2 2 0 96 6 28750 0 215 583 146 657 11 110 179 52 4355 9 6 0 85 7 4717 0 23 317 1 439 5 74 162 40 1464 3 2 0 96 March 2, 2026 at 06:56:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 653 0 49 2606 201 584 19 83 48 12 2113 2 2 0 96 1 1795 0 191 394 42 699 33 98 54 12 2619 4 2 0 94 2 3285 0 12 395 3 572 19 97 88 24 2114 5 2 0 92 3 370 0 0 344 6 614 25 103 58 14 2400 4 1 0 94 4 489 0 1 363 5 652 30 105 47 18 1924 2 1 0 97 5 842 0 15 270 5 493 19 78 72 9 1825 2 2 0 97 6 12729 0 86 444 104 431 12 73 84 3 1987 5 6 0 89 7 3782 0 2 233 7 427 18 62 98 10 2808 2 2 0 96 March 2, 2026 at 06:56:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2380 201 110 1 1 0 0 9 0 1 0 99 1 2 0 14 186 54 112 0 1 0 0 273 0 0 0 100 2 0 0 462 24 1 14 0 0 2 0 0 0 1 0 99 3 40 0 0 92 7 16 0 1 0 0 311 0 0 0 100 4 0 0 0 83 3 6 0 0 0 0 303 0 0 0 100 5 0 0 7 103 11 20 0 0 0 0 269 0 0 0 100 6 0 0 46 280 102 8 0 2 2 0 1 0 1 0 99 7 0 0 0 91 2 51 1 1 2 0 1389 0 0 0 100 March 2, 2026 at 06:56:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 102 0 0 0 0 21 0 0 0 100 1 0 0 14 109 53 106 1 0 0 0 266 0 0 0 100 2 0 0 0 17 1 12 0 0 0 0 0 0 0 0 100 3 0 0 0 20 7 14 0 0 0 0 309 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 300 0 0 0 100 5 1 0 7 15 3 12 0 1 0 0 260 0 0 0 100 6 0 0 4 209 102 2 0 0 0 0 1 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 1382 0 0 0 100 March 2, 2026 at 06:57:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 112 0 1 0 0 0 0 0 0 100 1 0 0 14 111 54 109 0 1 0 0 268 0 0 0 100 2 0 0 0 17 1 12 0 0 0 0 0 0 0 0 100 3 0 0 0 19 7 14 0 0 0 0 309 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 300 0 0 0 100 5 0 0 7 15 3 10 0 0 0 0 260 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 14 3 38 1 1 1 0 1382 0 0 0 100 March 2, 2026 at 06:57:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1609 0 76 3013 206 1368 43 254 227 84 4409 4 4 0 92 1 3455 0 272 743 17 1291 55 256 183 56 3808 7 4 0 89 2 1488 0 28 613 2 1054 41 194 195 65 6036 4 3 0 93 3 948 0 26 696 61 1243 41 232 146 50 3957 3 3 0 93 4 6028 0 26 712 19 1090 35 205 240 56 3973 9 4 0 87 5 3689 0 18 566 6 964 30 181 217 49 5099 8 4 0 89 6 9219 0 200 895 124 1067 31 182 245 47 4283 5 4 0 90 7 37052 0 200 550 4 1076 27 170 190 79 4952 12 10 0 78 March 2, 2026 at 06:57:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2320 200 106 0 0 0 0 22 0 0 0 100 1 3 0 70 54 18 48 0 2 8 0 15 0 1 0 99 2 7 0 14 36 4 22 3 0 7 0 366 1 0 0 99 3 22 0 0 24 1 6 0 1 0 0 309 0 0 0 100 4 6 0 0 27 3 8 0 1 0 0 317 0 0 0 100 5 53 0 7 43 8 33 0 3 0 0 293 0 0 0 100 6 0 0 4 294 135 76 0 2 0 0 6 0 0 0 100 7 9 0 7 31 3 44 0 3 0 0 1403 0 0 0 100 March 2, 2026 at 06:57:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2402 218 154 1 3 0 0 18 0 1 0 99 1 0 0 42 103 13 32 0 1 2 0 7 0 1 0 99 2 0 0 476 42 9 42 0 2 2 0 276 0 1 0 99 3 0 0 0 129 23 52 0 2 0 0 305 0 0 0 100 4 0 0 0 82 3 4 0 0 0 0 300 0 0 0 100 5 0 0 7 95 11 8 0 0 0 0 260 0 0 0 100 6 0 0 4 279 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 89 2 43 1 0 1 0 1372 0 0 0 100 March 2, 2026 at 06:57:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2353 250 202 0 1 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 2 0 0 14 33 10 30 0 0 0 0 275 0 0 0 100 3 0 0 0 15 1 16 0 1 0 0 300 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 300 0 0 0 100 5 0 0 7 11 2 6 0 0 0 0 260 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 12 2 36 1 0 1 0 1372 0 0 0 100 March 2, 2026 at 06:57:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1186 0 65 2725 238 799 12 128 85 60 2753 3 3 0 94 1 1972 0 29 444 5 615 18 126 68 54 2014 2 2 0 96 2 598 0 26 399 14 586 11 113 45 50 2041 1 1 0 97 3 1645 0 15 367 4 628 8 126 56 49 2168 3 2 0 96 4 1993 0 206 321 12 515 8 98 55 48 2790 3 3 0 94 5 3782 0 135 371 5 638 20 93 110 61 5287 3 3 0 94 6 7411 0 130 554 102 707 10 132 131 74 3659 3 3 0 94 7 41286 0 212 404 4 623 15 104 140 68 4562 12 10 0 78 March 2, 2026 at 06:57:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 652 0 31 2473 201 424 13 49 120 3 899 3 1 0 96 1 362 0 7 181 4 320 8 45 108 1 467 4 1 0 96 2 309 0 14 128 5 217 14 33 95 0 1065 1 1 0 98 3 439 0 0 234 61 439 6 50 73 1 1505 1 1 0 98 4 387 0 70 212 4 401 7 54 120 2 788 1 2 0 97 5 375 0 7 217 18 366 9 36 90 4 901 1 1 0 98 6 411 0 4 384 104 328 6 51 73 1 1335 1 1 0 98 7 881 0 0 197 38 304 2 28 73 0 1802 1 1 0 98 March 2, 2026 at 06:57:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2380 201 77 0 3 0 0 287 0 1 0 99 1 0 0 0 82 1 5 0 1 0 0 12 0 0 0 100 2 0 0 476 57 4 45 0 2 2 0 266 0 1 0 99 3 0 0 0 81 1 4 0 0 0 0 300 0 0 0 100 4 0 0 42 91 8 18 0 1 2 0 9 0 1 0 99 5 0 0 7 193 53 122 0 1 0 0 264 0 0 0 100 6 0 0 4 281 102 2 0 0 0 0 300 0 0 0 100 7 0 0 0 82 1 34 1 1 0 0 1081 0 0 0 100 March 2, 2026 at 06:57:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 202 122 1 0 0 0 13 0 0 0 100 1 1 0 0 13 3 10 0 0 0 0 303 0 0 0 100 2 0 0 14 11 4 8 0 0 0 0 266 0 0 0 100 3 0 0 0 15 2 10 0 0 0 0 306 0 0 0 100 4 0 0 0 20 8 14 0 0 0 0 9 0 0 0 100 5 0 0 7 116 57 108 0 1 0 0 260 0 0 0 100 6 0 0 4 211 103 4 0 0 0 0 301 0 0 0 100 7 0 0 0 13 1 39 1 0 0 0 1080 0 0 0 100 March 2, 2026 at 06:57:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2305 201 110 0 0 0 0 1 0 0 0 100 1 0 0 0 11 2 6 0 0 0 0 294 0 0 0 100 2 0 0 14 11 4 8 1 0 0 0 266 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 4 0 0 0 20 8 14 0 0 0 0 9 0 0 0 100 5 0 0 7 113 52 110 0 1 0 0 260 0 0 0 100 6 0 0 3 217 103 16 0 1 0 0 301 0 0 0 100 7 0 0 0 10 1 34 1 0 1 0 1082 0 0 0 100 March 2, 2026 at 06:57:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9769 0 128 2964 202 1003 36 185 176 65 3706 6 4 0 89 1 1669 0 43 632 4 1156 38 202 155 81 4232 5 4 0 91 2 872 0 52 512 7 900 25 175 101 57 3700 3 2 0 94 3 1541 0 121 564 5 1034 29 178 79 64 4219 4 3 0 94 4 35208 0 124 543 6 934 29 151 67 55 4778 13 9 0 78 5 786 0 15 508 19 867 27 159 107 45 3358 4 2 0 94 6 2421 0 12 765 105 977 16 162 108 45 5131 6 3 0 91 7 11326 0 374 536 30 973 20 138 178 61 5148 5 6 0 90 March 2, 2026 at 06:57:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 4 2372 206 185 0 11 46 0 9 0 1 0 99 1 0 0 0 71 2 105 0 15 79 0 295 0 0 0 100 2 2 0 84 43 4 66 0 9 69 0 266 0 1 0 99 3 0 0 7 122 56 204 0 21 72 0 300 0 1 0 99 4 0 0 0 60 2 80 0 15 67 0 0 0 0 0 100 5 0 0 7 61 2 77 0 12 69 0 263 0 0 0 100 6 0 0 2 273 104 106 0 19 65 0 300 0 0 0 100 7 0 0 0 161 51 207 0 16 76 0 1093 0 0 0 100 March 2, 2026 at 06:57:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2391 206 100 0 3 0 0 9 0 1 0 99 1 0 0 0 109 2 30 0 2 0 0 296 0 0 0 100 2 0 0 56 80 4 10 0 0 2 0 266 0 1 0 99 3 0 0 462 18 1 8 0 0 2 0 300 0 1 0 99 4 0 0 0 170 46 96 0 3 0 0 0 0 0 0 100 5 0 0 7 83 2 6 0 0 0 0 260 0 0 0 100 6 0 0 4 283 103 4 0 0 0 0 300 0 0 0 100 7 0 0 0 102 7 52 1 0 1 0 1080 0 0 0 100 March 2, 2026 at 06:57:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2324 208 132 2 0 0 0 22 0 0 0 99 1 0 0 0 15 1 18 0 1 0 0 301 0 0 0 100 2 0 0 14 11 4 8 1 0 0 0 266 0 0 0 100 3 0 0 0 13 1 8 0 0 0 0 305 0 0 0 100 4 0 0 0 108 52 102 0 0 0 0 0 0 0 0 100 5 0 0 7 17 8 8 0 0 1 0 260 0 0 0 100 6 0 0 4 211 103 4 0 0 0 0 300 0 0 0 100 7 0 0 0 20 1 47 1 0 0 0 1082 0 0 0 100 March 2, 2026 at 06:57:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 38270 0 88 2901 206 1007 33 174 122 48 5060 14 11 0 75 1 7890 0 43 682 3 1111 38 199 167 67 5298 6 5 0 89 2 4573 0 380 517 6 922 21 136 152 67 3732 4 3 0 93 3 3781 0 14 595 7 1039 43 175 148 59 4839 5 3 0 92 4 1983 0 127 508 34 856 16 162 94 39 2778 5 2 0 93 5 2883 0 126 464 5 784 16 119 78 50 3655 4 2 0 93 6 684 0 28 738 109 966 20 136 84 55 4324 4 2 0 94 7 3555 0 11 416 2 741 18 119 136 58 4207 4 3 0 93 March 2, 2026 at 06:57:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 49 0 24 2324 204 91 0 5 3 0 22 0 0 0 99 1 0 0 70 18 2 10 0 3 7 0 313 0 1 0 99 2 4 0 14 35 4 23 0 2 1 0 281 0 0 0 100 3 25 0 0 28 3 10 0 0 7 0 310 0 0 0 100 4 1 0 0 27 2 8 0 3 1 0 9 0 0 0 100 5 0 0 7 156 54 137 1 1 1 0 262 0 0 0 100 6 0 0 4 228 103 10 0 1 1 0 316 0 0 0 100 7 13 0 0 37 4 48 0 1 0 0 1104 0 0 0 100 March 2, 2026 at 06:57:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2422 208 181 1 12 68 0 9 0 1 0 99 1 0 0 28 110 3 102 0 23 73 0 296 0 1 0 99 2 0 0 14 111 6 92 0 13 58 0 267 0 0 0 100 3 0 0 343 119 58 209 0 17 91 0 300 0 1 0 99 4 0 0 0 135 2 129 0 20 88 0 0 0 0 0 100 5 0 0 7 210 55 196 0 11 78 0 264 0 0 0 100 6 0 0 4 308 105 91 0 10 55 0 300 0 0 0 100 7 0 0 0 101 2 101 1 9 55 0 1081 0 0 0 100 March 2, 2026 at 06:57:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2333 207 72 0 2 0 0 10 0 0 0 99 1 0 0 0 26 1 4 0 0 0 0 294 0 0 0 100 2 0 0 14 27 3 6 1 0 0 0 266 0 0 0 100 3 0 0 119 14 2 8 0 0 1 0 300 0 0 0 100 4 0 0 0 70 1 44 0 0 0 0 0 0 0 0 100 5 0 0 7 132 54 113 0 1 0 0 261 0 0 0 100 6 0 0 3 228 103 4 0 0 0 0 300 0 0 0 100 7 0 0 0 33 1 40 1 0 2 0 1081 0 0 0 100 March 2, 2026 at 06:57:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 48 0 26 2425 210 276 3 33 16 17 321 0 1 0 99 1 466 0 27 84 2 112 1 25 20 22 1569 0 1 0 99 2 42 0 25 83 3 126 1 34 23 20 580 0 1 0 99 3 74 0 9 87 3 121 1 34 30 16 607 0 1 0 99 4 5271 0 119 75 1 153 4 27 80 26 1503 1 2 0 97 5 2727 0 25 179 43 227 0 34 47 15 940 1 2 0 97 6 77 0 10 327 120 168 1 31 17 24 672 0 0 0 100 7 35 0 0 110 1 185 1 22 15 15 1421 0 0 0 99 March 2, 2026 at 06:57:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1384 0 168 2757 204 904 20 150 136 41 3546 3 4 0 92 1 1630 0 260 466 3 802 28 160 88 34 2979 3 3 0 94 2 1327 0 24 428 5 706 31 137 77 33 3015 3 2 0 96 3 34251 0 193 520 3 781 37 142 61 27 3731 11 9 0 80 4 5735 0 131 516 19 784 17 127 99 39 3905 5 3 0 92 5 2730 0 16 478 4 822 24 120 66 32 2734 3 2 0 95 6 6349 0 18 739 128 795 28 118 97 27 4050 7 3 0 90 7 1431 0 3 382 9 633 16 94 57 43 4279 6 2 0 92 March 2, 2026 at 06:57:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2372 201 96 0 2 2 0 0 0 1 0 99 1 0 0 462 30 1 20 0 2 2 0 2 0 1 0 99 2 2 0 14 87 3 10 0 0 0 0 561 0 0 0 100 3 0 0 0 90 4 14 0 1 0 0 309 0 0 0 100 4 40 0 0 97 8 48 1 0 0 0 1115 0 0 0 99 5 0 0 7 85 3 10 0 0 0 0 263 0 0 0 100 6 0 0 4 385 153 104 0 0 0 0 300 0 0 0 100 7 0 0 0 85 0 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:57:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 203 188 0 13 82 0 1 0 1 0 99 1 0 0 0 55 2 89 0 14 70 0 1 0 0 0 100 2 0 0 14 55 3 97 1 10 53 0 559 0 0 0 100 3 0 0 0 104 58 189 0 14 51 0 300 0 0 0 100 4 0 0 0 64 8 129 2 15 69 0 1090 0 0 0 99 5 0 0 7 80 17 113 0 14 78 0 260 0 0 0 100 6 0 0 4 331 137 173 0 14 94 0 300 0 0 0 100 7 0 0 0 51 0 93 0 17 63 0 0 0 0 0 100 March 2, 2026 at 06:57:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 117 0 3 0 0 7 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 14 9 3 7 0 1 0 0 544 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 21 8 44 1 0 0 0 1091 0 0 0 100 5 0 0 7 118 53 112 0 0 0 0 260 0 0 0 100 6 0 0 3 214 103 8 0 1 0 0 300 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:57:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40585 0 276 2959 204 1214 43 222 121 73 5682 13 11 0 76 1 3461 0 16 665 2 1164 31 196 105 61 4436 4 4 0 92 2 1150 0 40 591 3 911 47 171 115 48 2960 4 2 0 94 3 2195 0 12 667 15 1102 35 181 80 52 5037 5 3 0 92 4 3878 0 39 616 9 977 33 166 117 53 4430 5 3 0 92 5 4811 0 140 497 29 829 19 135 135 62 3341 5 4 0 92 6 2303 0 32 751 110 977 31 158 123 66 4211 7 3 0 90 7 4866 0 308 478 12 844 25 120 137 37 4890 5 4 0 92 March 2, 2026 at 06:57:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 17 2322 203 41 0 5 0 0 311 0 0 0 99 1 3 0 0 154 19 136 0 3 0 0 11 0 0 0 100 2 3 0 84 16 2 14 0 2 6 0 285 0 1 0 99 3 0 0 0 28 3 13 0 3 7 0 310 0 0 0 100 4 0 0 7 27 3 38 1 2 1 0 1109 0 0 0 100 5 10 0 7 32 3 14 0 2 0 0 282 0 0 0 100 6 0 0 4 228 103 7 2 1 0 0 301 0 0 0 100 7 62 0 0 100 37 82 0 1 2 0 21 0 0 0 100 March 2, 2026 at 06:57:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2395 217 139 0 3 1 0 294 0 1 0 99 1 0 0 0 161 35 76 0 2 1 0 0 0 0 0 100 2 0 0 56 87 4 22 1 2 3 0 266 0 1 0 99 3 0 0 462 21 4 8 0 0 3 0 300 0 1 0 99 4 0 0 0 85 3 34 0 1 1 0 1080 0 0 0 100 5 1 0 7 86 3 8 0 1 1 0 263 0 0 0 100 6 0 0 7 286 104 8 0 1 0 0 301 0 0 0 100 7 0 0 0 93 7 12 0 0 1 0 9 0 0 0 100 March 2, 2026 at 06:57:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2398 251 287 0 14 88 0 294 0 1 0 99 1 0 0 0 56 2 92 0 21 85 0 3 0 0 0 100 2 0 0 14 46 3 77 0 12 70 0 266 0 0 0 100 3 0 0 0 109 60 202 0 16 84 0 300 0 0 0 100 4 0 0 0 63 3 299 1 20 64 0 1413 0 1 0 99 5 0 0 7 52 4 85 0 9 86 0 261 0 0 0 100 6 0 0 4 248 103 79 0 10 81 0 300 0 0 0 100 7 0 0 0 47 6 75 0 12 42 0 9 0 0 0 100 March 2, 2026 at 06:57:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8029 0 188 2577 212 612 15 108 138 58 3760 3 5 0 93 1 2686 0 16 297 0 515 10 123 91 64 1735 1 2 0 97 2 650 0 23 273 6 444 6 91 54 51 3105 2 1 0 97 3 855 0 116 260 6 479 6 103 42 41 2204 1 1 0 98 4 915 0 186 262 4 485 8 95 46 62 3372 1 2 0 97 5 16970 0 17 272 4 410 3 68 43 52 1509 5 4 0 92 6 2547 0 40 566 138 403 8 76 64 25 1619 3 2 0 95 7 783 0 11 242 12 352 8 53 79 34 1608 2 1 0 97 March 2, 2026 at 06:57:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3115 0 43 2608 203 620 17 77 65 12 2234 2 2 0 95 1 5823 0 14 362 2 472 20 71 115 13 2000 5 2 0 93 2 463 0 14 344 51 516 9 63 54 14 1561 2 1 0 97 3 543 0 0 290 5 526 28 76 66 16 2113 2 2 0 96 4 730 0 1 209 3 398 7 57 47 16 2315 2 1 0 97 5 17037 0 14 241 13 400 8 50 36 7 1875 6 6 0 89 6 1913 0 251 394 106 424 7 53 58 18 2092 4 3 0 94 7 486 0 0 245 2 441 10 56 66 15 1379 3 1 0 96 March 2, 2026 at 06:57:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2375 200 106 0 1 0 0 0 0 1 0 99 1 0 0 0 90 1 10 0 1 0 0 294 0 0 0 100 2 2 0 14 166 44 89 1 1 0 0 266 0 0 0 100 3 0 0 462 37 12 28 0 1 2 0 300 0 1 0 99 4 0 0 0 87 5 38 1 0 0 0 1083 0 0 0 100 5 40 0 7 95 7 18 0 1 0 0 271 0 0 0 100 6 0 0 46 281 104 8 0 1 2 0 301 0 1 0 99 7 0 0 0 78 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:57:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 108 0 0 0 0 0 0 0 0 100 1 0 0 0 11 2 6 0 1 0 0 296 0 0 0 100 2 0 0 14 10 2 6 0 1 0 0 266 0 0 0 100 3 0 0 0 113 54 108 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 1082 0 0 0 100 5 0 0 7 25 8 22 0 1 0 0 269 0 0 0 100 6 0 0 4 217 103 16 0 1 0 0 300 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:57:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2348 200 187 0 18 77 0 0 0 1 0 99 1 0 0 0 64 3 108 0 19 94 0 295 0 0 0 100 2 0 0 14 45 2 66 0 12 47 0 266 0 0 0 100 3 0 0 0 210 111 298 0 16 65 0 300 0 0 0 100 4 0 0 0 49 2 114 1 12 61 0 1081 0 0 0 100 5 0 0 7 66 8 105 0 7 54 0 269 0 0 0 100 6 0 0 4 256 103 96 0 18 95 0 300 0 0 0 100 7 0 0 0 40 0 70 0 16 55 0 0 0 0 0 100 March 2, 2026 at 06:57:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2990 0 265 2807 201 1010 39 177 123 59 5756 5 5 0 90 1 11086 0 358 567 3 1015 30 199 167 67 4583 7 6 0 87 2 6462 0 29 496 2 838 15 161 131 73 4686 5 3 0 92 3 1194 0 13 605 22 1055 32 196 115 66 3869 3 2 0 95 4 2845 0 12 549 3 799 21 145 95 59 4358 5 2 0 93 5 2779 0 34 452 8 712 11 118 84 44 2631 4 2 0 94 6 34870 0 134 681 105 875 25 166 71 45 4320 12 8 0 80 7 1177 0 14 452 32 733 18 124 68 45 2448 3 2 0 95 March 2, 2026 at 06:57:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 87 2314 202 31 2 5 6 0 35 0 2 0 98 1 40 0 0 136 4 131 0 7 6 0 301 0 0 0 99 2 4 0 21 34 1 21 1 3 3 0 301 0 0 0 100 3 0 0 0 26 3 10 0 0 0 0 310 0 0 0 100 4 0 0 0 34 5 46 1 1 0 0 1113 0 0 0 100 5 22 0 7 39 10 18 0 0 1 0 281 0 0 0 100 6 1 0 4 229 102 12 0 1 0 0 312 0 0 0 100 7 9 0 0 127 51 113 0 1 1 0 9 0 0 0 100 March 2, 2026 at 06:57:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 46 2370 201 102 0 2 2 0 0 0 1 0 99 1 0 0 462 30 7 22 0 0 2 0 11 0 1 0 99 2 0 0 14 100 2 30 0 1 0 0 560 0 0 0 100 3 0 0 0 84 3 8 0 1 0 0 300 0 0 0 100 4 0 0 0 88 3 38 1 1 2 0 1080 0 0 0 100 5 0 0 7 83 2 8 0 0 0 0 260 0 0 0 100 6 0 0 3 281 102 2 0 0 0 0 300 0 0 0 100 7 0 0 0 179 51 102 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:57:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 201 104 0 0 1 0 0 0 0 0 100 1 0 0 0 19 7 12 0 0 1 0 9 0 0 0 100 2 0 0 14 19 3 12 0 1 1 0 561 0 0 0 100 3 0 0 0 13 4 6 0 0 1 0 300 0 0 0 100 4 0 0 0 12 4 34 0 0 1 0 1082 0 0 0 100 5 0 0 7 12 3 6 0 0 1 0 260 0 0 0 100 6 0 0 3 209 102 2 0 0 1 0 300 0 0 0 100 7 0 0 0 111 52 106 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:57:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5331 0 100 2960 202 1114 35 216 159 60 3389 5 4 0 91 1 11524 0 300 591 10 1082 53 232 296 71 4739 5 4 0 90 2 24467 0 34 570 4 968 38 205 427 54 5313 10 6 0 84 3 853 0 5 627 71 1105 47 229 164 60 3467 3 2 0 95 4 30802 0 28 570 5 1054 35 219 441 59 6332 11 11 0 78 5 5234 0 33 541 4 818 34 175 168 53 2861 4 2 0 94 6 2415 0 14 790 107 899 29 195 140 44 2554 4 2 0 94 7 4667 0 374 475 35 862 28 143 148 59 3373 4 4 0 93 March 2, 2026 at 06:57:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 106 0 101 2355 205 124 5 23 11 2 415 2 2 0 96 1 866 0 0 200 30 223 3 21 25 0 634 1 1 0 98 2 107 0 14 57 5 51 2 9 3 0 929 1 0 0 98 3 753 0 0 108 22 142 10 25 37 4 246 1 0 0 99 4 557 0 0 78 4 141 11 28 30 3 1696 1 1 0 98 5 381 0 14 76 4 102 4 16 18 0 684 2 0 0 97 6 772 0 4 239 101 37 1 8 23 1 452 1 0 0 99 7 568 0 0 72 3 117 11 20 21 3 614 1 0 0 99 March 2, 2026 at 06:57:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2313 203 108 1 3 3 0 4 0 1 0 99 1 0 0 14 27 1 18 0 1 4 0 7 0 0 0 100 2 0 0 14 39 9 34 0 0 0 0 577 0 0 0 100 3 0 0 0 115 53 106 0 0 0 0 1 0 0 0 100 4 0 0 0 17 4 36 1 0 0 0 1377 0 0 0 100 5 0 0 7 27 9 12 0 0 0 0 286 0 0 0 100 6 0 0 4 216 102 4 0 1 0 0 1 0 0 0 100 7 1 0 0 18 2 14 0 2 0 0 309 0 0 0 100 March 2, 2026 at 06:57:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 31 2370 202 108 0 0 1 0 21 0 1 0 99 1 0 0 448 13 0 8 0 1 2 0 0 0 1 0 99 2 0 0 14 98 8 26 1 0 0 0 569 0 0 0 100 3 0 0 0 177 52 104 0 0 0 0 0 0 0 0 100 4 0 0 0 83 4 40 1 2 0 0 1378 0 0 0 100 5 0 0 7 84 2 18 0 1 0 0 260 0 0 0 100 6 0 0 4 277 102 2 0 0 0 0 1 0 0 0 100 7 0 0 0 78 2 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 104 0 0 0 0 0 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 14 27 7 24 0 0 0 0 569 0 0 0 100 3 0 0 0 109 52 104 0 0 0 0 0 0 0 0 100 4 0 0 0 12 4 36 0 0 0 0 1379 0 0 0 100 5 0 0 7 13 2 10 0 1 1 0 260 0 0 0 100 6 0 0 4 212 101 12 0 1 0 0 0 0 0 0 100 7 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 42614 0 102 3077 203 1415 71 271 274 68 6903 17 12 0 71 1 7070 0 201 838 12 1404 57 282 295 60 5179 8 4 0 88 2 2008 0 22 801 18 1402 28 234 247 78 4644 4 3 0 93 3 2316 0 207 807 67 1441 52 283 224 67 5932 7 4 0 88 4 723 0 10 676 5 1200 43 225 206 71 5023 6 3 0 91 5 4523 0 251 564 3 1087 26 195 265 71 3754 4 6 0 89 6 1680 0 30 856 118 1156 32 235 190 52 4772 6 3 0 91 7 3308 0 9 585 6 1043 24 178 225 44 3842 4 3 0 93 March 2, 2026 at 06:57:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2315 202 109 1 5 5 0 26 0 2 0 98 1 21 0 0 42 1 30 0 6 6 0 14 0 1 0 99 2 26 0 14 31 2 16 1 0 0 0 570 0 0 0 100 3 24 0 0 29 4 15 0 2 1 0 12 0 0 0 100 4 41 0 0 39 8 52 1 2 0 0 1424 0 0 0 99 5 1 0 7 29 2 14 0 1 0 0 272 0 0 0 100 6 0 0 4 326 151 108 0 2 0 0 27 0 0 0 100 7 5 0 7 24 2 9 1 3 0 0 313 0 0 0 100 March 2, 2026 at 06:57:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2375 202 120 1 2 2 0 8 0 1 0 99 1 0 0 462 25 0 24 0 1 3 0 5 0 1 0 99 2 0 0 14 94 2 22 1 1 0 0 567 0 0 0 100 3 0 0 0 86 3 8 0 0 0 0 0 0 0 0 100 4 0 0 0 94 8 44 1 0 0 0 1396 0 0 0 99 5 0 0 7 90 7 6 0 0 0 0 260 0 0 0 100 6 0 0 4 379 151 100 0 0 0 0 0 0 0 0 100 7 0 0 0 90 3 17 0 1 0 0 307 0 0 0 100 March 2, 2026 at 06:57:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 106 0 0 0 0 0 0 0 0 100 1 0 0 0 7 1 4 0 1 0 0 2 0 0 0 100 2 0 0 14 18 2 14 1 0 0 0 560 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 22 9 46 0 0 0 0 1396 0 0 0 100 5 0 0 7 11 2 6 0 0 0 0 260 0 0 0 100 6 0 0 4 307 151 100 0 0 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35905 0 217 2892 203 1009 23 157 496 54 5775 15 12 0 73 1 33772 0 10 635 1 959 31 165 577 56 3806 12 7 0 82 2 5825 0 207 500 3 916 25 159 134 69 4886 6 3 0 91 3 6687 0 24 650 14 1034 21 178 130 66 4466 7 4 0 89 4 1840 0 191 558 12 1054 31 174 102 69 4380 4 3 0 93 5 1073 0 25 443 5 744 19 103 92 63 4176 3 2 0 94 6 1891 0 41 750 140 969 24 159 210 51 3460 4 3 0 93 7 3452 0 193 398 3 694 12 122 152 41 3027 3 3 0 94 March 2, 2026 at 06:57:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 17 2364 205 182 1 19 81 0 26 0 1 0 99 1 41 0 7 121 27 155 0 24 58 0 30 0 0 0 100 2 5 0 14 132 2 218 0 18 67 0 569 0 0 0 100 3 25 0 0 189 88 168 0 16 94 0 10 0 0 0 100 4 6 0 0 69 4 121 1 18 69 0 1127 1 0 0 98 5 13 0 7 76 6 104 0 16 80 0 568 0 0 0 100 6 0 0 74 276 101 110 0 19 78 0 18 0 1 0 99 7 52 0 0 68 1 96 0 12 92 0 327 0 1 0 99 March 2, 2026 at 06:57:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2342 203 108 0 0 0 0 0 0 1 0 99 1 0 0 0 155 56 116 0 1 0 0 9 0 0 0 100 2 0 0 14 53 2 16 0 1 0 0 561 0 0 0 100 3 0 0 0 47 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 45 2 32 1 0 0 0 1081 0 0 0 100 5 0 0 7 48 4 10 0 1 0 0 564 0 0 0 100 6 0 0 11 242 101 3 0 2 4 0 0 0 1 0 99 7 0 0 231 11 1 6 0 0 4 0 300 0 1 0 99 March 2, 2026 at 06:57:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2351 205 126 2 1 0 0 13 0 1 0 99 1 0 0 0 164 57 120 0 0 0 0 16 0 0 0 100 2 0 0 14 53 2 14 0 1 0 0 566 0 0 0 100 3 0 0 0 51 3 8 0 1 1 0 1 0 0 0 100 4 0 0 0 48 2 32 1 0 0 0 1081 0 0 0 100 5 2 0 7 60 8 20 0 2 0 0 561 0 0 0 100 6 0 0 39 244 102 4 0 0 2 0 1 0 1 0 99 7 0 0 231 18 1 13 0 1 2 0 300 0 1 0 99 March 2, 2026 at 06:57:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 114 0 0 0 0 0 0 0 0 100 1 0 0 0 119 56 114 0 0 0 0 6 0 0 0 100 2 0 0 14 10 3 6 1 0 0 0 561 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 1080 0 0 0 100 5 0 0 7 14 3 10 0 1 1 0 561 0 0 0 100 6 0 0 4 215 102 14 0 1 0 0 1 0 0 0 100 7 0 0 0 8 1 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1472 0 105 2878 203 1041 34 204 98 52 3298 5 3 0 92 1 2199 0 144 605 17 1033 30 186 113 43 4969 4 4 0 92 2 6528 0 143 493 10 828 23 149 163 36 6274 5 4 0 91 3 10020 0 202 631 5 1203 33 209 174 63 5704 8 5 0 87 4 4635 0 196 675 32 1116 23 172 119 60 4750 4 6 0 90 5 3034 0 27 442 4 779 34 159 111 48 3980 5 2 0 92 6 2158 0 23 778 103 947 23 167 83 62 3424 5 2 0 93 7 33756 0 18 453 2 786 24 145 90 56 3105 10 8 0 81 March 2, 2026 at 06:57:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2370 203 208 0 13 99 0 1 0 1 0 99 1 40 0 70 77 6 115 0 16 73 0 9 0 1 0 99 2 3 0 14 114 3 193 0 18 56 0 560 0 0 0 100 3 0 0 7 164 77 144 0 18 78 0 0 0 0 0 100 4 0 0 0 73 4 132 1 14 71 0 1095 0 0 0 99 5 0 0 7 66 3 90 0 7 75 0 563 0 0 0 100 6 0 0 4 341 136 168 0 20 88 0 0 0 0 0 100 7 0 0 0 63 1 87 0 12 62 0 300 0 0 0 100 March 2, 2026 at 06:57:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 507 2314 202 119 0 2 1 0 0 0 1 0 99 1 0 0 0 106 7 28 0 1 1 0 11 0 0 0 100 2 0 0 14 83 3 8 0 1 0 0 560 0 0 0 100 3 0 0 0 183 52 106 0 0 0 0 0 0 0 0 100 4 0 0 0 82 2 34 1 1 1 0 1087 0 0 0 100 5 0 0 7 84 3 8 0 0 0 0 561 0 0 0 100 6 0 0 4 281 101 2 0 0 0 0 0 0 0 0 100 7 0 0 0 82 1 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:57:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2329 220 156 1 1 0 0 18 0 0 0 99 1 0 0 0 29 6 26 0 0 0 0 14 0 0 0 100 2 1 0 14 11 3 10 1 0 0 0 567 0 0 0 100 3 0 0 0 77 36 72 0 1 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 1088 0 0 0 100 5 0 0 7 23 12 8 0 0 0 0 559 0 0 0 100 6 0 0 4 209 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 11 1 9 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2718 0 264 2901 233 1184 19 174 115 53 5573 5 4 0 91 1 1826 0 129 594 9 1108 51 216 107 61 4010 5 3 0 92 2 911 0 36 524 22 842 21 144 85 33 3173 4 2 0 94 3 3054 0 9 538 3 880 30 183 113 50 4065 6 3 0 91 4 42150 0 324 478 2 881 36 168 173 74 6972 13 11 0 76 5 10373 0 45 552 3 687 24 120 139 50 3749 6 4 0 90 6 916 0 12 743 102 977 28 176 84 63 3359 3 2 0 95 7 1466 0 14 462 2 792 28 124 84 49 3519 4 2 0 94 March 2, 2026 at 06:57:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 91 2315 205 121 0 4 6 0 20 0 2 0 98 1 1 0 0 39 1 22 0 3 7 0 15 0 0 0 99 2 6 0 14 134 54 120 0 2 2 0 571 0 0 0 100 3 9 0 0 31 4 9 0 2 1 0 18 0 0 0 100 4 3 0 0 35 5 44 1 1 2 0 1096 0 0 0 100 5 0 0 14 30 4 10 0 2 4 0 569 0 0 0 100 6 18 0 7 237 104 16 0 1 1 0 29 0 0 0 100 7 9 0 0 26 2 4 0 1 1 0 309 0 0 0 100 March 2, 2026 at 06:57:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 38 2412 208 198 0 12 91 0 10 0 2 0 98 1 0 0 350 79 1 128 0 14 75 0 2 0 1 0 99 2 0 0 14 268 53 306 0 16 45 0 560 0 0 0 100 3 0 0 0 155 61 70 0 10 95 0 0 0 0 0 100 4 0 0 0 113 3 133 1 15 97 0 1079 0 1 0 99 5 0 0 7 101 4 74 0 12 62 0 565 0 0 0 100 6 0 0 4 302 101 81 0 16 70 0 0 0 0 0 100 7 0 0 0 121 1 114 0 17 64 0 300 0 0 0 100 March 2, 2026 at 06:57:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2319 208 127 0 2 0 0 9 0 1 0 99 1 0 0 0 24 0 2 0 0 0 0 0 0 0 0 100 2 0 0 14 133 53 110 2 0 1 0 560 0 0 0 100 3 0 0 0 28 1 16 0 1 0 0 0 0 0 0 100 4 0 0 0 28 3 36 1 0 0 0 1078 0 0 0 100 5 0 0 7 30 4 10 0 0 0 0 560 0 0 0 100 6 0 0 4 223 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 23 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1007 0 92 2539 211 529 12 81 55 37 3373 3 3 0 94 1 1187 0 193 238 1 427 7 91 39 34 1305 1 2 0 97 2 2747 0 40 363 52 436 13 63 37 39 1941 3 1 0 96 3 421 0 18 265 4 438 9 90 71 50 1632 1 2 0 97 4 2315 0 3 224 3 398 7 85 68 30 2510 1 2 0 97 5 5350 0 122 203 8 351 8 64 86 42 2300 2 2 0 96 6 2450 0 16 414 102 356 3 68 62 35 1500 1 1 0 98 7 135 0 7 191 1 318 3 57 46 36 1523 1 0 0 99 March 2, 2026 at 06:57:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1313 0 120 2592 205 616 23 109 70 31 2396 3 3 0 94 1 880 0 3 319 2 513 25 104 73 28 1601 2 2 0 96 2 462 0 14 265 3 422 20 89 29 21 3812 4 1 0 95 3 33280 0 9 394 38 608 26 90 42 21 2332 10 7 0 82 4 1380 0 115 286 12 504 12 65 51 26 2499 3 2 0 95 5 5250 0 199 206 3 353 11 71 95 40 2171 3 2 0 95 6 4261 0 14 544 107 443 23 79 68 22 1472 2 2 0 96 7 902 0 9 253 2 422 16 70 93 41 1715 2 1 0 97 March 2, 2026 at 06:58:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2374 202 104 0 3 2 0 0 0 1 0 99 1 0 0 462 21 1 16 0 2 2 0 2 0 1 0 99 2 2 0 14 83 3 6 0 0 0 0 562 0 0 0 100 3 0 0 0 172 40 92 0 4 0 0 1 0 0 0 100 4 40 0 0 121 19 70 1 2 0 0 1084 0 0 0 99 5 0 0 7 85 3 8 0 0 0 0 563 0 0 0 100 6 0 0 4 285 101 12 0 1 0 0 0 0 0 0 100 7 0 0 0 83 1 4 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:58:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2343 202 170 0 13 59 0 0 0 1 0 99 1 0 0 0 54 1 95 0 18 75 0 1 0 0 0 100 2 0 0 14 101 3 187 1 16 55 0 560 0 0 0 100 3 0 0 0 219 110 194 0 15 64 0 0 0 0 0 100 4 0 0 0 71 10 142 1 17 78 0 1088 0 0 0 99 5 0 0 7 52 3 89 0 11 62 0 561 0 0 0 100 6 0 0 4 244 101 70 0 13 48 0 0 0 0 0 100 7 0 0 0 57 1 101 0 12 86 0 300 0 0 0 100 March 2, 2026 at 06:58:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 203 116 0 0 0 0 1 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 2 2 0 14 11 3 4 2 0 0 0 667 1 0 0 99 3 0 0 0 110 51 106 0 2 0 0 0 0 0 0 100 4 0 0 0 22 8 46 1 0 1 0 1086 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 559 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:58:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5647 0 92 2866 216 1094 41 210 153 68 4795 4 4 0 91 1 34407 0 48 540 0 979 33 205 116 61 4104 11 10 0 79 2 1160 0 5 486 3 800 27 168 99 43 3590 3 2 0 95 3 4351 0 223 606 37 899 34 163 121 48 3891 7 3 0 90 4 3905 0 304 524 10 843 22 144 90 49 4381 6 4 0 90 5 1264 0 17 479 12 787 26 148 170 42 2991 3 2 0 95 6 3609 0 19 679 102 832 34 165 164 39 4381 6 4 0 91 7 9562 0 162 395 2 707 16 133 174 72 4312 6 5 0 89 March 2, 2026 at 06:58:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 27 0 17 2326 204 122 0 2 2 0 8 0 0 0 99 1 3 0 14 32 3 20 0 4 6 0 282 0 0 0 99 2 19 0 7 26 1 8 0 3 1 0 303 0 0 0 100 3 22 0 70 113 51 106 0 0 7 0 9 0 1 0 99 4 0 0 0 31 4 38 2 1 2 0 1108 0 0 0 100 5 1 0 7 29 3 14 0 3 0 0 566 0 0 0 100 6 42 0 4 237 107 20 0 3 0 0 15 0 0 0 100 7 0 0 0 34 3 15 0 2 0 0 320 0 0 0 100 March 2, 2026 at 06:58:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2378 202 104 0 0 1 0 0 0 1 0 99 1 0 0 476 17 2 6 0 0 3 0 266 0 1 0 99 2 0 0 0 88 2 8 0 0 1 0 294 0 0 0 100 3 0 0 42 111 18 36 0 1 3 0 0 0 1 0 99 4 0 0 0 156 38 106 1 1 1 0 1077 0 0 0 99 5 0 0 7 86 4 6 0 0 1 0 563 0 0 0 100 6 0 0 7 301 108 22 0 2 0 0 9 0 0 0 100 7 0 0 0 83 2 4 0 1 1 0 300 0 0 0 100 March 2, 2026 at 06:58:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2344 202 180 0 10 70 0 0 0 1 0 99 1 5 0 14 69 4 124 0 10 71 0 274 0 0 0 100 2 3 0 0 108 1 199 0 12 55 0 305 0 0 0 100 3 0 0 0 108 64 72 1 11 74 0 1 0 0 0 100 4 0 0 0 94 17 172 1 15 62 0 1078 0 1 0 99 5 0 0 7 115 39 143 0 11 48 0 561 0 0 0 100 6 0 0 4 263 107 91 0 15 60 0 9 0 0 0 100 7 0 0 0 54 3 97 1 11 73 0 300 0 0 0 100 March 2, 2026 at 06:58:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3086 0 170 2555 212 505 21 82 108 55 3213 2 3 0 95 1 7122 0 46 334 1 432 10 78 95 57 3392 4 3 0 93 2 33995 0 207 295 3 511 12 97 55 55 2368 9 7 0 84 3 1424 0 123 268 1 484 6 94 49 55 2465 2 2 0 97 4 398 0 12 268 3 504 6 100 47 54 2360 1 1 0 98 5 220 0 24 323 45 446 5 75 33 30 1651 1 1 0 98 6 467 0 21 463 109 419 9 96 81 43 1425 1 2 0 97 7 3111 0 13 223 4 344 18 73 83 41 2107 2 2 0 95 March 2, 2026 at 06:58:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 457 0 45 2612 206 653 26 102 57 4 2221 2 2 0 96 1 3239 0 193 399 33 710 33 111 103 14 2541 5 2 0 93 2 5275 0 84 381 19 545 22 77 111 9 1971 4 4 0 91 3 1182 0 3 337 3 610 31 117 78 15 2514 2 2 0 96 4 1008 0 7 289 4 535 17 85 48 23 2665 2 2 0 96 5 953 0 7 222 9 358 11 69 63 10 2203 3 1 0 96 6 815 0 4 514 103 577 20 97 51 11 1574 4 1 0 95 7 914 0 0 223 3 380 12 55 53 5 1967 2 1 0 97 March 2, 2026 at 06:58:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2384 201 122 0 2 0 0 0 0 1 0 99 1 0 0 14 79 1 4 0 1 0 0 266 0 0 0 100 2 0 0 42 153 39 82 0 1 3 0 0 0 1 0 99 3 40 0 462 52 19 44 0 1 3 0 302 0 1 0 99 4 0 0 0 87 3 38 1 0 1 0 1081 0 1 0 99 5 0 0 7 87 3 8 0 1 0 0 563 0 0 0 100 6 0 0 4 283 102 2 0 0 0 0 1 0 0 0 100 7 0 0 0 83 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:58:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 201 114 0 1 0 0 0 0 0 0 100 1 0 0 14 16 3 18 1 1 0 0 269 0 0 0 100 2 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 3 0 0 0 121 58 116 0 0 0 0 303 0 0 0 100 4 0 0 0 12 3 36 1 0 0 0 1080 0 0 0 99 5 0 0 7 12 3 8 0 0 0 0 560 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:58:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2342 201 177 0 8 60 0 0 0 1 0 99 1 0 0 14 44 3 77 0 11 80 0 267 0 0 0 100 2 0 0 0 99 1 182 0 13 66 0 0 0 0 0 100 3 0 0 0 234 118 228 0 19 92 0 304 0 0 0 100 4 0 0 0 56 3 124 1 17 61 0 1082 0 1 0 99 5 2 0 7 56 3 95 0 16 42 0 561 0 0 0 100 6 0 0 3 239 101 68 0 15 54 0 0 0 0 0 100 7 0 0 0 47 2 79 0 7 69 0 300 0 0 0 100 March 2, 2026 at 06:58:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1362 0 75 2805 204 901 21 181 109 43 2677 3 3 0 94 1 1489 0 33 545 3 959 37 186 115 42 3662 4 3 0 93 2 13391 0 313 555 2 868 24 141 204 63 7171 8 6 0 87 3 7676 0 136 644 18 1066 27 181 147 67 5114 6 4 0 89 4 1172 0 24 598 17 1127 20 185 134 75 4682 3 3 0 94 5 3388 0 213 503 26 909 25 144 111 74 3734 5 2 0 92 6 1142 0 14 682 102 877 20 145 85 53 3325 6 2 0 92 7 34094 0 26 397 2 712 21 135 75 45 3007 12 9 0 79 March 2, 2026 at 06:58:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 17 2320 200 116 1 1 4 0 9 0 1 0 99 1 3 0 84 20 3 20 0 1 6 0 293 0 1 0 99 2 0 0 0 28 1 11 0 2 1 0 17 0 0 0 100 3 6 0 0 32 1 26 0 2 6 0 311 0 0 0 100 4 19 0 0 114 45 128 0 2 1 0 1104 0 0 0 100 5 9 0 7 56 20 34 0 3 0 0 587 0 0 0 100 6 53 0 11 242 108 28 0 2 0 0 29 0 0 0 100 7 1 0 0 31 2 21 0 1 0 0 334 0 0 0 100 March 2, 2026 at 06:58:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2374 200 110 0 0 0 0 0 0 1 0 99 1 0 0 56 78 3 8 1 0 2 0 269 0 1 0 99 2 0 0 0 83 1 6 0 0 0 0 0 0 0 0 100 3 0 0 462 14 1 4 0 0 2 0 294 0 1 0 99 4 0 0 0 186 54 138 1 0 0 0 1080 0 0 0 99 5 0 0 7 84 3 8 0 0 0 0 559 0 0 0 100 6 0 0 4 295 108 16 0 0 0 0 9 0 0 0 100 7 0 0 0 84 3 8 0 1 0 0 301 0 0 0 100 March 2, 2026 at 06:58:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2301 200 112 0 1 0 0 0 0 0 0 100 1 0 0 14 8 2 2 0 0 1 0 266 0 0 0 100 2 0 0 0 12 2 4 0 0 1 0 0 0 0 0 100 3 0 0 0 12 2 4 0 1 1 0 294 0 0 0 100 4 0 0 0 119 55 138 2 0 2 0 1082 0 0 0 100 5 0 0 7 20 4 18 0 1 1 0 561 0 0 0 100 6 0 0 7 222 108 14 0 0 1 0 9 0 0 0 100 7 0 0 0 12 3 4 0 0 1 0 299 0 0 0 100 March 2, 2026 at 06:58:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 28892 0 201 2940 202 1092 49 246 423 61 3637 11 11 0 78 1 7625 0 28 622 13 1050 36 227 295 66 4330 4 4 0 92 2 2858 0 20 578 5 979 30 191 208 40 3698 3 3 0 93 3 8889 0 373 584 60 982 58 205 232 61 6450 5 6 0 89 4 10314 0 28 683 40 952 43 193 217 43 4897 10 4 0 86 5 1467 0 16 528 3 960 24 173 192 65 4005 3 3 0 94 6 1727 0 191 759 114 1011 32 200 161 68 3057 4 2 0 94 7 23684 0 24 483 7 850 38 154 454 43 3104 8 6 0 86 March 2, 2026 at 06:58:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 795 0 108 2336 201 174 1 21 43 3 530 1 2 0 97 1 684 0 20 108 22 108 5 14 20 0 1280 1 1 0 98 2 630 0 0 89 2 146 12 27 41 3 473 2 0 0 97 3 652 0 1 88 7 118 9 23 35 0 747 1 1 0 98 4 404 0 0 114 33 151 2 13 18 3 1429 1 1 0 98 5 407 0 0 58 7 62 2 13 15 4 474 1 0 0 98 6 145 0 3 283 102 117 7 28 5 0 368 0 0 0 99 7 376 0 0 77 2 126 14 26 4 1 399 2 0 0 97 March 2, 2026 at 06:58:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2339 200 119 0 1 2 0 0 0 1 0 99 1 0 0 21 158 57 126 1 1 0 0 847 0 0 0 100 2 0 0 0 45 1 4 0 0 0 0 0 0 0 0 100 3 0 0 238 15 1 12 0 0 3 0 301 0 1 0 99 4 0 0 0 58 5 44 1 0 1 0 1088 0 0 0 100 5 0 0 0 63 12 14 0 0 0 0 308 0 0 0 100 6 0 0 4 249 103 6 0 0 1 0 1 0 0 0 100 7 0 0 0 52 1 19 0 1 1 0 0 0 0 0 100 March 2, 2026 at 06:58:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 241 2310 201 99 0 4 1 0 21 0 1 0 99 1 0 0 21 175 54 138 0 3 1 0 825 0 0 0 100 2 0 0 0 46 1 6 0 0 0 0 0 0 0 0 100 3 0 0 0 41 1 2 0 0 0 0 294 0 0 0 100 4 0 0 0 48 4 38 1 0 0 0 1081 0 0 0 100 5 0 0 0 55 7 14 0 0 0 0 309 0 0 0 100 6 0 0 3 245 103 4 0 0 0 0 1 0 0 0 100 7 0 0 0 43 1 6 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2303 200 112 0 0 0 0 0 0 1 0 99 1 0 0 21 114 55 110 0 0 0 0 828 0 0 0 100 2 0 0 0 11 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 294 0 0 0 100 4 0 0 0 20 5 44 1 0 0 0 1090 0 0 0 100 5 0 0 0 23 6 18 0 0 0 0 326 0 0 0 100 6 0 0 4 211 102 2 0 0 0 0 0 0 0 0 100 7 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2591 0 207 3041 212 1412 45 225 191 49 5716 4 5 0 91 1 2200 0 225 755 29 1356 27 223 201 57 4667 4 6 0 90 2 1508 0 123 690 5 1274 30 177 192 54 3785 4 3 0 93 3 9665 0 18 721 66 1222 38 207 287 54 5818 7 6 0 88 4 43020 0 42 703 5 973 31 167 253 46 6004 16 11 0 73 5 1301 0 15 535 7 972 24 159 186 63 4269 4 3 0 94 6 2406 0 192 807 107 1111 24 179 160 53 3776 6 3 0 92 7 978 0 11 496 2 856 24 128 165 60 2345 4 2 0 94 March 2, 2026 at 06:58:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 87 2307 201 83 0 3 4 0 0 0 2 0 98 1 42 0 21 86 15 72 1 3 4 0 839 0 1 0 99 2 0 0 7 117 47 102 0 3 0 0 0 0 0 0 100 3 0 0 0 28 1 14 0 1 0 0 294 0 0 0 100 4 0 0 0 27 3 6 0 0 0 0 0 0 0 0 100 5 0 0 0 27 2 36 1 0 0 0 1401 0 0 0 100 6 0 0 4 224 102 2 0 0 0 0 0 0 0 0 100 7 0 0 0 22 1 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2371 200 116 0 0 3 0 0 0 1 0 99 1 0 0 483 42 13 42 0 1 3 0 852 0 1 0 99 2 0 0 0 185 51 108 0 0 0 0 0 0 0 0 100 3 0 0 0 82 1 8 0 1 0 0 301 0 0 0 100 4 0 0 0 87 3 10 0 0 0 0 5 0 0 0 100 5 0 0 0 93 9 38 2 1 0 0 1416 0 0 0 99 6 0 0 4 281 102 2 0 0 0 0 0 0 0 0 100 7 0 0 0 84 1 9 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 21 22 10 20 0 0 0 0 835 0 0 0 100 2 0 0 0 109 51 104 0 0 0 0 0 0 0 0 100 3 0 0 0 11 1 6 0 0 0 0 294 0 0 0 100 4 0 0 0 16 3 18 0 1 0 0 0 0 0 0 100 5 0 0 0 12 2 36 1 0 0 0 1392 0 0 0 100 6 0 0 4 209 102 2 0 0 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8087 0 82 2943 201 1219 58 247 204 65 6134 5 6 0 89 1 41827 0 179 678 11 1117 63 243 163 58 5599 15 11 0 73 2 928 0 23 690 35 1154 44 226 106 59 3522 3 4 0 93 3 3635 0 21 652 4 1159 55 237 124 70 5720 5 3 0 92 4 1238 0 18 564 18 994 31 200 85 49 3845 5 2 0 93 5 654 0 4 486 4 757 32 163 66 34 4913 5 2 0 93 6 3573 0 485 699 107 966 39 188 88 55 4754 6 4 0 90 7 3573 0 19 584 2 933 39 172 114 71 3222 5 3 0 92 March 2, 2026 at 06:58:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 54 0 17 2374 205 199 1 18 57 0 25 0 1 0 99 1 20 0 84 63 3 108 1 21 82 0 584 0 1 0 99 2 0 0 0 201 36 291 1 14 78 0 23 0 0 0 99 3 6 0 0 179 84 148 2 16 98 0 321 0 0 0 99 4 6 0 14 91 6 128 1 21 65 0 268 0 0 0 100 5 3 0 0 80 4 138 2 10 88 0 1414 0 0 0 99 6 1 0 4 258 102 74 0 18 47 0 8 0 0 0 100 7 0 0 0 87 2 126 0 12 94 0 1 0 0 0 100 March 2, 2026 at 06:58:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2376 209 120 0 0 0 0 13 0 1 0 99 1 0 0 42 62 3 10 0 1 3 0 568 0 1 0 99 2 0 0 343 16 0 10 0 1 4 0 0 0 1 0 99 3 0 0 0 163 51 106 0 1 1 0 294 0 0 0 100 4 0 0 7 73 5 22 0 2 0 0 263 0 0 0 100 5 0 0 0 71 5 44 0 1 0 0 1396 0 0 0 100 6 0 0 4 263 102 4 0 0 0 0 1 0 0 0 100 7 0 0 0 66 0 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2334 207 118 0 0 0 0 9 0 0 0 99 1 0 0 14 36 5 20 0 0 0 0 582 0 0 0 100 2 0 0 119 8 0 4 0 0 1 0 0 0 0 0 100 3 0 0 0 127 51 108 0 0 0 0 301 0 0 0 100 4 0 0 7 38 6 16 0 0 0 0 266 0 0 0 100 5 0 0 0 41 8 48 1 1 0 0 1393 0 0 0 100 6 0 0 4 228 103 4 0 0 0 0 1 0 0 0 100 7 0 0 0 35 0 16 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 79 0 13 2405 208 265 1 29 20 23 419 0 1 0 99 1 54 0 35 86 2 127 1 28 18 14 951 0 0 0 99 2 31 0 2 78 0 88 0 15 12 13 269 0 0 0 100 3 39 0 20 192 51 236 0 24 9 16 481 0 1 0 99 4 25 0 25 71 5 87 0 23 8 11 471 0 0 0 99 5 74 0 9 84 5 141 2 24 4 21 1622 0 0 0 99 6 21 0 8 273 103 76 0 19 9 7 207 0 0 0 100 7 3145 0 112 57 0 110 5 15 57 29 2097 1 1 0 98 March 2, 2026 at 06:58:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8257 0 99 2902 217 934 34 182 169 43 3392 4 4 0 92 1 2033 0 27 471 22 821 17 187 107 60 3993 4 3 0 93 2 862 0 5 406 1 695 26 146 107 44 3552 5 2 0 93 3 1177 0 3 438 3 787 27 161 111 44 3051 3 2 0 95 4 690 0 78 408 10 740 24 149 62 42 3294 3 2 0 94 5 1409 0 9 418 15 599 17 90 56 18 3935 4 2 0 94 6 2612 0 188 591 105 658 21 123 91 26 2784 4 2 0 93 7 42970 0 322 378 4 712 41 111 172 52 3624 14 11 0 75 March 2, 2026 at 06:58:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2427 200 207 0 13 73 0 0 0 1 0 99 1 42 0 14 237 59 204 0 16 62 0 576 0 0 0 99 2 0 0 462 99 1 170 0 13 48 0 1 0 1 0 99 3 0 0 0 177 52 88 0 19 52 0 0 0 1 0 99 4 0 0 49 125 8 97 0 15 76 0 556 0 1 0 99 5 0 0 0 128 3 124 1 11 81 0 1394 0 1 0 99 6 0 0 4 319 101 79 0 18 69 0 0 0 0 0 100 7 0 0 0 121 0 83 0 13 80 0 0 0 0 0 100 March 2, 2026 at 06:58:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 14 125 61 122 0 0 0 0 578 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 4 0 0 7 17 7 12 0 0 0 0 554 0 0 0 100 5 0 0 0 14 3 38 1 0 0 0 1392 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 114 0 0 0 0 0 0 0 0 100 1 0 0 14 136 61 144 0 1 0 0 589 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 0 6 0 0 0 0 7 0 0 0 100 4 0 0 7 21 7 16 0 0 0 0 560 0 0 0 100 5 0 0 0 21 9 38 0 0 1 0 1393 0 0 0 100 6 0 0 4 207 101 0 0 0 0 0 0 0 0 0 100 7 0 0 0 8 0 5 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4753 0 346 2907 201 1055 24 187 116 62 4542 8 4 0 88 1 1785 0 21 820 34 1375 32 236 87 56 4786 4 3 0 93 2 2011 0 15 593 2 991 21 163 115 39 3639 4 3 0 93 3 4065 0 231 600 2 999 33 187 90 59 3580 5 4 0 91 4 1529 0 12 552 9 904 25 160 129 48 4050 3 3 0 94 5 10293 0 261 499 14 928 21 135 161 55 6742 6 5 0 89 6 38107 0 46 792 106 937 37 167 137 48 4921 13 10 0 77 7 787 0 14 553 8 983 26 148 107 61 3690 4 2 0 94 March 2, 2026 at 06:58:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 24 2318 201 121 0 6 2 0 27 0 0 0 99 1 9 0 0 36 4 20 0 2 0 0 322 0 0 0 100 2 25 0 0 25 2 4 0 2 1 0 10 0 0 0 100 3 1 0 70 18 2 8 0 2 8 0 13 0 1 0 99 4 0 0 7 35 7 18 0 0 6 0 567 0 0 0 100 5 0 0 0 69 23 74 1 0 1 0 1413 0 0 0 99 6 4 0 18 293 135 76 0 4 1 0 284 0 0 0 100 7 53 0 0 39 7 22 0 1 2 0 17 0 0 0 100 March 2, 2026 at 06:58:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2435 216 224 0 13 46 0 0 0 1 0 99 1 0 0 0 131 4 106 0 17 77 0 307 0 0 0 100 2 0 0 0 172 0 185 0 15 47 0 11 0 0 0 100 3 0 0 42 176 57 97 0 15 80 0 1 0 1 0 99 4 0 0 469 71 6 112 0 11 93 0 557 0 1 0 99 5 0 0 0 127 3 124 1 9 76 0 1394 0 1 0 99 6 0 0 18 385 137 141 0 13 58 0 266 0 0 0 100 7 0 0 0 124 7 82 0 13 85 0 9 0 0 0 100 March 2, 2026 at 06:58:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 250 208 0 0 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 4 0 0 7 20 6 22 0 1 0 0 554 0 0 0 100 5 0 0 0 15 4 40 0 0 0 0 1394 0 0 0 100 6 0 0 18 211 103 6 1 0 0 0 266 0 0 0 100 7 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:58:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3137 0 158 2636 244 676 15 111 73 52 1858 2 3 0 95 1 17228 0 148 311 5 556 10 111 78 52 3272 6 4 0 90 2 1876 0 24 335 1 386 4 78 65 44 1764 1 1 0 97 3 939 0 12 276 1 459 6 96 67 52 3944 2 1 0 97 4 909 0 14 292 8 469 9 92 39 56 2435 2 1 0 97 5 2021 0 196 269 12 442 6 80 51 37 2637 2 2 0 96 6 109 0 32 458 105 435 9 89 62 40 2144 1 1 0 97 7 4728 0 17 234 11 351 7 66 82 40 1379 1 2 0 96 March 2, 2026 at 06:58:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 812 0 32 2643 202 714 29 109 46 7 1430 2 2 0 96 1 22243 0 79 308 3 528 31 97 124 9 2828 8 8 0 84 2 4295 0 10 351 3 467 19 69 88 8 2485 3 2 0 96 3 478 0 2 323 2 613 35 104 32 16 2080 2 1 0 96 4 848 0 185 375 46 666 13 82 40 13 2738 3 2 0 95 5 964 0 0 289 4 517 18 74 54 20 3064 4 2 0 95 6 597 0 16 500 105 501 22 77 32 6 1890 4 1 0 94 7 2393 0 13 267 8 564 14 65 60 19 1527 3 1 0 96 March 2, 2026 at 06:58:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2377 200 102 0 1 0 0 0 0 1 0 99 1 40 0 42 87 7 16 0 0 2 0 10 0 1 0 99 2 0 0 0 85 2 8 0 1 0 0 599 0 0 0 100 3 0 0 0 81 0 4 0 1 0 0 0 0 0 0 100 4 0 0 469 124 57 114 0 0 2 0 556 0 1 0 99 5 0 0 0 84 1 36 1 1 0 0 1093 0 0 0 100 6 2 0 18 297 103 24 0 1 0 0 266 0 0 0 100 7 0 0 0 79 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2350 200 196 0 12 68 0 0 0 1 0 99 1 0 0 0 62 8 95 0 17 59 0 10 0 0 0 100 2 0 0 0 106 3 195 0 9 67 0 601 0 0 0 100 3 0 0 0 106 55 95 0 15 71 0 0 0 0 0 100 4 0 0 7 169 58 219 0 14 83 0 555 0 0 0 100 5 0 0 0 55 1 132 0 13 82 0 1093 0 0 0 99 6 0 0 18 238 103 58 1 12 58 0 266 0 0 0 100 7 0 0 0 47 0 82 0 10 100 0 0 0 0 0 100 March 2, 2026 at 06:58:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 108 0 0 0 0 0 0 0 0 100 1 0 0 0 23 9 18 0 0 0 0 12 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 601 0 0 0 100 3 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 4 0 0 7 118 57 112 1 0 0 0 554 0 0 0 100 5 0 0 0 10 1 34 1 0 1 0 1093 0 0 0 100 6 0 0 18 213 103 8 0 1 0 0 266 0 0 0 100 7 0 0 0 11 0 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3394 0 100 2829 201 854 24 161 89 46 2739 4 4 0 92 1 2649 0 210 502 9 903 27 161 120 65 3802 5 3 0 92 2 8115 0 126 461 3 804 28 146 161 56 6260 5 4 0 91 3 6270 0 195 494 2 970 22 184 166 69 3856 5 3 0 92 4 5361 0 57 596 42 875 23 162 102 60 3736 5 4 0 91 5 33806 0 8 482 11 750 28 152 81 73 3061 11 8 0 81 6 2040 0 140 625 113 744 9 141 110 46 5411 5 2 0 93 7 1610 0 7 345 0 596 13 121 68 57 2907 3 2 0 95 March 2, 2026 at 06:58:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 17 2320 202 116 0 3 2 0 13 0 0 0 99 1 0 0 70 17 3 10 0 1 6 0 15 0 1 0 99 2 0 0 0 27 2 10 1 1 0 0 610 0 0 0 100 3 13 0 0 58 18 42 0 1 0 0 16 0 0 0 100 4 9 0 14 104 40 90 0 3 6 0 551 0 1 0 99 5 0 0 0 25 1 8 0 2 0 0 7 0 0 0 100 6 43 0 18 235 106 47 1 2 0 0 1419 0 0 0 99 7 25 0 0 21 1 2 0 0 0 0 10 0 0 0 100 March 2, 2026 at 06:58:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2375 200 112 0 0 1 0 0 0 1 0 99 1 0 0 42 86 3 18 0 1 3 0 0 0 1 0 99 2 0 0 0 88 3 8 0 0 1 0 600 0 0 0 100 3 0 0 0 182 51 104 0 1 0 0 0 0 0 0 100 4 0 0 469 26 6 14 0 0 3 0 260 0 1 0 99 5 0 0 0 82 1 2 0 1 1 0 0 0 0 0 100 6 0 0 21 298 111 50 2 0 1 0 1660 0 0 0 99 7 0 0 0 80 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:58:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2349 201 192 0 13 74 0 1 0 1 0 99 1 0 0 0 57 3 97 0 18 86 0 2 0 0 0 100 2 0 0 0 102 2 193 0 16 51 0 601 0 0 0 100 3 0 0 0 204 108 178 0 18 56 0 1 0 0 0 100 4 0 0 7 53 5 89 0 14 67 0 260 0 0 0 100 5 0 0 0 55 0 99 0 11 60 0 0 0 0 0 100 6 0 0 18 263 111 134 0 15 73 0 1662 0 0 0 99 7 0 0 0 44 1 77 0 11 61 0 0 0 0 0 100 March 2, 2026 at 06:58:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1424 0 156 2757 202 848 16 148 67 60 2744 2 2 0 95 1 1432 0 184 418 4 727 22 154 55 61 2636 3 2 0 95 2 5021 0 26 452 2 569 18 104 108 41 3519 4 3 0 93 3 5459 0 41 538 36 726 26 122 106 52 3183 5 3 0 93 4 3587 0 198 461 18 823 17 138 102 54 4887 3 4 0 94 5 38652 0 151 414 3 736 21 125 105 56 3344 11 10 0 79 6 2942 0 30 653 115 829 17 141 85 59 4960 3 3 0 94 7 1170 0 22 347 1 636 12 114 65 77 2615 3 2 0 95 March 2, 2026 at 06:58:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 538 0 31 2440 202 340 14 45 29 2 952 1 1 0 98 1 613 0 0 268 54 407 17 53 30 5 1228 1 1 0 98 2 505 0 0 107 2 168 9 31 22 4 746 1 1 0 98 3 166 0 70 106 2 195 7 38 24 1 654 1 1 0 98 4 316 0 7 132 10 202 9 30 20 1 1572 3 1 0 96 5 634 0 0 80 7 100 4 20 25 0 493 1 0 0 99 6 296 0 24 297 104 187 16 36 10 2 1821 1 1 0 98 7 586 0 0 119 1 205 22 24 36 2 620 3 1 0 97 March 2, 2026 at 06:58:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 108 0 0 0 0 0 0 0 0 100 1 0 0 0 130 60 122 1 1 0 0 304 0 0 0 100 2 0 0 0 13 1 4 0 0 0 0 300 0 0 0 100 3 0 0 27 12 0 5 0 2 4 0 263 0 1 0 99 4 0 0 21 27 6 26 0 1 3 0 563 0 1 0 99 5 0 0 0 11 0 0 0 0 0 0 0 0 0 0 100 6 0 0 5 225 105 44 2 3 4 0 1088 0 0 0 99 7 0 0 0 10 0 2 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2370 200 108 0 0 0 0 0 0 1 0 99 1 0 0 0 189 58 114 0 0 0 0 304 0 0 0 100 2 0 0 0 82 2 10 0 1 0 0 300 0 0 0 100 3 0 0 42 72 1 6 0 0 1 0 266 0 1 0 99 4 0 0 7 88 7 18 0 0 0 0 569 0 0 0 100 5 0 0 0 77 0 6 0 0 0 0 18 0 0 0 100 6 0 0 452 219 103 38 1 1 2 0 1085 0 1 0 99 7 0 0 0 73 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2349 200 189 0 15 59 0 1 0 1 0 99 1 0 0 0 71 13 111 1 13 70 0 309 0 0 0 100 2 0 0 0 220 52 320 0 17 54 0 312 0 0 0 100 3 0 0 14 116 66 91 0 17 80 0 266 0 0 0 100 4 0 0 7 65 6 110 0 19 86 0 560 0 0 0 100 5 0 0 0 48 0 85 0 9 56 0 0 0 0 0 100 6 0 0 4 256 103 127 1 21 56 0 1083 0 0 0 99 7 0 0 0 43 0 69 0 10 59 0 0 0 0 0 100 March 2, 2026 at 06:58:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8064 0 263 2921 202 1104 38 177 135 80 4042 7 5 0 89 1 37259 0 132 659 12 1232 35 209 152 77 4558 12 9 0 79 2 1861 0 15 522 11 873 23 169 60 60 3995 6 2 0 92 3 2020 0 202 532 3 926 27 160 67 53 4064 6 2 0 91 4 1175 0 19 592 32 979 22 169 102 47 4616 3 3 0 94 5 3869 0 134 431 5 703 19 122 79 51 4865 3 3 0 94 6 3490 0 27 654 113 826 15 138 121 41 4283 3 4 0 93 7 5606 0 45 431 2 647 23 113 147 38 2679 4 3 0 92 March 2, 2026 at 06:58:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 81 2309 202 112 1 3 6 0 12 0 1 0 99 1 40 0 0 36 7 20 0 1 6 0 302 0 0 0 99 2 0 0 0 36 2 18 0 1 0 0 300 0 0 0 100 3 2 0 14 111 46 100 0 1 0 0 271 0 0 0 100 4 0 0 7 40 11 22 0 0 0 0 566 0 0 0 100 5 0 0 0 23 5 0 0 0 0 0 0 0 0 0 100 6 0 0 2 226 103 38 1 1 0 0 1084 0 0 0 100 7 0 0 0 23 1 9 0 1 1 0 0 0 0 0 100 March 2, 2026 at 06:58:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 46 2368 200 114 0 0 2 0 0 0 1 0 99 1 0 0 454 34 9 28 0 1 2 0 305 0 1 0 99 2 0 0 0 84 2 8 0 1 0 0 300 0 0 0 100 3 0 0 14 176 51 102 0 0 0 0 266 0 0 0 100 4 0 0 7 87 6 12 0 0 0 0 561 0 0 0 100 5 0 0 0 78 0 2 0 0 0 0 0 0 0 0 100 6 0 0 3 293 103 48 1 0 1 0 1084 0 0 0 100 7 0 0 0 76 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 112 0 1 2 0 1 0 0 0 100 1 0 0 0 23 9 16 0 0 1 0 303 0 0 0 100 2 0 0 0 13 3 6 0 0 1 0 300 0 0 0 100 3 0 0 14 107 52 104 0 1 0 0 266 0 0 0 100 4 0 0 7 18 7 12 0 0 1 0 559 0 0 0 100 5 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 6 0 0 3 222 103 48 1 1 1 0 1084 0 0 0 100 7 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:58:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10656 0 264 2998 202 1368 53 240 285 66 5749 6 6 0 87 1 17678 0 165 811 8 1341 47 231 401 58 6359 9 8 0 84 2 2036 0 231 724 7 1356 39 206 217 67 4395 4 3 0 93 3 34947 0 2 825 95 1198 45 195 543 59 4273 14 7 0 79 4 4152 0 35 671 12 993 38 195 188 54 4960 8 3 0 89 5 14239 0 201 526 9 946 26 174 292 69 3925 8 5 0 87 6 5552 0 21 773 104 1104 31 210 198 43 4552 6 6 0 89 7 503 0 10 502 4 839 22 138 172 30 2491 5 2 0 93 March 2, 2026 at 06:58:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 17 2368 250 212 0 2 0 0 6 0 0 0 100 1 6 0 0 22 1 6 0 2 0 0 304 0 0 0 100 2 2 0 70 22 3 15 0 2 5 0 309 0 1 0 99 3 0 0 7 28 1 17 1 5 5 0 8 0 0 0 100 4 6 0 14 25 4 9 1 1 0 0 580 0 0 0 100 5 0 0 7 31 4 12 0 1 0 0 280 0 0 0 100 6 14 0 4 236 105 46 1 2 3 0 1113 0 0 0 100 7 53 0 0 42 6 28 1 2 0 0 14 0 0 0 100 March 2, 2026 at 06:58:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2418 252 234 1 1 0 0 15 0 1 0 99 1 0 0 0 60 2 4 0 0 0 0 296 0 0 0 100 2 0 0 14 64 3 10 0 0 3 0 300 0 1 0 99 3 0 0 343 15 1 12 0 1 4 0 6 0 1 0 99 4 0 0 14 64 5 10 0 1 0 0 566 0 0 0 100 5 1 0 7 72 9 10 0 0 0 0 264 0 0 0 100 6 0 0 4 271 104 42 1 0 0 0 1083 0 0 0 100 7 0 0 0 73 6 19 0 0 1 0 9 0 0 0 100 March 2, 2026 at 06:58:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2381 254 170 0 2 0 0 24 0 1 0 99 1 0 0 0 26 1 2 0 0 0 0 294 0 0 0 100 2 0 0 14 81 3 58 0 1 0 0 300 0 0 0 100 3 0 0 119 9 0 2 0 0 1 0 0 0 0 0 100 4 0 0 14 29 4 6 0 0 0 0 567 0 0 0 100 5 0 0 7 30 2 8 0 1 0 0 260 0 0 0 100 6 0 0 4 237 105 40 1 0 1 0 1079 0 0 0 100 7 0 0 0 36 6 12 0 0 0 0 10 0 0 0 100 March 2, 2026 at 06:59:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3155 0 123 2399 250 300 3 10 35 20 1622 1 2 0 97 1 67 0 15 69 2 90 0 24 18 11 587 0 1 0 99 2 42 0 19 69 3 91 1 22 14 17 622 0 0 0 99 3 34 0 3 62 0 66 0 16 13 8 297 0 0 0 100 4 21 0 14 53 4 59 1 14 4 9 816 0 0 0 100 5 15 0 9 57 2 73 1 16 6 9 738 0 0 0 100 6 17 0 15 258 104 93 4 13 9 11 1227 0 0 0 99 7 21 0 2 64 8 71 0 11 14 10 180 0 0 0 100 March 2, 2026 at 06:59:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3905 0 109 2875 202 859 21 161 166 45 2680 3 4 0 93 1 3846 0 257 662 9 1150 26 186 203 46 3662 3 4 0 92 2 34094 0 35 546 3 819 22 139 209 39 3860 15 10 0 74 3 3312 0 14 556 69 852 29 163 191 46 3193 3 3 0 94 4 1833 0 196 428 6 751 9 141 143 43 3327 4 2 0 93 5 1908 0 124 378 4 665 14 125 166 52 3932 4 2 0 94 6 2626 0 21 706 124 919 22 160 162 50 3569 5 2 0 93 7 1522 0 18 402 15 676 14 114 170 40 2673 3 2 0 95 March 2, 2026 at 06:59:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2378 201 2 0 1 0 0 0 0 1 0 99 1 0 0 42 78 2 6 0 1 2 0 296 0 1 0 99 2 0 0 0 188 0 110 0 0 0 0 0 0 0 0 100 3 0 0 462 20 2 10 0 1 2 0 300 0 1 0 99 4 45 0 14 95 9 16 2 0 0 0 401 1 0 0 99 5 0 0 7 87 3 10 0 0 0 0 564 0 0 0 100 6 0 0 4 387 154 138 1 1 1 0 1083 0 0 0 100 7 0 0 0 81 0 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2307 202 14 0 1 0 0 7 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 2 0 0 0 117 0 110 0 0 0 0 0 0 0 0 100 3 0 0 0 17 2 20 0 1 0 0 308 0 0 0 100 4 0 0 14 20 9 16 0 0 0 0 275 0 0 0 100 5 0 0 7 20 8 10 0 0 0 0 560 0 0 0 100 6 0 0 2 321 155 148 1 0 0 0 1097 0 0 0 100 7 0 0 0 10 0 7 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:59:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2321 216 134 0 2 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 296 0 0 0 100 2 0 0 0 14 0 6 0 1 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 1 0 300 0 0 0 100 4 0 0 14 26 9 28 0 1 0 0 275 0 0 0 100 5 0 0 7 13 3 10 0 0 0 0 561 0 0 0 100 6 0 0 4 265 129 88 0 2 0 0 1084 0 0 0 100 7 0 0 0 28 10 22 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1304 0 119 2809 223 932 21 160 89 53 4627 4 6 0 90 1 35895 0 125 555 6 959 43 176 139 47 6040 15 10 0 76 2 8298 0 129 498 13 827 24 155 163 61 3992 4 4 0 92 3 7639 0 30 547 5 869 27 165 171 56 4646 5 3 0 92 4 6770 0 219 543 21 870 19 144 164 63 3468 5 3 0 92 5 1625 0 3 453 5 765 14 149 65 65 2524 3 2 0 95 6 1383 0 208 640 105 780 23 138 108 45 4286 3 3 0 93 7 794 0 19 491 2 823 27 115 101 60 2537 4 2 0 94 March 2, 2026 at 06:59:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 87 2366 205 193 1 20 78 0 19 0 2 0 98 1 1 0 7 139 4 214 1 19 57 0 307 0 1 0 99 2 0 0 0 175 50 192 0 15 57 0 17 0 0 0 100 3 25 0 7 143 63 123 0 15 78 0 574 0 0 0 100 4 4 0 14 69 3 104 1 20 84 0 280 0 0 0 100 5 23 0 0 64 3 78 1 14 64 0 329 0 0 0 100 6 0 0 4 283 106 136 1 15 75 0 1130 0 0 0 99 7 1 0 0 58 1 76 0 10 47 0 14 0 0 0 100 March 2, 2026 at 06:59:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2368 207 116 0 0 3 0 9 0 1 0 99 1 0 0 350 14 1 8 0 0 4 0 294 0 1 0 99 2 0 0 7 161 50 106 0 2 0 0 0 0 0 0 100 3 0 0 7 66 4 8 0 0 0 0 563 0 0 0 100 4 0 0 14 61 3 4 0 0 0 0 266 0 0 0 100 5 0 0 0 66 2 8 0 1 0 0 301 0 0 0 100 6 0 0 4 281 104 56 1 2 2 0 1091 0 0 0 100 7 0 0 0 60 0 2 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 136 2319 207 125 1 2 0 0 14 0 1 0 99 1 0 0 0 29 2 4 0 0 0 0 296 0 0 0 100 2 0 0 0 132 50 108 0 0 0 0 0 0 0 0 100 3 0 0 7 33 4 12 0 0 0 0 567 0 0 0 100 4 0 0 14 29 4 6 0 0 0 0 267 0 0 0 100 5 0 0 0 36 7 8 0 0 0 0 324 0 0 0 100 6 0 0 4 249 106 56 1 0 1 0 1103 0 0 0 100 7 0 0 0 29 0 7 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:59:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1029 0 257 2589 208 508 12 78 48 30 1324 1 3 0 96 1 13679 0 120 238 1 399 14 81 48 43 3445 5 3 0 92 2 4447 0 19 343 45 522 6 88 93 54 2038 2 2 0 96 3 8133 0 146 322 6 480 9 95 117 58 3667 4 3 0 93 4 267 0 25 250 3 429 3 91 49 55 1780 1 1 0 98 5 998 0 17 235 1 366 9 75 58 47 2468 2 2 0 96 6 522 0 22 458 110 476 7 90 38 50 2501 1 2 0 97 7 224 0 11 191 0 262 4 59 52 25 978 1 1 0 98 March 2, 2026 at 06:59:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1694 0 277 2519 218 488 17 71 67 10 1654 2 3 0 95 1 20809 0 7 290 4 488 20 79 35 9 2102 8 6 0 85 2 2221 0 18 296 2 454 18 71 52 11 1175 3 2 0 95 3 4151 0 17 351 6 532 16 67 84 11 3146 4 2 0 94 4 4004 0 16 248 6 421 19 65 87 14 2497 4 2 0 94 5 167 0 0 213 1 392 17 62 23 14 1424 2 1 0 98 6 381 0 5 479 126 467 8 66 40 7 2419 2 1 0 97 7 589 0 0 211 9 366 9 64 35 7 1097 1 1 0 98 March 2, 2026 at 06:59:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 45 2451 244 240 0 14 70 0 294 0 2 0 98 1 0 0 462 136 2 227 0 22 84 0 0 0 1 0 99 2 0 0 0 140 7 107 0 19 72 0 0 0 1 0 99 3 40 0 7 212 67 129 0 19 71 0 869 0 0 0 99 4 2 0 14 134 3 116 0 22 85 0 269 0 0 0 100 5 0 0 0 110 2 54 0 11 51 0 1 0 0 0 100 6 0 0 4 327 104 117 1 16 85 0 1089 0 0 0 99 7 0 0 0 125 0 86 0 10 55 0 0 0 0 0 100 March 2, 2026 at 06:59:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 201 51 0 2 1 0 287 0 0 0 100 1 0 0 0 82 2 75 0 1 0 0 14 0 0 0 100 2 0 0 0 110 50 106 0 0 0 0 0 0 0 0 100 3 1 0 7 14 5 10 0 0 0 0 859 0 0 0 100 4 0 0 14 20 9 16 0 0 0 0 275 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 4 216 105 38 1 0 1 0 1091 0 0 0 100 7 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 116 0 0 0 0 5 0 0 0 100 1 0 0 0 14 2 14 0 1 0 0 294 0 0 0 100 2 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 3 0 0 7 16 5 14 0 0 0 0 868 0 0 0 100 4 0 0 14 20 9 16 0 0 0 0 275 0 0 0 100 5 0 0 0 13 6 2 0 1 1 0 0 0 0 0 100 6 0 0 4 221 106 46 0 0 0 0 1103 0 0 0 100 7 0 0 0 11 0 11 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3038 0 292 2922 200 1257 37 196 107 75 3707 6 4 0 91 1 2924 0 19 600 4 1054 28 201 138 51 4597 5 3 0 92 2 2688 0 363 542 20 937 27 150 100 66 3820 5 4 0 92 3 42815 0 43 613 7 1084 35 175 200 75 7237 13 13 0 74 4 8030 0 49 689 18 835 22 154 132 58 3619 5 3 0 91 5 1341 0 29 499 19 865 19 142 120 63 3920 4 3 0 93 6 756 0 23 730 105 1039 26 175 87 62 4851 3 2 0 95 7 1839 0 13 430 3 773 25 138 76 54 3062 5 2 0 92 March 2, 2026 at 06:59:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 21 2326 205 120 0 2 0 0 15 0 0 0 99 1 27 0 0 30 3 12 0 1 8 0 304 0 0 0 99 2 1 0 0 38 4 24 0 3 1 0 5 0 0 0 100 3 1 0 0 28 3 10 0 1 2 0 605 0 0 0 100 4 0 0 77 22 5 14 0 1 8 0 281 0 1 0 99 5 0 0 0 126 51 106 0 1 1 0 10 0 0 0 100 6 3 0 28 231 105 42 1 2 5 0 1364 0 0 0 100 7 49 0 0 36 6 16 0 0 1 0 27 0 0 0 100 March 2, 2026 at 06:59:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2431 203 208 0 8 84 0 0 0 1 0 99 1 0 0 462 109 3 188 0 13 75 0 294 0 1 0 99 2 0 0 0 137 4 108 0 19 61 0 2 0 0 0 100 3 0 0 0 195 60 118 0 19 90 0 600 0 0 0 99 4 0 0 49 125 5 99 0 13 85 0 260 0 1 0 99 5 0 0 0 216 51 183 0 18 61 0 0 0 0 0 100 6 0 0 18 318 106 99 1 13 83 0 1344 0 0 0 99 7 0 0 0 122 7 69 0 5 35 0 9 0 0 0 100 March 2, 2026 at 06:59:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2323 217 144 0 1 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 2 0 0 0 12 1 8 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 1 0 0 601 0 0 0 100 4 0 0 7 11 4 6 0 0 0 0 260 0 0 0 100 5 0 0 0 78 35 72 0 1 0 0 1 0 0 0 100 6 0 0 18 212 104 36 1 0 0 0 1344 0 0 0 100 7 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:59:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 34539 0 175 2729 239 753 24 120 69 53 2907 11 9 0 80 1 1253 0 14 399 3 660 21 162 93 51 3767 3 2 0 94 2 8103 0 124 357 3 612 17 119 119 53 4531 3 4 0 93 3 6779 0 10 441 5 623 16 137 135 60 4552 3 3 0 94 4 1950 0 370 334 7 610 17 136 81 53 2704 2 2 0 96 5 2779 0 15 406 17 642 14 109 67 56 2135 2 2 0 96 6 3831 0 59 636 107 671 16 129 79 55 3470 4 2 0 94 7 572 0 51 352 7 592 12 97 72 51 2050 2 2 0 96 March 2, 2026 at 06:59:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 601 0 39 2584 248 646 24 88 43 2 1881 4 2 0 94 1 280 0 0 274 2 462 25 79 33 1 1677 2 1 0 96 2 107 0 0 273 3 488 29 69 13 2 1572 2 1 0 97 3 763 0 0 267 3 505 35 83 41 2 1808 2 1 0 97 4 399 0 7 249 5 471 21 75 26 2 1831 2 1 0 97 5 712 0 0 204 5 316 17 51 34 0 1187 1 1 0 98 6 698 0 16 456 108 469 23 80 50 4 2720 2 1 0 97 7 322 0 70 196 2 355 18 51 27 1 1367 3 2 0 95 March 2, 2026 at 06:59:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2425 251 204 0 0 0 0 0 0 1 0 99 1 0 0 462 23 1 14 0 1 2 0 0 0 1 0 99 2 0 0 0 86 3 10 0 0 0 0 296 0 0 0 100 3 0 0 0 79 1 2 0 0 0 0 300 0 0 0 100 4 0 0 7 97 10 22 0 0 0 0 281 0 0 0 100 5 0 0 0 85 1 10 0 0 0 0 18 0 0 0 100 6 0 0 18 286 105 38 1 0 1 0 1348 0 0 0 100 7 0 0 42 75 1 4 0 0 2 0 300 0 1 0 99 March 2, 2026 at 06:59:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2399 252 281 0 13 62 0 0 0 1 0 99 1 0 0 0 113 2 206 0 18 97 0 5 0 0 0 100 2 0 0 0 60 2 103 0 17 63 0 305 0 0 0 100 3 0 0 0 111 57 97 0 9 66 0 300 0 0 0 100 4 3 0 7 61 8 102 0 14 81 0 268 0 0 0 100 5 0 0 0 39 2 53 0 10 41 0 1 0 0 0 100 6 0 0 18 250 104 110 1 13 76 0 1348 0 0 0 99 7 0 0 0 55 1 98 0 15 87 0 300 0 0 0 100 March 2, 2026 at 06:59:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2357 251 210 0 1 0 0 0 0 0 0 100 1 0 0 0 15 1 10 0 0 0 0 0 0 0 0 100 2 0 0 0 14 3 10 0 0 0 0 296 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 7 21 9 16 0 0 0 0 269 0 0 0 100 5 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 6 0 0 18 212 104 36 1 0 1 0 1346 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:59:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1446 0 97 2889 214 1147 31 171 81 65 4137 4 3 0 92 1 1127 0 26 733 38 1208 19 164 108 40 3880 4 3 0 93 2 12358 0 413 415 3 758 15 122 226 52 6358 7 6 0 88 3 10621 0 58 662 6 998 27 172 150 58 4968 10 5 0 85 4 2087 0 199 490 7 895 13 162 122 65 3649 5 2 0 93 5 1161 0 8 494 8 844 11 124 89 68 2992 3 2 0 96 6 33763 0 41 730 107 922 19 151 89 61 4171 13 9 0 78 7 1040 0 24 396 5 701 23 116 71 43 3890 3 2 0 94 March 2, 2026 at 06:59:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2319 201 108 0 2 3 0 10 0 0 0 100 1 1 0 0 141 52 134 0 2 8 0 14 0 0 0 99 2 0 0 7 29 3 16 0 3 0 0 314 0 0 0 100 3 25 0 0 23 1 4 0 0 0 0 310 0 0 0 100 4 9 0 7 25 3 7 0 2 1 0 292 0 0 0 100 5 13 0 0 27 2 10 0 1 0 0 11 0 0 0 100 6 3 0 18 229 103 17 0 3 0 0 287 0 0 0 100 7 40 0 70 32 7 62 1 2 6 0 1394 0 1 0 98 March 2, 2026 at 06:59:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2377 201 102 0 0 1 0 0 0 1 0 99 1 0 0 462 41 9 26 0 0 3 0 0 0 1 0 99 2 0 0 0 182 46 110 0 2 2 0 294 0 0 0 100 3 0 0 0 83 2 4 0 1 1 0 300 0 0 0 100 4 0 0 7 84 4 4 0 0 1 0 260 0 0 0 100 5 0 0 0 85 2 4 0 0 1 0 0 0 0 0 100 6 0 0 21 282 103 6 0 1 0 0 266 0 0 0 100 7 0 0 42 91 8 46 1 0 4 0 1383 0 1 0 98 March 2, 2026 at 06:59:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2345 201 173 0 10 80 0 0 0 1 0 99 1 0 0 0 104 1 189 0 12 74 0 0 0 0 0 100 2 0 0 0 156 53 198 0 17 74 0 296 0 0 0 100 3 0 0 0 97 54 78 0 14 71 0 301 0 0 0 100 4 0 0 7 57 4 253 0 17 64 0 592 0 0 0 100 5 0 0 0 39 1 63 0 15 35 0 0 0 0 0 100 6 0 0 18 250 103 85 1 15 78 0 266 0 0 0 100 7 0 0 0 67 10 131 1 10 67 0 1385 0 0 0 99 March 2, 2026 at 06:59:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4036 0 84 2904 204 1006 27 201 89 55 3182 8 3 0 89 1 33828 0 37 534 3 881 42 192 52 45 3630 12 10 0 78 2 1338 0 11 580 34 940 32 165 82 40 4253 4 4 0 92 3 5469 0 30 550 3 970 35 185 167 40 4550 4 4 0 92 4 8747 0 311 478 3 877 26 161 179 55 4737 5 5 0 91 5 6351 0 146 549 8 888 35 141 108 68 4931 6 3 0 90 6 2067 0 203 681 116 850 17 160 96 67 3875 4 2 0 93 7 1277 0 12 432 11 749 13 117 81 70 3656 2 2 0 95 March 2, 2026 at 06:59:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 17 2325 201 108 0 2 0 0 8 0 0 0 100 1 9 0 0 32 3 21 0 4 0 0 20 0 0 0 100 2 35 0 0 133 55 118 1 2 6 0 309 0 1 0 99 3 0 0 70 18 1 12 0 2 6 0 311 0 1 0 99 4 0 0 7 34 2 27 0 5 0 0 30 0 0 0 100 5 25 0 7 37 9 13 1 1 2 0 289 1 0 0 99 6 97 0 18 256 110 39 1 2 0 0 318 0 0 0 100 7 0 0 0 30 2 46 1 0 0 0 1397 0 0 0 100 March 2, 2026 at 06:59:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2341 201 110 0 0 0 0 0 0 1 0 99 1 0 0 0 41 1 4 0 1 0 0 0 0 0 0 100 2 0 0 231 86 37 78 0 0 4 0 295 0 1 0 99 3 0 0 7 75 17 39 0 2 4 0 300 0 1 0 99 4 0 0 0 43 1 4 0 1 0 0 0 0 0 0 100 5 0 0 7 45 2 6 0 1 0 0 263 0 0 0 100 6 0 0 18 258 110 20 0 0 0 0 276 0 0 0 100 7 0 0 0 44 2 34 1 0 1 0 1381 0 0 0 100 March 2, 2026 at 06:59:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 255 2308 201 111 0 4 1 0 0 0 1 0 99 1 0 0 0 46 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 54 3 12 0 1 0 0 296 0 0 0 100 3 0 0 14 150 51 107 0 1 1 0 300 0 1 0 99 4 0 0 0 49 2 4 0 1 0 0 0 0 0 0 100 5 0 0 7 53 2 18 0 1 0 0 260 0 0 0 100 6 0 0 18 263 109 18 1 0 0 0 275 0 0 0 100 7 0 0 0 48 2 34 1 0 0 0 1381 0 0 0 100 March 2, 2026 at 06:59:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2347 201 194 0 13 54 0 0 0 1 0 99 1 0 0 0 96 1 182 0 14 70 0 0 0 0 0 100 2 0 0 0 53 2 88 0 13 62 0 294 0 0 0 100 3 0 0 0 180 96 164 0 18 70 0 300 0 0 0 100 4 0 0 0 83 14 127 0 19 99 0 0 0 0 0 100 5 0 0 7 50 6 77 0 11 62 0 261 0 0 0 100 6 0 0 17 276 109 130 0 20 77 0 272 0 0 0 100 7 0 0 0 50 2 109 1 9 41 0 1380 0 0 0 99 March 2, 2026 at 06:59:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37618 0 291 2860 232 1048 31 164 150 67 5634 14 11 0 75 1 6358 0 140 602 4 1155 41 220 184 75 4690 6 4 0 90 2 4508 0 20 551 5 978 33 162 127 68 4039 7 3 0 90 3 6558 0 149 632 11 973 32 177 142 63 4556 6 3 0 91 4 2283 0 11 553 10 873 25 163 88 57 2842 3 2 0 95 5 942 0 23 486 3 805 22 127 78 52 2755 3 2 0 96 6 1088 0 34 696 107 859 18 146 97 45 3945 3 3 0 94 7 4347 0 196 418 5 784 15 127 117 56 4427 3 4 0 93 March 2, 2026 at 06:59:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 73 2325 218 138 0 3 5 0 0 0 2 0 98 1 40 0 0 60 10 52 0 4 6 0 24 0 1 0 99 2 0 0 0 88 34 72 0 2 0 0 294 0 0 0 100 3 0 0 0 18 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 23 2 6 0 0 0 0 7 0 0 0 100 5 0 0 7 31 7 6 0 0 0 0 263 0 0 0 100 6 2 0 25 226 103 14 0 2 0 0 271 0 0 0 100 7 0 0 0 31 2 53 0 2 1 0 1381 0 0 0 100 March 2, 2026 at 06:59:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 46 2426 250 222 0 1 3 0 0 0 1 0 99 1 0 0 462 32 8 26 0 0 2 0 9 0 1 0 99 2 0 0 0 86 3 10 0 0 0 0 296 0 0 0 100 3 0 0 0 79 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 80 2 2 0 0 0 0 0 0 0 0 100 5 1 0 7 82 2 6 0 0 0 0 260 0 0 0 100 6 0 0 17 285 103 8 1 0 0 0 266 0 0 0 100 7 0 0 0 85 2 38 1 2 1 0 1382 0 0 0 100 March 2, 2026 at 06:59:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2350 250 210 0 0 1 0 0 0 0 0 100 1 0 0 0 23 9 16 0 0 1 0 9 0 0 0 100 2 0 0 0 16 3 10 0 0 1 0 294 0 0 0 100 3 0 0 0 9 2 2 0 0 1 0 300 0 0 0 100 4 0 0 0 10 3 2 0 0 1 0 0 0 0 0 100 5 0 0 7 11 3 4 0 0 1 0 260 0 0 0 100 6 0 0 17 211 103 6 0 0 1 0 266 0 0 0 100 7 0 0 0 12 3 36 1 1 0 0 1382 0 0 0 100 March 2, 2026 at 06:59:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8494 0 188 2914 229 1122 43 215 252 56 5227 5 5 0 90 1 8375 0 145 829 20 1343 39 259 225 66 4527 6 5 0 89 2 6784 0 33 670 6 1057 31 190 225 72 4462 6 5 0 89 3 2158 0 213 664 58 1209 45 218 205 58 4472 6 3 0 90 4 35208 0 224 544 5 1006 38 221 124 63 3892 14 9 0 77 5 853 0 11 571 10 932 32 166 142 45 2583 3 2 0 95 6 1158 0 35 690 103 858 20 178 183 48 4686 3 3 0 94 7 808 0 17 414 2 712 26 121 170 42 3519 3 2 0 95 March 2, 2026 at 06:59:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 24 2318 201 14 0 4 0 0 11 0 0 0 100 1 25 0 0 127 1 113 0 0 7 0 11 0 0 0 100 2 0 0 0 31 2 20 0 2 0 0 310 0 0 0 100 3 8 0 70 18 2 14 0 2 6 0 325 0 1 0 99 4 1 0 0 81 28 64 0 3 0 0 8 0 0 0 100 5 0 0 7 78 27 61 0 4 0 0 266 0 0 0 100 6 62 0 18 237 108 24 1 2 0 0 298 0 0 0 100 7 3 0 0 27 2 39 1 2 5 0 1402 0 0 0 100 March 2, 2026 at 06:59:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2363 200 114 0 2 0 0 0 0 1 0 99 1 0 0 350 31 3 26 0 1 3 0 14 0 1 0 99 2 0 0 0 66 2 6 0 1 0 0 294 0 0 0 100 3 0 0 35 61 2 7 0 2 3 0 300 0 1 0 99 4 0 0 0 163 51 104 0 0 0 0 8 0 0 0 100 5 0 0 7 75 10 10 0 0 0 0 264 0 0 0 100 6 0 0 18 284 110 22 1 0 0 0 281 0 0 0 100 7 0 0 0 71 3 43 1 0 1 0 1382 0 0 0 100 March 2, 2026 at 06:59:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 200 112 0 0 0 0 21 0 0 0 100 1 0 0 0 24 1 6 0 1 0 0 0 0 0 0 100 2 0 0 0 31 2 10 0 0 0 0 294 0 0 0 100 3 0 0 112 16 2 19 0 1 0 0 300 0 0 0 100 4 0 0 0 123 51 100 0 0 0 0 0 0 0 0 100 5 0 0 7 28 3 6 0 0 0 0 260 0 0 0 100 6 0 0 18 239 110 18 0 0 0 0 276 0 0 0 100 7 0 0 0 27 2 34 1 0 0 0 1381 0 0 0 100 March 2, 2026 at 06:59:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1259 0 62 2606 200 627 14 127 79 58 1627 1 2 0 97 1 688 0 16 296 5 471 10 100 54 46 2158 1 2 0 97 2 436 0 51 266 2 421 14 102 134 37 2648 1 2 0 97 3 1664 0 189 263 2 427 9 82 37 47 2950 3 2 0 95 4 374 0 16 366 47 529 7 92 78 48 2036 1 2 0 97 5 5632 0 138 241 3 422 8 75 120 57 3147 2 3 0 95 6 7446 0 224 529 111 472 6 91 108 46 2555 4 3 0 94 7 10308 0 10 261 3 276 7 49 222 28 1931 4 2 0 94 March 2, 2026 at 06:59:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26838 0 39 2630 202 675 35 123 397 14 2735 11 9 0 80 1 2037 0 177 341 14 625 19 114 149 19 2674 4 2 0 94 2 1086 0 70 335 3 580 10 74 110 26 1734 2 2 0 96 3 426 0 3 419 54 785 23 104 120 13 1767 2 2 0 96 4 557 0 7 263 3 477 12 89 139 7 1225 3 1 0 96 5 232 0 7 244 5 395 10 63 126 6 1636 2 1 0 96 6 2473 0 20 584 142 631 17 84 124 9 1678 2 2 0 96 7 28033 0 14 271 1 382 20 57 354 13 2967 9 5 0 86 March 2, 2026 at 06:59:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 3 2387 206 124 0 0 0 0 9 0 1 0 99 1 0 0 0 88 4 10 0 0 0 0 894 0 0 0 100 2 0 0 42 77 1 6 0 0 2 0 0 0 1 0 99 3 0 0 462 16 2 6 0 0 2 0 0 0 1 0 99 4 0 0 0 84 1 4 0 0 0 0 0 0 0 0 100 5 0 0 7 96 5 24 0 2 0 0 264 0 0 0 100 6 2 0 18 381 152 102 1 0 0 0 268 0 0 0 100 7 0 0 0 82 2 34 1 0 0 0 1083 0 0 0 100 March 2, 2026 at 06:59:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 206 124 0 0 0 0 9 0 0 0 99 1 0 0 0 15 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 15 3 14 0 0 0 0 15 0 0 0 100 5 0 0 7 24 9 16 0 4 0 0 267 0 0 0 100 6 0 0 17 316 152 118 0 1 0 0 271 0 0 0 100 7 0 0 0 12 1 36 1 0 0 0 1081 0 0 0 100 March 2, 2026 at 06:59:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2317 206 118 0 1 0 0 10 0 0 0 99 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 14 1 9 0 1 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 1 0 0 0 100 5 3 0 7 12 3 6 0 0 0 0 262 0 0 0 100 6 0 0 18 307 152 102 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 36 1 1 0 0 1083 0 0 0 100 March 2, 2026 at 06:59:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 674 0 14 2406 208 254 0 34 76 17 844 0 1 0 98 1 36 0 11 159 38 211 2 36 24 19 1688 0 0 0 99 2 83 0 15 99 2 147 1 38 429 27 337 0 3 0 97 3 33 0 4 88 3 107 1 30 24 15 285 0 0 0 99 4 112 0 17 102 15 132 0 26 285 18 1171 0 1 0 99 5 35 0 34 92 7 123 2 25 852 11 494 0 1 0 99 6 2380 0 34 311 117 153 5 27 39 13 993 1 2 0 98 7 734 0 128 60 2 154 2 25 59 17 1094 0 1 0 98 March 2, 2026 at 06:59:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2372 201 228 0 12 65 0 0 0 1 0 99 1 0 0 0 173 53 211 0 18 59 0 894 0 0 0 100 2 0 0 0 75 0 113 0 13 43 0 0 0 0 0 100 3 0 0 0 146 80 250 0 14 64 0 1 0 1 0 99 4 0 0 0 101 22 123 0 15 53 0 20 0 0 0 100 5 0 0 7 54 3 66 0 3 33 0 259 0 0 0 100 6 0 0 25 268 102 111 1 17 78 0 266 0 0 0 100 7 0 0 56 38 2 82 1 7 43 0 745 0 1 0 98 March 2, 2026 at 06:59:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2373 200 112 0 1 0 0 0 0 1 0 99 1 0 0 0 182 53 108 0 0 0 0 894 0 0 0 99 2 0 0 0 77 0 2 0 0 0 0 0 0 0 0 100 3 0 0 455 19 3 10 0 0 2 0 0 0 1 0 99 4 0 0 0 118 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 84 4 10 0 0 0 0 260 0 0 0 100 6 0 0 17 279 102 4 0 1 0 0 266 0 0 0 100 7 0 0 35 76 1 34 1 0 3 0 743 0 1 0 99 March 2, 2026 at 06:59:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 114 0 0 0 0 0 0 0 0 100 1 1 0 0 121 53 126 0 2 0 0 902 0 0 0 100 2 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 3 0 0 0 13 3 10 0 1 0 0 3 0 0 0 100 4 0 0 0 56 24 50 0 1 0 0 30 0 0 0 100 5 0 0 7 22 9 12 0 2 0 0 263 0 0 0 100 6 0 0 18 209 103 4 0 0 0 0 267 0 0 0 100 7 0 0 0 13 2 39 0 0 0 0 746 0 0 0 100 March 2, 2026 at 06:59:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 114 53 110 0 1 0 0 894 0 0 0 100 2 0 0 0 12 0 12 0 1 0 0 0 0 0 0 100 3 0 0 0 13 4 8 0 0 0 0 1 0 0 0 100 4 0 0 0 48 22 44 0 1 0 0 20 0 0 0 100 5 0 0 7 12 3 6 0 0 0 0 259 0 0 0 100 6 0 0 18 209 103 4 0 0 0 0 267 0 0 0 100 7 0 0 0 8 1 32 1 0 0 0 742 0 0 0 100 March 2, 2026 at 06:59:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 100 0 2 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 10 0 0 0 0 5 0 0 0 100 4 1 0 0 63 23 58 0 1 0 0 30 0 0 0 100 5 0 0 7 20 6 16 0 1 0 0 279 0 0 0 100 6 0 0 18 210 102 4 1 1 0 0 270 0 0 0 100 7 0 0 0 11 2 36 1 0 0 0 745 0 0 0 100 March 2, 2026 at 06:59:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 114 0 0 1 0 0 0 0 0 100 1 1 0 0 115 54 113 0 1 2 0 898 0 0 0 100 2 0 0 0 10 0 6 0 1 0 0 11 0 0 0 100 3 0 0 0 19 3 22 0 2 5 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 17 210 102 8 0 0 1 0 266 0 0 0 100 7 0 0 0 9 1 34 0 0 0 0 744 0 0 0 100 March 2, 2026 at 06:59:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 0 0 0 0 100 4 0 0 0 53 22 54 0 1 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 0 0 745 0 0 0 100 March 2, 2026 at 06:59:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 113 53 108 1 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 19 5 14 0 0 0 0 8 0 0 0 100 4 0 0 0 49 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 24 10 14 0 1 0 0 290 0 0 0 100 6 0 0 18 212 102 14 0 0 0 0 279 0 0 0 100 7 0 0 0 10 1 37 0 0 0 0 743 0 0 0 100 March 2, 2026 at 06:59:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 50 22 44 0 0 0 0 20 0 0 0 100 5 0 0 7 18 3 20 0 1 0 0 259 0 0 0 100 6 0 0 18 207 102 2 1 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 0 0 744 0 0 0 100 March 2, 2026 at 06:59:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 110 0 0 1 0 0 0 0 0 100 1 0 0 0 114 54 110 0 1 0 0 894 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 13 4 6 0 0 1 0 0 0 0 0 100 4 0 0 0 50 23 42 0 0 1 0 20 0 0 0 100 5 0 0 7 15 4 8 0 0 1 0 259 0 0 0 100 6 0 0 18 212 102 12 0 1 1 0 266 0 0 0 100 7 0 0 0 10 2 32 1 0 2 0 744 0 0 0 100 March 2, 2026 at 06:59:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 114 0 0 2 0 0 0 0 0 100 1 0 0 0 113 53 110 0 0 2 0 893 0 0 0 100 2 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 3 0 0 0 14 4 10 0 0 2 0 1 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 0 0 18 210 102 8 0 0 3 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 0 0 745 0 0 0 100 March 2, 2026 at 06:59:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 18 211 103 6 0 0 0 0 267 0 0 0 100 7 0 0 0 14 1 44 1 1 1 0 743 0 0 0 100 March 2, 2026 at 06:59:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 124 0 1 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 15 3 10 0 0 0 0 5 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 23 9 14 0 0 0 0 267 0 0 0 100 6 0 0 17 218 105 18 1 0 0 0 282 0 0 0 100 7 0 0 0 15 2 41 1 0 1 0 746 0 0 0 100 March 2, 2026 at 06:59:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 201 112 0 0 0 0 21 0 0 0 100 1 0 0 0 114 53 108 1 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 6 0 0 0 0 259 0 0 0 100 6 0 0 17 209 103 4 0 0 0 0 267 0 0 0 100 7 0 0 0 7 1 34 0 1 0 0 742 0 0 0 100 March 2, 2026 at 07:00:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 118 53 120 0 1 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 114 0 0 0 0 0 0 0 0 100 1 0 0 0 114 53 110 0 1 0 0 894 0 0 0 100 2 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 19 3 20 0 1 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 18 211 103 8 0 0 0 0 267 0 0 0 100 7 0 0 0 10 1 34 1 0 0 0 744 0 0 0 100 March 2, 2026 at 07:00:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 2 0 17 210 102 2 3 0 0 0 405 1 0 0 99 7 0 0 0 10 2 34 1 0 1 0 745 0 0 0 100 March 2, 2026 at 07:00:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 114 0 0 1 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 893 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 15 3 12 0 0 0 0 5 0 0 0 100 4 0 0 0 53 22 52 0 1 0 0 20 0 0 0 100 5 0 0 7 23 10 12 0 1 0 0 266 0 0 0 100 6 0 0 17 217 104 18 0 0 0 0 283 0 0 0 100 7 0 0 0 13 1 39 1 0 0 0 743 0 0 0 100 March 2, 2026 at 07:00:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 112 53 108 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 50 22 44 0 1 0 0 20 0 0 0 100 5 0 0 7 18 3 20 0 1 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2301 200 110 0 0 1 0 0 0 0 0 100 1 0 0 0 115 54 108 0 0 1 0 894 0 0 0 100 2 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 14 4 6 0 0 1 0 0 0 0 0 100 4 0 0 0 51 23 42 0 0 1 0 20 0 0 0 100 5 0 0 7 14 4 6 0 0 1 0 259 0 0 0 100 6 0 0 21 210 103 6 0 1 0 0 267 0 0 0 100 7 0 0 0 11 2 32 1 0 1 0 743 0 0 0 100 March 2, 2026 at 07:00:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 116 0 0 0 0 0 0 0 0 100 1 0 0 0 115 54 112 0 1 0 0 899 0 0 0 100 2 0 0 0 10 0 6 0 1 0 0 11 0 0 0 100 3 0 0 0 13 4 6 0 0 0 0 1 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 3 10 0 0 0 0 259 0 0 0 100 6 0 0 18 215 102 18 0 1 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 114 54 110 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 18 209 102 4 0 0 0 0 266 0 0 0 100 7 0 0 0 12 1 44 0 1 0 0 742 0 0 0 100 March 2, 2026 at 07:00:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 114 54 110 0 0 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 8 0 0 0 0 5 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 23 9 14 0 0 0 0 267 0 0 0 100 6 0 0 18 218 105 18 0 0 0 0 283 0 0 0 100 7 0 0 0 13 2 39 1 0 0 0 746 0 0 0 100 March 2, 2026 at 07:00:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 200 122 0 1 0 0 0 0 0 0 100 1 0 0 0 115 54 112 1 1 0 0 893 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 6 0 0 0 0 259 0 0 0 100 6 0 0 18 211 104 6 0 0 0 0 268 0 0 0 100 7 0 0 0 10 1 34 1 0 1 0 743 0 0 0 100 March 2, 2026 at 07:00:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 114 0 0 1 0 0 0 0 0 100 1 0 0 0 120 54 122 0 1 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 0 0 18 208 102 2 1 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 114 0 0 0 0 0 0 0 0 100 1 0 0 0 114 54 110 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 17 209 102 6 0 0 0 0 266 0 0 0 100 7 0 0 0 9 1 34 1 0 0 0 744 0 0 0 100 March 2, 2026 at 07:00:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 116 54 112 0 0 0 0 895 0 0 0 100 2 0 0 0 12 0 14 0 1 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 116 54 110 1 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 1 0 0 0 0 0 100 3 0 0 0 19 2 20 0 1 1 0 5 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 22 8 12 1 1 0 0 264 0 0 0 100 6 0 0 18 219 106 16 0 0 0 0 281 0 0 0 100 7 0 0 0 10 1 37 0 0 0 0 742 0 0 0 100 March 2, 2026 at 07:00:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 114 54 110 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 259 0 0 0 100 6 0 0 18 208 102 2 1 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 745 0 0 0 100 March 2, 2026 at 07:00:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 1 0 0 0 0 0 100 1 0 0 0 116 55 112 0 1 0 0 894 0 0 0 100 2 0 0 0 11 1 4 0 0 1 0 0 0 0 0 100 3 0 0 0 13 3 6 0 0 1 0 0 0 0 0 100 4 0 0 0 55 23 52 0 1 1 0 20 0 0 0 100 5 0 0 7 13 4 6 0 0 1 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 1 0 266 0 0 0 100 7 0 0 0 9 2 32 0 0 1 0 744 0 0 0 100 March 2, 2026 at 07:00:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 118 0 0 0 0 0 0 0 0 100 1 0 0 0 116 55 112 0 1 0 0 894 0 0 0 100 2 0 0 0 12 2 7 0 2 0 0 0 0 0 0 100 3 0 0 0 14 4 10 0 1 0 0 1 0 0 0 100 4 0 0 0 52 23 46 0 0 1 0 20 0 0 0 100 5 0 0 7 20 4 20 0 1 0 0 259 0 0 0 100 6 0 0 18 211 103 8 0 0 0 0 266 0 0 0 100 7 0 0 0 12 3 36 1 0 2 0 745 0 0 0 100 March 2, 2026 at 07:00:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 114 54 110 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 18 209 103 4 0 0 0 0 267 0 0 0 100 7 0 0 0 8 1 32 1 0 0 0 742 0 0 0 100 March 2, 2026 at 07:00:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 117 0 0 0 0 0 0 0 0 100 1 0 0 0 114 54 110 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 8 0 0 0 0 5 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 27 13 16 0 0 0 0 266 0 0 0 100 6 0 0 18 223 105 34 1 1 0 0 285 0 0 0 100 7 0 0 0 14 2 40 0 0 0 0 746 0 0 0 100 March 2, 2026 at 07:00:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 112 0 0 0 0 21 0 0 0 100 1 0 0 0 116 54 110 1 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 46 21 40 0 0 0 0 19 0 0 0 100 5 0 0 7 12 3 6 0 0 0 0 259 0 0 0 100 6 0 0 18 211 103 6 0 0 0 0 267 0 0 0 100 7 0 0 0 13 1 44 1 2 1 0 743 0 0 0 100 March 2, 2026 at 07:00:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 24 9 18 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 143 68 140 0 1 0 0 29 0 0 0 100 5 0 0 7 14 3 12 0 0 0 0 277 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 745 0 0 0 100 March 2, 2026 at 07:00:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 201 126 0 1 0 0 0 0 0 0 100 1 0 0 0 16 5 12 0 0 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 148 72 142 0 0 0 0 20 0 0 0 100 5 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 6 0 0 18 211 103 8 0 0 0 0 267 0 0 0 100 7 0 0 0 11 1 36 0 0 0 0 743 0 0 0 100 March 2, 2026 at 07:00:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2303 200 114 0 0 1 0 0 0 0 0 100 1 0 0 0 19 4 20 0 1 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 118 57 110 0 0 0 0 20 0 0 0 100 5 0 0 7 44 18 40 0 1 0 0 259 0 0 0 100 6 0 0 18 207 102 2 1 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 0 0 746 0 0 0 100 March 2, 2026 at 07:00:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 114 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 893 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 8 0 0 0 0 5 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 123 62 112 0 1 0 0 264 0 0 0 100 6 0 0 18 215 104 16 0 0 0 0 281 0 0 0 100 7 0 0 0 13 1 39 1 0 0 0 742 0 0 0 100 March 2, 2026 at 07:00:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 16 4 12 0 0 0 0 894 0 0 0 100 2 0 0 0 15 0 16 0 1 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 0 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 1 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2301 200 110 0 0 1 0 0 0 0 0 100 1 0 0 0 17 5 10 0 0 1 0 894 0 0 0 100 2 0 0 0 12 1 4 0 0 1 0 0 0 0 0 100 3 0 0 0 17 3 16 0 1 1 0 0 0 0 0 100 4 0 0 0 51 23 42 0 0 1 0 20 0 0 0 100 5 0 0 7 114 54 106 0 0 1 0 259 0 0 0 100 6 0 0 21 210 103 6 0 1 0 0 267 0 0 0 100 7 0 0 0 11 2 32 1 0 2 0 744 0 0 0 100 March 2, 2026 at 07:00:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 114 0 0 0 0 0 0 0 0 100 1 0 0 0 15 4 10 1 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 4 0 0 0 49 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 0 0 0 259 0 0 0 100 6 0 0 18 210 102 6 1 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 18 6 14 0 0 0 0 898 0 0 0 100 2 0 0 0 8 0 4 0 0 0 0 1 0 0 0 100 3 0 0 0 11 2 6 0 0 1 0 0 0 0 0 100 4 0 0 0 51 22 51 0 1 1 0 20 0 0 0 100 5 0 0 7 116 55 112 0 0 0 0 262 0 0 0 100 6 0 0 18 208 102 4 0 0 0 0 267 0 0 0 100 7 0 0 0 8 1 32 1 0 0 0 742 0 0 0 100 March 2, 2026 at 07:00:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 8 0 0 0 0 5 0 0 0 100 4 0 0 0 50 22 44 0 0 0 0 20 0 0 0 100 5 0 0 7 128 59 124 0 1 0 0 263 0 0 0 100 6 0 0 18 216 105 14 0 0 0 0 280 0 0 0 100 7 0 0 0 14 2 42 0 0 0 0 746 0 0 0 100 March 2, 2026 at 07:00:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2305 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 47 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 1 0 0 259 0 0 0 100 6 0 0 17 213 105 8 0 0 0 0 269 0 0 0 100 7 0 0 0 7 1 32 1 0 0 0 743 0 0 0 100 March 2, 2026 at 07:00:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 114 53 110 0 0 0 0 259 0 0 0 100 6 0 0 18 215 103 16 1 1 0 0 267 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 745 0 0 0 100 March 2, 2026 at 07:00:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 116 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 114 54 110 0 0 0 0 260 0 0 0 100 6 0 0 18 211 102 8 0 0 0 0 266 0 0 0 100 7 0 0 0 16 1 46 1 1 0 0 742 0 0 0 100 March 2, 2026 at 07:00:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 49 22 42 1 0 0 0 20 0 0 0 100 5 0 0 7 114 55 108 0 0 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 1 0 746 0 0 0 100 March 2, 2026 at 07:00:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 124 0 1 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 893 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 4 0 0 0 51 22 48 0 1 0 0 29 0 0 0 100 5 0 0 7 119 58 112 0 0 0 0 267 0 0 0 100 6 0 0 18 215 104 10 0 0 0 0 273 0 0 0 100 7 0 0 0 13 1 39 1 0 2 0 743 0 0 0 100 March 2, 2026 at 07:00:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 20 4 22 1 1 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 50 23 44 0 0 0 0 21 0 0 0 100 5 0 0 7 112 53 108 0 0 0 0 259 0 0 0 100 6 0 0 18 208 102 2 1 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 2 0 744 0 0 0 100 March 2, 2026 at 07:00:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 110 0 0 1 0 0 0 0 0 100 1 0 0 0 16 5 10 0 0 1 0 894 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 11 3 4 0 0 1 0 0 0 0 0 100 4 0 0 0 50 23 44 0 1 0 0 20 0 0 0 100 5 0 0 7 113 54 106 0 0 1 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 1 0 266 0 0 0 100 7 0 0 0 9 2 32 0 0 1 0 744 0 0 0 100 March 2, 2026 at 07:00:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 116 0 0 0 0 0 0 0 0 100 1 0 0 0 16 4 12 0 0 0 0 893 0 0 0 100 2 0 0 0 13 0 14 0 1 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 0 0 0 259 0 0 0 100 6 0 0 18 209 102 6 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 745 0 0 0 100 March 2, 2026 at 07:00:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 1 0 0 0 0 0 100 3 0 0 0 14 2 16 0 1 1 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 114 54 110 0 0 0 0 260 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 9 1 32 2 0 2 0 743 0 0 0 100 March 2, 2026 at 07:00:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 114 0 0 1 0 0 0 0 0 100 1 0 0 0 15 4 10 1 0 0 0 895 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 58 24 58 0 0 0 0 36 0 0 0 100 5 0 0 7 127 62 116 0 0 0 0 290 0 0 0 100 6 0 0 18 213 103 8 1 0 0 0 272 0 0 0 100 7 0 0 0 13 2 41 0 0 0 0 744 0 0 0 100 March 2, 2026 at 07:00:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 201 112 0 0 0 0 21 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 893 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 55 22 54 0 1 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 1 0 0 259 0 0 0 100 6 0 0 17 209 103 4 0 0 0 0 267 0 0 0 100 7 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 March 2, 2026 at 07:00:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 895 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 50 22 44 0 0 0 0 20 0 0 0 100 5 0 0 7 118 53 120 0 1 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 0 0 745 0 0 0 100 March 2, 2026 at 07:00:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 114 0 0 1 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 893 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 114 54 110 0 0 0 0 260 0 0 0 100 6 0 0 18 209 102 6 0 0 0 0 266 0 0 0 100 7 0 0 0 10 1 34 1 0 1 0 742 0 0 0 100 March 2, 2026 at 07:00:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 50 23 44 0 0 0 0 21 0 0 0 100 5 0 0 7 114 53 110 0 0 1 0 259 0 0 0 100 6 0 0 18 213 102 14 1 1 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 746 0 0 0 100 March 2, 2026 at 07:00:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 114 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 57 24 56 0 0 0 0 34 0 0 0 100 5 0 0 7 120 59 112 0 0 1 0 266 0 0 0 100 6 0 0 18 213 102 8 0 0 0 0 271 0 0 0 100 7 0 0 0 16 1 49 0 1 0 0 743 0 0 0 100 March 2, 2026 at 07:00:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 0 0 0 259 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 10 2 34 1 0 1 0 744 0 0 0 100 March 2, 2026 at 07:00:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2307 200 122 0 1 1 0 0 0 0 0 100 1 0 0 0 17 5 10 0 0 1 0 894 0 0 0 100 2 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 12 3 4 0 0 1 0 0 0 0 0 100 4 0 0 0 51 23 42 0 0 1 0 20 0 0 0 100 5 0 0 7 114 54 106 0 0 1 0 259 0 0 0 100 6 0 0 21 208 102 4 0 1 0 0 266 0 0 0 100 7 0 0 0 13 2 34 1 0 1 0 744 0 0 0 100 March 2, 2026 at 07:00:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 116 0 0 2 0 0 0 0 0 100 1 0 0 0 19 4 22 0 1 0 0 894 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 4 0 0 0 50 23 44 0 0 0 0 21 0 0 0 100 5 0 0 7 112 53 108 0 0 0 0 259 0 0 0 100 6 0 0 18 210 102 6 1 0 0 0 266 0 0 0 100 7 0 0 0 9 2 34 0 0 0 0 744 0 0 0 100 March 2, 2026 at 07:00:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 114 54 110 0 0 0 0 260 0 0 0 100 6 0 0 18 207 102 2 0 0 0 0 266 0 0 0 100 7 0 0 0 8 1 32 1 0 0 0 743 0 0 0 100 March 2, 2026 at 07:00:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 200 114 0 0 0 0 0 0 0 0 100 1 0 0 0 16 4 12 0 0 1 0 895 0 0 0 100 2 0 0 0 12 0 14 0 1 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 57 24 56 0 0 0 0 33 0 0 0 100 5 0 0 7 124 62 114 0 0 1 0 267 0 0 0 100 6 0 0 18 213 103 10 0 0 0 0 275 0 0 0 100 7 0 0 0 13 2 41 0 0 1 0 744 0 0 0 100 March 2, 2026 at 07:00:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 894 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 15 2 16 0 1 0 0 0 0 0 0 100 4 0 0 0 48 22 42 0 0 0 0 20 0 0 0 100 5 0 0 7 112 53 108 0 1 0 0 259 0 0 0 100 6 0 0 18 209 103 4 0 0 0 0 267 0 0 0 100 7 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 March 2, 2026 at 07:00:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 4 2437 200 385 0 3 2 1 96 0 1 0 99 1 25 0 0 56 6 84 0 1 7 0 1167 0 1 0 99 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 1 0 0 0 100 4 0 0 0 30 12 24 0 0 0 0 23 0 0 0 100 5 0 0 7 381 312 124 0 0 16 0 290 0 0 0 100 6 1867 0 22 221 103 18 4 2 0 0 398 0 1 0 99 7 13 0 0 154 3 306 1 2 10 0 796 0 0 0 99 March 2, 2026 at 07:00:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2348 201 204 0 8 51 0 0 0 1 0 99 1 1 0 0 69 6 115 0 12 61 0 930 0 0 0 99 2 0 0 0 49 0 82 0 4 55 0 0 0 0 0 100 3 0 0 0 121 73 223 0 13 36 0 0 0 0 0 100 4 0 0 0 46 2 79 0 18 33 0 2 0 0 0 100 5 0 0 7 173 66 202 0 9 41 0 260 0 0 0 100 6 0 0 17 253 102 94 0 12 42 0 269 0 0 0 100 7 0 0 0 33 1 82 0 9 25 0 745 0 0 0 100 March 2, 2026 at 07:00:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2438 205 346 11 5 3 0 77 0 1 0 99 1 0 0 0 22 6 16 0 0 0 0 905 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 2 6 0 0 0 0 2 0 0 0 100 5 0 0 7 383 302 161 5 4 21 0 377 0 0 0 100 6 0 0 18 208 102 4 0 0 0 0 266 0 0 0 100 7 633 0 0 186 2 340 3 3 4 0 782 0 1 0 99 March 2, 2026 at 07:00:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2336 206 166 0 0 1 0 33 0 0 0 100 1 6 0 0 28 5 30 0 0 1 0 939 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 12 0 1 0 0 9 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 7 184 122 112 0 1 1 0 262 0 0 0 100 6 0 0 18 209 102 6 0 0 0 0 266 0 0 0 100 7 0 0 0 24 1 62 0 0 3 0 743 0 0 0 100