March 2, 2026 at 06:52:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1045 0 145 4439 140 5903 60 366 1284 44 4893 11 9 0 80 1 1040 0 54 1282 20 4130 19 527 1524 56 8182 5 7 0 88 2 794 0 73 1376 26 2712 15 353 1369 49 5133 3 6 0 91 3 1017 0 1299 1331 528 3170 31 381 1305 31 8032 19 8 0 73 4 1154 0 89 1355 24 3833 19 387 1491 54 7717 3 8 0 89 5 883 0 73 4202 3176 3203 18 312 1547 33 8609 3 8 0 90 6 728 0 74 1322 21 4168 17 335 1387 65 10471 3 9 0 88 7 809 0 33 2310 18 7021 32 369 1357 28 7262 5 8 0 87 March 2, 2026 at 06:52:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5524 0 62 2395 131 700 14 159 1251 72 2669 4 31 0 65 1 2270 0 10 449 1 892 18 164 1783 67 1937 5 2 0 92 2 6119 0 26 342 1 752 17 157 1570 64 2930 4 5 0 90 3 4433 0 20 543 235 799 24 162 1619 43 2079 8 8 0 84 4 8206 0 48 342 3 829 13 200 2887 95 2689 3 5 0 92 5 11053 0 81 456 58 807 32 211 1927 84 5324 18 10 0 72 6 4763 0 30 458 7 823 12 193 1773 48 1856 2 6 0 92 7 4173 0 70 388 56 580 25 164 1739 64 3254 18 11 0 71 March 2, 2026 at 06:52:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2170 144 184 8 1 39 0 280 0 16 0 84 1 0 0 0 43 1 49 11 17 72 0 25 0 12 0 88 2 0 0 0 25 0 8 8 3 67 0 0 0 15 0 85 3 0 0 0 105 75 46 7 10 78 0 22 0 13 0 87 4 30 0 0 29 3 38 7 4 77 0 1058 0 16 0 84 5 0 0 10 324 109 278 1 42 226 0 259 0 4 0 96 6 0 0 0 33 2 13 8 4 74 0 257 0 15 0 85 7 40 0 17 253 106 136 1 31 282 0 577 0 4 0 96 March 2, 2026 at 06:52:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2197 100 238 5 87 550 0 0 0 5 0 95 1 27 0 0 126 9 319 2 99 620 0 1636 0 2 0 98 2 0 0 0 169 1 313 4 86 585 0 1 0 4 0 96 3 0 0 0 432 332 910 3 95 591 0 294 0 2 0 98 4 0 0 0 101 3 248 4 91 645 0 0 0 4 0 96 5 0 0 10 303 103 246 3 85 634 0 259 0 3 0 97 6 0 0 2 106 2 257 5 86 634 0 2 0 4 0 96 7 0 0 17 400 148 347 3 90 568 0 266 0 4 0 96 March 2, 2026 at 06:52:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2191 100 352 0 85 556 0 0 0 2 0 98 1 0 0 0 107 3 294 0 89 622 0 1662 0 2 0 98 2 0 0 0 101 2 248 0 83 577 0 7 0 1 0 99 3 0 0 0 429 334 906 0 90 526 0 294 0 1 0 99 4 0 0 0 102 2 260 0 100 557 0 8 0 2 0 98 5 0 0 10 303 109 242 0 84 545 0 258 0 1 0 99 6 0 0 0 104 1 258 0 87 627 0 0 0 2 0 98 7 0 0 17 415 154 374 0 88 547 0 266 0 1 0 99 March 2, 2026 at 06:52:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2445 100 822 1 76 566 0 0 0 2 0 98 1 0 0 0 211 42 386 0 74 739 0 1627 0 2 0 98 2 0 0 0 115 0 250 1 65 578 0 0 0 1 0 99 3 0 0 0 357 252 233 0 52 572 0 294 0 1 0 99 4 0 0 0 109 2 243 0 68 578 0 0 0 1 0 99 5 0 0 10 307 103 249 0 78 577 0 259 0 1 0 99 6 0 0 0 121 4 263 2 69 644 0 3 0 1 0 99 7 0 0 17 338 115 277 1 55 554 0 266 0 1 0 99 March 2, 2026 at 06:52:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3142 0 0 2460 102 825 127 121 216 12 1796 12 3 0 85 1 2752 0 0 384 8 692 85 101 150 14 3292 11 2 0 87 2 2495 0 0 406 25 738 166 105 149 4 1812 14 2 0 84 3 5259 0 0 362 7 991 193 124 220 10 2909 19 4 0 77 4 3262 0 0 332 7 676 136 117 213 4 2279 18 4 0 78 5 4428 0 12 460 110 413 59 72 106 15 2171 27 9 0 64 6 1909 0 1 272 9 445 45 79 133 14 2214 23 2 0 75 7 1313 0 415 459 105 587 58 73 122 14 2445 12 2 0 85 March 2, 2026 at 06:52:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2204 101 288 0 32 363 0 2 0 2 0 98 1 2 0 25 185 8 383 3 50 293 0 1718 0 1 0 99 2 0 0 0 166 2 328 0 45 494 0 1 0 1 0 99 3 0 0 0 225 115 223 0 50 402 0 307 0 1 0 99 4 3 0 0 114 2 219 1 47 361 0 54 1 1 0 98 5 2 0 3 394 148 287 0 38 330 0 8 0 1 0 99 6 15 0 0 103 4 187 0 41 372 0 20 0 1 0 99 7 18 0 38 301 107 186 1 26 342 0 624 0 1 0 99 March 2, 2026 at 06:52:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 110 0 0 0 0 1 0 1 0 99 1 7 0 0 112 53 136 1 0 4 0 1718 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 6 0 294 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 6 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 7 0 0 24 227 112 24 0 0 0 0 533 0 0 0 100 March 2, 2026 at 06:52:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 106 0 2 0 0 1 0 1 0 99 1 0 0 0 132 53 158 1 4 1 0 1719 0 0 0 99 2 0 0 0 11 2 6 0 0 0 0 6 0 0 0 100 3 0 0 1 11 1 10 0 1 0 0 297 0 0 0 100 4 0 0 0 14 2 12 0 1 0 0 13 0 0 0 100 5 0 0 3 216 109 2 0 0 0 0 0 0 0 0 100 6 1 0 3 15 2 12 0 1 0 0 12 0 0 0 100 7 0 0 24 232 112 30 0 0 0 0 535 0 0 0 100 March 2, 2026 at 06:52:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 0 0 1 0 99 1 0 0 0 113 53 138 0 0 5 0 1714 0 0 0 99 2 0 0 0 12 0 10 0 1 0 0 0 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 294 0 0 0 100 4 0 0 0 9 2 2 0 0 0 0 0 0 0 0 100 5 0 0 3 211 103 4 0 0 0 0 1 0 0 0 100 6 0 0 0 12 1 8 0 2 0 0 0 0 0 0 100 7 0 0 24 231 114 28 0 0 0 0 534 0 0 0 100 March 2, 2026 at 06:52:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 237 0 17 2172 101 255 2 29 16 15 577 0 2 0 98 1 75 0 7 70 7 97 3 27 17 2 961 0 0 0 99 2 191 0 0 161 51 189 2 23 19 3 305 0 0 0 99 3 44 0 14 65 2 125 3 21 26 3 1794 0 1 0 98 4 20 0 0 51 4 72 1 16 18 3 210 0 1 0 99 5 5226 0 18 270 105 102 5 15 36 9 666 4 1 0 95 6 741 0 2 74 5 116 0 19 45 4 413 0 1 0 99 7 424 0 35 272 108 137 7 18 43 9 951 0 1 0 99 March 2, 2026 at 06:52:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2107 100 103 0 1 0 0 0 0 1 0 99 1 0 0 0 26 2 22 0 1 17 0 592 0 0 0 100 2 44 0 0 123 55 114 0 0 1 0 7 0 0 0 100 3 2 0 0 21 2 48 1 2 6 0 1327 0 0 0 100 4 0 0 0 12 1 4 0 1 4 0 0 0 0 0 100 5 0 0 10 213 102 6 0 2 0 0 0 0 0 0 100 6 0 0 0 16 2 8 0 0 0 0 0 0 0 0 100 7 0 0 24 218 106 12 0 0 0 0 572 0 0 0 100 March 2, 2026 at 06:52:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 119 2104 100 99 0 3 0 0 0 0 1 0 99 1 0 0 0 37 2 14 0 1 10 0 600 0 0 0 100 2 0 0 0 38 8 14 0 0 0 0 8 0 0 0 100 3 0 0 0 129 49 135 1 3 4 0 1320 0 0 0 99 4 0 0 0 33 4 16 0 1 2 0 3 0 0 0 100 5 0 0 3 230 102 6 0 0 0 0 0 0 0 0 100 6 0 0 0 33 3 12 0 1 0 0 2 0 0 0 100 7 0 0 24 233 106 14 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:52:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2105 100 108 0 1 0 0 0 0 1 0 99 1 0 0 0 19 2 10 0 0 15 0 605 0 0 0 100 2 0 0 0 17 5 10 0 0 0 0 8 0 0 0 100 3 0 0 0 113 52 136 1 0 4 0 1322 0 0 0 100 4 0 0 0 15 3 12 0 0 0 0 10 0 0 0 100 5 0 0 3 219 108 6 0 1 0 0 8 0 0 0 100 6 4 0 0 19 2 17 0 1 0 0 9 0 0 0 100 7 0 0 24 218 106 12 0 0 0 0 526 0 0 0 100 March 2, 2026 at 06:52:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 211 0 0 2865 104 1380 31 243 22 0 6199 6 3 0 91 1 319 0 0 816 5 1505 53 273 21 1 7838 7 2 0 91 2 232 0 0 682 7 1127 21 187 2 2 5084 6 2 0 93 3 93 0 0 722 12 1352 43 292 34 1 9560 6 2 0 91 4 130 0 0 640 8 1125 24 234 15 1 5487 5 2 0 93 5 162 0 3 823 105 1020 11 156 6 0 4004 5 2 0 94 6 97 0 0 675 41 1159 32 240 4 1 6599 6 2 0 93 7 124 0 388 719 109 985 21 131 15 0 5214 6 2 0 92 March 2, 2026 at 06:52:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 2117 107 122 0 1 0 0 10 0 1 0 99 1 0 0 0 18 3 18 0 5 3 0 600 0 0 0 100 2 0 0 0 11 1 10 0 4 0 0 4 0 0 0 100 3 0 0 0 15 3 42 1 0 3 0 1332 0 0 0 100 4 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 211 101 6 0 0 0 0 13 0 0 0 100 6 0 0 0 126 52 124 0 1 0 0 0 0 0 0 100 7 0 0 24 219 108 16 0 0 0 0 526 0 0 0 100 March 2, 2026 at 06:52:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 101 0 0 2223 104 300 1 41 248 18 171 0 1 0 99 1 666 0 2 120 2 211 4 50 253 12 1579 1 1 0 98 2 58 0 0 100 1 175 1 35 233 9 114 0 1 0 99 3 9 0 0 191 76 218 3 36 186 5 1450 0 1 0 99 4 14 0 0 103 1 156 0 34 195 0 48 0 1 0 99 5 0 0 3 285 102 129 1 29 197 0 16 0 1 0 99 6 8 0 0 230 55 307 1 30 212 1 107 0 1 0 99 7 2619 0 138 359 107 324 3 29 141 10 952 1 1 0 98 March 2, 2026 at 06:52:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 104 110 0 0 0 0 5 0 1 0 99 1 0 0 0 11 3 6 0 0 3 0 594 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 34 2 0 6 0 1422 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 5 0 0 3 210 101 4 0 0 0 0 10 0 0 0 100 6 0 0 0 123 52 118 0 1 0 0 0 0 0 0 100 7 0 0 24 221 107 24 0 2 0 0 526 0 0 0 100 March 2, 2026 at 06:52:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2122 108 126 0 2 0 0 327 0 1 0 99 1 0 0 0 17 4 12 1 0 10 0 607 0 0 0 100 2 0 0 0 12 0 14 0 1 0 0 7 0 0 0 100 3 0 0 0 12 3 38 0 0 9 0 1440 0 0 0 100 4 0 0 0 13 1 14 0 1 0 0 22 0 0 0 100 5 0 0 3 216 106 6 0 1 0 0 8 0 0 0 100 6 0 0 0 125 57 120 0 0 0 0 10 0 0 0 100 7 0 0 24 224 107 18 0 2 0 0 526 0 0 0 100 March 2, 2026 at 06:52:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 0 0 1 0 99 1 0 0 0 22 7 18 1 0 9 0 618 0 0 0 100 2 0 0 0 7 0 4 0 0 0 0 18 0 0 0 100 3 0 0 0 10 2 34 1 0 9 0 1419 0 0 0 100 4 0 0 0 8 1 4 0 0 0 0 10 0 0 0 100 5 0 0 3 209 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 117 53 110 0 2 0 0 0 0 0 0 100 7 0 0 24 214 106 10 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:52:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 271 0 3 2228 101 358 9 41 5 0 1993 2 1 0 97 1 219 0 0 63 8 86 2 17 7 1 1676 2 1 0 97 2 92 0 0 117 3 288 4 59 4 1 1933 1 0 0 98 3 7 0 0 117 4 268 7 46 14 0 3203 1 1 0 98 4 82 0 0 109 3 233 11 47 1 0 2460 2 1 0 97 5 141 0 7 292 102 259 10 35 10 0 1352 1 0 0 98 6 374 0 0 223 57 398 9 52 7 1 2042 1 1 0 98 7 29 0 112 315 107 424 6 44 12 0 2547 1 1 0 98 March 2, 2026 at 06:52:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2168 100 232 0 24 135 0 0 0 1 0 99 1 0 0 0 63 3 107 0 19 127 0 608 0 0 0 99 2 0 0 0 67 6 118 0 14 138 0 9 0 0 0 100 3 0 0 0 134 76 277 2 21 114 0 1424 0 1 0 99 4 0 0 0 81 1 153 0 24 160 0 0 0 0 0 100 5 0 0 3 271 101 129 0 22 127 0 0 0 0 0 100 6 0 0 0 184 53 247 0 25 126 0 0 0 0 0 100 7 0 0 24 258 106 108 0 16 117 0 527 0 0 0 100 March 2, 2026 at 06:52:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2116 101 122 0 7 6 0 13 0 1 0 99 1 0 0 9 17 2 12 1 4 8 0 594 0 1 0 99 2 0 0 0 30 7 33 0 6 15 0 38 0 0 0 100 3 0 0 0 30 5 58 1 3 5 0 1456 0 0 0 99 4 14 0 0 23 2 20 0 4 3 0 28 0 0 0 100 5 0 0 3 222 102 21 0 1 8 2 83 0 0 0 100 6 0 0 0 125 54 125 0 9 8 0 21 0 0 0 100 7 0 0 24 226 106 31 0 4 6 2 592 0 0 0 100 March 2, 2026 at 06:52:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 117 0 1 0 0 0 0 1 0 99 1 0 0 7 11 2 6 0 1 2 0 598 0 0 0 100 2 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 3 8 0 0 32 9 62 1 1 3 0 1375 0 0 0 99 4 0 0 0 20 5 18 0 0 0 0 15 0 0 0 100 5 0 0 3 215 106 4 0 0 0 0 6 0 0 0 100 6 0 0 0 118 53 112 0 0 0 0 7 0 0 0 100 7 0 0 24 217 106 14 0 1 0 0 525 0 0 0 100 March 2, 2026 at 06:52:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2105 100 111 0 0 0 0 0 0 1 0 99 1 0 0 0 29 2 6 0 0 1 0 601 0 0 0 100 2 1 0 7 24 1 4 0 1 0 0 1 0 0 0 100 3 0 0 0 41 8 48 1 0 4 0 1345 0 0 0 99 4 0 0 0 35 4 18 0 1 0 0 6 0 0 0 100 5 0 0 3 224 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 136 54 112 0 1 0 0 2 0 0 0 100 7 23 0 24 232 107 12 0 0 0 0 532 0 0 0 100 March 2, 2026 at 06:52:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 102 116 0 1 0 0 3 0 1 0 99 1 0 0 0 11 2 4 1 0 4 0 601 0 0 0 100 2 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 34 12 56 1 1 4 0 1351 0 0 0 99 4 0 0 0 10 1 6 0 1 0 0 6 0 0 0 100 5 0 0 3 208 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 116 53 110 0 0 0 0 0 0 0 0 100 7 0 0 24 216 106 12 0 0 0 0 526 0 0 0 100 March 2, 2026 at 06:52:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 0 2973 108 1594 37 273 242 0 5672 6 3 0 90 1 13 0 0 794 28 1414 34 298 290 0 8393 6 3 0 91 2 34 0 0 752 3 1304 23 200 252 0 4652 5 2 0 92 3 15 0 0 848 92 1479 34 280 229 0 9256 6 3 0 91 4 42 0 0 817 6 1509 33 285 305 0 5457 6 3 0 91 5 25 0 3 830 104 1086 18 194 285 1 4165 5 2 0 93 6 12 0 0 681 27 1180 27 255 259 0 7104 6 2 0 92 7 28 0 360 734 109 1042 16 163 191 0 5181 5 2 0 93 March 2, 2026 at 06:52:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 2122 107 122 0 1 0 0 12 0 1 0 99 1 0 0 0 114 53 110 0 1 8 0 605 0 0 0 100 2 0 0 0 11 0 12 0 1 0 0 1 0 0 0 100 3 0 0 0 12 2 38 1 1 8 0 1356 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 5 0 0 3 210 102 2 0 0 0 0 2 0 0 0 100 6 0 0 0 15 3 10 0 2 0 0 0 0 0 0 100 7 8 0 24 213 106 10 0 0 0 0 570 0 0 0 100 March 2, 2026 at 06:52:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2119 107 126 0 1 0 0 8 0 1 0 99 1 0 0 0 109 52 104 0 0 5 0 607 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 12 2 38 1 0 7 0 1347 0 0 0 100 4 0 0 0 13 3 10 0 0 0 0 7 0 0 0 100 5 0 0 3 216 106 6 0 1 0 0 8 0 0 0 100 6 0 0 0 22 4 20 0 0 0 0 12 0 0 0 100 7 0 0 24 220 107 16 1 0 1 0 526 0 0 0 100 March 2, 2026 at 06:52:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 106 120 0 0 0 0 8 0 1 0 99 1 0 0 0 109 52 104 0 0 4 0 592 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 19 2 50 2 1 3 0 1348 0 0 0 100 4 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 209 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 17 3 12 0 0 0 0 0 0 0 0 100 7 0 0 24 213 106 10 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:52:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2129 111 130 0 0 1 0 341 0 1 0 99 1 0 0 0 116 53 112 1 2 0 0 604 0 0 0 100 2 0 0 0 8 1 2 0 0 1 0 3 0 0 0 100 3 0 0 0 16 4 38 1 1 1 0 1339 0 0 0 100 4 0 0 0 16 2 14 0 1 1 0 0 0 0 0 100 5 0 0 3 208 101 0 0 0 1 0 0 0 0 0 100 6 0 0 0 25 7 20 0 0 1 0 9 0 0 0 100 7 0 0 24 215 106 12 0 0 1 0 525 0 0 0 100 March 2, 2026 at 06:52:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 110 0 1 1 0 0 0 1 0 99 1 0 0 0 110 52 104 1 0 1 0 601 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 16 2 46 0 1 6 0 1359 0 0 0 100 4 0 0 0 9 1 4 0 0 3 0 0 0 0 0 100 5 0 0 3 212 103 4 0 1 2 0 0 0 0 0 100 6 0 0 0 28 9 24 0 1 0 0 8 0 0 0 100 7 0 0 24 213 106 10 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:52:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 0 2153 104 150 0 9 7 3 136 0 1 0 99 1 1920 0 0 79 20 75 2 8 5 5 915 0 1 0 99 2 17 0 0 35 0 48 0 11 8 9 141 0 0 0 100 3 11 0 0 109 34 142 1 7 15 2 1451 0 0 0 99 4 739 0 113 29 1 53 0 6 6 13 92 0 0 0 99 5 713 0 3 249 101 67 2 11 11 15 961 1 0 0 98 6 80 0 2 60 10 59 1 9 7 3 144 0 0 0 100 7 15 0 24 243 106 38 0 4 2 3 628 0 0 0 100 March 2, 2026 at 06:52:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 106 0 1 0 0 0 0 1 0 99 1 0 0 0 10 2 4 0 0 10 0 609 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 25 8 48 2 0 13 0 1432 0 0 0 99 4 0 0 0 98 45 96 0 1 0 0 5 0 0 0 100 5 0 0 3 225 107 13 0 2 0 0 7 0 0 0 100 6 1 0 0 36 9 40 0 1 0 0 18 0 0 0 100 7 0 0 24 217 106 14 0 0 2 0 526 0 0 0 100 March 2, 2026 at 06:52:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2102 100 108 0 1 0 0 0 0 1 0 99 1 0 0 0 12 2 10 0 0 9 0 600 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 1 0 0 12 3 36 1 0 9 0 1422 0 0 0 100 4 0 0 0 112 52 106 0 0 0 0 2 0 0 0 100 5 0 0 3 208 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 28 9 22 0 1 0 0 323 0 0 0 100 7 0 0 24 214 106 10 1 0 0 0 525 0 0 0 100 March 2, 2026 at 06:52:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 108 0 0 0 0 0 0 1 0 99 1 0 0 0 11 2 4 2 0 6 0 601 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 3 0 0 0 100 3 0 0 0 13 3 38 1 0 12 0 1431 0 0 0 100 4 0 0 0 123 58 118 0 0 0 0 13 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 22 5 18 0 0 0 0 5 0 0 0 100 7 0 0 24 218 106 20 0 1 0 0 527 0 0 0 100 March 2, 2026 at 06:52:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 0 2109 101 120 0 1 0 0 5 0 1 0 99 1 0 0 0 9 2 4 0 0 5 0 598 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 43 0 1 11 0 1429 0 0 0 100 4 0 0 0 116 55 112 0 0 0 0 5 0 0 0 100 5 0 0 3 210 102 4 0 0 2 0 5 0 0 0 100 6 0 0 0 17 4 12 0 0 0 0 2 0 0 0 100 7 0 0 24 215 106 12 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:52:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 100 110 0 1 0 0 0 0 1 0 99 1 0 0 0 11 3 6 0 0 8 0 602 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 12 2 36 2 0 5 0 1426 0 0 0 100 4 0 0 0 117 56 112 0 0 0 0 6 0 0 0 100 5 0 0 3 208 101 2 0 0 0 0 0 0 0 0 100 6 0 0 0 17 3 10 0 0 0 0 0 0 0 0 100 7 0 0 24 215 106 12 0 1 0 0 525 0 0 0 100 March 2, 2026 at 06:52:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 101 112 0 3 2 0 1 0 1 0 99 1 0 0 0 19 2 14 0 2 1 0 609 0 0 0 100 2 0 0 0 10 0 10 0 1 2 0 0 0 0 0 100 3 0 0 0 13 3 38 1 0 6 0 1436 0 0 0 100 4 0 0 0 120 56 116 0 0 0 0 326 0 0 0 100 5 0 0 3 218 109 6 0 0 0 0 7 0 0 0 100 6 0 0 0 28 7 28 0 0 0 0 17 0 0 0 100 7 0 0 24 218 107 14 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:52:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 0 0 1 0 99 1 0 0 0 10 2 4 1 0 5 0 596 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 17 2 48 1 1 11 0 1435 0 0 0 100 4 0 0 0 109 51 102 0 0 0 0 0 0 0 0 100 5 0 0 3 211 102 4 0 0 0 0 1 0 0 0 100 6 0 0 0 28 9 22 1 0 0 0 8 0 0 0 100 7 0 0 24 214 106 12 0 0 0 0 525 0 0 0 100 March 2, 2026 at 06:52:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 1 0 0 0 1 0 99 1 0 0 0 14 3 6 1 0 9 0 601 0 0 0 100 2 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 3 0 0 0 15 4 38 1 0 10 0 1425 0 0 0 99 4 0 0 0 111 52 106 0 1 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 1 0 0 0 0 0 100 6 0 0 0 38 14 28 0 0 1 0 16 0 0 0 100 7 0 0 24 216 106 14 1 2 1 0 532 0 0 0 100 March 2, 2026 at 06:52:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 102 116 0 1 0 0 4 0 1 0 99 1 0 0 0 9 2 4 0 0 7 0 601 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 22 2 52 2 0 9 0 1428 0 0 0 100 4 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 23 7 18 0 1 0 0 5 0 0 0 100 7 0 0 24 213 106 10 0 0 0 0 526 0 0 0 100 March 2, 2026 at 06:52:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 256 0 0 2239 132 384 6 42 7 0 1711 3 2 0 96 1 255 0 0 106 4 275 2 52 12 2 2470 1 1 0 98 2 223 0 0 133 4 270 7 45 4 1 1549 1 0 0 98 3 0 0 0 109 3 302 4 42 8 0 2923 1 1 0 98 4 71 0 0 121 19 296 12 46 5 0 1645 1 0 0 99 5 77 0 3 321 105 246 0 31 2 0 969 2 0 0 98 6 99 0 0 111 8 242 4 41 1 1 1816 1 0 0 98 7 245 0 108 247 106 181 5 13 2 2 1835 2 1 0 97 March 2, 2026 at 06:52:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2159 150 216 0 1 0 0 0 0 1 0 99 1 0 0 0 10 2 4 1 0 2 0 594 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 22 8 48 0 0 2 0 1439 0 0 0 100 4 0 0 0 9 1 6 0 0 0 0 5 0 0 0 100 5 0 0 3 222 113 4 0 0 0 0 7 0 0 0 100 6 1 0 0 27 6 28 0 0 0 0 20 0 0 0 100 7 0 0 24 220 106 16 0 0 0 0 526 0 0 0 100 March 2, 2026 at 06:52:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2154 150 208 0 0 0 0 0 0 1 0 99 1 0 0 0 9 2 4 0 0 5 0 602 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 1 0 0 24 8 48 1 1 4 0 1439 0 0 0 99 4 0 0 0 17 2 14 0 1 0 0 1 0 0 0 100 5 0 0 3 209 101 2 0 1 0 0 0 0 0 0 100 6 0 0 0 17 4 12 0 1 0 0 2 0 0 0 100 7 0 0 24 215 106 12 1 0 0 0 526 0 0 0 100 March 2, 2026 at 06:52:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2141 136 180 0 0 0 0 3 0 1 0 99 1 0 0 0 10 2 4 1 0 3 0 605 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 36 13 58 3 0 1 0 1449 0 0 0 99 4 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 5 0 0 3 218 103 16 0 1 0 0 0 0 0 0 100 6 0 0 0 47 18 44 0 2 0 0 4 0 0 0 100 7 0 0 24 213 106 10 0 0 0 0 526 0 0 0 100 March 2, 2026 at 06:53:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2173 103 219 1 20 137 0 31 0 1 0 99 1 0 0 0 71 2 122 0 24 128 0 613 0 0 0 100 2 0 0 9 52 1 86 0 14 122 0 7 0 1 0 99 3 0 0 14 159 69 204 1 22 157 0 1491 0 1 0 99 4 0 0 7 125 1 240 0 31 135 0 0 0 1 0 99 5 0 0 3 278 102 148 0 29 168 1 157 0 0 0 100 6 1 0 0 171 47 225 0 26 147 0 22 0 0 0 100 7 0 0 24 282 113 143 0 27 149 0 526 0 0 0 99 March 2, 2026 at 06:53:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 109 130 0 0 0 0 14 0 1 0 99 1 0 0 0 14 3 8 1 0 1 0 599 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 36 2 0 1 0 1344 0 0 0 100 4 0 0 0 12 2 6 0 0 0 0 1 0 0 0 100 5 0 0 10 210 101 4 0 1 0 0 0 0 0 0 100 6 0 0 0 21 4 20 0 1 0 0 1 0 0 0 100 7 0 0 24 314 156 110 0 0 0 0 527 0 0 0 100 March 2, 2026 at 06:53:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2134 107 130 0 0 0 0 10 0 1 0 99 1 0 0 0 25 2 4 0 0 2 0 599 0 0 0 100 2 0 0 0 25 2 4 0 0 0 0 2 0 0 0 100 3 0 0 112 12 2 39 0 1 3 0 1340 0 0 0 99 4 0 0 0 25 1 6 0 0 0 0 5 0 0 0 100 5 0 0 3 233 107 6 0 0 0 0 7 0 0 0 100 6 0 0 0 42 6 26 0 1 1 0 15 0 0 0 100 7 0 0 24 339 157 124 0 1 1 0 527 0 0 0 100 March 2, 2026 at 06:53:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2119 106 122 1 0 0 0 9 0 1 0 99 1 0 0 0 14 3 10 0 0 3 0 609 0 0 0 100 2 0 0 0 10 1 6 0 0 0 0 19 0 0 0 100 3 0 0 7 13 2 36 2 0 6 0 1339 0 0 0 99 4 0 0 0 10 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 212 102 4 0 0 0 0 1 0 0 0 100 6 0 0 0 14 3 8 0 0 0 0 0 0 0 0 100 7 0 0 24 316 156 112 1 0 0 0 525 0 0 0 100 March 2, 2026 at 06:53:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 14 2792 110 1282 28 238 13 0 5422 6 3 0 91 1 37 0 0 675 4 1252 37 272 28 0 8013 7 2 0 91 2 39 0 0 670 7 1132 24 179 17 0 5329 6 2 0 93 3 17 0 0 611 4 1106 30 237 43 1 8746 6 2 0 92 4 18 0 0 605 3 1073 23 234 16 0 5149 5 2 0 93 5 10 0 3 765 102 950 16 158 17 0 4041 5 2 0 94 6 34 0 0 590 32 997 20 204 17 0 6068 5 2 0 94 7 6 0 345 666 130 787 22 123 46 0 4172 4 2 0 94 March 2, 2026 at 06:53:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2169 101 232 0 30 222 0 266 0 1 0 99 1 0 0 0 105 2 201 2 37 254 1 600 0 1 0 99 2 0 0 0 81 1 152 0 25 232 0 0 0 0 0 100 3 0 0 0 155 87 168 1 28 218 0 1350 0 1 0 99 4 0 0 0 87 2 171 0 29 195 0 0 0 1 0 99 5 0 0 3 263 101 121 0 30 218 0 0 0 1 0 99 6 0 0 0 100 8 174 0 25 239 0 6 0 1 0 99 7 0 0 10 433 154 352 0 21 203 0 260 0 1 0 99 March 2, 2026 at 06:53:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2103 101 114 0 0 0 0 269 0 1 0 99 1 0 0 0 13 4 8 0 0 1 0 605 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 36 1 0 0 0 1350 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 5 0 0 3 209 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 26 9 22 0 0 0 0 11 0 0 0 100 7 0 0 10 311 154 106 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:53:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2107 101 114 0 0 0 0 266 0 1 0 99 1 0 0 0 11 3 6 0 0 13 0 602 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 38 2 0 5 0 1350 0 0 0 100 4 0 0 0 9 1 6 0 0 0 0 5 0 0 0 100 5 0 0 3 216 106 6 0 0 0 0 5 0 0 0 100 6 0 0 0 33 9 36 0 1 0 0 17 0 0 0 100 7 0 0 10 314 154 110 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:53:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 650 0 14 2138 101 137 1 10 6 3 1223 1 1 0 98 1 13 0 0 50 4 47 0 11 3 3 669 0 0 0 100 2 1891 0 0 33 1 29 2 6 4 5 313 0 0 0 99 3 16 0 0 44 2 76 0 8 11 3 1500 0 0 0 99 4 25 0 0 38 3 32 0 7 6 7 29 0 0 0 100 5 734 0 116 224 101 50 0 7 7 11 186 0 0 0 99 6 141 0 0 66 9 82 0 13 9 12 485 0 0 0 100 7 18 0 12 349 154 151 0 7 8 2 373 0 0 0 100 March 2, 2026 at 06:53:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 102 114 0 0 0 0 267 0 1 0 99 1 0 0 0 12 2 6 2 0 1 0 609 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 25 9 50 1 0 0 0 1438 0 0 0 99 4 0 0 0 8 1 4 0 1 0 0 10 0 0 0 100 5 0 0 3 209 101 2 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 10 0 0 0 0 1 0 0 0 100 7 0 0 10 312 154 108 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:53:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 161 0 7 2258 102 459 14 50 134 0 1796 3 2 0 96 1 365 0 7 301 2 622 11 83 142 2 2911 2 1 0 97 2 193 0 0 220 1 486 15 67 101 0 1642 2 1 0 97 3 233 0 0 280 69 504 12 74 146 0 3620 2 1 0 97 4 133 0 0 294 43 565 7 67 120 1 1569 1 1 0 98 5 60 0 2 367 101 327 9 58 94 0 1542 2 1 0 98 6 0 0 7 171 3 360 10 69 168 0 2325 2 1 0 98 7 2 0 86 352 113 329 3 50 116 0 1820 1 1 0 98 March 2, 2026 at 06:53:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 101 108 0 0 6 0 20 0 1 0 99 1 0 0 14 25 5 24 0 3 7 0 884 0 0 0 100 2 0 0 0 25 5 28 0 3 0 0 19 0 0 0 100 3 0 0 0 16 2 36 2 1 14 0 1442 0 0 0 100 4 0 0 0 115 52 110 0 1 0 0 4 0 0 0 100 5 0 0 3 218 104 10 0 0 0 0 9 0 0 0 100 6 0 0 7 24 5 19 1 3 0 0 263 0 0 0 100 7 0 0 17 211 102 6 0 1 0 0 4 0 0 0 100 March 2, 2026 at 06:53:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2121 101 123 0 8 9 2 141 0 1 0 99 1 1 0 14 35 3 42 0 9 16 0 877 0 0 0 100 2 0 0 0 32 8 30 0 5 5 0 32 0 1 0 99 3 0 0 0 28 3 66 1 7 8 0 1490 0 0 0 99 4 0 0 0 118 52 117 0 4 3 1 24 0 0 0 100 5 0 0 3 226 107 27 0 9 15 0 32 0 0 0 100 6 0 0 29 31 8 40 1 7 9 0 280 0 0 0 100 7 0 0 10 222 103 19 0 1 4 0 4 0 0 0 100 March 2, 2026 at 06:53:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2107 100 114 0 1 0 0 1 0 1 0 99 1 0 0 14 12 3 6 2 0 2 0 872 0 0 0 100 2 0 0 0 12 2 4 0 1 0 0 0 0 0 0 100 3 0 0 0 19 2 44 1 1 0 0 1344 0 0 0 100 4 0 0 0 110 51 102 0 0 0 0 0 0 0 0 100 5 0 0 3 216 105 6 0 0 0 0 4 0 0 0 100 6 0 0 7 35 13 31 0 1 0 0 268 0 0 0 100 7 0 0 3 213 103 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2120 100 114 0 1 1 0 0 0 1 0 99 1 25 0 21 34 5 14 0 1 3 0 886 0 0 0 100 2 0 0 0 27 2 2 0 0 1 0 0 0 0 0 100 3 0 0 0 37 3 44 1 0 1 0 1339 0 0 0 100 4 0 0 0 131 53 106 0 0 1 0 2 0 0 0 100 5 0 0 7 231 103 8 0 1 0 0 5 0 0 0 100 6 0 0 119 40 15 31 0 0 1 0 274 0 0 0 100 7 0 0 7 229 102 4 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:53:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2144 100 167 0 8 69 0 0 0 1 0 99 1 1 0 14 93 3 169 0 15 57 0 865 0 0 0 100 2 0 0 0 51 1 91 0 13 71 0 0 0 0 0 100 3 0 0 0 107 50 127 2 12 85 0 1338 0 1 0 99 4 0 0 0 141 45 183 0 13 94 0 0 0 0 0 100 5 0 0 3 246 102 76 0 14 67 0 1 0 0 0 100 6 0 0 14 92 17 141 0 19 58 0 268 0 0 0 99 7 0 0 3 239 102 63 0 9 60 0 0 0 0 0 100 March 2, 2026 at 06:53:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2674 101 1104 33 175 54 0 4288 5 2 0 93 1 1 0 14 596 4 1054 38 218 22 0 6180 5 2 0 93 2 3 0 0 483 1 826 21 152 43 0 4686 5 2 0 93 3 2 0 0 519 2 972 29 183 27 1 6432 4 2 0 94 4 6 0 0 511 2 875 19 182 36 0 4552 4 1 0 94 5 0 0 3 652 104 769 19 129 26 0 3424 3 1 0 95 6 0 0 7 485 21 861 18 165 47 0 5204 4 1 0 95 7 1 0 255 685 143 859 22 118 9 0 3740 4 1 0 95 March 2, 2026 at 06:53:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 0 2314 101 450 7 75 10 0 1454 2 1 0 97 1 0 0 14 219 9 361 12 62 10 0 1857 1 1 0 98 2 0 0 0 191 4 279 5 47 9 0 1819 1 0 0 98 3 4 0 0 261 51 427 11 70 11 0 3865 2 1 0 98 4 12 0 0 205 2 367 6 64 8 0 1810 2 1 0 98 5 38 0 5 359 108 276 7 45 21 0 1455 2 1 0 98 6 0 0 7 189 7 345 12 64 13 0 2192 2 1 0 97 7 0 0 101 363 103 294 5 39 7 0 817 1 0 0 99 March 2, 2026 at 06:53:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 649 0 0 2138 100 126 1 7 5 5 912 1 1 0 98 1 10 0 14 49 5 47 0 10 4 2 354 0 0 0 100 2 4 0 0 35 3 20 0 5 10 1 327 0 0 0 100 3 5 0 0 142 55 170 1 6 7 3 1708 0 0 0 99 4 2609 0 120 26 2 49 2 5 9 7 427 1 1 0 99 5 132 0 3 244 101 68 0 10 7 17 148 0 0 0 100 6 37 0 9 54 5 57 0 8 9 2 443 0 0 0 100 7 34 0 3 246 102 39 0 9 11 2 119 0 0 0 100 March 2, 2026 at 06:53:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 104 0 0 0 0 0 0 1 0 99 1 0 0 14 26 7 24 0 0 0 0 276 0 0 0 100 2 0 0 0 11 3 6 0 0 8 0 299 0 0 0 100 3 0 0 0 116 55 140 1 0 3 0 1726 0 0 0 99 4 0 0 0 8 1 4 0 0 0 0 10 0 0 0 100 5 0 0 3 211 102 4 0 0 0 0 1 0 0 0 100 6 0 0 7 21 4 22 0 1 0 0 263 0 0 0 100 7 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2164 100 221 0 21 203 0 0 0 1 0 99 1 1 0 14 92 5 169 0 27 183 0 271 0 1 0 99 2 0 0 0 120 3 228 1 30 228 0 299 0 0 0 100 3 0 0 0 243 126 263 3 30 235 0 1719 0 1 0 99 4 0 0 0 76 3 142 1 27 216 0 12 0 1 0 99 5 0 0 3 270 101 132 0 25 185 0 0 0 0 0 100 6 0 0 7 67 4 125 0 24 210 0 260 0 0 0 100 7 0 0 3 266 102 123 0 23 215 0 0 0 0 0 100 March 2, 2026 at 06:53:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 11 0 1 0 99 1 0 0 14 15 5 10 1 0 0 0 588 0 0 0 100 2 0 0 0 36 10 32 0 1 2 0 315 0 0 0 100 3 0 0 0 38 15 60 1 1 4 0 1723 0 0 0 99 4 0 0 0 61 27 56 0 1 0 0 12 0 0 0 100 5 0 0 3 237 115 32 0 1 0 0 3 0 0 0 100 6 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 7 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 75 0 0 2168 101 219 5 26 2 0 1478 1 1 0 98 1 4 0 14 68 1 157 2 26 4 0 2049 1 0 0 99 2 285 0 0 81 8 143 5 24 6 1 1906 2 1 0 97 3 70 0 0 84 7 299 4 30 5 0 3289 1 1 0 98 4 23 0 0 99 4 186 5 29 3 0 1561 2 0 0 98 5 221 0 17 361 156 244 3 20 3 0 1576 2 0 0 98 6 295 0 7 62 4 99 2 15 2 2 1475 2 0 0 98 7 40 0 73 256 103 209 5 22 2 0 1655 2 0 0 98 March 2, 2026 at 06:53:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 100 116 0 2 1 0 9 0 1 0 99 1 5 0 14 11 2 4 0 1 0 0 269 0 0 0 100 2 0 0 0 20 2 14 0 0 8 0 310 0 0 0 100 3 0 0 0 23 6 48 1 1 3 0 1734 0 0 0 99 4 0 0 0 22 5 16 0 0 0 0 13 0 0 0 100 5 0 0 3 314 152 108 0 1 0 0 10 0 0 0 100 6 0 0 7 20 4 14 0 0 0 0 264 0 0 0 100 7 0 0 17 211 102 6 0 2 4 0 9 0 0 0 100 March 2, 2026 at 06:53:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 101 106 0 1 1 0 3 0 1 0 99 1 0 0 14 9 2 6 0 1 0 0 266 0 0 0 100 2 0 0 0 20 3 12 1 0 3 0 301 0 0 0 100 3 0 0 0 34 13 56 2 0 3 0 1743 0 0 0 99 4 0 0 0 13 3 6 0 0 1 0 2 0 0 0 100 5 0 0 3 307 151 100 0 0 1 0 0 0 0 0 100 6 0 0 7 17 6 10 0 0 1 0 261 0 0 0 100 7 0 0 3 208 102 2 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:53:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 8 2159 100 179 1 22 125 0 8 0 2 0 98 1 0 0 28 140 3 251 2 25 136 3 419 0 1 0 99 2 0 0 0 95 2 146 0 20 125 0 314 0 0 0 100 3 0 0 0 143 68 163 2 21 141 0 1677 0 1 0 99 4 2 0 7 64 2 132 0 26 172 2 19 0 1 0 99 5 0 0 3 367 151 213 0 21 127 0 12 0 0 0 100 6 1 0 7 77 4 134 0 26 118 0 282 0 1 0 99 7 0 0 3 277 108 123 0 18 118 0 11 0 0 0 99 March 2, 2026 at 06:53:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 106 54 0 2 0 0 9 0 1 0 99 1 0 0 14 9 1 5 0 1 0 0 266 0 0 0 100 2 0 0 0 85 2 76 0 1 1 0 302 0 0 0 100 3 0 0 0 22 4 48 1 1 1 0 1635 0 0 0 100 4 0 0 0 12 2 6 0 0 0 0 2 0 0 0 100 5 0 0 10 308 151 102 0 1 0 0 0 0 0 0 100 6 0 0 7 16 4 10 0 0 0 0 260 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2141 109 124 0 0 0 0 11 0 1 0 99 1 0 0 126 7 1 5 0 1 0 0 266 0 0 0 100 2 0 0 0 36 2 14 1 0 2 0 300 0 0 0 100 3 0 0 0 30 4 40 0 0 1 0 1637 0 0 0 100 4 0 0 0 35 5 18 0 0 0 0 15 0 0 0 100 5 0 0 3 332 156 106 0 0 0 0 7 0 0 0 100 6 0 0 7 33 4 16 0 1 0 0 265 0 0 0 100 7 0 0 3 227 102 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 106 116 1 0 0 0 9 0 1 0 99 1 0 0 21 8 1 4 0 0 0 0 266 0 0 0 100 2 0 0 0 19 2 12 1 0 1 0 307 0 0 0 100 3 0 0 0 18 4 40 2 0 3 0 1637 0 0 0 100 4 0 0 0 17 3 16 0 1 0 0 3 0 0 0 100 5 0 0 3 308 151 100 0 0 0 0 0 0 0 0 100 6 0 0 7 19 5 12 0 1 0 0 261 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2869 110 1362 43 253 36 1 5648 7 3 0 90 1 14 0 14 769 6 1383 42 287 28 0 7714 7 2 0 91 2 26 0 0 675 7 1157 35 197 35 0 5858 6 2 0 92 3 21 0 0 664 8 1187 35 275 21 0 8149 6 2 0 92 4 4 0 0 731 44 1224 29 241 32 0 7094 5 2 0 93 5 8 0 3 767 110 922 19 171 20 0 4669 4 1 0 94 6 2 0 7 570 12 1054 25 215 41 0 6732 5 2 0 93 7 33 0 367 745 106 1028 16 137 13 0 4644 5 2 0 93 March 2, 2026 at 06:53:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2169 100 220 1 30 212 0 0 0 1 0 99 1 0 0 14 82 1 169 1 35 216 0 266 0 1 0 99 2 0 0 0 153 4 301 1 33 168 0 293 0 1 0 99 3 0 0 0 173 86 166 0 35 246 0 593 0 1 0 99 4 0 0 0 177 49 249 1 36 249 0 352 0 1 0 99 5 0 0 3 273 101 154 0 25 200 0 693 0 1 0 99 6 0 0 7 91 8 156 0 30 209 0 265 0 1 0 99 7 0 0 3 272 103 139 0 25 222 0 10 0 1 0 99 March 2, 2026 at 06:53:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 667 0 0 2135 100 130 2 14 10 11 981 1 1 0 98 1 57 0 14 48 2 55 1 8 8 8 395 0 0 0 100 2 14 0 0 46 3 54 0 10 11 7 404 0 0 0 100 3 2 0 0 54 6 43 0 8 7 1 652 0 0 0 100 4 710 0 113 26 3 45 0 5 6 8 72 0 0 0 99 5 116 0 3 336 147 165 1 4 7 9 1239 0 0 0 99 6 13 0 9 86 12 86 0 7 3 5 409 0 0 0 100 7 1904 0 3 240 102 38 2 5 3 3 409 0 1 0 99 March 2, 2026 at 06:53:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 108 0 0 0 0 1 0 1 0 99 1 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 2 0 0 0 11 3 6 0 0 2 0 294 0 0 0 100 3 0 0 0 21 3 16 1 0 5 0 615 0 0 0 100 4 0 0 0 19 5 18 0 0 0 0 16 0 0 0 100 5 0 0 3 245 121 64 0 0 0 0 1136 0 0 0 100 6 0 0 7 104 46 104 0 1 0 0 275 0 0 0 100 7 0 0 3 219 103 20 0 1 0 0 11 0 0 0 100 March 2, 2026 at 06:53:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 2 0 0 10 0 1 0 99 1 0 0 14 9 2 8 0 0 0 0 275 0 0 0 100 2 0 0 0 13 3 10 0 0 3 0 318 0 0 0 100 3 0 0 0 20 2 16 1 0 2 0 599 0 0 0 100 4 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 212 103 34 1 0 0 0 1127 0 0 0 100 6 0 0 7 123 58 118 0 0 0 0 580 0 0 0 100 7 0 0 3 215 105 10 0 1 0 0 5 0 0 0 100 March 2, 2026 at 06:53:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 100 116 0 1 1 0 10 0 1 0 99 1 0 0 14 11 2 6 0 0 1 0 269 0 0 0 100 2 0 0 0 14 4 6 0 0 3 0 305 0 0 0 100 3 0 0 0 20 3 14 0 1 1 0 595 0 0 0 100 4 0 0 0 16 4 8 0 1 1 0 3 0 0 0 100 5 0 0 7 211 102 32 1 0 2 0 1127 0 0 0 100 6 0 0 7 118 56 110 0 0 1 0 261 0 0 0 100 7 0 0 7 226 109 18 0 0 1 0 10 0 0 0 100 March 2, 2026 at 06:53:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 122 0 0 2236 105 437 7 42 142 1 1553 1 2 0 98 1 507 0 14 178 2 369 5 49 111 1 2105 1 1 0 98 2 272 0 0 145 5 292 9 44 120 0 1599 2 1 0 97 3 142 0 0 275 115 289 5 41 144 1 2140 2 1 0 97 4 1 0 0 121 2 455 2 57 125 0 1447 1 1 0 98 5 63 0 3 314 103 297 10 43 160 0 2810 2 1 0 96 6 10 0 7 150 9 286 5 49 140 0 1906 1 1 0 98 7 19 0 115 306 106 244 6 43 147 0 1400 1 1 0 98 March 2, 2026 at 06:53:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 108 0 1 0 0 0 0 1 0 99 1 0 0 14 6 1 2 1 0 0 0 266 0 0 0 100 2 0 0 0 24 9 18 0 0 3 0 302 0 0 0 100 3 0 0 0 114 52 106 1 0 5 0 594 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 5 0 0 3 212 102 34 1 0 0 0 1133 0 0 0 100 6 0 0 7 14 4 10 0 0 0 0 260 0 0 0 100 7 0 0 3 211 102 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2116 101 132 0 6 8 0 16 0 1 0 99 1 0 0 22 14 1 28 0 8 15 0 273 0 1 0 99 2 0 0 0 50 12 50 1 2 7 1 414 0 0 0 100 3 0 0 0 130 52 135 1 5 8 1 688 0 0 0 100 4 0 0 0 27 3 29 0 3 3 0 39 0 0 0 100 5 0 0 3 226 107 52 1 6 10 0 1148 0 0 0 99 6 0 0 7 25 4 21 0 5 2 0 266 0 0 0 100 7 0 0 3 218 102 12 0 3 8 0 14 0 0 0 100 March 2, 2026 at 06:53:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 117 0 0 0 0 0 0 1 0 99 1 0 0 21 9 1 4 0 1 0 0 266 0 0 0 100 2 0 0 0 24 9 18 0 0 3 0 304 0 0 0 100 3 0 0 0 113 52 106 0 0 3 0 593 0 0 0 100 4 0 0 0 15 2 14 0 1 0 0 2 0 0 0 100 5 0 0 3 211 102 32 1 0 0 0 1046 0 0 0 100 6 2 0 7 19 5 12 0 1 0 0 261 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2106 100 73 0 2 0 0 0 0 1 0 99 1 0 0 14 66 1 44 0 3 0 0 266 0 0 0 100 2 0 0 0 48 12 26 1 1 2 0 312 0 0 0 100 3 0 0 0 128 53 108 0 0 3 0 599 0 0 0 100 4 0 0 0 29 4 8 0 0 0 0 3 0 0 0 100 5 0 0 3 225 102 32 0 0 0 0 1044 0 0 0 100 6 0 0 7 30 4 10 0 0 0 0 260 0 0 0 100 7 0 0 3 224 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2107 100 106 0 2 1 0 0 0 1 0 99 1 0 0 14 11 1 12 0 1 0 0 266 0 0 0 100 2 0 0 0 25 8 20 1 0 3 0 316 0 0 0 100 3 0 0 0 111 52 104 1 0 1 0 594 0 0 0 100 4 0 0 0 26 4 18 0 2 1 0 4 0 0 0 100 5 0 0 3 214 102 38 1 1 2 0 1043 0 0 0 100 6 0 0 7 16 4 12 0 0 2 0 260 0 0 0 100 7 0 0 3 210 102 4 0 0 2 0 0 0 0 0 100 March 2, 2026 at 06:53:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2840 103 1376 41 244 8 0 5603 6 3 0 91 1 5 0 14 757 26 1344 47 277 44 0 7610 6 2 0 92 2 24 0 0 785 11 1297 39 192 36 0 5579 7 2 0 91 3 9 0 0 750 29 1320 32 263 21 0 8604 6 2 0 92 4 1 0 0 656 6 1233 33 236 8 0 5930 5 2 0 94 5 44 0 5 781 104 937 19 155 37 0 4938 5 2 0 93 6 1 0 7 503 4 909 31 221 40 0 6220 5 2 0 94 7 5 0 339 658 103 844 13 136 12 0 4535 4 1 0 95 March 2, 2026 at 06:53:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 110 0 1 0 0 1 0 1 0 99 1 0 0 14 106 51 104 0 0 0 0 269 0 0 0 100 2 0 0 0 28 11 24 0 0 3 0 312 0 0 0 100 3 0 0 0 12 2 9 0 1 2 0 594 0 0 0 100 4 0 0 0 27 5 26 0 0 0 0 16 0 0 0 100 5 0 0 3 219 108 38 1 0 0 0 1051 0 0 0 100 6 0 0 7 14 3 12 0 0 0 0 265 0 0 0 100 7 0 0 3 217 104 12 0 0 0 0 22 0 0 0 100 March 2, 2026 at 06:53:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 0 2136 100 139 0 8 9 4 68 0 1 0 99 1 36 0 14 69 17 69 1 7 8 7 329 0 0 0 100 2 3 0 0 115 41 99 0 3 8 1 325 0 0 0 100 3 3 0 0 40 2 35 0 5 5 2 638 0 0 0 100 4 1364 0 114 34 1 52 2 3 7 9 986 2 1 0 98 5 117 0 3 253 104 102 1 12 8 15 1202 0 0 0 99 6 41 0 10 55 5 61 1 11 6 7 493 0 0 0 100 7 1903 0 3 242 102 38 1 7 7 4 399 0 1 0 99 March 2, 2026 at 06:53:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 102 0 0 1 0 0 0 1 0 99 1 0 0 14 11 2 6 0 2 1 0 266 0 0 0 100 2 0 0 0 127 59 120 0 1 4 0 303 0 0 0 100 3 0 0 0 15 3 6 1 0 4 0 595 0 0 0 100 4 0 0 0 27 3 24 0 1 1 0 2 0 0 0 100 5 0 0 7 212 103 34 0 0 1 0 1130 0 0 0 100 6 0 0 7 16 5 8 0 0 1 0 261 0 0 0 100 7 0 0 7 212 102 8 1 1 0 0 13 0 0 0 100 March 2, 2026 at 06:53:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2170 100 233 0 21 195 0 0 0 1 0 99 1 0 0 14 68 2 137 0 28 224 0 271 0 1 0 99 2 0 0 0 164 56 210 0 23 180 0 620 0 1 0 99 3 0 0 0 149 76 285 1 34 187 0 593 0 1 0 99 4 0 0 0 85 2 153 0 33 256 0 0 0 1 0 99 5 0 0 3 277 103 175 1 23 235 0 1128 0 1 0 99 6 0 0 7 76 3 143 0 21 186 0 260 0 1 0 99 7 0 0 3 257 103 101 0 19 195 0 2 0 0 0 100 March 2, 2026 at 06:53:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 100 106 0 1 0 0 20 0 1 0 99 1 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 2 0 0 0 111 52 106 0 0 1 0 302 0 0 0 100 3 0 0 0 9 2 4 0 0 2 0 594 0 0 0 100 4 0 0 0 21 3 16 0 0 0 0 3 0 0 0 100 5 0 0 3 219 105 44 1 1 0 0 1126 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 7 0 0 3 220 108 14 0 0 0 0 8 0 0 0 100 March 2, 2026 at 06:53:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 111 0 0 2184 101 327 8 36 7 2 1656 1 1 0 98 1 308 0 14 49 2 100 7 15 1 3 1539 2 1 0 98 2 139 0 4 125 20 227 12 27 14 0 1192 2 0 0 97 3 236 0 0 159 34 312 16 36 7 1 2138 1 1 0 98 4 144 0 0 114 3 282 3 37 8 0 1725 1 0 0 98 5 5 0 3 282 114 209 4 29 0 0 2352 1 1 0 98 6 241 0 7 77 3 369 7 37 1 1 2399 2 1 0 97 7 0 0 73 252 107 119 3 19 0 0 799 2 0 0 98 March 2, 2026 at 06:53:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 104 0 0 0 0 0 0 1 0 99 1 0 0 14 14 2 10 0 0 0 0 266 0 0 0 100 2 0 0 0 11 2 6 0 0 3 0 295 0 0 0 100 3 0 0 0 111 52 106 1 1 4 0 594 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 5 0 0 3 224 109 46 1 0 0 0 1142 0 0 0 100 6 0 0 7 16 4 10 0 1 0 0 261 0 0 0 100 7 0 0 3 210 103 4 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:53:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2117 100 126 0 4 4 0 20 0 1 0 99 1 0 0 21 25 1 29 0 10 8 0 286 0 0 0 100 2 0 0 0 22 2 15 2 1 4 0 310 0 0 0 100 3 0 0 0 125 54 122 1 6 11 0 619 0 0 0 100 4 0 0 0 18 1 20 0 5 5 2 81 0 0 0 100 5 0 0 3 252 116 74 2 0 2 0 1243 0 0 0 99 6 0 0 15 34 5 39 0 3 12 0 271 0 1 0 99 7 0 0 3 218 102 16 0 5 12 0 17 0 0 0 100 March 2, 2026 at 06:53:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2160 100 215 0 24 115 0 0 0 1 0 99 1 0 0 14 84 2 142 0 23 132 0 266 0 0 0 100 2 0 0 7 58 2 103 0 18 113 0 298 0 0 0 100 3 0 0 0 243 131 371 0 27 136 0 594 0 0 0 99 4 0 0 0 82 3 155 0 34 155 0 3 0 0 0 100 5 0 0 3 288 110 173 1 22 114 0 1057 0 1 0 99 6 0 0 7 76 3 141 0 30 123 0 260 0 0 0 99 7 0 0 3 256 102 105 0 23 112 0 0 0 0 0 100 March 2, 2026 at 06:53:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2107 100 113 0 0 0 0 0 0 1 0 99 1 0 0 14 23 1 2 0 0 0 0 266 0 0 0 100 2 1 0 0 32 3 10 0 0 0 0 313 0 0 0 100 3 21 0 7 132 55 112 0 1 2 0 600 0 0 0 100 4 0 0 0 30 4 8 0 0 0 0 6 0 0 0 100 5 0 0 3 241 109 46 1 0 0 0 1053 0 0 0 99 6 0 0 7 29 3 8 0 0 0 0 260 0 0 0 100 7 0 0 3 225 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 101 116 0 0 0 0 1 0 1 0 99 1 0 0 14 7 1 2 0 0 0 0 266 0 0 0 100 2 0 0 0 12 2 6 0 0 1 0 292 0 0 0 100 3 0 0 0 119 54 114 1 0 0 0 618 0 0 0 100 4 0 0 0 21 5 20 0 1 0 0 16 0 0 0 100 5 0 0 3 229 112 44 1 1 0 0 1049 0 0 0 100 6 0 0 7 29 8 28 0 2 0 0 274 0 0 0 100 7 0 0 3 222 104 22 0 2 0 0 2 0 0 0 100 March 2, 2026 at 06:53:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 17 0 0 2777 100 1297 31 252 33 0 5327 7 3 0 90 1 16 0 0 648 1 1185 42 267 43 0 7918 6 2 0 92 2 44 0 0 629 2 1070 21 198 11 0 5168 5 2 0 93 3 21 0 0 681 33 1185 29 234 25 0 8212 6 2 0 92 4 3 0 0 590 3 1046 13 230 16 0 5727 5 2 0 93 5 31 0 3 714 105 870 16 142 51 0 4769 5 2 0 94 6 6 0 10 589 9 1066 27 228 15 0 6517 6 2 0 92 7 25 0 343 619 121 770 13 122 11 1 4229 4 1 0 95 March 2, 2026 at 06:53:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 108 0 0 1 0 0 0 1 0 99 1 0 0 0 14 2 4 0 2 1 0 0 0 0 0 100 2 0 0 0 13 2 4 1 0 1 0 299 0 0 0 100 3 0 0 0 15 4 6 0 0 3 0 594 0 0 0 100 4 0 0 0 19 6 8 0 0 1 0 3 0 0 0 100 5 0 0 7 216 104 38 1 1 1 0 1045 0 0 0 100 6 1 0 14 32 13 22 1 0 1 0 279 0 0 0 100 7 0 0 14 314 154 110 0 0 1 0 273 0 0 0 100 March 2, 2026 at 06:53:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2212 100 267 0 38 230 0 41 0 1 0 99 1 632 0 0 123 2 185 1 39 240 0 910 1 1 0 98 2 2610 0 113 111 1 228 2 35 246 8 698 1 2 0 98 3 140 0 0 235 99 257 0 42 286 17 777 0 1 0 99 4 35 0 2 116 2 201 0 38 251 9 163 0 1 0 99 5 12 0 3 407 103 405 1 27 204 6 1178 0 1 0 99 6 11 0 14 119 6 203 0 40 226 0 389 0 1 0 99 7 27 0 10 408 155 275 0 33 220 5 324 0 1 0 99 March 2, 2026 at 06:53:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 0 0 1 0 99 1 0 0 0 9 1 4 0 1 0 0 1 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 294 0 0 0 100 3 0 0 0 17 3 14 1 1 1 0 594 0 0 0 100 4 0 0 0 11 3 6 0 1 0 0 2 0 0 0 100 5 0 0 3 213 103 36 1 0 1 0 1131 0 0 0 100 6 0 0 14 17 6 14 0 0 0 0 271 0 0 0 100 7 0 0 10 312 154 108 0 0 0 0 270 0 0 0 100 March 2, 2026 at 06:53:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 112 0 0 0 0 3 0 1 0 99 1 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 1 2 0 0 5 0 296 0 0 0 100 3 0 0 0 17 3 14 1 1 1 0 599 0 0 0 100 4 0 0 0 19 5 16 0 0 0 0 16 0 0 0 100 5 0 0 3 223 108 44 1 1 0 0 1135 0 0 0 100 6 0 0 14 26 9 24 0 0 0 0 595 0 0 0 100 7 0 0 10 318 154 118 0 1 1 0 275 0 0 0 100 March 2, 2026 at 06:53:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 100 110 0 0 0 0 0 0 1 0 99 1 0 0 0 13 2 10 0 1 0 0 14 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 309 0 0 0 100 3 0 0 0 24 7 20 0 0 3 0 604 0 0 0 100 4 0 0 0 18 4 20 0 1 0 0 9 0 0 0 100 5 0 0 2 222 111 38 1 0 0 0 1128 0 0 0 100 6 0 0 14 11 2 6 0 1 0 0 266 0 0 0 100 7 0 0 11 314 155 110 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:53:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 70 0 0 2201 120 334 9 41 1 0 1367 1 1 0 98 1 39 0 0 99 0 314 2 34 2 0 1359 1 0 0 99 2 1 0 0 71 1 105 3 19 7 0 1328 1 0 0 98 3 137 0 0 106 11 212 11 35 1 0 2490 3 1 0 97 4 228 0 0 69 2 83 4 16 14 0 1045 3 0 0 97 5 440 0 26 303 105 229 10 30 3 1 3051 2 1 0 97 6 133 0 28 52 2 116 3 18 2 1 1400 2 0 0 98 7 0 0 94 332 134 215 1 27 3 0 1794 1 0 0 99 March 2, 2026 at 06:54:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2215 143 315 0 26 162 0 25 0 1 0 99 1 0 0 0 88 2 155 0 24 197 0 26 0 0 0 99 2 0 0 0 64 1 114 1 12 209 0 307 0 0 0 100 3 18 0 0 146 78 120 2 19 111 0 619 0 1 0 99 4 0 0 0 83 3 161 0 29 177 0 8 0 0 0 99 5 0 0 3 281 108 166 0 23 175 0 1155 0 1 0 99 6 0 0 14 92 5 171 1 23 177 0 293 0 0 0 99 7 0 0 24 347 111 269 0 20 115 0 278 0 1 0 99 March 2, 2026 at 06:54:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2109 100 117 0 6 3 0 0 0 1 0 99 1 0 0 0 17 0 14 0 7 12 0 14 0 0 0 100 2 0 0 0 16 1 12 0 1 4 0 319 0 0 0 100 3 0 0 8 25 3 26 1 6 14 0 610 0 1 0 99 4 0 0 7 24 3 26 0 3 3 1 106 0 0 0 100 5 0 0 3 247 112 78 1 3 6 1 1234 0 1 0 99 6 0 0 14 47 12 60 0 8 8 0 278 0 0 0 100 7 0 0 10 302 144 95 0 1 4 0 273 0 0 0 100 March 2, 2026 at 06:54:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 101 119 0 1 0 0 1 0 1 0 99 1 0 0 0 10 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 8 1 2 0 0 1 0 300 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 594 0 0 0 100 4 0 0 0 40 15 36 0 0 0 0 22 0 0 0 100 5 0 0 10 228 111 44 2 1 1 0 1055 0 1 0 99 6 0 0 14 118 52 118 0 2 1 0 281 0 0 0 100 7 0 0 10 223 105 26 0 1 0 0 261 0 0 0 100 March 2, 2026 at 06:54:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2102 100 111 0 0 0 0 0 0 1 0 99 1 0 0 0 28 1 8 0 0 0 0 9 0 0 0 100 2 0 0 0 30 3 10 0 0 5 0 320 0 0 0 100 3 0 0 0 25 2 4 0 0 1 0 594 0 0 0 100 4 0 0 0 36 8 14 0 0 0 0 9 0 0 0 100 5 0 0 3 235 104 42 1 0 0 0 1044 0 1 0 99 6 0 0 14 126 52 108 0 2 0 0 266 0 0 0 100 7 0 0 10 230 105 10 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2111 100 122 0 1 1 0 0 0 1 0 99 1 0 0 0 13 1 4 0 0 1 0 0 0 0 0 100 2 0 0 0 14 3 4 1 0 1 0 309 0 0 0 100 3 0 0 0 15 3 6 1 0 5 0 597 0 0 0 100 4 0 0 0 33 12 24 0 1 1 0 16 0 0 0 100 5 0 0 7 217 104 38 1 0 1 0 1044 0 1 0 99 6 0 0 14 115 54 106 1 0 1 0 267 0 0 0 100 7 0 0 14 215 104 10 0 1 0 0 260 0 0 0 100 March 2, 2026 at 06:54:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 2765 100 1272 53 243 109 1 4597 6 2 0 92 1 21 0 0 661 0 1204 47 282 120 0 6415 5 2 0 93 2 1 0 0 576 3 991 30 188 122 0 4725 5 2 0 94 3 3 0 0 613 81 1114 47 258 159 0 7509 5 2 0 93 4 34 0 0 627 10 1124 29 229 146 0 4873 5 2 0 93 5 14 0 3 697 106 894 14 154 128 0 4852 4 2 0 94 6 4 0 14 650 43 1133 36 218 139 0 5375 4 2 0 94 7 2 0 290 672 108 904 27 158 128 0 3503 3 2 0 95 March 2, 2026 at 06:54:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 0 2268 101 389 7 63 4 0 1064 1 1 0 97 1 1 0 0 187 2 312 9 73 6 0 1990 1 0 0 98 2 4 0 0 155 6 250 5 49 2 0 1161 1 0 0 98 3 0 0 0 131 3 218 9 55 8 0 2574 1 0 0 98 4 3 0 0 227 52 306 4 55 4 0 1675 1 0 0 98 5 1 0 3 366 104 294 6 44 6 0 2052 1 1 0 98 6 2 0 14 141 4 246 8 60 7 0 1736 1 0 0 98 7 1 0 94 357 107 273 1 30 6 0 900 1 0 0 99 March 2, 2026 at 06:54:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 112 0 1 0 0 0 0 1 0 99 1 0 0 0 11 1 6 0 1 0 0 10 0 0 0 100 2 0 0 0 28 10 24 0 1 0 0 18 0 0 0 100 3 0 0 0 14 3 10 0 0 2 0 624 0 0 0 100 4 0 0 0 117 53 118 0 1 2 0 299 0 0 0 100 5 0 0 3 220 108 40 1 0 0 0 1051 0 0 0 100 6 0 0 14 17 4 18 0 0 0 0 279 0 0 0 100 7 0 0 10 217 104 14 0 1 0 0 263 0 0 0 100 March 2, 2026 at 06:54:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 0 10 1 6 0 0 0 0 10 0 0 0 100 2 0 0 0 16 5 8 1 0 0 0 6 0 0 0 100 3 0 0 0 9 2 4 0 0 1 0 600 0 0 0 100 4 0 0 0 117 54 108 1 0 0 0 296 0 0 0 100 5 0 0 3 220 103 48 1 1 1 0 1044 0 0 0 100 6 0 0 14 10 2 6 1 1 0 0 266 0 0 0 100 7 0 0 10 216 105 12 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2137 100 133 0 9 2 4 71 0 1 0 99 1 4 0 0 36 1 23 0 7 2 2 67 0 0 0 100 2 18 0 0 51 8 47 0 6 2 4 102 0 0 0 100 3 1898 0 0 42 2 36 4 7 7 2 977 0 1 0 99 4 656 0 0 124 45 115 4 8 11 4 1249 1 0 0 98 5 727 0 117 255 113 118 1 9 10 10 1185 0 1 0 99 6 137 0 14 50 2 71 0 16 15 13 423 0 0 0 100 7 19 0 12 245 104 49 0 9 5 8 362 0 0 0 100 March 2, 2026 at 06:54:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2159 101 221 0 30 209 0 0 0 1 0 99 1 0 0 0 84 6 159 0 31 233 0 8 0 1 0 99 2 0 0 0 79 3 130 0 24 171 0 332 0 1 0 99 3 0 0 0 134 69 125 0 24 191 0 609 0 1 0 99 4 0 0 0 73 4 138 0 27 187 0 296 0 1 0 99 5 0 0 3 308 124 182 1 13 155 0 1130 0 1 0 99 6 0 0 14 135 32 199 0 29 187 0 267 0 1 0 99 7 0 0 10 324 104 232 0 25 132 0 260 0 0 0 100 March 2, 2026 at 06:54:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 56 0 0 2237 100 474 20 45 6 0 1624 1 1 0 98 1 15 0 0 83 6 219 5 29 4 0 1489 2 0 0 98 2 137 0 0 111 0 294 11 41 9 1 1769 1 0 0 98 3 103 0 0 96 3 267 9 43 7 0 2153 1 0 0 98 4 4 0 0 55 4 124 7 24 3 0 1508 2 0 0 98 5 262 0 3 257 104 111 8 18 6 4 2378 2 1 0 97 6 81 0 14 190 44 480 10 45 1 0 2603 2 1 0 97 7 422 0 80 304 112 451 4 36 3 0 2218 2 1 0 98 March 2, 2026 at 06:54:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 108 0 0 0 0 1 0 1 0 99 1 0 0 0 25 8 22 0 1 0 0 12 0 0 0 100 2 0 0 0 15 1 8 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 8 0 0 2 0 618 0 0 0 100 4 0 0 0 19 6 12 1 0 1 0 302 0 0 0 100 5 0 0 3 223 110 40 1 0 2 0 1140 0 0 0 100 6 7 0 14 19 4 20 1 0 0 0 282 0 0 0 100 7 0 0 10 317 155 116 0 0 0 0 263 0 0 0 100 March 2, 2026 at 06:54:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 104 0 1 0 0 0 0 1 0 99 1 0 0 0 21 7 16 0 1 0 0 9 0 0 0 100 2 0 0 0 15 1 10 0 0 0 0 1 0 0 0 100 3 0 0 0 10 2 4 1 0 5 0 600 0 0 0 100 4 0 0 0 12 3 4 0 0 3 0 294 0 0 0 100 5 0 0 3 214 103 36 0 0 0 0 1133 0 0 0 100 6 0 0 14 12 2 10 0 0 0 0 266 0 0 0 100 7 0 0 10 318 155 118 0 1 0 0 261 0 0 0 100 March 2, 2026 at 06:54:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2129 101 132 0 5 6 0 90 0 1 0 99 1 0 0 7 127 51 129 0 8 9 0 33 0 0 0 100 2 0 0 8 25 1 24 1 4 7 0 8 0 1 0 99 3 0 0 0 20 3 16 0 1 4 0 636 0 0 0 100 4 0 0 14 27 6 25 0 7 16 0 311 0 0 0 100 5 0 0 3 220 103 40 1 2 5 0 1048 0 0 0 100 6 0 0 14 38 11 33 0 4 4 0 312 0 0 0 100 7 0 0 10 230 107 35 1 7 18 1 335 0 0 0 100 March 2, 2026 at 06:54:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2158 100 195 0 20 104 0 0 0 1 0 99 1 0 0 0 169 52 222 0 26 111 0 0 0 1 0 99 2 0 0 7 67 0 112 0 16 136 0 0 0 0 0 100 3 0 0 0 125 69 100 1 21 149 0 599 0 0 0 100 4 0 0 0 76 3 136 0 22 152 0 294 0 1 0 99 5 0 0 3 258 103 135 1 14 132 0 1044 0 1 0 99 6 0 0 14 83 9 142 1 21 132 0 276 0 0 0 100 7 0 0 10 317 104 216 0 16 98 0 260 0 0 0 100 March 2, 2026 at 06:54:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2129 104 70 0 2 2 0 5 0 1 0 99 1 0 0 0 113 23 88 0 1 0 0 0 0 0 0 100 2 0 0 0 39 1 20 0 1 2 0 0 0 0 0 100 3 1 0 7 29 3 8 0 1 1 0 603 0 0 0 100 4 0 0 112 54 22 47 1 1 0 0 299 0 0 0 100 5 0 0 3 253 113 60 1 2 0 0 1042 0 0 0 100 6 0 0 14 45 11 24 0 0 0 0 277 0 0 0 100 7 0 0 10 228 104 6 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 106 0 0 0 0 1 0 0 0 100 1 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 16 0 10 0 0 0 0 0 0 0 0 100 3 0 0 0 19 2 18 1 2 2 0 603 0 0 0 100 4 0 0 7 15 3 12 0 1 0 0 299 0 0 0 100 5 0 0 3 321 158 140 1 0 1 0 1047 0 0 0 100 6 0 0 14 35 12 34 0 0 0 0 289 0 0 0 100 7 0 0 10 216 104 12 0 0 0 0 263 0 0 0 100 March 2, 2026 at 06:54:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 0 2966 106 1695 50 248 39 1 5993 7 3 0 90 1 18 0 0 783 7 1379 50 297 19 0 7438 7 2 0 91 2 9 0 0 810 37 1302 19 205 58 0 6194 5 2 0 93 3 18 0 0 681 10 1177 39 246 32 1 8626 6 2 0 92 4 3 0 0 585 6 1011 18 249 38 0 6079 6 2 0 92 5 16 0 3 816 111 1076 15 162 9 0 6333 5 2 0 94 6 12 0 14 631 9 1152 34 237 55 0 7297 6 2 0 92 7 6 0 388 671 108 897 13 136 37 0 5136 5 2 0 93 March 2, 2026 at 06:54:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 108 0 1 0 0 0 0 1 0 99 1 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 2 0 0 0 108 50 103 0 1 0 0 0 0 0 0 100 3 0 0 0 19 6 14 0 0 4 0 600 0 0 0 100 4 0 0 0 18 4 18 0 1 3 0 304 0 0 0 100 5 0 0 3 214 104 38 0 0 1 0 1045 0 0 0 100 6 0 0 14 10 2 6 1 0 0 0 267 0 0 0 100 7 0 0 10 212 104 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2174 100 233 0 23 198 0 0 0 1 0 99 1 0 0 0 91 2 180 0 36 235 0 0 0 1 0 99 2 0 0 0 170 50 229 0 22 209 0 0 0 1 0 99 3 0 0 0 153 82 135 1 27 198 0 612 0 1 0 99 4 0 0 0 82 7 140 1 28 170 0 308 0 0 0 99 5 0 0 3 280 103 184 1 21 203 0 1045 0 1 0 99 6 0 0 14 119 1 238 0 32 216 0 266 0 1 0 99 7 0 0 10 300 104 194 0 21 204 0 260 0 1 0 99 March 2, 2026 at 06:54:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 100 0 0 0 0 0 0 1 0 99 1 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 110 50 104 1 1 0 0 3 0 0 0 100 3 0 0 0 33 9 28 1 1 0 0 611 0 0 0 100 4 0 0 0 18 6 12 0 0 0 0 306 0 0 0 100 5 0 0 3 213 103 36 1 0 0 0 1045 0 1 0 99 6 0 0 14 9 2 6 0 0 0 0 267 0 0 0 100 7 0 0 10 211 104 6 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 108 0 0 0 0 1 0 1 0 99 1 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 3 0 0 0 34 7 34 0 1 2 0 913 0 0 0 100 4 0 0 0 25 8 24 0 0 5 0 322 0 0 0 100 5 0 0 3 228 112 48 1 0 0 0 1057 0 1 0 99 6 0 0 14 16 3 18 0 0 0 0 280 0 0 0 100 7 0 0 10 218 105 16 0 0 0 0 264 0 0 0 100 March 2, 2026 at 06:54:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 102 0 1 0 0 0 0 1 0 99 1 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 2 0 0 0 107 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 19 2 14 0 1 4 0 605 0 0 0 100 4 0 0 0 20 4 18 0 1 2 0 304 0 0 0 100 5 0 0 3 221 107 44 1 0 1 0 1049 0 1 0 99 6 0 0 14 8 1 4 1 0 0 0 266 0 0 0 100 7 0 0 10 213 105 8 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2103 100 104 0 0 1 0 0 0 1 0 99 1 0 0 0 20 1 12 0 0 1 0 0 0 0 0 100 2 0 0 0 108 51 100 0 0 1 0 0 0 0 0 100 3 0 0 0 15 4 8 0 0 3 0 599 0 0 0 100 4 0 0 0 27 8 20 1 0 4 0 332 0 0 0 100 5 1 0 7 226 109 46 1 0 1 0 1058 0 1 0 99 6 0 0 14 13 3 8 0 1 1 0 268 0 0 0 100 7 0 0 14 213 104 10 0 1 0 0 260 0 0 0 100 March 2, 2026 at 06:54:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 102 0 3 0 0 0 0 1 0 99 1 0 0 0 18 1 14 0 0 1 0 0 0 0 0 100 2 0 0 0 107 50 104 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 1 0 3 0 600 0 0 0 100 4 0 0 0 25 7 18 0 1 0 0 308 0 0 0 100 5 0 0 3 227 106 54 1 1 0 0 1050 0 1 0 99 6 0 0 14 10 2 8 0 0 3 0 266 0 0 0 100 7 0 0 10 212 104 8 0 0 2 0 260 0 0 0 100 March 2, 2026 at 06:54:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 102 0 0 0 0 0 0 1 0 99 1 0 0 0 16 0 12 0 1 0 0 3 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 6 1 0 1 0 600 0 0 0 100 4 0 0 0 20 7 16 0 0 0 0 306 0 0 0 100 5 0 0 3 222 106 46 1 0 2 0 1365 0 0 0 99 6 0 0 14 24 6 26 0 1 1 0 273 0 0 0 100 7 7 0 10 211 104 6 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2103 100 104 0 0 0 0 0 0 1 0 99 1 0 0 0 15 0 10 0 0 0 0 0 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 8 0 0 3 0 599 0 0 0 100 4 0 0 0 15 4 12 0 0 5 0 309 0 0 0 100 5 0 0 3 219 107 38 0 0 0 0 1052 0 0 0 100 6 0 0 14 34 11 36 1 0 0 0 292 0 0 0 100 7 0 0 10 215 104 12 0 0 0 0 263 0 0 0 100 March 2, 2026 at 06:54:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 0 2151 100 145 0 12 6 2 181 0 1 0 99 1 22 0 0 47 0 44 0 9 4 5 61 0 0 0 100 2 19 0 0 138 50 132 0 9 4 3 54 0 0 0 100 3 34 0 0 48 4 32 0 5 8 1 627 0 0 0 100 4 25 0 0 46 8 29 1 4 4 0 388 0 0 0 100 5 3250 0 116 235 102 94 5 1 9 13 2383 2 2 0 96 6 122 0 14 59 6 89 0 13 10 19 441 0 0 0 100 7 20 0 13 254 105 72 0 13 7 9 426 0 0 0 100 March 2, 2026 at 06:54:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 118 0 1 0 0 0 0 1 0 99 1 0 0 0 17 1 12 0 1 0 0 0 0 0 0 100 2 0 0 0 110 52 106 0 1 1 0 1 0 0 0 100 3 0 0 0 14 4 8 1 0 4 0 601 0 0 0 100 4 0 0 0 15 5 10 0 1 1 0 304 0 0 0 100 5 0 0 3 214 103 38 1 1 1 0 1122 0 0 0 100 6 0 0 14 19 7 16 0 0 1 0 271 0 0 0 100 7 0 0 10 213 104 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 100 108 0 1 0 0 0 0 1 0 99 1 0 0 0 18 1 14 0 0 1 0 0 0 0 0 100 2 0 0 0 107 50 104 0 0 0 0 0 0 0 0 100 3 0 0 0 14 3 8 1 0 1 0 604 0 0 0 100 4 0 0 0 18 5 16 0 0 2 0 311 0 0 0 100 5 0 0 3 217 104 42 1 0 0 0 1125 0 0 0 99 6 0 0 14 19 6 18 0 0 2 0 589 0 0 0 100 7 0 0 10 213 104 10 0 0 2 0 260 0 0 0 100 March 2, 2026 at 06:54:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 44 0 1 0 0 0 0 1 0 99 1 0 0 0 74 0 70 0 1 0 0 0 0 0 0 100 2 0 0 0 111 50 110 0 1 0 0 0 0 0 0 100 3 0 0 0 14 4 10 0 2 1 0 600 0 0 0 100 4 0 0 0 15 5 10 0 0 1 0 305 0 0 0 100 5 0 0 3 225 109 50 0 0 0 0 1135 0 0 0 99 6 0 0 14 13 4 10 0 0 0 0 268 0 0 0 100 7 0 0 10 211 104 6 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 54 0 3 0 0 1 0 1 0 99 1 0 0 0 75 0 68 0 1 0 0 0 0 0 0 100 2 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 3 0 0 0 20 3 18 0 1 5 0 621 0 0 0 100 4 0 0 0 20 6 16 1 0 10 0 312 0 0 0 100 5 0 0 3 235 115 52 2 0 0 0 1139 0 0 0 99 6 0 0 14 17 4 16 0 0 0 0 280 0 0 0 100 7 0 0 10 217 105 14 0 0 0 0 264 0 0 0 100 March 2, 2026 at 06:54:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 108 0 1 0 0 0 0 1 0 99 1 0 0 0 14 1 10 0 1 1 0 9 0 0 0 100 2 0 0 0 108 50 106 0 1 0 0 18 0 0 0 100 3 0 0 0 10 2 4 1 0 1 0 598 0 0 0 100 4 0 0 0 17 5 10 0 0 3 0 305 0 0 0 100 5 0 0 3 221 107 42 1 0 0 0 1127 0 0 0 99 6 0 0 14 10 2 6 1 0 0 0 266 0 0 0 100 7 0 0 10 213 105 8 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 98 0 0 2246 102 398 9 51 8 0 2107 1 1 0 97 1 74 0 0 107 4 297 8 35 4 0 1653 2 1 0 97 2 238 0 0 271 51 464 20 54 9 2 1734 2 1 0 98 3 182 0 0 139 4 317 11 53 11 0 2473 2 1 0 98 4 111 0 0 185 10 408 14 60 11 0 2469 2 1 0 97 5 23 0 3 283 105 181 7 23 3 0 2404 3 1 0 96 6 5 0 14 125 5 282 7 48 4 0 2448 1 1 0 98 7 313 0 94 308 105 221 10 34 6 0 2406 2 1 0 97 March 2, 2026 at 06:54:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2166 101 214 0 15 134 0 0 0 1 0 99 1 0 0 0 72 2 126 0 27 144 0 0 0 0 0 100 2 0 0 0 241 50 375 0 30 108 0 0 0 0 0 100 3 0 0 0 181 95 166 1 26 159 0 611 0 0 0 99 4 0 0 0 92 4 158 0 31 144 0 294 0 0 0 100 5 0 0 3 271 102 154 1 17 147 0 1134 0 1 0 99 6 0 0 14 66 3 122 0 21 111 0 267 0 0 0 100 7 0 0 10 258 104 105 0 12 118 0 260 0 0 0 100 March 2, 2026 at 06:54:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 100 0 1 0 0 0 0 1 0 99 1 0 0 0 16 0 12 0 0 0 0 3 0 0 0 100 2 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 3 0 0 0 28 11 24 0 0 9 0 612 0 0 0 100 4 0 0 0 16 5 8 1 0 10 0 296 0 0 0 100 5 0 0 3 210 102 34 1 0 1 0 1134 0 0 0 100 6 0 0 14 9 2 6 0 1 0 0 266 0 0 0 100 7 0 0 10 211 104 6 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 100 108 0 1 0 0 3 0 1 0 99 1 0 0 0 15 0 10 0 0 0 0 0 0 0 0 100 2 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 3 0 0 0 30 11 26 1 0 7 0 611 0 0 0 100 4 0 0 0 16 4 12 0 0 7 0 299 0 0 0 100 5 0 0 3 224 108 50 1 1 2 0 1139 0 0 0 100 6 0 0 14 16 4 16 0 0 0 0 278 0 0 0 100 7 0 0 10 214 104 10 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2113 100 119 0 10 8 0 25 0 1 0 99 1 0 0 14 20 0 21 0 7 12 0 6 0 0 0 100 2 0 0 0 120 50 116 0 2 1 0 21 0 0 0 100 3 0 0 9 37 11 32 0 3 17 0 623 0 1 0 99 4 0 0 0 33 6 29 1 2 9 0 325 0 0 0 100 5 0 0 3 232 102 61 1 5 6 0 1077 0 0 0 100 6 0 0 14 18 2 13 1 2 5 0 338 0 0 0 100 7 0 0 10 226 106 28 0 2 5 1 347 0 0 0 100 March 2, 2026 at 06:54:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 112 0 1 0 0 3 0 1 0 99 1 0 0 7 10 0 7 0 3 0 0 0 0 0 0 100 2 0 0 0 108 51 102 0 0 0 0 1 0 0 0 100 3 0 0 0 12 3 6 0 0 2 0 598 0 0 0 100 4 0 0 0 16 4 6 0 0 0 0 294 0 0 0 100 5 0 0 3 212 102 34 1 0 1 0 1044 0 0 0 100 6 0 0 14 12 3 8 0 0 0 0 267 0 0 0 100 7 0 0 10 231 113 26 0 0 0 0 275 0 0 0 100 March 2, 2026 at 06:54:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2127 102 116 0 0 0 0 2 0 1 0 99 1 0 0 112 15 1 11 0 0 1 0 0 0 0 0 100 2 0 0 0 125 50 106 0 1 0 0 0 0 0 0 100 3 0 0 0 28 3 6 1 0 3 0 606 0 0 0 100 4 0 0 0 32 5 10 1 0 5 0 296 0 0 0 100 5 0 0 3 229 102 36 1 1 0 0 1044 0 1 0 99 6 0 0 14 31 2 18 0 1 2 0 266 0 0 0 100 7 0 0 10 241 110 22 0 0 3 0 269 0 0 0 100 March 2, 2026 at 06:54:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 103 116 0 0 0 0 5 0 1 0 99 1 0 0 7 10 0 6 0 0 0 0 1 0 0 0 100 2 0 0 0 107 50 102 0 0 0 0 1 0 0 0 100 3 0 0 0 15 4 8 1 0 5 0 597 0 0 0 100 4 0 0 0 15 5 8 0 0 3 0 295 0 0 0 100 5 0 0 3 214 103 36 1 0 0 0 1046 0 0 0 99 6 0 0 14 12 2 8 0 0 0 0 266 0 0 0 100 7 0 0 10 229 110 28 0 1 0 0 269 0 0 0 100 March 2, 2026 at 06:54:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 2854 104 1359 24 245 20 0 6326 6 3 0 91 1 16 0 0 761 3 1309 39 269 22 0 6714 6 2 0 92 2 6 0 0 674 19 1096 27 191 73 0 5726 6 2 0 92 3 17 0 0 694 6 1308 43 257 23 0 8497 5 2 0 93 4 3 0 0 748 29 1296 33 251 16 0 6387 6 2 0 92 5 3 0 3 791 109 1016 33 161 16 1 6242 5 2 0 93 6 2 0 14 683 6 1264 32 248 66 0 7252 7 2 0 91 7 34 0 374 700 115 882 17 138 42 0 4567 5 2 0 93 March 2, 2026 at 06:54:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 100 74 0 3 0 0 0 0 1 0 99 1 0 0 0 60 2 52 0 1 0 0 3 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 8 0 0 7 0 598 0 0 0 100 4 0 0 0 114 54 106 0 0 4 0 294 0 0 0 100 5 0 0 3 212 102 36 1 0 1 0 1053 0 1 0 99 6 0 0 14 16 5 12 1 0 0 0 269 0 0 0 100 7 0 0 10 227 111 20 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:54:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 0 2136 100 119 0 10 5 0 97 0 1 0 99 1 8 0 0 64 3 51 0 7 5 1 70 0 0 0 100 2 2614 0 114 32 1 57 2 9 9 7 400 1 1 0 99 3 147 0 0 58 5 78 0 12 23 14 803 0 0 0 100 4 19 0 3 154 56 158 0 12 15 8 441 0 0 0 100 5 25 0 7 248 102 84 1 11 5 5 1271 0 1 0 99 6 642 0 14 34 3 24 1 5 4 3 1158 1 0 0 98 7 23 0 14 250 110 42 0 6 5 2 316 0 0 0 100 March 2, 2026 at 06:54:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2184 100 190 0 28 214 0 0 0 1 0 99 1 0 0 0 146 1 210 0 32 217 0 0 0 1 0 99 2 0 0 0 67 0 127 0 16 167 0 0 0 0 0 100 3 0 0 0 165 87 309 1 31 202 0 600 0 1 0 99 4 0 0 0 190 54 264 1 30 264 0 294 0 1 0 99 5 0 0 3 275 102 177 1 25 211 0 1138 0 1 0 99 6 0 0 14 75 1 152 0 31 244 0 266 0 1 0 99 7 0 0 10 279 108 142 0 23 152 0 265 0 0 0 99 March 2, 2026 at 06:54:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 2 0 1 0 99 1 0 0 0 15 0 10 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 1 0 0 0 0 0 100 3 0 0 0 13 3 8 1 1 4 0 599 0 0 0 100 4 0 0 0 118 55 116 0 1 5 0 296 0 0 0 100 5 0 0 3 211 102 34 1 0 0 0 1127 0 0 0 100 6 0 0 14 9 1 8 0 0 0 0 271 0 0 0 100 7 0 0 10 223 109 20 0 0 0 0 585 0 0 0 100 March 2, 2026 at 06:54:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2120 108 120 0 2 0 0 13 0 1 0 99 1 0 0 0 16 0 10 0 0 0 0 0 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 3 0 0 0 100 3 0 0 0 12 3 8 0 0 6 0 601 0 0 0 100 4 0 0 0 125 54 123 0 2 3 0 308 0 0 0 100 5 0 0 3 228 108 52 1 1 1 0 1155 0 0 0 100 6 0 0 14 13 3 12 0 0 0 0 273 0 0 0 100 7 0 0 10 216 105 10 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 147 0 0 2195 104 290 8 29 4 2 1914 2 1 0 96 1 316 0 0 140 32 223 5 31 3 0 1635 2 1 0 98 2 4 0 0 104 0 232 4 32 5 0 1553 1 0 0 99 3 182 0 0 98 5 289 4 38 11 0 2192 1 0 0 98 4 213 0 0 115 23 256 7 38 9 1 1772 1 0 0 99 5 17 0 3 254 104 129 17 14 1 0 2121 3 1 0 96 6 76 0 14 51 1 109 5 16 1 0 1201 2 0 0 97 7 105 0 108 310 106 330 3 26 3 0 1772 1 0 0 98 March 2, 2026 at 06:54:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 106 0 1 0 0 4 0 1 0 99 1 0 0 0 72 28 64 0 0 0 0 0 0 0 0 100 2 0 0 0 52 23 46 0 1 0 0 0 0 0 0 100 3 0 0 0 12 3 6 1 0 3 0 602 0 0 0 100 4 0 0 0 13 4 8 1 0 0 0 294 0 0 0 100 5 0 0 3 213 102 36 1 1 0 0 1133 0 0 0 100 6 0 0 14 12 1 14 0 1 0 0 266 0 0 0 100 7 0 0 10 232 114 26 0 0 0 0 274 0 0 0 100 March 2, 2026 at 06:54:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2192 103 259 0 28 136 0 22 0 1 0 99 1 0 0 0 88 1 153 1 19 140 0 27 0 1 0 99 2 0 0 0 156 43 214 0 26 169 0 14 0 0 0 100 3 0 0 0 156 95 284 0 27 109 0 617 0 1 0 99 4 0 0 8 106 12 176 0 25 153 0 363 0 1 0 99 5 0 0 3 277 102 167 1 17 114 0 1216 0 1 0 99 6 0 0 28 95 1 182 0 36 174 0 280 0 1 0 99 7 0 0 10 289 111 144 1 24 157 0 304 0 1 0 99 March 2, 2026 at 06:54:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2118 106 120 0 0 0 0 7 0 1 0 99 1 0 0 7 9 0 4 0 2 0 0 0 0 0 0 100 2 0 0 0 15 0 8 0 1 0 0 0 0 0 0 100 3 0 0 0 14 4 8 0 0 2 0 598 0 0 0 100 4 0 0 0 117 56 110 0 0 1 0 296 0 0 0 100 5 0 0 3 212 102 34 1 0 0 0 1047 0 0 0 100 6 0 0 14 10 1 7 0 1 0 0 266 0 0 0 100 7 0 0 10 217 105 10 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:54:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2147 110 138 0 3 1 0 16 0 1 0 99 1 0 0 0 34 4 10 0 1 0 0 6 0 0 0 100 2 0 0 0 30 0 8 0 1 0 0 0 0 0 0 100 3 0 0 0 34 5 16 0 2 1 0 649 0 0 0 100 4 0 0 0 140 58 122 0 0 0 0 310 0 0 0 100 5 1 0 3 234 107 38 1 0 0 0 1052 0 0 0 100 6 0 0 126 12 1 11 1 0 0 0 271 0 0 0 100 7 0 0 10 237 106 14 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2120 107 112 1 0 0 0 13 0 1 0 99 1 0 0 0 17 0 12 0 1 0 0 0 0 0 0 100 2 0 0 0 13 1 12 0 1 0 0 0 0 0 0 100 3 0 0 0 19 2 12 1 0 2 0 601 0 0 0 100 4 0 0 0 114 54 106 1 0 0 0 294 0 0 0 100 5 0 0 3 213 102 36 1 1 0 0 1047 0 0 0 100 6 0 0 21 11 1 6 0 0 0 0 266 0 0 0 100 7 0 0 10 216 106 10 0 0 0 0 261 0 0 0 100 March 2, 2026 at 06:54:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 20 0 0 2891 108 1450 45 258 32 0 6432 6 3 0 91 1 15 0 7 790 1 1399 48 277 15 0 7995 7 2 0 91 2 0 0 0 703 3 1166 17 215 23 0 5773 6 2 0 92 3 20 0 0 691 5 1310 43 278 40 0 8555 6 2 0 92 4 0 0 0 730 38 1243 29 236 25 0 6984 5 2 0 93 5 3 0 3 801 117 948 14 160 9 1 3934 4 1 0 94 6 0 0 0 580 4 1015 28 219 23 1 6193 5 2 0 93 7 3 0 367 688 105 918 28 136 40 0 4581 5 2 0 93 March 2, 2026 at 06:54:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2183 103 249 0 23 256 0 0 0 1 0 99 1 0 0 7 90 8 164 0 26 219 0 266 0 1 0 99 2 0 0 0 78 0 157 1 25 197 0 0 0 1 0 99 3 0 0 0 166 81 320 1 37 217 0 611 0 1 0 99 4 0 0 0 85 4 191 2 35 247 0 1338 0 1 0 99 5 0 0 3 384 151 265 1 24 227 0 0 0 1 0 99 6 0 0 0 82 2 155 0 31 249 0 0 0 1 0 99 7 0 0 17 269 104 132 0 24 177 0 266 0 1 0 99 March 2, 2026 at 06:54:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 51 0 2 2135 102 140 0 6 4 6 85 0 1 0 99 1 15 0 7 50 9 41 1 8 3 2 383 0 0 0 100 2 2535 0 0 41 0 32 4 6 2 4 1205 2 1 0 98 3 28 0 0 54 2 65 0 9 16 8 724 0 0 0 100 4 12 0 0 54 6 87 1 10 20 5 1461 0 0 0 99 5 7 0 3 339 151 134 0 7 8 2 66 0 0 0 100 6 721 0 116 20 0 46 0 8 6 8 117 0 0 0 99 7 97 0 17 251 103 71 0 7 5 13 396 0 0 0 100 March 2, 2026 at 06:54:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 116 0 2 0 0 3 0 1 0 99 1 0 0 7 23 9 20 0 0 0 0 271 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 20 2 14 1 0 3 0 609 0 0 0 100 4 0 0 0 22 6 48 2 0 2 0 1435 0 0 0 99 5 0 0 3 315 156 106 0 0 1 0 7 0 0 0 100 6 0 0 0 9 0 6 0 0 0 0 5 0 0 0 100 7 0 0 17 213 103 8 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:54:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 103 114 0 2 0 0 1 0 1 0 99 1 0 0 7 27 10 22 0 1 0 0 589 0 0 0 100 2 0 0 0 12 0 8 0 1 0 0 5 0 0 0 100 3 0 0 0 11 3 6 0 0 4 0 602 0 0 0 100 4 0 0 0 19 5 44 1 0 5 0 1429 0 0 0 100 5 0 0 3 314 151 114 0 1 0 0 0 0 0 0 100 6 0 0 0 9 0 2 0 1 0 0 0 0 0 0 100 7 0 0 17 210 104 6 0 0 0 0 268 0 0 0 100 March 2, 2026 at 06:54:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 106 0 0 0 0 0 0 1 0 99 1 0 0 7 12 4 8 0 0 0 0 260 0 0 0 100 2 0 0 0 23 5 18 0 1 0 0 6 0 0 0 100 3 0 0 0 11 2 6 1 0 4 0 609 0 0 0 100 4 0 0 0 13 4 36 1 0 2 0 1420 0 0 0 100 5 0 0 3 282 137 74 0 0 0 0 0 0 0 0 100 6 0 0 0 41 14 42 0 2 0 0 0 0 0 0 100 7 0 0 17 210 104 6 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:55:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2192 101 264 3 37 143 0 925 2 1 0 97 1 280 0 7 141 4 350 4 54 139 0 1879 2 1 0 98 2 108 0 0 116 3 211 7 33 141 0 1402 3 1 0 96 3 421 0 0 197 69 338 4 56 160 0 2461 2 1 0 97 4 14 0 0 187 6 519 3 50 109 0 3072 1 1 0 98 5 0 0 3 317 101 321 7 42 125 0 1433 1 1 0 98 6 59 0 0 198 31 465 3 55 112 0 1472 1 1 0 99 7 18 0 87 315 123 286 3 35 94 0 1735 2 1 0 98 March 2, 2026 at 06:55:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 107 130 0 1 0 0 20 0 1 0 99 1 0 0 7 15 4 10 0 1 8 0 269 0 0 0 100 2 0 0 0 20 1 14 0 0 0 0 7 0 0 0 100 3 0 0 0 21 5 19 1 2 4 0 615 0 0 0 100 4 0 0 0 20 5 42 2 1 1 0 1430 0 0 0 100 5 0 0 3 213 102 4 0 1 6 0 10 0 0 0 100 6 14 0 0 12 0 7 0 1 3 0 22 0 0 0 100 7 0 0 31 314 153 118 0 1 0 0 269 0 0 0 100 March 2, 2026 at 06:55:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 8 2140 111 145 0 5 4 0 24 0 1 0 99 1 0 0 21 25 4 32 0 5 8 0 284 0 0 0 100 2 0 0 0 24 0 36 0 5 9 3 153 0 0 0 100 3 0 0 0 25 2 27 1 7 9 0 645 0 0 0 100 4 0 0 0 40 9 71 2 3 15 0 1454 0 0 0 99 5 0 0 3 224 106 18 0 4 6 1 13 0 0 0 100 6 0 0 0 29 1 33 0 11 10 0 21 0 0 0 100 7 0 0 24 322 154 125 0 3 11 0 267 0 0 0 100 March 2, 2026 at 06:55:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2106 101 106 0 1 0 0 0 0 1 0 99 1 0 0 7 17 4 15 0 0 0 0 269 0 0 0 100 2 0 0 0 17 0 12 0 0 0 0 18 0 0 0 100 3 0 0 0 33 12 24 0 0 7 0 611 0 0 0 100 4 0 0 0 15 4 38 1 1 3 0 1344 0 0 0 100 5 0 0 3 209 101 2 0 0 0 0 0 0 0 0 100 6 0 0 0 12 0 4 0 1 0 0 0 0 0 0 100 7 0 0 17 314 154 108 1 0 0 0 267 0 0 0 100 March 2, 2026 at 06:55:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2123 101 100 0 2 1 0 0 0 1 0 99 1 0 0 119 28 4 19 0 2 1 0 260 0 0 0 100 2 0 0 0 39 1 20 0 2 1 0 0 0 0 0 100 3 0 0 0 47 12 22 1 0 2 0 610 0 0 0 100 4 0 0 0 87 31 92 1 3 2 0 1340 0 0 0 99 5 0 0 7 236 106 12 0 1 1 0 0 0 0 0 100 6 0 0 0 58 16 34 0 1 1 0 1 0 0 0 100 7 0 0 21 239 110 16 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:55:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2152 106 185 0 10 48 0 3 0 1 0 99 1 0 0 14 68 3 123 0 19 48 0 260 0 0 0 100 2 0 0 0 54 0 82 0 8 45 0 0 0 0 0 100 3 0 0 0 135 72 111 1 18 70 0 620 0 0 0 99 4 0 0 0 104 4 220 1 16 51 0 1337 0 0 0 99 5 0 0 3 260 101 102 0 14 63 0 0 0 0 0 100 6 0 0 0 139 45 179 0 12 46 0 0 0 0 0 100 7 0 0 17 239 103 68 0 8 41 0 266 0 0 0 100 March 2, 2026 at 06:55:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 2777 143 1313 30 173 48 0 4132 5 2 0 92 1 35 0 16 538 4 929 35 206 21 0 5421 4 2 0 94 2 58 0 0 517 0 898 21 147 14 0 4345 4 1 0 94 3 15 0 0 552 16 977 28 173 12 0 5594 4 2 0 94 4 0 0 0 467 8 827 19 164 50 0 5531 4 2 0 94 5 5 0 3 609 104 708 13 113 14 0 3585 3 1 0 95 6 1 0 0 400 0 756 12 159 24 0 4308 3 1 0 96 7 1 0 255 531 103 670 6 103 12 0 4054 4 1 0 95 March 2, 2026 at 06:55:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2352 107 522 11 91 3 0 1757 2 1 0 96 1 0 0 7 274 4 464 19 83 7 0 2718 2 1 0 97 2 0 0 0 195 1 286 6 57 14 0 1910 2 1 0 98 3 0 0 0 222 4 373 12 81 14 0 2436 2 1 0 98 4 0 0 0 221 5 408 11 76 6 0 2985 2 1 0 97 5 0 0 3 460 156 344 2 45 2 0 1267 1 0 0 98 6 1 0 0 172 2 297 8 73 13 0 2014 1 0 0 98 7 0 0 129 354 104 272 6 46 3 0 1719 1 1 0 98 March 2, 2026 at 06:55:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2116 106 116 0 0 0 0 9 0 1 0 99 1 0 0 7 11 3 8 0 0 0 0 263 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 21 1 22 0 1 4 0 309 0 0 0 100 4 0 0 0 18 6 40 1 0 1 0 1345 0 0 0 100 5 0 0 3 310 152 104 0 0 0 0 1 0 0 0 100 6 0 0 0 17 4 12 0 1 2 0 298 0 0 0 100 7 0 0 17 208 103 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 105 112 0 0 0 0 5 0 1 0 99 1 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 16 1 12 0 0 0 0 303 0 0 0 100 4 0 0 0 16 5 38 2 0 0 0 1342 0 0 0 100 5 0 0 3 308 151 102 0 0 0 0 0 0 0 0 100 6 0 0 0 12 1 6 1 0 3 0 294 0 0 0 100 7 0 0 17 210 104 6 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:55:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2170 105 217 0 26 187 0 8 0 1 0 99 1 0 0 7 77 3 142 0 31 245 0 261 0 1 0 99 2 0 0 0 66 1 123 1 17 154 0 1 0 0 0 100 3 0 0 0 169 83 157 0 32 278 0 319 0 1 0 99 4 0 0 0 174 6 366 0 33 227 0 1345 0 1 0 99 5 0 0 3 364 145 231 0 24 263 0 0 0 1 0 99 6 0 0 0 107 12 184 0 23 202 0 303 0 1 0 99 7 0 0 17 277 104 149 0 21 182 0 266 0 1 0 99 March 2, 2026 at 06:55:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 104 110 0 0 0 0 324 0 1 0 99 1 0 0 7 22 8 20 0 0 0 0 268 0 0 0 100 2 0 0 0 7 0 4 0 0 0 0 6 0 0 0 100 3 0 0 0 18 2 14 0 0 2 0 306 0 0 0 100 4 0 0 0 19 6 42 1 0 0 0 1345 0 0 0 100 5 0 0 3 213 101 12 0 1 1 0 0 0 0 0 100 6 0 0 0 111 51 106 0 0 1 0 294 0 0 0 100 7 0 0 17 207 102 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 38 0 0 2144 102 149 0 9 5 6 93 0 1 0 99 1 33 0 7 55 7 64 0 8 5 6 419 0 0 0 100 2 727 0 121 21 0 45 0 6 7 10 152 0 0 0 99 3 123 0 0 65 2 78 1 10 16 13 474 0 0 0 100 4 20 0 2 58 9 87 1 13 7 2 1492 0 0 0 99 5 10 0 3 243 106 35 0 10 7 2 62 0 0 0 100 6 642 0 0 138 46 129 1 4 7 3 1212 1 0 0 98 7 1893 0 17 260 111 54 3 8 4 5 598 0 1 0 99 March 2, 2026 at 06:55:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 106 0 0 0 0 0 0 1 0 99 1 0 0 7 27 10 20 0 0 0 0 271 0 0 0 100 2 0 0 0 6 0 2 0 1 1 0 3 0 0 0 100 3 0 0 0 17 1 14 0 0 4 0 319 0 0 0 100 4 0 0 0 16 5 38 2 0 0 0 1430 0 0 0 100 5 0 0 3 210 101 4 0 0 0 0 0 0 0 0 100 6 0 0 0 17 1 20 1 1 1 0 294 0 0 0 100 7 0 0 17 311 154 108 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:55:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 104 0 0 1 0 0 0 1 0 99 1 0 0 7 25 8 18 0 0 1 0 267 0 0 0 100 2 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 3 0 0 0 19 2 12 0 0 4 0 310 0 0 0 100 4 0 0 0 22 7 42 1 0 1 0 1427 0 0 0 99 5 0 0 7 209 101 4 0 1 0 0 0 0 0 0 100 6 0 0 0 17 3 8 0 0 7 0 295 0 0 0 100 7 0 0 21 315 153 114 0 1 1 0 284 0 0 0 100 March 2, 2026 at 06:55:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 105 118 0 0 0 0 10 0 1 0 99 1 0 0 7 19 6 16 0 0 0 0 580 0 0 0 100 2 0 0 0 7 0 4 0 0 0 0 5 0 0 0 100 3 0 0 0 19 1 16 0 0 3 0 303 0 0 0 100 4 0 0 0 18 6 42 1 0 2 0 1426 0 0 0 100 5 0 0 3 209 101 4 0 0 1 0 0 0 0 0 100 6 0 0 0 12 1 8 0 0 12 0 294 0 0 0 100 7 0 0 17 309 153 106 0 0 2 0 266 0 0 0 100 March 2, 2026 at 06:55:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2115 107 116 1 2 0 0 8 0 1 0 99 1 0 0 7 16 3 18 0 1 0 0 260 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 18 1 14 1 1 0 0 320 0 0 0 100 4 0 0 0 19 7 42 1 0 0 0 1429 0 0 0 100 5 0 0 3 208 101 2 0 0 0 0 0 0 0 0 100 6 0 0 0 11 1 4 0 0 0 0 294 0 0 0 100 7 0 0 17 313 153 107 0 2 1 0 266 0 0 0 100 March 2, 2026 at 06:55:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2116 105 102 0 2 0 0 11 0 1 0 99 1 0 0 7 34 3 28 0 1 1 0 260 0 0 0 100 2 0 0 0 11 0 12 0 1 0 0 0 0 0 0 100 3 0 0 0 12 1 10 0 0 4 0 324 0 0 0 100 4 0 0 0 25 7 52 2 1 0 0 1436 0 0 0 100 5 21 0 3 218 108 8 0 0 0 0 12 0 0 0 100 6 23 0 0 14 2 12 1 0 2 0 306 0 0 0 100 7 0 0 17 312 153 108 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2119 107 126 0 0 0 0 9 0 1 0 99 1 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 3 0 0 0 100 3 0 0 0 10 1 6 0 1 0 0 307 0 0 0 100 4 0 0 0 16 6 40 0 0 0 0 1424 0 0 0 100 5 0 0 3 210 102 4 0 0 0 0 1 0 0 0 100 6 0 0 0 15 3 8 0 1 0 0 296 0 0 0 100 7 0 0 17 309 153 106 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 104 118 1 0 0 0 323 0 1 0 99 1 0 0 7 21 7 20 0 0 0 0 270 0 0 0 100 2 0 0 0 9 0 6 0 1 0 0 5 0 0 0 100 3 0 0 0 11 1 6 0 0 2 0 315 0 0 0 100 4 0 0 0 20 5 48 1 1 0 0 1422 0 0 0 100 5 0 0 3 210 102 4 0 0 0 0 1 0 0 0 100 6 0 0 0 14 3 10 0 0 2 0 298 0 0 0 100 7 0 0 17 308 153 104 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 112 0 0 0 0 0 0 1 0 99 1 0 0 7 24 8 22 1 0 0 0 269 0 0 0 100 2 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 3 0 0 0 12 1 10 0 0 1 0 312 0 0 0 100 4 0 0 0 26 9 48 1 0 1 0 1427 0 0 0 100 5 0 0 3 213 101 14 0 1 2 0 0 0 0 0 100 6 0 0 0 11 1 8 0 1 5 0 294 0 0 0 100 7 0 0 17 309 153 106 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:55:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 112 0 0 0 0 0 0 1 0 99 1 0 0 7 22 9 18 0 0 0 0 268 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 13 2 10 0 0 3 0 315 0 0 0 100 4 0 0 0 16 5 38 2 0 0 0 1423 0 0 0 100 5 0 0 3 208 101 2 0 0 0 0 0 0 0 0 100 6 0 0 0 12 2 6 1 0 1 0 294 0 0 0 100 7 0 0 17 308 153 104 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 330 0 0 2191 102 319 8 41 9 0 2446 2 1 0 96 1 335 0 7 111 8 257 1 29 5 0 1703 1 0 0 98 2 75 0 0 72 0 173 9 26 1 0 1146 2 0 0 98 3 0 0 0 79 1 212 11 39 1 0 1983 1 0 0 98 4 0 0 0 118 7 276 5 30 4 0 2997 1 1 0 98 5 3 0 3 270 107 159 8 18 1 0 794 3 0 0 97 6 232 0 0 96 2 230 7 32 3 0 1741 1 1 0 98 7 207 0 87 369 154 310 10 28 1 0 2036 2 1 0 98 March 2, 2026 at 06:55:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 110 0 3 1 0 11 0 1 0 99 1 17 0 7 15 3 10 0 1 0 0 274 0 0 0 100 2 0 0 0 12 1 6 0 2 0 0 14 0 0 0 100 3 0 0 0 19 1 16 0 3 4 0 316 0 0 0 100 4 0 0 0 23 6 50 0 1 0 0 1448 0 0 0 100 5 0 0 3 230 108 22 0 1 0 0 26 0 0 0 100 6 0 0 0 32 5 28 0 1 2 0 349 0 0 0 100 7 4 0 31 311 154 108 0 1 0 0 284 0 0 0 100 March 2, 2026 at 06:55:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 106 0 0 1 0 0 0 1 0 99 1 0 0 7 17 4 10 0 0 1 0 260 0 0 0 100 2 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 3 0 0 0 18 2 10 0 0 2 0 293 0 0 0 100 4 0 0 0 41 16 62 2 1 0 0 1448 0 0 0 99 5 0 0 7 209 101 2 0 0 1 0 0 0 0 0 100 6 0 0 0 15 4 6 0 0 1 0 295 0 0 0 100 7 0 0 21 310 153 106 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:55:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2164 101 213 0 19 150 0 0 0 1 0 99 1 0 0 7 84 3 159 1 28 146 0 260 0 0 0 100 2 0 0 0 67 0 130 0 21 153 0 0 0 0 0 100 3 0 0 0 169 88 136 2 33 124 0 301 0 0 0 99 4 0 0 0 103 11 205 3 29 171 0 1443 0 1 0 99 5 0 0 3 313 103 202 1 25 123 0 2 0 1 0 99 6 0 0 0 121 2 232 1 34 175 0 297 0 0 0 99 7 0 0 17 380 153 256 0 20 157 0 266 0 1 0 99 March 2, 2026 at 06:55:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 114 0 1 0 0 0 0 1 0 99 1 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 15 1 10 0 0 4 0 300 0 0 0 100 4 0 0 0 15 5 38 1 0 1 0 1436 0 0 0 100 5 0 0 3 220 107 14 0 0 0 0 9 0 0 0 100 6 0 0 0 13 3 8 0 0 5 0 295 0 0 0 100 7 0 0 17 310 153 106 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 8 2115 101 45 0 7 8 0 0 0 1 0 99 1 0 0 7 26 4 27 0 5 11 0 292 0 0 0 100 2 0 0 14 12 0 14 0 8 11 0 9 0 0 0 100 3 0 0 7 110 2 110 0 6 3 0 318 0 0 0 100 4 0 0 0 33 6 67 1 1 5 1 1447 0 0 0 99 5 0 0 3 249 116 42 0 2 6 0 50 0 0 0 100 6 1 0 0 22 2 19 0 1 5 0 321 0 0 0 100 7 0 0 17 323 153 122 1 2 5 0 344 0 0 0 100 March 2, 2026 at 06:55:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 98 0 2 0 0 0 0 1 0 99 1 0 0 7 24 3 16 0 1 0 0 260 0 0 0 100 2 0 0 0 13 0 13 0 2 0 0 0 0 0 0 100 3 0 0 0 18 1 12 0 1 6 0 296 0 0 0 100 4 0 0 7 20 6 44 1 2 0 0 1349 0 0 0 100 5 0 0 3 231 111 24 1 0 0 0 17 0 0 0 100 6 0 0 0 16 3 8 0 1 5 0 295 0 0 0 100 7 0 0 17 310 153 106 0 0 0 0 269 0 0 0 100 March 2, 2026 at 06:55:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 103 112 0 0 0 0 0 0 1 0 99 1 0 0 7 30 4 10 0 1 1 0 260 0 0 0 100 2 0 0 112 13 2 7 0 1 0 0 0 0 0 0 100 3 0 0 0 41 2 24 0 2 2 0 298 0 0 0 100 4 0 0 0 34 5 40 2 0 0 0 1346 0 0 0 100 5 0 0 3 245 111 24 0 1 1 0 15 0 0 0 100 6 0 0 0 30 3 9 1 1 4 0 294 0 0 0 100 7 0 0 17 325 153 106 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 101 106 0 1 0 0 0 0 1 0 99 1 0 0 7 17 3 14 0 0 0 0 260 0 0 0 100 2 0 0 7 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 18 1 12 0 0 6 0 305 0 0 0 100 4 0 0 0 20 7 44 0 0 0 0 1348 0 0 0 100 5 0 0 3 229 110 22 0 0 1 0 11 0 0 0 100 6 0 0 0 14 2 10 0 0 3 0 297 0 0 0 100 7 0 0 17 310 153 106 0 0 2 0 266 0 0 0 100 March 2, 2026 at 06:55:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 2848 105 1437 36 248 32 0 6086 6 3 0 91 1 1 0 7 703 4 1311 34 272 21 0 7643 7 2 0 91 2 0 0 0 685 8 1171 28 186 24 0 5327 5 2 0 93 3 2 0 0 702 4 1346 45 229 36 0 7504 6 2 0 92 4 1 0 0 585 7 1032 29 226 25 0 6844 5 2 0 93 5 2 0 3 793 107 1027 16 157 28 0 4254 5 1 0 94 6 0 0 0 590 5 1079 25 219 43 0 6302 5 2 0 93 7 0 0 353 741 143 955 16 147 20 0 4271 5 2 0 93 March 2, 2026 at 06:55:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 110 0 1 0 0 1 0 1 0 99 1 0 0 7 15 3 8 2 0 0 0 270 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 6 0 0 0 100 3 0 0 0 18 2 15 0 1 4 0 321 0 0 0 100 4 0 0 0 26 7 52 1 0 0 0 1359 0 0 0 100 5 0 0 3 223 106 18 0 2 0 0 9 0 0 0 100 6 0 0 0 13 2 10 0 0 1 0 299 0 0 0 100 7 0 0 17 313 154 108 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:55:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1898 0 0 2145 101 155 2 11 5 4 449 0 1 0 98 1 658 0 7 51 4 56 1 9 9 8 1204 1 0 0 98 2 16 0 0 55 7 61 0 10 8 7 106 0 0 0 100 3 5 0 0 42 1 37 1 7 4 3 395 0 0 0 100 4 8 0 0 42 4 56 2 4 3 0 1465 0 0 0 100 5 722 0 116 219 101 42 0 4 6 8 112 0 0 0 99 6 144 0 0 50 2 67 1 12 16 12 432 0 0 0 100 7 15 0 19 343 156 140 1 6 6 5 389 0 0 0 100 March 2, 2026 at 06:55:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 110 0 2 0 0 0 0 1 0 99 1 0 0 7 15 4 10 0 0 1 0 270 0 0 0 100 2 0 0 0 15 5 8 0 0 1 0 5 0 0 0 100 3 0 0 0 11 2 4 0 1 2 0 293 0 0 0 100 4 0 0 0 16 5 38 0 0 2 0 1428 0 0 0 100 5 0 0 3 212 102 6 0 0 2 0 2 0 0 0 100 6 0 0 0 25 4 18 0 2 3 0 295 0 0 0 100 7 0 0 17 311 153 108 0 1 1 0 266 0 0 0 100 March 2, 2026 at 06:55:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2205 105 298 0 38 244 0 261 0 1 0 99 1 0 0 0 107 6 199 0 35 305 0 12 0 1 0 99 2 0 0 0 92 3 170 0 27 228 0 321 0 1 0 99 3 0 0 0 185 94 174 0 37 217 0 303 0 1 0 99 4 0 0 0 98 5 212 1 39 224 0 1429 0 1 0 99 5 0 0 3 268 101 127 0 30 221 0 0 0 1 0 99 6 0 0 0 98 1 195 0 37 274 0 294 0 1 0 99 7 0 0 17 467 151 423 0 34 152 0 267 0 1 0 99 March 2, 2026 at 06:55:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2156 153 208 0 0 0 0 260 0 1 0 99 1 0 0 0 26 9 20 1 2 0 0 9 0 0 0 100 2 0 0 0 7 0 4 0 1 0 0 20 0 0 0 100 3 0 0 0 16 1 10 0 0 0 0 302 0 0 0 100 4 0 0 0 14 4 38 1 1 0 0 1428 0 0 0 100 5 0 0 3 210 102 4 0 0 0 0 2 0 0 0 100 6 0 0 0 9 1 4 0 0 0 0 294 0 0 0 100 7 0 0 17 209 103 4 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 141 0 7 2218 109 279 4 43 9 0 1874 1 1 0 98 1 0 0 0 178 4 257 7 37 1 0 1411 1 0 0 98 2 1 0 0 57 0 177 3 32 13 0 1286 1 0 0 98 3 71 0 0 86 3 157 6 33 10 0 1921 2 0 0 98 4 89 0 0 100 8 248 12 41 2 0 2201 2 1 0 98 5 1 0 3 290 114 159 8 35 1 0 1518 2 0 0 98 6 377 0 0 150 44 229 5 28 8 0 3383 3 1 0 96 7 172 0 101 262 105 197 3 30 8 0 1940 2 0 0 98 March 2, 2026 at 06:55:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2108 102 8 0 1 0 0 260 0 1 0 99 1 0 0 0 116 1 110 0 0 0 0 0 0 0 0 100 2 0 0 0 10 0 10 0 1 0 0 3 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 298 0 0 0 100 4 0 0 0 28 11 20 1 0 0 0 312 0 0 0 100 5 0 0 3 214 104 8 0 0 0 0 3 0 0 0 100 6 0 0 0 90 40 110 1 1 3 0 1429 0 0 0 100 7 0 0 17 235 116 32 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:55:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 28 2111 102 62 1 8 3 0 267 0 1 0 99 1 0 0 0 99 6 98 0 4 4 1 98 0 0 0 100 2 0 0 0 20 1 16 1 4 11 0 9 0 0 0 100 3 0 0 0 22 1 19 1 2 8 0 321 0 0 0 100 4 0 0 0 34 9 30 0 2 4 0 343 0 0 0 100 5 0 0 3 219 103 18 0 5 12 0 28 0 0 0 100 6 0 0 0 24 3 52 1 7 18 0 1421 0 0 0 100 7 0 0 25 318 153 119 0 7 16 0 273 0 1 0 99 March 2, 2026 at 06:55:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2161 102 230 0 20 101 0 260 0 1 0 99 1 0 0 7 86 8 143 0 27 148 0 9 0 0 0 99 2 0 0 0 58 0 109 0 24 130 0 0 0 0 0 100 3 0 0 0 141 70 133 0 26 163 0 300 0 0 0 99 4 0 0 0 79 4 139 0 26 142 0 300 0 0 0 100 5 0 0 3 256 103 100 0 17 115 0 2 0 1 0 99 6 0 0 0 139 2 295 1 36 102 0 1338 0 1 0 99 7 0 0 17 355 153 204 0 23 124 0 266 0 0 0 100 March 2, 2026 at 06:55:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 119 2113 104 121 0 0 0 0 264 0 1 0 99 1 0 0 0 39 6 18 0 1 0 0 6 0 0 0 100 2 0 0 0 27 2 8 0 1 0 0 3 0 0 0 100 3 0 0 0 27 2 6 0 0 1 0 297 0 0 0 100 4 0 0 0 43 8 186 1 1 0 0 633 0 0 0 100 5 0 0 3 229 103 10 0 1 0 0 4 0 0 0 100 6 0 0 0 28 2 36 1 0 1 0 1338 0 0 0 100 7 0 0 17 325 153 104 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2111 103 120 0 0 0 0 261 0 1 0 99 1 0 0 0 30 10 22 0 0 0 0 14 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 11 1 7 0 1 2 0 300 0 0 0 100 4 0 0 0 21 6 18 0 0 0 0 313 0 0 0 100 5 0 0 3 220 108 10 0 0 0 0 9 0 0 0 100 6 0 0 0 16 2 42 1 0 2 0 1346 0 0 0 100 7 0 0 17 314 154 110 0 1 0 0 267 0 0 0 100 March 2, 2026 at 06:55:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 7 2888 131 1501 42 243 43 1 6372 7 3 0 90 1 1 0 0 754 8 1409 43 296 59 1 7523 6 2 0 92 2 0 0 0 764 9 1344 32 193 46 0 5677 6 2 0 92 3 15 0 0 687 8 1241 32 241 20 0 7322 6 2 0 92 4 4 0 0 632 7 1120 35 238 58 0 6400 6 2 0 92 5 0 0 3 839 104 1083 23 167 47 0 4550 5 2 0 93 6 3 0 0 580 5 1105 31 224 39 0 7824 5 2 0 93 7 0 0 367 662 123 842 13 134 33 0 4791 5 2 0 94 March 2, 2026 at 06:55:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2159 152 214 1 0 1 0 260 0 1 0 99 1 0 0 0 27 9 20 0 0 1 0 9 0 0 0 100 2 0 0 0 9 2 0 0 0 1 0 0 0 0 0 100 3 0 0 0 9 2 2 0 0 5 0 298 0 0 0 100 4 0 0 0 16 5 10 0 1 0 0 300 0 0 0 100 5 0 0 3 214 103 8 0 0 3 0 2 0 0 0 100 6 0 0 0 21 4 50 1 2 9 0 1359 0 0 0 100 7 0 0 17 208 103 4 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:55:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 49 0 7 2224 121 316 1 33 207 7 300 0 1 0 99 1 8 0 0 118 5 186 0 39 200 4 61 0 1 0 99 2 4 0 0 171 0 315 0 35 183 1 60 0 0 0 100 3 718 0 112 176 77 207 1 39 191 9 447 0 1 0 99 4 710 0 0 123 5 214 2 40 235 9 1257 1 1 0 98 5 68 0 5 341 122 207 0 28 227 3 157 0 1 0 99 6 1902 0 0 149 16 256 4 42 187 1 1902 1 1 0 98 7 20 0 17 308 104 189 1 39 208 5 379 0 1 0 99 March 2, 2026 at 06:55:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2107 102 116 0 1 0 0 260 0 1 0 99 1 0 0 0 17 5 12 0 0 0 0 5 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 4 0 298 0 0 0 100 4 0 0 0 13 4 8 0 0 0 0 303 0 0 0 100 5 0 0 3 216 104 10 0 0 0 0 5 0 0 0 100 6 0 0 0 114 52 138 0 1 1 0 1432 0 0 0 99 7 0 0 17 214 103 14 0 1 1 0 266 0 0 0 100 March 2, 2026 at 06:55:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2112 102 124 0 1 0 0 262 0 1 0 99 1 0 0 0 26 7 26 0 1 0 0 329 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 3 0 0 0 100 3 0 0 0 8 1 4 0 0 7 0 306 0 0 0 100 4 0 0 0 23 7 22 0 0 0 0 315 0 0 0 100 5 0 0 3 218 108 8 0 0 0 0 7 0 0 0 100 6 0 0 0 116 52 142 1 0 5 0 1430 0 0 0 99 7 0 0 17 214 103 12 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:55:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2122 110 132 0 0 0 0 273 0 1 0 99 1 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 5 0 294 0 0 0 100 4 0 0 0 13 4 6 0 0 0 0 300 0 0 0 100 5 0 0 3 215 104 10 0 1 0 0 6 0 0 0 100 6 0 0 0 118 53 142 1 1 5 0 1442 0 0 0 99 7 0 0 17 208 103 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:55:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 245 0 7 2226 137 289 6 33 2 0 1875 2 1 0 97 1 3 0 0 102 4 175 6 28 6 0 1443 2 0 0 98 2 5 0 0 71 1 117 4 28 6 1 1470 1 0 0 99 3 0 0 0 65 5 147 2 22 14 0 1285 2 0 0 98 4 97 0 0 102 6 199 9 37 5 0 2093 1 0 0 98 5 26 0 3 272 105 124 1 27 4 0 1563 1 0 0 99 6 220 0 0 101 20 158 7 15 10 0 3137 3 1 0 96 7 216 0 127 309 106 268 3 30 9 1 1588 1 1 0 98 March 2, 2026 at 06:55:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2219 152 324 1 18 125 0 260 0 1 0 99 1 0 0 0 69 1 128 0 23 140 0 0 0 0 0 100 2 0 0 0 62 0 114 0 19 127 0 0 0 0 0 100 3 0 0 0 173 84 172 1 26 171 0 304 0 1 0 99 4 0 0 0 76 4 139 0 24 145 0 300 0 0 0 100 5 0 0 3 283 108 138 1 16 110 0 10 0 0 0 100 6 0 0 0 155 2 318 1 28 142 0 1428 0 1 0 99 7 0 0 17 261 103 118 0 21 134 0 266 0 0 0 100 March 2, 2026 at 06:55:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 15 2145 131 177 0 5 7 0 267 0 1 0 99 1 0 0 21 61 22 71 0 6 7 1 92 0 0 0 100 2 1 0 0 16 0 10 0 5 8 0 14 0 0 0 100 3 0 0 0 18 2 10 0 2 6 0 306 0 0 0 100 4 0 0 0 20 5 19 0 5 13 0 310 0 0 0 100 5 0 0 3 242 111 39 2 1 5 0 34 0 0 0 100 6 0 0 0 25 2 53 2 6 11 0 1362 0 0 0 99 7 0 0 17 224 103 28 1 7 7 0 359 0 0 0 100 March 2, 2026 at 06:55:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2111 103 118 0 1 0 0 261 0 1 0 99 1 0 0 0 118 52 111 0 3 0 0 0 0 0 0 100 2 0 0 7 10 0 6 0 1 1 0 4 0 0 0 100 3 0 0 0 18 2 18 0 1 0 0 317 0 0 0 100 4 0 0 0 22 5 18 0 1 0 0 313 0 0 0 100 5 0 0 3 239 117 28 0 0 0 0 21 0 0 0 100 6 0 0 0 17 2 40 1 0 3 0 1342 0 0 0 100 7 0 0 17 214 104 10 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:55:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2126 102 114 0 0 0 0 260 0 1 0 99 1 0 0 112 69 31 63 0 0 0 0 0 0 0 0 100 2 0 0 0 67 21 46 0 2 0 0 0 0 0 0 100 3 0 0 0 26 1 6 0 2 2 0 307 0 0 0 100 4 0 0 0 35 3 18 1 1 0 0 300 0 0 0 100 5 0 0 3 237 107 14 1 0 0 0 5 0 0 0 100 6 0 0 0 31 2 36 2 0 1 0 1337 0 0 0 100 7 0 0 17 231 106 10 0 0 0 0 269 0 0 0 100 March 2, 2026 at 06:55:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 102 114 0 0 1 0 260 0 1 0 99 1 0 0 7 16 3 8 0 0 1 0 0 0 0 0 100 2 0 0 0 89 41 78 0 0 1 0 0 0 0 0 100 3 0 0 0 32 12 24 0 1 1 0 293 0 0 0 100 4 0 0 0 18 4 8 0 0 1 0 300 0 0 0 100 5 0 0 7 233 112 24 0 0 1 0 13 0 0 0 100 6 0 0 0 16 4 36 0 0 1 0 1339 0 0 0 100 7 0 0 21 211 103 8 0 1 0 0 269 0 0 0 100 March 2, 2026 at 06:55:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 41 0 0 2989 101 1682 41 305 226 0 6480 8 3 0 89 1 69 0 7 786 3 1509 43 328 243 0 8524 7 3 0 90 2 44 0 0 793 0 1398 31 241 218 0 6153 5 2 0 92 3 2 0 0 947 116 1548 47 311 254 0 7781 6 3 0 91 4 23 0 13 737 5 1348 28 308 229 0 6680 5 2 0 92 5 8 0 2 864 107 1151 26 192 244 0 4418 5 2 0 93 6 3 0 0 654 10 1223 30 284 253 0 7357 5 2 0 92 7 10 0 351 824 117 1181 20 166 241 0 4802 5 2 0 92 March 2, 2026 at 06:55:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 97 0 4 0 0 0 0 1 0 99 1 0 0 7 20 3 22 0 0 0 0 280 0 0 0 100 2 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 3 0 0 0 26 1 18 1 0 3 0 297 0 0 0 100 4 0 0 14 15 4 8 0 1 0 0 566 0 0 0 100 5 0 0 3 214 104 6 0 0 0 0 2 0 0 0 100 6 0 0 0 26 9 50 1 0 1 0 1345 0 0 0 99 7 0 0 3 308 152 102 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 0 2142 100 147 0 7 8 6 103 0 1 0 99 1 1348 0 120 43 5 75 2 10 6 12 1280 2 1 0 98 2 1982 0 0 49 0 51 2 5 8 14 314 0 1 0 99 3 79 0 3 40 1 47 0 11 8 8 516 0 0 0 100 4 17 0 14 58 7 63 1 8 3 4 700 0 0 0 100 5 9 0 2 249 109 41 0 7 6 6 56 0 0 0 100 6 17 0 0 58 9 83 3 6 5 2 1536 0 0 0 99 7 4 0 4 334 152 124 0 5 4 1 50 0 0 0 100 March 2, 2026 at 06:55:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 108 0 0 0 0 0 0 0 0 100 1 0 0 7 13 3 10 0 1 1 0 270 0 0 0 100 2 0 0 0 10 0 10 0 1 1 0 0 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 301 0 0 0 100 4 0 0 14 12 4 8 0 1 0 0 566 0 0 0 100 5 0 0 3 214 104 8 0 0 0 0 3 0 0 0 100 6 0 0 0 23 7 46 0 1 0 0 1426 0 0 0 99 7 0 0 3 308 152 102 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2102 100 110 0 0 0 0 3 0 1 0 99 1 0 0 7 14 3 14 0 1 0 0 273 0 0 0 100 2 0 0 0 7 0 2 0 0 1 0 0 0 0 0 100 3 0 0 0 10 1 16 0 1 3 0 295 0 0 0 100 4 0 0 14 14 4 8 1 0 0 0 565 0 0 0 100 5 0 0 3 210 102 4 0 0 0 0 0 0 0 0 100 6 0 0 0 34 12 56 1 1 6 0 1750 0 0 0 99 7 0 0 3 312 153 108 0 0 0 0 3 0 0 0 100 March 2, 2026 at 06:56:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 100 112 0 0 3 0 0 0 1 0 99 1 0 0 7 17 3 18 1 0 3 0 280 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 4 0 0 4 0 302 0 0 0 100 4 0 0 14 14 4 12 0 0 3 0 567 0 0 0 100 5 0 0 3 212 103 6 0 0 0 0 2 0 0 0 100 6 0 0 0 17 4 42 1 0 2 0 1419 0 0 0 99 7 0 0 3 321 158 116 0 0 2 0 8 0 0 0 100 March 2, 2026 at 06:56:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 351 0 0 2190 100 339 11 37 2 0 1921 2 1 0 97 1 171 0 7 106 3 228 3 35 7 1 1910 2 0 0 98 2 171 0 0 132 19 268 15 37 4 0 1377 1 0 0 98 3 92 0 0 116 2 253 4 41 5 2 1989 1 0 0 98 4 42 0 0 103 6 272 8 40 0 0 2146 2 0 0 97 5 94 0 13 296 102 331 3 34 4 0 1756 1 1 0 98 6 26 0 0 64 3 140 11 22 7 0 2300 3 1 0 97 7 1 0 85 332 138 202 3 23 5 0 1442 1 0 0 98 March 2, 2026 at 06:56:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 112 0 0 0 0 1 0 1 0 99 1 0 0 7 27 10 22 1 0 0 0 273 0 0 0 100 2 0 0 0 106 50 102 0 1 0 0 3 0 0 0 100 3 0 0 0 8 1 4 0 0 1 0 301 0 0 0 100 4 0 0 0 22 5 20 0 0 0 0 314 0 0 0 100 5 0 0 17 226 109 22 0 1 0 0 273 0 0 0 100 6 0 0 0 17 3 42 2 0 2 0 1433 0 0 0 100 7 0 0 3 215 103 8 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:56:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2117 100 126 0 5 8 0 21 0 1 0 99 1 0 0 15 45 13 49 1 1 5 0 292 0 1 0 99 2 0 0 0 125 50 125 0 6 5 0 42 0 0 0 100 3 0 0 0 17 1 15 1 1 13 1 370 0 0 0 100 4 0 0 0 25 3 28 0 3 6 0 324 0 0 0 100 5 0 0 17 218 103 21 0 6 15 0 271 0 0 0 100 6 0 0 7 25 3 51 0 2 9 1 1419 0 0 0 100 7 0 0 3 220 104 16 1 5 3 0 28 0 0 0 100 March 2, 2026 at 06:56:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 113 0 0 1 0 1 0 1 0 99 1 0 0 7 18 5 8 0 0 1 0 260 0 0 0 100 2 0 0 0 108 51 100 0 0 1 0 0 0 0 0 100 3 0 0 0 11 2 4 0 1 12 0 311 0 0 0 100 4 0 0 0 34 12 28 0 1 0 0 315 0 0 0 100 5 0 0 17 219 106 14 0 0 1 0 271 0 0 0 100 6 0 0 0 25 5 50 1 1 11 0 1343 0 0 0 100 7 0 0 10 211 103 4 0 1 1 0 0 0 0 0 100 March 2, 2026 at 06:56:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 119 2218 100 340 0 24 108 0 0 0 1 0 99 1 0 0 7 97 3 140 0 21 165 0 260 0 0 0 100 2 21 0 0 159 43 187 0 17 120 0 5 0 0 0 100 3 25 0 0 167 74 150 0 23 142 0 304 0 1 0 99 4 0 0 0 102 11 139 1 27 150 0 311 0 0 0 99 5 0 0 17 284 105 120 1 19 137 0 271 0 1 0 99 6 0 0 0 92 4 164 2 27 130 0 1332 0 1 0 99 7 0 0 3 293 103 140 0 18 117 0 0 0 0 0 100 March 2, 2026 at 06:56:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2106 100 112 0 0 0 0 0 0 1 0 99 1 0 0 7 12 3 8 0 1 0 0 260 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 108 51 102 0 0 4 0 298 0 0 0 100 4 0 0 0 25 9 18 0 0 0 0 306 0 0 0 100 5 0 0 17 213 104 8 0 0 0 0 268 0 0 0 100 6 0 0 0 15 3 40 1 0 4 0 1333 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 2660 102 1076 27 174 33 0 4401 5 2 0 93 1 4 0 7 546 4 1029 31 203 18 0 5471 5 2 0 94 2 1 0 0 432 0 762 21 155 27 0 3971 4 1 0 95 3 0 0 0 538 43 957 28 196 17 0 6116 5 2 0 94 4 29 0 0 451 16 796 14 168 43 0 4882 4 1 0 94 5 9 0 17 728 111 893 11 118 17 0 3224 3 1 0 96 6 3 0 0 415 3 812 24 145 34 0 6288 4 2 0 94 7 1 0 241 546 107 652 12 85 10 0 2683 2 1 0 96 March 2, 2026 at 06:56:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2339 102 525 9 71 15 0 1977 2 1 0 97 1 3 0 7 205 4 318 13 68 11 0 1992 2 1 0 97 2 0 0 0 195 5 326 8 46 11 0 1621 2 1 0 98 3 20 0 0 192 1 355 10 75 11 0 2117 2 1 0 98 4 0 0 0 193 4 316 6 61 2 0 1538 1 0 0 98 5 0 0 17 358 105 262 4 39 10 0 1692 1 0 0 98 6 0 0 0 248 52 390 10 55 13 0 2917 1 1 0 98 7 1 0 115 335 103 246 3 41 2 0 1215 1 0 0 98 March 2, 2026 at 06:56:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1907 0 2 2148 102 145 3 12 14 8 757 0 1 0 98 1 73 0 7 67 3 84 0 14 13 9 425 0 0 0 100 2 5 0 0 49 7 41 0 8 7 3 81 0 0 0 100 3 100 0 0 36 0 34 1 5 3 7 87 0 0 0 100 4 5 0 0 39 4 27 1 5 3 2 387 0 0 0 100 5 28 0 17 233 103 28 0 6 5 4 324 0 0 0 100 6 1300 0 144 120 47 132 2 5 28 11 1239 2 1 0 98 7 68 0 3 294 111 93 1 10 12 4 1265 0 0 0 99 March 2, 2026 at 06:56:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2183 101 260 2 28 173 0 881 0 1 0 99 1 0 0 7 115 3 205 2 33 200 0 590 0 1 0 99 2 0 0 0 147 4 289 0 29 225 0 5 0 1 0 99 3 0 0 0 178 90 180 0 36 218 0 0 0 0 0 100 4 0 0 0 92 4 176 0 34 216 0 300 0 1 0 99 5 0 0 17 296 104 184 1 28 210 0 268 0 1 0 99 6 0 0 0 78 2 185 0 39 208 0 511 0 0 0 100 7 0 0 3 375 153 246 0 30 236 0 10 0 1 0 99 March 2, 2026 at 06:56:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 110 0 0 1 0 294 0 1 0 99 1 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 2 0 0 0 15 4 10 0 1 0 0 5 0 0 0 100 3 0 0 0 12 1 12 0 1 0 0 1 0 0 0 100 4 0 0 0 14 4 8 0 0 0 0 301 0 0 0 100 5 0 0 17 210 103 6 0 0 0 0 266 0 0 0 100 6 0 0 0 14 3 38 1 0 0 0 1421 0 0 0 100 7 0 0 3 311 153 106 0 0 0 0 11 0 0 0 100 March 2, 2026 at 06:56:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 116 0 0 1 0 301 0 1 0 99 1 0 0 7 11 3 8 0 0 0 0 260 0 0 0 100 2 0 0 0 12 3 6 0 0 0 0 319 0 0 0 100 3 0 0 0 10 1 8 0 0 0 0 26 0 0 0 100 4 0 0 0 21 5 20 0 0 0 0 316 0 0 0 100 5 0 0 17 235 115 26 0 0 0 0 284 0 0 0 100 6 0 0 0 16 3 42 1 0 3 0 1430 0 0 0 100 7 0 0 3 314 153 110 0 0 0 0 11 0 0 0 100 March 2, 2026 at 06:56:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 277 0 0 2168 101 284 6 17 8 0 1170 3 1 0 96 1 373 0 7 72 3 111 7 18 3 0 2334 3 1 0 96 2 54 0 0 84 0 149 6 26 3 0 1287 1 0 0 98 3 202 0 0 79 0 156 4 27 2 0 1496 2 0 0 98 4 1 0 0 98 6 200 5 32 2 0 1850 1 0 0 99 5 2 0 17 287 107 177 5 33 2 0 1674 1 0 0 98 6 107 0 0 80 3 276 6 36 2 0 2732 1 1 0 98 7 6 0 87 356 155 236 9 23 5 0 1687 1 1 0 98 March 2, 2026 at 06:56:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 110 0 0 2 0 308 0 1 0 99 1 0 0 7 18 4 10 1 0 1 0 263 0 0 0 100 2 0 0 0 10 2 0 0 0 1 0 0 0 0 0 100 3 0 0 0 28 10 18 1 0 1 0 14 0 0 0 100 4 0 0 0 19 4 10 0 0 2 0 300 0 0 0 100 5 5 0 21 221 105 20 1 1 2 0 295 0 0 0 100 6 0 0 0 18 5 38 1 0 4 0 1429 0 0 0 100 7 0 0 7 310 152 104 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:56:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2171 101 240 0 29 136 0 292 0 1 0 99 1 0 0 7 80 4 143 0 27 132 0 260 0 0 0 100 2 0 0 0 140 0 261 0 26 89 0 0 0 0 0 100 3 0 0 0 174 88 158 0 24 164 0 6 0 1 0 99 4 0 0 0 124 27 217 0 25 157 0 1433 0 1 0 99 5 0 0 17 278 107 133 0 13 90 0 266 0 0 0 100 6 0 0 0 71 3 134 0 31 127 0 294 0 0 0 100 7 0 0 3 301 124 149 0 28 136 0 0 0 0 0 100 March 2, 2026 at 06:56:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2123 102 111 2 5 21 0 322 0 1 0 99 1 0 0 7 37 10 30 0 1 1 0 288 0 0 0 100 2 0 0 0 18 0 13 0 3 3 0 25 0 0 0 100 3 0 0 8 23 3 22 0 4 5 0 18 0 1 0 99 4 0 0 21 26 4 67 1 11 10 1 1374 0 0 0 99 5 0 0 17 346 154 150 0 10 6 1 354 0 0 0 100 6 0 0 0 23 2 30 0 7 21 0 298 0 0 0 100 7 0 0 3 217 102 23 0 5 12 3 68 0 0 0 100 March 2, 2026 at 06:56:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 101 120 0 3 11 0 306 0 1 0 99 1 0 0 7 30 11 26 1 0 0 0 276 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 0 23 4 44 2 1 0 0 1353 0 0 0 99 5 0 0 24 317 159 108 0 1 1 0 266 0 0 0 100 6 1 0 0 25 2 26 1 0 7 0 305 0 0 0 100 7 0 0 3 214 102 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2104 101 113 0 0 3 0 294 0 1 0 99 1 0 0 7 49 12 26 0 0 0 0 272 0 0 0 100 2 8 0 0 23 0 2 0 0 0 0 3 0 0 0 100 3 0 0 0 22 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 36 6 42 1 1 0 0 1345 0 0 0 100 5 0 0 17 331 154 110 0 0 0 0 268 0 0 0 100 6 0 0 7 28 2 8 0 2 5 0 294 0 0 0 100 7 0 0 3 227 103 4 0 0 0 0 5 0 0 0 100 March 2, 2026 at 06:56:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2112 102 114 0 0 2 0 301 0 1 0 99 1 0 0 7 28 11 24 0 0 0 0 271 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 3 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 17 4 38 1 0 0 0 1341 0 0 0 100 5 0 0 17 286 140 78 1 0 0 0 267 0 0 0 100 6 0 0 0 45 16 40 0 3 4 0 294 0 0 0 100 7 0 0 3 216 102 16 0 2 0 0 0 0 0 0 100 March 2, 2026 at 06:56:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 2955 133 1620 36 285 244 1 6764 6 3 0 90 1 11 0 7 806 15 1437 46 305 252 0 7742 7 3 0 90 2 7 0 0 782 3 1358 32 238 286 0 5182 6 2 0 92 3 5 0 0 847 87 1438 45 317 283 0 9140 6 3 0 91 4 45 0 0 756 12 1341 34 268 210 1 7495 6 3 0 91 5 2 0 17 919 105 1248 17 203 219 0 4775 5 2 0 93 6 18 0 0 742 8 1412 31 272 305 0 7071 6 3 0 92 7 22 0 353 738 104 986 19 161 254 1 3567 4 2 0 94 March 2, 2026 at 06:56:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 104 0 0 1 0 303 0 1 0 99 1 0 0 7 82 39 74 0 0 0 0 260 0 0 0 100 2 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 36 15 32 0 1 0 0 1 0 0 0 100 4 0 0 0 28 10 50 2 1 0 0 1351 0 0 0 100 5 0 0 17 219 103 16 0 0 0 0 276 0 0 0 100 6 0 0 0 12 2 6 1 0 2 0 294 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 102 108 0 3 2 0 293 0 1 0 99 1 0 0 7 20 2 16 0 1 0 0 265 0 0 0 100 2 0 0 0 12 1 12 0 1 1 0 0 0 0 0 100 3 0 0 0 109 51 106 0 0 0 0 24 0 0 0 100 4 1 0 0 25 8 50 1 0 0 0 1357 0 0 0 99 5 0 0 17 229 113 18 1 0 0 0 283 0 0 0 100 6 1 0 0 21 5 20 0 0 1 0 308 0 0 0 100 7 0 0 3 213 103 8 0 1 1 0 1 0 0 0 100 March 2, 2026 at 06:56:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 112 1 1 3 0 300 0 1 0 99 1 0 0 7 10 2 4 0 0 0 0 260 0 0 0 100 2 0 0 0 15 1 16 0 0 0 0 0 0 0 0 100 3 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 4 0 0 0 24 8 48 1 0 1 0 1351 0 0 0 100 5 0 0 17 210 103 6 0 0 0 0 266 0 0 0 100 6 0 0 0 12 2 8 0 1 3 0 297 0 0 0 100 7 0 0 3 212 104 6 0 0 0 0 2 0 0 0 100 March 2, 2026 at 06:56:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 728 0 113 2120 101 160 0 9 17 13 436 0 1 0 99 1 132 0 7 53 3 66 0 10 9 9 394 0 0 0 100 2 661 0 2 42 2 43 1 9 15 8 979 1 0 0 98 3 20 0 0 160 56 168 0 11 6 5 174 0 0 0 100 4 14 0 0 57 8 81 1 7 4 2 1908 0 0 0 99 5 16 0 17 249 106 49 0 6 2 3 386 0 0 0 99 6 1889 0 0 40 4 23 2 5 6 1 600 0 1 0 99 7 11 0 3 230 102 17 0 5 10 2 21 0 0 0 100 March 2, 2026 at 06:56:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 112 0 0 3 0 292 0 1 0 99 1 0 0 7 11 2 8 0 1 1 0 260 0 0 0 100 2 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 3 0 0 0 123 56 124 0 1 1 0 6 0 0 0 100 4 0 0 0 20 4 44 2 0 5 0 1427 0 0 0 100 5 0 0 17 212 103 10 0 0 0 0 276 0 0 0 100 6 0 0 0 12 2 6 1 0 0 0 294 0 0 0 100 7 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2159 101 305 4 29 9 0 1592 1 1 0 98 1 420 0 7 64 2 198 2 22 7 0 1775 2 1 0 98 2 171 0 0 65 1 243 0 25 6 2 1427 1 0 0 99 3 3 0 0 92 12 239 2 31 6 0 1457 1 0 0 98 4 135 0 6 197 49 325 6 27 3 0 3007 1 1 0 98 5 5 0 16 255 105 101 2 19 8 0 1404 2 0 0 98 6 36 0 0 63 3 111 4 22 14 0 2003 2 0 0 97 7 208 0 84 235 103 84 3 16 3 0 1353 3 1 0 96 March 2, 2026 at 06:56:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 112 0 0 3 0 298 0 1 0 99 1 0 0 7 15 3 8 1 0 0 0 265 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 4 0 0 0 117 54 142 1 0 0 0 1441 0 0 0 99 5 0 0 17 218 108 6 1 0 0 0 265 0 0 0 100 6 0 0 0 20 4 20 0 0 3 0 309 0 0 0 100 7 0 0 3 223 108 18 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:56:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2134 107 93 1 4 3 0 329 0 1 0 99 1 0 0 7 72 2 67 0 5 5 0 288 0 0 0 100 2 0 0 0 18 2 14 0 3 1 0 7 0 0 0 100 3 0 0 0 14 0 10 0 2 3 0 13 0 0 0 100 4 0 0 9 119 50 146 0 7 12 0 1356 0 1 0 99 5 0 0 31 233 109 42 0 8 17 0 268 0 0 0 100 6 0 0 7 25 2 27 1 7 5 1 332 0 0 0 100 7 0 0 3 231 107 37 0 5 12 3 168 0 0 0 100 March 2, 2026 at 06:56:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2128 111 134 0 1 14 0 306 0 1 0 99 1 0 0 7 17 3 14 0 5 0 0 260 0 0 0 100 2 0 0 0 15 2 15 0 6 4 0 0 0 0 0 100 3 0 0 0 11 1 8 0 3 1 0 0 0 0 0 100 4 0 0 0 22 6 44 2 2 1 0 1344 0 0 0 100 5 0 0 17 318 154 115 0 3 1 0 266 0 0 0 100 6 0 0 0 22 3 20 1 2 17 0 294 0 0 0 100 7 0 0 10 210 102 6 0 2 0 0 0 0 0 0 100 March 2, 2026 at 06:56:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2203 108 235 2 31 159 0 309 0 1 0 99 1 0 0 7 115 2 175 0 38 158 0 260 0 0 0 99 2 0 0 0 81 1 126 0 30 162 0 0 0 0 0 100 3 0 0 0 181 85 153 0 28 165 0 0 0 1 0 99 4 0 0 0 118 6 213 1 31 176 0 1345 0 1 0 99 5 0 0 129 364 148 232 0 22 171 0 268 0 1 0 99 6 0 0 0 185 3 319 0 31 159 0 295 0 0 0 99 7 0 0 10 304 108 149 0 23 138 0 0 0 1 0 99 March 2, 2026 at 06:56:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2160 143 196 0 1 1 0 316 0 1 0 99 1 0 0 14 10 2 6 0 1 0 0 260 0 0 0 100 2 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 10 1 4 0 0 0 0 2 0 0 0 100 4 0 0 0 23 7 44 1 0 0 0 1346 0 0 0 100 5 0 0 24 213 103 8 0 0 0 0 266 0 0 0 100 6 0 0 0 16 2 10 0 1 7 0 297 0 0 0 100 7 0 0 3 248 118 44 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:56:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2928 127 1472 39 256 29 0 6041 7 3 0 91 1 11 0 7 761 12 1345 42 304 38 0 8730 6 2 0 91 2 1 0 0 744 28 1239 29 215 34 1 5862 7 2 0 91 3 19 0 0 665 3 1190 35 255 37 0 8000 6 2 0 92 4 34 0 0 674 9 1199 32 246 31 0 7780 6 2 0 91 5 23 0 17 805 113 1001 21 158 21 0 5312 5 2 0 93 6 10 0 0 581 6 1093 20 234 23 0 7146 6 2 0 93 7 35 0 367 782 107 1121 27 159 20 0 4713 4 2 0 94 March 2, 2026 at 06:56:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 104 0 0 2 0 302 0 1 0 99 1 0 0 7 16 4 12 0 0 0 0 270 0 0 0 100 2 0 0 0 110 51 108 0 0 0 0 21 0 0 0 100 3 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 4 0 0 0 16 4 38 2 0 0 0 1334 0 0 0 100 5 0 0 17 227 111 22 0 0 0 0 277 0 0 0 100 6 0 0 0 13 2 8 1 0 3 0 304 0 0 0 100 7 0 0 3 218 103 12 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:56:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 734 0 112 2129 101 145 0 14 17 11 508 0 1 0 99 1 120 0 7 87 3 102 0 17 9 15 469 0 0 0 100 2 49 0 2 159 53 179 0 12 11 17 114 0 0 0 100 3 639 0 0 43 1 41 2 12 4 4 950 1 0 0 98 4 5 0 0 53 5 71 0 5 8 4 1470 0 0 0 99 5 0 0 21 248 110 30 1 4 3 0 287 0 0 0 100 6 27 0 0 47 7 40 0 4 16 5 396 0 0 0 100 7 1902 0 7 242 102 34 2 6 7 4 334 0 1 0 99 March 2, 2026 at 06:56:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2185 101 253 1 28 227 0 301 0 1 0 99 1 0 0 7 90 3 175 0 45 252 0 260 0 1 0 99 2 0 0 0 258 51 417 0 31 201 0 0 0 1 0 99 3 0 0 0 169 82 174 0 37 234 0 0 0 1 0 99 4 0 0 0 96 4 212 1 31 221 0 1418 0 1 0 99 5 0 0 17 293 107 177 0 26 228 0 271 0 1 0 99 6 0 0 0 86 2 160 0 36 229 0 304 0 0 0 99 7 0 0 3 273 103 137 0 25 198 0 0 0 1 0 99 March 2, 2026 at 06:56:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 112 0 2 4 0 314 0 1 0 99 1 0 0 7 11 2 4 0 0 0 0 260 0 0 0 100 2 0 0 0 108 51 104 0 1 0 0 3 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 0 17 4 42 1 0 0 0 1418 0 0 0 99 5 0 0 17 228 111 24 0 0 0 0 598 0 0 0 100 6 0 0 0 15 3 12 0 0 0 0 300 0 0 0 100 7 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 112 0 0 0 0 285 0 1 0 99 1 0 0 7 12 2 10 0 0 0 0 265 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 4 0 0 0 39 11 66 4 1 2 0 1433 0 0 0 100 5 0 0 17 216 109 6 0 0 0 0 266 0 0 0 100 6 0 0 0 21 4 22 0 0 2 0 327 0 0 0 100 7 0 0 3 211 102 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 199 0 0 2187 107 222 6 26 5 0 1977 2 1 0 97 1 88 0 9 112 3 155 8 32 3 0 1614 1 0 0 98 2 12 0 0 110 20 185 3 24 4 0 1374 1 0 0 98 3 350 0 21 67 1 132 6 25 8 0 1644 1 1 0 98 4 14 0 0 130 37 257 6 29 3 0 2552 2 1 0 98 5 308 0 17 277 105 179 5 20 5 0 1405 2 0 0 97 6 27 0 0 64 3 145 6 29 5 0 2104 2 0 0 98 7 95 0 87 244 102 177 3 23 4 1 1237 2 0 0 98 March 2, 2026 at 06:56:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 110 0 0 1 0 302 0 1 0 99 1 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 2 0 0 0 19 7 14 0 0 0 0 9 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 1 0 0 0 100 4 0 0 0 111 52 132 1 0 0 0 1423 0 0 0 100 5 0 0 17 215 105 12 0 1 0 0 266 0 0 0 100 6 0 0 0 11 2 6 0 0 2 0 294 0 0 0 100 7 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2171 101 192 0 29 137 0 324 0 1 0 99 1 0 0 7 96 2 176 0 25 167 0 273 0 0 0 99 2 1 0 0 140 7 250 0 24 111 0 30 0 0 0 100 3 0 0 12 146 70 142 0 32 138 0 15 0 0 0 100 4 0 0 0 85 5 179 1 29 142 0 1353 0 1 0 99 5 0 0 17 372 140 212 0 25 105 1 418 0 1 0 99 6 0 0 9 122 18 207 0 36 160 0 298 0 1 0 99 7 0 0 17 282 103 153 0 24 146 0 37 0 1 0 99 March 2, 2026 at 06:56:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2116 104 116 0 0 5 0 299 0 1 0 99 1 0 0 7 13 3 8 0 1 0 0 261 0 0 0 100 2 0 0 0 11 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 31 10 26 0 0 0 0 18 0 0 0 100 4 0 0 7 19 5 42 2 1 0 0 1335 0 0 0 100 5 0 0 17 216 105 12 0 0 1 0 285 0 0 0 100 6 0 0 0 115 52 110 0 0 3 0 303 0 0 0 100 7 0 0 3 216 102 15 0 2 0 0 0 0 0 0 100 March 2, 2026 at 06:56:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2124 102 116 0 1 4 0 301 0 1 0 99 1 0 0 7 26 2 8 0 0 0 0 265 0 0 0 100 2 0 0 0 23 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 39 7 19 1 0 0 0 7 0 0 0 100 4 0 0 0 35 4 44 1 0 0 0 1341 0 0 0 100 5 0 0 17 235 109 10 1 1 0 0 268 0 0 0 100 6 0 0 0 138 55 118 1 0 9 0 308 0 0 0 100 7 0 0 115 219 105 15 0 0 0 0 6 0 0 0 100 March 2, 2026 at 06:56:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 107 126 1 4 5 0 311 0 1 0 99 1 0 0 7 11 2 4 0 0 0 0 260 0 0 0 100 2 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 26 3 16 0 1 0 0 3 0 0 0 100 4 0 0 0 16 4 40 1 0 0 0 1337 0 0 0 100 5 0 0 17 211 103 6 0 0 0 0 266 0 0 0 100 6 0 0 0 112 52 106 0 0 5 0 294 0 0 0 100 7 0 0 10 214 103 8 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:56:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 0 2879 108 1474 37 213 20 0 5936 6 3 0 91 1 9 0 7 707 5 1271 34 263 39 0 7206 7 2 0 91 2 6 0 0 659 4 1146 22 174 19 0 5006 5 2 0 93 3 33 0 0 582 12 1061 28 223 42 1 7758 6 2 0 92 4 0 0 6 610 5 1097 17 209 12 0 7366 5 2 0 94 5 7 0 3 794 104 1024 17 153 24 0 4960 5 2 0 93 6 30 0 0 627 36 1115 24 203 23 0 6005 5 2 0 93 7 22 0 353 660 108 872 16 125 45 1 4651 5 2 0 93 March 2, 2026 at 06:56:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2193 107 263 0 21 222 0 310 0 1 0 99 1 0 0 7 99 3 186 0 26 233 0 280 0 0 0 99 2 0 0 0 151 1 305 0 29 210 0 0 0 0 0 100 3 0 0 0 264 130 274 0 31 225 0 0 0 1 0 99 4 0 0 0 85 4 189 2 33 214 0 1335 0 1 0 99 5 0 0 3 287 103 160 0 27 210 0 0 0 1 0 99 6 0 0 0 76 1 143 0 26 220 0 294 0 1 0 99 7 0 0 17 276 106 144 0 26 231 0 266 0 1 0 99 March 2, 2026 at 06:56:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 243 0 0 2156 109 159 1 6 7 5 1163 0 1 0 99 1 441 0 7 43 2 47 0 10 5 5 436 1 0 0 99 2 13 0 0 38 1 38 0 8 5 3 153 0 0 0 100 3 728 0 113 131 51 166 0 8 6 8 152 0 0 0 99 4 130 0 0 52 4 92 1 10 8 12 1525 0 0 0 99 5 19 0 3 245 105 47 0 6 3 5 121 0 0 0 100 6 1894 0 0 39 2 31 3 8 10 3 623 0 1 0 99 7 17 0 17 238 104 37 1 6 8 6 332 0 0 0 100 March 2, 2026 at 06:56:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2116 105 124 1 1 2 0 304 0 1 0 99 1 0 0 7 12 2 10 0 0 0 0 275 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 108 50 104 0 1 0 0 0 0 0 0 100 4 0 0 0 21 4 52 0 1 0 0 1425 0 0 0 100 5 0 0 3 216 108 4 0 0 2 0 0 0 0 0 100 6 0 0 0 18 3 18 0 0 9 0 308 0 0 0 100 7 0 0 17 214 104 10 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:56:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 109 110 1 2 6 0 631 0 1 0 99 1 0 0 7 34 3 26 0 2 0 0 264 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 107 50 104 0 1 0 0 2 0 0 0 100 4 0 0 0 15 4 38 1 0 0 0 1417 0 0 0 100 5 0 0 3 217 106 10 0 0 0 0 4 0 0 0 100 6 0 0 0 11 1 8 0 1 12 0 299 0 0 0 100 7 0 0 17 210 104 6 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:56:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 112 0 0 8 0 308 0 1 0 99 1 0 0 7 10 2 8 0 0 0 0 280 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 115 55 110 0 0 0 0 7 0 0 0 100 4 0 0 0 21 5 44 2 0 1 0 1420 0 0 0 100 5 0 0 3 220 104 20 0 1 0 0 4 0 0 0 100 6 0 0 0 9 1 4 0 0 8 0 294 0 0 0 100 7 0 0 17 210 104 6 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:56:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 248 0 0 2251 101 434 1 49 191 0 1929 1 2 0 97 1 36 0 7 140 2 419 2 61 163 0 1545 2 1 0 97 2 2 0 0 110 1 242 0 46 140 0 661 2 1 0 97 3 381 0 0 326 164 461 1 53 138 0 1439 1 1 0 98 4 3 0 0 160 5 347 3 64 160 0 2700 1 1 0 98 5 13 0 3 399 125 482 0 54 168 0 1286 1 1 0 98 6 39 0 0 268 2 720 6 58 149 0 1566 1 1 0 98 7 187 0 87 312 105 210 4 41 119 0 1823 3 1 0 96 March 2, 2026 at 06:56:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 105 121 0 1 1 0 283 0 1 0 99 1 0 0 7 15 3 9 0 1 1 0 300 0 0 0 100 2 0 0 0 22 7 13 0 1 5 0 20 0 0 0 100 3 1 0 0 14 1 8 1 1 0 1 17 0 0 0 100 4 0 0 0 21 5 15 0 1 0 0 507 0 0 0 100 5 0 0 3 315 152 110 0 1 0 0 3 0 0 0 100 6 0 0 0 14 1 6 0 0 2 0 295 0 0 0 100 7 0 0 31 210 104 6 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:56:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2133 109 149 1 6 15 0 29 0 1 0 99 1 0 0 14 22 3 21 1 4 10 0 578 0 0 0 100 2 1 0 0 20 1 30 2 6 11 2 115 0 0 0 100 3 0 0 0 23 2 23 1 4 4 0 52 0 0 0 100 4 0 0 0 27 3 57 1 3 7 2 995 0 0 0 100 5 0 0 11 314 150 115 0 7 17 0 312 0 1 0 99 6 0 0 0 50 12 47 0 2 10 0 322 0 0 0 100 7 0 0 17 229 105 29 0 1 4 0 273 0 0 0 100 March 2, 2026 at 06:56:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 101 115 0 2 1 0 0 0 1 0 99 1 0 0 7 17 3 8 0 1 1 0 560 0 0 0 100 2 0 0 7 20 7 16 0 1 0 0 6 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 13 3 36 0 0 0 0 1036 0 0 0 100 5 0 0 3 216 103 6 1 0 0 0 300 0 0 0 100 6 0 0 0 110 51 104 0 0 0 0 294 0 0 0 100 7 0 0 17 221 105 15 0 2 2 0 267 0 0 0 100 March 2, 2026 at 06:56:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2105 100 111 0 1 1 0 0 0 1 0 99 1 0 0 7 31 4 6 1 0 4 0 566 0 0 0 100 2 0 0 0 48 11 24 0 0 1 0 12 0 0 0 100 3 0 0 0 29 3 6 0 1 1 0 5 0 0 0 100 4 0 0 0 34 4 38 1 0 1 0 1035 0 1 0 99 5 0 0 7 231 104 8 0 0 1 0 302 0 0 0 100 6 0 0 0 132 54 106 1 0 2 0 297 0 0 0 100 7 0 0 21 229 104 8 1 1 0 0 266 0 0 0 100 March 2, 2026 at 06:56:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2174 100 238 0 19 81 0 0 0 1 0 99 1 0 0 7 95 3 167 0 26 116 0 554 0 0 0 99 2 0 0 0 82 11 136 1 29 83 0 11 0 0 0 100 3 0 0 0 206 120 156 0 25 91 0 3 0 0 0 100 4 0 0 0 83 4 180 2 21 67 0 1033 0 0 0 99 5 0 0 3 270 103 115 1 11 64 0 300 0 0 0 100 6 0 0 0 277 51 437 0 22 77 0 294 0 0 0 100 7 0 0 17 280 104 149 0 15 80 0 266 0 0 0 100 March 2, 2026 at 06:56:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 18 0 0 2648 100 1143 27 195 43 0 4606 6 2 0 92 1 2 0 7 535 3 944 34 215 15 0 6379 5 2 0 93 2 6 0 0 564 12 988 29 158 23 0 4905 5 2 0 93 3 33 0 0 557 7 1045 30 202 17 0 5468 5 2 0 94 4 12 0 0 470 3 882 22 190 25 0 6403 5 2 0 93 5 6 0 3 708 104 888 22 142 11 0 4337 4 1 0 95 6 3 0 0 551 46 936 23 182 10 0 5679 4 1 0 95 7 19 0 269 553 107 689 10 103 11 0 4035 4 1 0 95 March 2, 2026 at 06:56:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 0 2241 101 344 8 45 3 0 845 1 1 0 98 1 1 0 7 126 5 216 10 45 23 0 1999 1 0 0 98 2 7 0 0 134 3 204 4 29 2 0 714 1 0 0 99 3 1 0 0 205 49 290 9 49 2 0 1275 1 0 0 98 4 7 0 0 131 3 235 5 43 3 0 2368 1 1 0 99 5 0 0 3 315 110 148 4 25 22 0 1049 1 0 0 99 6 1 0 0 107 4 168 6 39 8 0 1494 1 0 0 98 7 0 0 87 316 105 199 1 28 2 0 946 1 0 0 99 March 2, 2026 at 06:56:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 63 0 0 2143 100 145 0 9 4 4 38 0 1 0 99 1 34 0 7 46 4 44 0 8 5 7 626 0 0 0 100 2 8 0 0 38 4 29 0 6 3 3 19 0 0 0 100 3 0 0 0 138 54 128 0 6 1 0 129 0 0 0 100 4 2832 0 113 41 3 96 4 3 8 14 2229 1 1 0 98 5 497 0 3 259 105 87 1 18 13 12 523 1 0 0 98 6 29 0 1 59 2 74 1 15 20 7 485 0 0 0 100 7 18 0 17 245 104 43 1 7 7 2 371 0 0 0 100 March 2, 2026 at 06:56:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 108 0 0 0 0 0 0 1 0 99 1 0 0 7 14 3 8 1 0 4 0 567 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 5 0 0 0 100 3 0 0 0 106 50 102 0 0 0 0 10 0 0 0 100 4 0 0 0 12 3 36 0 0 0 0 1120 0 0 0 100 5 0 0 3 212 103 6 0 0 0 0 300 0 0 0 100 6 0 0 0 11 1 6 0 1 1 0 294 0 0 0 100 7 0 0 17 215 104 16 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:57:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2200 100 294 0 26 246 0 0 0 1 0 99 1 0 0 7 109 5 209 0 42 292 0 561 0 1 0 99 2 0 0 0 201 6 387 0 39 256 0 9 0 1 0 99 3 0 0 0 255 127 260 0 35 253 0 13 0 1 0 99 4 0 0 0 138 18 253 1 39 214 0 1117 0 1 0 99 5 0 0 3 316 110 226 0 38 254 0 302 0 1 0 99 6 0 0 0 80 1 162 0 35 228 0 294 0 1 0 99 7 0 0 17 275 104 159 0 37 226 0 266 0 1 0 99 March 2, 2026 at 06:57:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 7 13 3 8 0 0 7 0 557 0 0 0 100 2 0 0 0 15 4 9 1 1 0 0 319 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 0 27 8 54 1 1 0 0 1131 0 0 0 100 5 0 0 3 285 139 76 1 0 0 0 300 0 0 0 100 6 0 0 0 38 15 34 0 1 8 0 294 0 0 0 100 7 0 0 17 217 104 16 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 2206 101 367 8 35 4 0 1603 1 1 0 98 1 568 0 7 128 4 292 3 43 6 2 2138 1 1 0 98 2 6 0 0 74 2 208 4 25 9 0 956 3 0 0 97 3 58 0 0 129 6 350 4 33 7 0 1835 1 1 0 98 4 26 0 0 122 9 249 5 44 2 0 2729 1 1 0 98 5 44 0 3 283 110 205 8 21 2 0 2325 2 1 0 97 6 259 0 0 177 45 346 3 34 3 0 1957 2 1 0 98 7 141 0 101 253 106 80 3 16 1 2 1656 2 1 0 97 March 2, 2026 at 06:57:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 2109 101 87 0 3 9 0 15 0 1 0 99 1 0 0 7 59 10 54 0 5 4 0 587 0 0 0 100 2 0 0 0 17 1 12 0 1 0 0 25 0 0 0 100 3 0 0 0 108 50 102 0 1 0 0 14 0 0 0 100 4 0 0 0 19 5 38 0 1 0 0 1135 0 0 0 100 5 0 0 3 216 103 10 0 1 0 0 304 0 0 0 100 6 3 0 0 13 1 8 0 1 5 0 298 0 0 0 100 7 5 0 31 213 105 10 0 0 0 0 270 0 0 0 100 March 2, 2026 at 06:57:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 1 0 0 0 0 1 0 99 1 0 0 7 28 12 22 0 0 5 0 569 0 0 0 100 2 0 0 0 13 1 6 0 0 1 0 0 0 0 0 100 3 0 0 0 112 51 110 0 1 1 0 0 0 0 0 100 4 0 0 0 17 4 38 1 0 1 0 1123 0 0 0 100 5 0 0 3 214 104 8 0 0 1 0 302 0 0 0 100 6 0 0 0 12 3 4 0 0 12 0 295 0 0 0 100 7 0 0 17 210 104 6 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:57:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2245 100 376 1 28 118 1 100 0 1 0 99 1 0 0 7 92 6 159 0 27 154 0 590 0 0 0 99 2 0 0 9 71 0 129 1 28 126 1 7 0 0 0 100 3 0 0 0 243 116 238 1 30 152 2 77 0 1 0 99 4 0 0 7 96 10 157 0 35 124 0 17 0 1 0 99 5 0 0 3 276 104 155 3 21 142 0 1358 0 1 0 99 6 0 0 0 98 7 171 0 28 170 0 311 0 1 0 99 7 0 0 31 273 104 140 0 29 150 0 267 0 1 0 99 March 2, 2026 at 06:57:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2103 100 113 0 1 0 0 0 0 1 0 99 1 0 0 7 16 4 8 0 0 2 0 555 0 0 0 100 2 0 0 0 10 0 4 0 0 0 0 0 0 0 0 100 3 0 0 7 8 1 4 0 1 0 0 1 0 0 0 100 4 0 0 0 111 52 104 0 1 0 0 0 0 0 0 100 5 0 0 3 218 105 40 1 0 0 0 1339 0 0 0 100 6 0 0 0 32 11 24 1 0 4 0 309 0 0 0 100 7 8 0 17 215 104 8 0 1 0 0 269 0 0 0 100 March 2, 2026 at 06:57:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2107 100 113 0 0 0 0 0 0 1 0 99 1 0 0 7 32 4 12 1 0 6 0 566 0 0 0 100 2 0 0 0 23 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 26 1 6 0 0 0 0 23 0 0 0 100 4 1 0 0 140 56 122 0 1 2 0 15 0 0 0 100 5 0 0 3 242 109 52 0 1 2 0 1336 0 0 0 100 6 0 0 0 54 13 36 0 0 7 0 322 0 0 0 100 7 0 0 17 229 104 10 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2105 100 108 0 2 0 0 0 0 1 0 99 1 0 0 7 16 4 8 0 0 5 0 559 0 0 0 100 2 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 111 52 104 0 0 0 0 0 0 0 0 100 5 0 0 3 227 106 47 1 2 2 0 1337 0 0 0 100 6 0 0 0 25 7 28 0 2 6 0 300 0 0 0 100 7 0 0 17 212 104 6 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 57 0 0 2846 101 1437 36 220 11 0 5624 6 3 0 91 1 7 0 7 744 7 1370 27 255 31 0 7985 7 2 0 91 2 15 0 0 657 2 1095 20 194 38 0 5743 5 2 0 93 3 1 0 0 636 2 1206 32 241 35 0 7048 6 2 0 92 4 3 0 0 744 47 1294 25 238 23 1 5448 6 2 0 92 5 1 0 3 753 107 904 18 164 14 0 5622 4 2 0 94 6 33 0 0 540 6 997 28 190 34 0 6719 6 2 0 92 7 12 0 353 599 106 756 13 132 38 1 4930 4 2 0 94 March 2, 2026 at 06:57:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2189 100 275 0 33 215 0 10 0 1 0 99 1 0 0 7 96 8 175 0 34 221 0 571 0 1 0 99 2 0 0 0 78 0 150 0 31 185 0 0 0 0 0 100 3 0 0 0 181 88 197 0 33 259 0 0 0 1 0 99 4 0 0 0 180 51 264 0 24 252 0 0 0 1 0 99 5 0 0 3 289 107 186 1 23 208 0 1336 0 1 0 99 6 0 0 0 157 1 290 2 26 178 0 294 0 1 0 99 7 0 0 17 275 104 145 0 22 214 0 266 0 1 0 99 March 2, 2026 at 06:57:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2101 100 108 0 2 0 0 10 0 1 0 99 1 0 0 7 38 13 36 1 1 2 0 568 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 4 0 0 0 100 4 0 0 0 110 52 104 0 0 0 0 1 0 0 0 100 5 0 0 3 217 105 40 1 0 1 0 1335 0 0 0 100 6 0 0 0 11 2 6 0 0 3 0 295 0 0 0 100 7 0 0 17 215 104 9 0 2 0 0 266 0 0 0 100 March 2, 2026 at 06:57:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 101 116 0 0 0 0 11 0 1 0 99 1 0 0 7 26 9 24 1 0 3 0 574 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 21 0 0 0 100 4 0 0 0 110 51 106 0 0 0 0 7 0 0 0 100 5 0 0 3 226 113 42 1 0 3 0 1335 0 0 0 100 6 0 0 0 19 3 20 0 0 1 0 311 0 0 0 100 7 0 0 17 217 105 14 1 0 0 0 267 0 0 0 100 March 2, 2026 at 06:57:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 2140 102 140 0 10 6 4 44 0 1 0 99 1 25 0 7 59 9 48 0 7 6 3 991 0 0 0 100 2 1892 0 0 42 0 41 2 8 4 2 327 0 1 0 99 3 360 0 0 38 0 59 0 13 8 12 191 0 0 0 100 4 136 0 0 156 51 184 0 8 9 20 173 0 0 0 100 5 653 0 3 247 105 39 2 11 6 1 1236 1 0 0 98 6 407 0 113 30 1 94 0 14 6 6 1580 0 1 0 99 7 18 0 19 238 105 34 0 5 2 5 328 0 0 0 100 March 2, 2026 at 06:57:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2118 106 122 0 0 1 0 7 0 1 0 99 1 0 0 7 17 4 10 0 2 7 0 576 0 0 0 100 2 0 0 0 14 2 6 0 1 1 0 0 0 0 0 100 3 0 0 0 15 2 12 0 1 1 0 0 0 0 0 100 4 0 0 0 113 52 104 0 0 1 0 0 0 0 0 100 5 0 0 7 217 105 10 0 0 1 0 302 0 0 0 100 6 0 0 0 17 4 36 2 0 2 0 1413 0 0 0 100 7 1 0 21 212 104 8 0 1 0 0 296 0 0 0 100 March 2, 2026 at 06:57:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 288 0 0 2277 104 425 8 53 166 0 1907 3 2 0 96 1 122 0 7 356 8 796 15 102 135 0 3100 2 1 0 97 2 196 0 0 222 2 463 9 73 168 0 1952 2 1 0 97 3 35 0 0 208 70 252 10 47 120 0 1727 3 1 0 96 4 14 0 0 169 5 315 8 72 156 0 1360 2 1 0 97 5 130 0 2 482 144 562 11 76 119 1 2163 2 1 0 97 6 42 0 0 201 4 500 10 78 143 0 3182 1 1 0 98 7 274 0 116 396 111 452 9 61 132 0 1846 1 1 0 98 March 2, 2026 at 06:57:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 110 0 0 0 0 0 0 1 0 99 1 0 0 7 17 5 14 0 1 2 0 560 0 0 0 100 2 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 3 0 0 0 25 8 20 0 1 0 0 13 0 0 0 100 4 0 0 0 15 1 16 0 2 0 0 6 0 0 0 100 5 0 0 3 216 105 10 0 0 0 0 302 0 0 0 100 6 0 0 0 14 2 36 1 0 0 0 1417 0 0 0 100 7 0 0 17 312 155 108 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:57:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2120 101 126 0 4 10 0 21 0 1 0 99 1 2 0 18 28 4 36 1 6 13 0 595 0 0 0 100 2 0 0 0 19 1 13 0 0 0 0 17 0 0 0 100 3 0 0 0 46 12 52 1 6 16 0 108 0 0 0 100 4 0 0 0 25 1 20 0 2 5 0 19 0 0 0 100 5 0 0 3 231 109 21 1 3 3 0 301 0 0 0 100 6 0 0 9 29 4 75 0 1 15 1 1507 0 1 0 99 7 0 0 31 321 154 123 0 7 12 0 282 0 0 0 99 March 2, 2026 at 06:57:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 100 108 0 0 0 0 0 0 1 0 99 1 0 0 7 16 3 10 1 0 3 0 558 0 0 0 100 2 0 0 7 6 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 22 8 16 0 0 0 0 7 0 0 0 100 4 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 219 106 12 0 0 0 0 303 0 0 0 100 6 0 0 0 14 2 36 2 1 0 0 1331 0 0 0 100 7 0 0 17 313 154 109 0 2 0 0 266 0 0 0 100 March 2, 2026 at 06:57:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 101 110 0 0 0 0 1 0 1 0 99 1 0 0 7 33 5 12 0 0 6 0 569 0 0 0 100 2 0 0 0 23 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 36 7 16 0 1 0 0 6 0 0 0 100 4 0 0 0 24 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 232 104 10 0 1 0 0 300 0 0 0 100 6 0 0 0 35 3 48 1 1 8 0 1329 0 0 0 100 7 0 0 129 312 154 109 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 100 110 0 0 2 0 0 0 1 0 99 1 0 0 7 14 3 10 0 0 0 0 561 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 25 9 20 0 0 0 0 14 0 0 0 100 4 0 0 0 13 1 10 0 0 3 0 3 0 0 0 100 5 0 0 3 217 105 10 0 0 0 0 302 0 0 0 100 6 0 0 0 18 3 42 1 0 4 0 1328 0 0 0 100 7 0 0 24 318 154 120 0 1 3 0 266 0 0 0 100 March 2, 2026 at 06:57:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 20 0 0 2871 102 1453 34 260 82 0 5934 7 3 0 90 1 8 0 7 745 10 1326 23 280 34 0 8590 6 2 0 91 2 0 0 0 729 3 1265 37 200 28 0 5602 6 2 0 92 3 5 0 0 683 8 1249 39 249 60 0 7968 6 2 0 91 4 1 0 0 670 7 1201 25 247 50 0 6113 5 2 0 93 5 17 0 3 847 108 1143 13 169 17 0 4798 5 2 0 94 6 26 0 0 570 4 1057 25 241 29 1 7726 5 2 0 93 7 0 0 381 747 150 933 18 151 62 1 4900 5 2 0 93 March 2, 2026 at 06:57:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 117 0 1 0 0 1 0 1 0 99 1 0 0 7 14 3 12 0 1 1 0 565 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 4 0 0 0 100 3 0 0 0 8 1 4 0 1 0 0 0 0 0 0 100 4 0 0 0 23 7 20 0 1 0 0 17 0 0 0 100 5 0 0 3 221 110 10 0 0 0 0 302 0 0 0 100 6 0 0 0 22 4 48 3 0 7 0 1341 0 0 0 100 7 0 0 17 322 154 124 0 0 0 0 277 0 0 0 100 March 2, 2026 at 06:57:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 647 0 0 2136 101 141 1 9 5 10 904 1 1 0 98 1 751 0 120 48 6 75 0 13 10 11 683 0 0 0 99 2 114 0 0 45 0 65 0 14 13 11 209 0 0 0 100 3 23 0 2 41 0 39 0 8 9 4 175 0 0 0 100 4 16 0 0 50 4 50 0 6 10 5 116 0 0 0 100 5 18 0 3 249 106 46 0 5 2 4 418 0 0 0 100 6 1906 0 0 39 2 63 4 5 13 2 1629 0 1 0 99 7 11 0 17 333 154 125 0 5 5 2 295 0 0 0 100 March 2, 2026 at 06:57:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 110 0 0 1 0 0 0 1 0 99 1 0 0 7 23 9 16 1 0 3 0 571 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 4 0 0 0 12 2 6 0 1 0 0 0 0 0 0 100 5 0 0 3 218 106 12 0 0 1 0 302 0 0 0 100 6 0 0 0 16 4 36 2 0 3 0 1414 0 0 0 99 7 0 0 17 310 153 106 1 0 1 0 276 0 0 0 100 March 2, 2026 at 06:57:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2192 104 286 0 33 219 0 5 0 1 0 99 1 0 0 7 101 10 182 0 31 220 0 882 0 1 0 99 2 0 0 0 74 0 144 0 26 213 0 0 0 1 0 99 3 0 0 0 167 87 323 0 41 203 0 4 0 1 0 99 4 0 0 0 94 1 183 0 41 216 0 8 0 1 0 99 5 0 0 3 294 106 173 2 29 259 0 304 0 1 0 99 6 0 0 0 91 3 208 0 36 251 0 1412 0 1 0 99 7 0 0 17 373 153 251 0 33 189 0 266 0 1 0 99 March 2, 2026 at 06:57:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2115 105 110 0 0 0 0 5 0 1 0 99 1 0 0 7 21 4 18 0 2 5 0 566 0 0 0 100 2 0 0 0 10 0 10 0 1 0 0 0 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 216 105 10 0 0 0 0 302 0 0 0 100 6 0 0 0 13 2 36 2 0 1 0 1412 0 0 0 100 7 0 0 17 310 153 106 1 0 0 0 276 0 0 0 100 March 2, 2026 at 06:57:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 168 0 0 2218 118 342 15 29 4 1 1571 2 1 0 97 1 170 0 7 189 10 393 15 59 4 0 2530 2 1 0 97 2 26 0 0 139 1 364 8 50 4 0 1802 2 0 0 98 3 1 0 0 59 1 85 2 25 17 0 1147 3 0 0 97 4 274 0 6 164 35 325 2 44 4 0 1661 1 1 0 98 5 102 0 17 295 110 169 5 29 3 3 1678 2 0 0 98 6 246 0 0 134 6 301 12 46 5 1 3128 2 1 0 97 7 22 0 115 275 106 195 3 29 5 0 1503 1 0 0 99 March 2, 2026 at 06:57:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 102 0 0 0 0 0 0 1 0 99 1 0 0 7 12 3 6 0 0 3 0 559 0 0 0 100 2 0 0 0 7 0 2 0 1 2 0 0 0 0 0 100 3 0 0 0 24 7 24 0 1 1 0 9 0 0 0 100 4 0 0 0 110 51 102 0 0 0 0 0 0 0 0 100 5 0 0 3 226 106 20 0 0 0 0 303 0 0 0 100 6 0 0 0 13 2 38 1 2 2 0 1417 0 0 0 100 7 0 0 17 208 103 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 14 2119 103 128 0 10 7 0 18 0 1 0 99 1 0 0 7 27 7 30 0 7 15 0 576 0 0 0 100 2 0 0 10 20 3 22 0 3 8 0 1 0 1 0 99 3 0 0 0 34 7 28 0 3 3 0 42 0 0 0 100 4 0 0 0 84 29 88 0 1 1 0 27 0 0 0 100 5 0 0 3 235 106 35 1 6 13 0 324 0 0 0 100 6 0 0 9 78 26 106 1 6 17 0 1424 0 0 0 99 7 0 0 17 222 104 24 0 3 8 0 410 0 0 0 100 March 2, 2026 at 06:57:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2170 101 237 0 33 136 0 0 0 1 0 99 1 0 0 7 95 9 161 1 29 147 0 564 0 1 0 99 2 0 0 0 70 1 124 1 21 162 0 0 0 0 0 100 3 0 0 0 153 89 125 0 35 122 0 1 0 0 0 99 4 0 0 0 77 1 141 0 27 130 0 0 0 0 0 100 5 0 0 3 292 106 164 0 24 145 0 302 0 1 0 99 6 0 0 7 194 52 302 2 33 168 0 1331 0 1 0 99 7 0 0 17 350 104 288 0 21 83 0 266 0 0 0 100 March 2, 2026 at 06:57:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2110 102 107 0 2 0 0 1 0 1 0 99 1 0 0 7 37 3 14 0 3 2 0 557 0 0 0 100 2 0 0 0 21 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 37 7 14 0 0 0 0 7 0 0 0 100 4 0 0 0 28 2 6 0 0 0 0 1 0 0 0 100 5 0 0 3 242 107 28 0 2 0 0 304 0 0 0 100 6 0 0 0 133 53 140 1 1 3 0 1329 0 0 0 100 7 0 0 17 226 103 6 1 1 0 0 266 0 0 0 100 March 2, 2026 at 06:57:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 102 117 0 1 0 0 1 0 1 0 99 1 0 0 7 14 3 10 1 0 5 0 566 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 5 0 0 0 100 3 0 0 0 37 13 28 0 0 0 0 40 0 0 0 100 4 0 0 0 12 1 8 0 1 0 0 10 0 0 0 100 5 0 0 3 228 112 12 0 1 0 0 302 0 0 0 100 6 0 0 0 41 11 72 1 2 0 0 1341 0 0 0 100 7 0 0 17 301 147 98 0 1 1 0 267 0 0 0 100 March 2, 2026 at 06:57:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2829 104 1337 31 235 23 0 5204 6 3 0 91 1 43 0 0 763 16 1311 43 269 38 0 7459 6 2 0 91 2 9 0 0 710 2 1216 31 187 50 0 5416 6 2 0 93 3 12 0 0 687 5 1265 42 225 20 0 7443 6 2 0 92 4 30 0 7 628 2 1128 26 238 21 0 6207 6 2 0 92 5 27 0 3 811 108 1024 29 150 17 0 5195 5 2 0 93 6 4 0 0 608 12 1176 33 244 50 0 8393 6 2 0 92 7 14 0 367 649 133 756 8 131 23 0 4436 5 2 0 94 March 2, 2026 at 06:57:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 104 0 1 1 0 0 0 1 0 99 1 0 0 0 110 52 102 0 0 5 0 294 0 0 0 100 2 0 0 0 20 2 8 0 0 1 0 0 0 0 0 100 3 0 0 0 18 6 8 0 0 1 0 5 0 0 0 100 4 0 0 7 20 5 12 0 1 1 0 271 0 0 0 100 5 0 0 7 217 105 10 0 0 1 0 301 0 0 0 100 6 0 0 0 25 7 44 2 1 2 0 1331 0 0 0 99 7 0 0 21 216 104 16 0 2 0 0 266 0 0 0 100 March 2, 2026 at 06:57:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 29 0 2 2229 101 297 0 49 250 12 179 0 2 0 98 1 30 0 0 226 30 324 0 63 249 5 475 0 1 0 99 2 13 0 0 119 1 188 0 37 185 2 50 0 1 0 99 3 6 0 0 239 117 215 1 40 190 2 77 0 1 0 99 4 0 0 7 121 3 208 1 45 235 0 304 0 1 0 99 5 20 0 3 314 104 198 0 28 287 1 341 0 1 0 99 6 1360 0 112 125 6 285 3 34 288 9 2319 2 2 0 97 7 2021 0 17 417 103 404 2 43 186 13 689 0 1 0 98 March 2, 2026 at 06:57:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 66 0 2 0 0 0 0 1 0 99 1 0 0 0 47 1 40 0 0 8 0 299 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 113 54 108 0 0 0 0 5 0 0 0 100 4 0 0 7 12 3 8 0 0 0 0 270 0 0 0 100 5 0 0 3 216 105 10 0 0 0 0 302 0 0 0 100 6 0 0 0 22 3 44 1 0 4 0 1413 0 0 0 100 7 0 0 17 209 103 6 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:57:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 72 0 3 1 0 5 0 1 0 99 1 0 0 0 63 2 60 1 2 8 0 316 0 0 0 100 2 0 0 0 12 1 12 0 1 1 0 1 0 0 0 100 3 0 0 0 126 58 124 1 0 0 0 332 0 0 0 100 4 0 0 7 14 3 12 0 0 0 0 274 0 0 0 100 5 0 0 3 220 109 8 1 0 0 0 300 0 0 0 100 6 1 0 0 25 4 54 0 0 4 0 1422 0 0 0 100 7 0 0 17 214 104 8 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 101 104 0 0 0 0 0 0 1 0 99 1 0 0 0 15 5 10 0 0 10 0 303 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 110 50 110 0 1 0 0 0 0 0 0 100 4 0 0 7 12 3 8 0 0 0 0 270 0 0 0 100 5 0 0 3 218 106 12 0 0 0 0 303 0 0 0 100 6 0 0 0 21 2 44 2 1 0 0 1412 0 0 0 100 7 0 0 17 210 104 6 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 58 0 0 2167 104 246 5 23 10 1 1236 2 1 0 97 1 283 0 0 74 7 102 7 20 10 1 1975 2 1 0 97 2 435 0 0 64 1 183 4 25 4 1 1823 1 0 0 98 3 274 0 0 123 28 217 2 24 7 0 1669 2 0 0 98 4 71 0 7 74 4 145 3 29 3 0 1475 1 0 0 98 5 31 0 3 270 106 162 7 26 2 0 2060 2 1 0 97 6 1 0 0 90 5 196 7 29 8 0 2744 1 0 0 99 7 4 0 101 315 124 216 4 22 2 0 1439 1 0 0 99 March 2, 2026 at 06:57:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2181 103 237 0 25 134 0 4 0 1 0 99 1 0 0 0 95 1 175 0 28 196 0 320 0 1 0 99 2 0 0 0 160 0 320 0 28 138 1 11 0 1 0 99 3 0 0 0 159 89 123 1 31 154 0 11 0 1 0 99 4 0 0 7 96 3 175 0 30 138 0 262 0 1 0 99 5 0 0 3 292 105 151 0 25 124 0 309 0 1 0 99 6 0 0 0 73 2 169 1 32 124 0 1430 0 1 0 99 7 0 0 31 390 159 261 0 24 185 0 281 0 1 0 99 March 2, 2026 at 06:57:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2120 102 108 0 5 2 0 13 0 1 0 99 1 0 0 0 28 4 35 1 7 18 2 462 0 0 0 100 2 0 0 8 16 0 14 0 5 6 0 3 0 1 0 99 3 0 0 0 19 1 12 0 3 7 0 7 0 0 0 100 4 0 0 7 31 6 188 1 1 2 0 624 0 0 0 100 5 0 0 3 244 105 41 1 6 4 0 308 0 0 0 100 6 2 0 7 23 2 58 1 5 9 0 1442 0 0 0 99 7 0 0 17 344 161 147 1 7 12 0 306 0 0 0 100 March 2, 2026 at 06:57:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 111 0 1 0 0 1 0 1 0 99 1 0 0 0 22 2 18 0 1 1 0 308 0 0 0 100 2 0 0 0 9 1 4 0 1 0 0 1 0 0 0 100 3 0 0 0 10 0 5 0 1 0 0 0 0 0 0 100 4 0 0 7 17 4 12 0 1 0 0 269 0 0 0 100 5 0 0 3 223 110 10 0 0 0 0 302 0 0 0 100 6 0 0 0 24 5 48 2 0 1 0 1340 0 0 0 100 7 0 0 24 336 163 134 1 1 0 0 283 0 0 0 100 March 2, 2026 at 06:57:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2108 101 107 0 0 0 0 0 0 1 0 99 1 0 0 0 33 5 12 0 1 6 0 300 0 0 0 100 2 0 0 0 29 0 8 0 1 0 0 0 0 0 0 100 3 0 0 0 21 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 28 3 8 0 0 0 0 260 0 0 0 100 5 0 0 3 232 104 10 0 0 0 0 300 0 0 0 100 6 0 0 0 43 6 54 1 1 5 0 1337 0 0 0 100 7 0 0 17 338 159 118 0 1 0 0 275 0 0 0 100 March 2, 2026 at 06:57:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 101 106 0 0 1 0 0 0 1 0 99 1 0 0 0 12 3 4 0 0 7 0 301 0 0 0 100 2 0 0 0 18 1 10 0 0 1 0 0 0 0 0 100 3 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 4 0 0 7 16 4 10 0 1 0 0 260 0 0 0 100 5 0 0 3 217 105 10 0 0 1 0 302 0 0 0 100 6 0 0 0 18 4 38 1 1 7 0 1328 0 0 0 99 7 0 0 17 326 159 126 0 1 1 0 275 0 0 0 100 March 2, 2026 at 06:57:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2771 102 1305 39 262 171 0 5338 5 3 0 92 1 0 0 0 745 5 1428 52 314 189 0 6724 5 2 0 92 2 0 0 0 592 0 944 29 185 127 0 5088 5 2 0 93 3 0 0 0 682 80 1196 58 302 180 0 7328 5 2 0 92 4 0 0 7 651 3 1173 38 225 165 1 5007 6 2 0 92 5 0 0 3 791 104 1069 28 185 185 0 4528 5 2 0 93 6 0 0 0 615 10 1161 40 251 156 0 6503 5 2 0 93 7 0 0 311 797 152 1056 22 158 122 0 4026 4 2 0 95 March 2, 2026 at 06:57:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 0 2228 102 308 4 33 5 0 743 1 1 0 98 1 9 0 0 131 3 213 10 37 8 0 1149 1 0 0 99 2 0 0 0 120 1 189 9 23 12 0 809 1 0 0 99 3 0 0 0 135 1 224 5 32 2 0 1069 1 0 0 99 4 0 0 7 87 4 138 2 32 5 0 1396 1 0 0 99 5 0 0 3 291 105 133 0 13 1 0 865 1 0 0 99 6 0 0 0 192 55 264 7 27 20 0 2130 1 1 0 98 7 0 0 73 265 104 102 2 19 1 0 724 0 0 0 99 March 2, 2026 at 06:57:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 101 106 0 0 0 0 0 0 1 0 99 1 0 0 0 24 4 22 0 3 4 0 308 0 0 0 100 2 0 0 0 12 1 12 0 1 0 0 1 0 0 0 100 3 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 4 0 0 7 15 3 12 0 1 0 0 278 0 0 0 100 5 0 0 3 221 111 8 0 0 0 0 300 0 0 0 100 6 0 0 0 137 61 168 1 0 3 0 1356 0 0 0 99 7 0 0 17 219 105 18 0 2 0 0 277 0 0 0 100 March 2, 2026 at 06:57:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 96 0 2 0 0 0 0 1 0 99 1 0 0 0 26 2 18 0 0 4 0 300 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 7 13 3 8 0 0 0 0 270 0 0 0 100 5 0 0 3 218 106 12 0 0 0 0 303 0 0 0 100 6 0 0 0 120 56 144 1 1 4 0 1334 0 0 0 99 7 0 0 17 208 103 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 110 0 0 0 0 0 0 1 0 99 1 0 0 0 9 2 4 0 0 3 0 295 0 0 0 100 2 0 0 0 9 1 4 0 0 1 0 1 0 0 0 100 3 0 0 0 12 0 12 0 1 2 0 0 0 0 0 100 4 0 0 7 12 3 8 0 0 0 0 270 0 0 0 100 5 0 0 3 215 104 8 1 0 0 0 300 0 0 0 100 6 0 0 0 42 17 64 1 0 1 0 1334 0 0 0 100 7 0 0 17 293 145 90 0 1 0 0 268 0 0 0 100 March 2, 2026 at 06:57:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2181 101 273 0 32 185 0 0 0 1 0 99 1 0 0 0 99 2 203 1 35 204 0 309 0 1 0 99 2 0 0 0 67 0 135 0 29 195 0 0 0 0 0 100 3 0 0 0 178 84 179 0 32 230 0 0 0 1 0 99 4 0 0 7 164 7 309 0 29 165 0 268 0 1 0 99 5 0 0 3 294 105 176 0 32 230 0 312 0 1 0 99 6 0 0 0 103 5 227 2 39 220 0 1650 0 1 0 99 7 0 0 17 374 154 249 0 30 238 0 267 0 1 0 99 March 2, 2026 at 06:57:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 114 0 0 0 0 1 0 1 0 99 1 0 0 0 10 2 7 0 1 0 0 306 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 27 11 22 0 0 0 0 275 0 0 0 100 5 0 0 3 217 104 12 1 0 0 0 328 0 0 0 100 6 0 0 0 12 2 38 0 0 1 0 1329 0 0 0 100 7 0 0 17 313 155 108 1 0 0 0 268 0 0 0 100 March 2, 2026 at 06:57:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 118 0 0 0 0 1 0 1 0 99 1 0 0 0 14 2 10 0 0 1 0 296 0 0 0 100 2 0 0 0 11 1 10 0 1 1 0 1 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 44 0 0 0 100 4 1 0 7 28 9 28 0 0 0 0 281 0 0 0 100 5 0 0 3 224 112 12 0 0 1 0 312 0 0 0 100 6 0 0 0 22 5 50 1 0 1 0 1342 0 0 0 100 7 0 0 17 319 156 120 0 0 0 0 276 0 0 0 100 March 2, 2026 at 06:57:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2120 113 136 0 1 0 0 0 0 1 0 99 1 0 0 0 9 2 4 0 0 6 0 309 0 0 0 100 2 0 0 0 7 0 2 0 1 1 0 0 0 0 0 100 3 0 0 0 9 0 10 0 1 2 0 0 0 0 0 100 4 0 0 7 21 8 14 0 0 0 0 265 0 0 0 100 5 0 0 3 216 104 10 1 0 0 0 310 0 0 0 100 6 0 0 0 12 2 36 1 0 2 0 1328 0 0 0 100 7 0 0 17 290 144 84 0 0 0 0 272 0 0 0 100 March 2, 2026 at 06:57:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2156 151 210 0 0 1 0 0 0 1 0 99 1 0 0 0 13 3 8 0 0 3 0 305 0 0 0 100 2 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 4 0 0 7 22 7 16 0 1 0 0 583 0 0 0 100 5 0 0 3 217 105 12 0 0 1 0 312 0 0 0 100 6 0 0 0 26 8 48 2 0 3 0 1337 0 0 0 99 7 0 0 17 210 104 6 0 0 1 0 267 0 0 0 100 March 2, 2026 at 06:57:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1905 0 0 2193 151 247 2 9 5 9 386 0 1 0 98 1 25 0 0 48 2 50 0 12 15 6 373 0 0 0 100 2 11 0 0 36 0 34 0 7 7 5 86 0 0 0 100 3 9 0 0 48 0 54 0 9 10 2 169 0 0 0 100 4 15 0 7 49 3 52 0 6 8 1 362 0 0 0 100 5 1357 0 115 233 104 56 2 6 7 11 1275 2 1 0 98 6 126 0 0 57 7 93 1 8 10 12 1403 0 0 0 99 7 20 0 19 242 106 42 1 6 7 6 388 0 0 0 100 March 2, 2026 at 06:57:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 0 2156 151 210 0 2 1 0 5 0 1 0 99 1 0 0 0 16 1 10 0 1 13 0 307 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 13 3 6 0 0 0 0 260 0 0 0 100 5 0 0 3 222 105 22 0 1 0 0 312 0 0 0 100 6 0 0 0 22 7 46 1 0 9 0 1417 0 0 0 99 7 24 0 17 210 104 6 0 0 1 0 271 0 0 0 100 March 2, 2026 at 06:57:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2156 151 206 0 0 0 0 0 0 1 0 99 1 0 0 0 17 1 14 0 0 2 0 298 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 3 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 4 0 0 7 13 3 10 0 0 0 0 266 0 0 0 100 5 0 0 3 224 110 10 1 0 0 0 310 0 0 0 100 6 0 0 0 45 15 70 1 0 1 0 1438 0 0 0 99 7 0 0 17 214 103 14 0 1 0 0 272 0 0 0 100 March 2, 2026 at 06:57:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 103 106 0 0 0 0 0 0 1 0 99 1 0 0 0 18 1 14 0 0 2 0 312 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 23 7 18 0 1 0 0 267 0 0 0 100 5 0 0 3 318 154 114 0 2 1 0 313 0 0 0 100 6 0 0 0 20 3 52 1 2 3 0 1731 0 0 0 99 7 0 0 17 210 104 6 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:57:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 106 0 0 0 0 0 0 1 0 99 1 0 0 0 15 1 10 0 1 5 0 297 0 0 0 100 2 0 0 0 7 1 2 0 1 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 21 8 16 0 0 0 0 266 0 0 0 100 5 0 0 3 289 141 82 0 0 0 0 311 0 0 0 100 6 0 0 0 43 16 68 1 1 1 0 1407 0 0 0 100 7 0 0 17 214 103 14 1 1 0 0 266 0 0 0 100 March 2, 2026 at 06:58:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 104 0 0 0 0 0 0 1 0 99 1 0 0 0 12 2 8 1 1 5 0 302 0 0 0 100 2 0 0 0 14 0 10 0 0 0 0 0 0 0 0 100 3 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 4 1 0 7 23 7 20 1 0 3 0 265 0 0 0 100 5 0 0 3 217 105 12 0 0 0 0 312 0 0 0 100 6 0 0 0 38 15 60 1 0 7 0 1407 0 0 0 99 7 0 0 17 288 142 86 0 1 1 0 266 0 0 0 100 March 2, 2026 at 06:58:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 196 0 0 2146 102 194 5 20 0 1 1262 3 1 0 96 1 1 0 1 60 2 114 5 25 4 0 1383 1 0 0 98 2 9 0 0 61 0 116 1 24 5 0 1231 1 0 0 99 3 521 0 0 87 0 216 3 24 5 0 1639 1 0 0 98 4 30 0 7 73 10 127 8 22 0 0 1923 2 0 0 97 5 328 0 3 260 104 177 5 25 1 0 1755 1 1 0 98 6 2 0 0 80 2 164 9 22 9 0 2546 2 0 0 98 7 0 0 101 341 155 233 2 22 0 0 1232 1 0 0 99 March 2, 2026 at 06:58:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2128 107 118 1 3 1 0 21 0 1 0 99 1 0 0 0 36 6 28 0 3 4 0 354 0 0 0 100 2 0 0 0 31 2 30 0 4 0 0 19 0 0 0 100 3 0 0 0 16 1 8 0 1 0 0 5 0 0 0 100 4 13 0 7 37 11 27 2 2 1 0 296 0 0 0 100 5 0 0 3 226 111 10 0 0 0 0 302 0 0 0 100 6 1 0 0 25 4 50 1 1 8 0 1427 0 0 0 100 7 5 0 45 315 154 112 0 0 0 0 287 0 0 0 100 March 2, 2026 at 06:58:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 104 0 1 0 0 0 0 1 0 99 1 0 0 0 14 3 10 0 0 9 0 315 0 0 0 100 2 0 0 0 15 0 12 0 0 0 0 18 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 21 8 16 0 0 0 0 265 0 0 0 100 5 0 0 3 214 104 8 0 0 0 0 301 0 0 0 100 6 0 0 0 12 2 36 1 0 4 0 1419 0 0 0 100 7 0 0 17 311 154 106 1 0 0 0 267 0 0 0 100 March 2, 2026 at 06:58:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 104 0 0 1 0 0 0 1 0 99 1 0 0 0 11 3 4 0 0 5 0 295 0 0 0 100 2 0 0 0 19 1 14 0 1 0 0 0 0 0 0 100 3 0 0 0 12 1 10 0 1 1 0 0 0 0 0 100 4 0 0 7 30 11 22 1 0 1 0 270 0 0 0 100 5 0 0 3 216 105 10 0 0 1 0 301 0 0 0 100 6 0 0 0 17 5 38 1 0 3 0 1422 0 0 0 100 7 0 0 17 308 153 104 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:58:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2159 101 206 0 23 112 0 0 0 1 0 99 1 0 0 0 69 2 130 0 26 172 0 305 0 0 0 100 2 0 0 0 68 0 123 0 17 120 0 0 0 0 0 100 3 0 0 0 149 76 139 0 18 152 0 0 0 0 0 100 4 0 0 7 160 10 295 0 27 146 0 267 0 0 0 99 5 0 0 3 280 104 143 1 25 139 0 300 0 1 0 99 6 0 0 0 75 2 172 1 25 129 0 1418 0 1 0 99 7 0 0 17 360 154 214 0 20 120 0 266 0 0 0 100 March 2, 2026 at 06:58:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2114 101 103 2 7 1 1 55 0 1 0 99 1 0 0 7 38 4 29 1 6 6 0 321 0 0 0 100 2 0 0 0 25 0 27 0 4 13 0 64 0 0 0 100 3 0 0 0 16 0 10 0 1 2 0 2 0 0 0 100 4 0 0 7 31 5 33 1 5 14 0 307 0 0 0 100 5 0 0 3 222 105 21 0 5 12 0 316 0 0 0 100 6 0 0 0 46 11 83 3 7 13 0 1399 0 0 0 99 7 0 0 26 317 153 112 0 2 4 0 273 0 1 0 99 March 2, 2026 at 06:58:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 113 0 0 0 0 0 0 1 0 99 1 0 0 0 16 2 12 0 0 1 0 313 0 0 0 100 2 0 0 7 16 1 10 0 1 0 0 0 0 0 0 100 3 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 4 0 0 7 18 3 18 0 1 1 0 267 0 0 0 100 5 0 0 3 221 110 8 0 0 1 0 300 0 0 0 100 6 0 0 0 41 13 68 1 0 4 0 1355 0 0 0 99 7 0 0 17 313 153 108 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:58:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2108 101 107 0 0 0 0 0 0 1 0 99 1 0 0 0 32 4 8 0 0 2 0 301 0 0 0 100 2 0 0 0 32 0 10 0 0 0 0 0 0 0 0 100 3 0 0 0 24 1 4 0 1 0 0 1 0 0 0 100 4 0 0 7 30 3 8 1 0 0 0 260 0 0 0 100 5 0 0 3 237 105 20 0 1 0 0 302 0 0 0 100 6 0 0 0 42 9 50 1 1 10 0 1339 0 0 0 99 7 0 0 17 325 153 104 1 0 0 0 266 0 0 0 100 March 2, 2026 at 06:58:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2107 101 106 0 0 0 0 0 0 1 0 99 1 0 0 0 13 2 6 1 1 9 0 305 0 0 0 100 2 0 0 0 14 0 8 0 0 0 0 0 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 12 3 6 0 0 0 0 260 0 0 0 100 5 0 0 3 218 105 10 1 0 0 0 301 0 0 0 100 6 0 0 0 24 8 48 0 0 2 0 1335 0 0 0 100 7 0 0 17 309 153 104 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:58:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 2939 105 1601 27 285 243 0 5928 7 3 0 90 1 7 0 0 801 6 1495 41 302 276 1 8186 7 3 0 90 2 3 0 0 773 1 1324 25 210 220 0 5464 5 2 0 92 3 25 0 0 838 91 1405 37 295 304 0 8116 6 3 0 91 4 52 0 7 769 7 1391 30 276 264 1 6551 6 2 0 92 5 9 0 3 1010 137 1361 25 206 258 0 5063 5 2 0 93 6 5 0 0 677 5 1270 23 256 253 0 7937 5 3 0 92 7 30 0 381 771 107 1094 17 165 198 0 4367 4 2 0 94 March 2, 2026 at 06:58:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2121 108 122 0 0 0 0 12 0 1 0 99 1 0 0 0 9 2 4 0 0 3 0 295 0 0 0 100 2 0 0 0 13 0 8 0 0 0 0 0 0 0 0 100 3 0 0 0 108 51 102 0 0 0 0 4 0 0 0 100 4 0 0 7 16 5 12 0 1 0 0 262 0 0 0 100 5 0 0 3 213 103 8 0 0 0 0 310 0 0 0 100 6 0 0 0 16 3 40 1 0 1 0 1329 0 0 0 100 7 0 0 17 213 103 14 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:58:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 643 0 0 2155 108 140 1 10 5 4 916 1 1 0 98 1 2 0 0 43 2 43 0 11 6 0 382 0 0 0 100 2 38 0 0 40 0 35 0 6 3 4 79 0 0 0 100 3 7 0 0 43 3 42 0 6 2 1 103 0 0 0 100 4 2604 0 121 36 6 57 2 5 3 10 682 1 1 0 98 5 145 0 3 357 156 175 0 13 20 13 510 0 0 0 100 6 22 0 3 58 6 102 1 11 15 10 1561 0 0 0 99 7 22 0 17 258 104 63 1 11 10 8 357 0 0 0 100 March 2, 2026 at 06:58:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 106 112 0 0 0 0 5 0 1 0 99 1 0 0 0 20 2 22 0 2 2 0 309 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 11 3 6 0 0 0 0 260 0 0 0 100 5 0 0 3 314 153 108 1 0 0 0 310 0 0 0 100 6 0 0 0 13 3 38 0 0 2 0 1412 0 0 0 100 7 0 0 17 212 104 8 0 1 1 0 267 0 0 0 100 March 2, 2026 at 06:58:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2115 105 116 0 1 0 0 326 0 1 0 99 1 0 0 0 21 2 14 0 0 5 0 301 0 0 0 100 2 0 0 0 16 2 14 0 1 1 0 0 0 0 0 100 3 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 4 0 0 7 15 4 8 0 0 1 0 260 0 0 0 100 5 0 0 3 315 154 110 0 0 1 0 312 0 0 0 100 6 0 0 0 24 7 46 2 0 5 0 1418 0 0 0 99 7 1 0 17 212 103 8 1 0 1 0 306 0 0 0 100 March 2, 2026 at 06:58:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 104 0 0 0 0 0 0 1 0 99 1 0 0 0 15 1 10 0 0 1 0 293 0 0 0 100 2 0 0 0 8 1 4 0 0 2 0 0 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 5 0 0 3 316 153 114 0 0 3 0 310 0 0 0 100 6 0 0 0 21 6 46 1 0 2 0 1415 0 0 0 99 7 0 0 17 211 104 8 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:58:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 84 0 0 2171 102 192 8 24 0 0 1409 2 1 0 97 1 202 0 0 170 6 267 3 25 5 0 1750 2 1 0 97 2 88 0 0 219 49 397 15 35 1 0 1539 2 1 0 97 3 0 0 0 82 1 273 4 33 0 0 1657 1 0 0 99 4 246 0 7 103 4 244 12 35 4 1 1751 2 1 0 97 5 156 0 3 322 108 294 3 30 8 0 2001 1 0 0 98 6 195 0 0 110 7 326 7 41 7 1 3242 2 1 0 97 7 77 0 101 328 107 301 7 33 9 0 2054 2 1 0 98 March 2, 2026 at 06:58:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 106 0 0 0 0 0 0 1 0 99 1 0 0 0 100 45 98 0 1 2 0 317 0 0 0 100 2 0 0 0 44 15 38 0 1 0 0 3 0 0 0 100 3 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 4 0 0 7 18 3 20 0 1 0 0 267 0 0 0 100 5 0 0 2 221 108 6 1 0 0 0 300 0 0 0 100 6 0 0 0 25 5 52 1 0 3 0 1433 0 0 0 100 7 0 0 18 211 103 8 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:58:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2119 101 90 1 7 4 1 91 0 1 0 99 1 0 0 0 129 56 154 1 4 5 1 601 0 0 0 100 2 0 0 0 27 1 25 0 8 14 0 21 0 0 0 100 3 0 0 14 19 2 15 1 6 8 0 19 0 0 0 100 4 0 0 7 25 4 28 1 11 11 0 286 0 0 0 100 5 0 0 12 223 104 20 0 6 14 0 303 0 1 0 99 6 0 0 7 67 7 58 2 5 4 0 1215 0 0 0 100 7 0 0 17 230 103 27 1 3 3 0 289 0 0 0 100 March 2, 2026 at 06:58:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 104 0 0 0 0 0 0 1 0 99 1 0 0 0 84 39 106 0 0 4 0 1330 0 0 0 100 2 0 0 0 17 1 12 0 0 0 0 2 0 0 0 100 3 0 0 0 37 14 33 0 2 0 0 0 0 0 0 100 4 0 0 7 18 5 12 0 0 0 0 263 0 0 0 100 5 0 0 3 218 103 16 0 1 0 0 300 0 0 0 100 6 0 0 0 26 8 20 0 0 6 0 303 0 0 0 100 7 0 0 24 209 103 6 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:58:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2187 101 220 0 21 128 0 0 0 1 0 99 1 0 0 0 85 3 155 1 31 136 0 1339 0 1 0 99 2 0 0 0 104 0 156 0 17 121 0 0 0 0 0 100 3 0 0 112 251 130 240 0 25 148 0 0 0 1 0 99 4 0 0 7 120 11 186 0 35 195 0 265 0 1 0 99 5 0 0 3 383 104 319 0 32 118 0 302 0 1 0 99 6 0 0 0 117 10 179 1 28 164 0 303 0 1 0 99 7 0 0 17 290 104 142 0 18 152 0 266 0 1 0 99 March 2, 2026 at 06:58:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 2110 102 108 0 1 0 0 12 0 1 0 99 1 1 0 0 14 3 38 1 0 2 0 1337 0 0 0 100 2 0 0 0 15 0 10 0 0 0 0 7 0 0 0 100 3 1 0 7 9 0 8 0 1 0 0 6 0 0 0 100 4 1 0 7 119 56 114 0 1 0 0 266 0 0 0 100 5 0 0 3 216 103 10 1 0 0 0 305 0 0 0 100 6 1 0 0 35 12 30 0 1 3 0 310 0 0 0 100 7 5 0 17 212 104 8 0 1 0 0 272 0 0 0 100 March 2, 2026 at 06:58:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2855 103 1380 30 252 29 0 7044 7 3 0 90 1 23 0 0 729 4 1346 39 280 26 0 7699 6 2 0 92 2 4 0 0 664 2 1138 24 205 25 0 6131 6 2 0 92 3 40 0 0 622 1 1154 41 242 53 3 7198 6 2 0 92 4 2 0 7 717 25 1234 29 222 22 0 6389 5 2 0 93 5 2 0 3 844 115 1065 16 175 18 1 4998 4 2 0 94 6 0 0 0 668 10 1205 32 238 33 0 6505 6 2 0 93 7 0 0 381 767 130 1020 17 139 37 0 4719 6 2 0 93 March 2, 2026 at 06:58:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 138 1 0 0 0 1044 0 1 0 99 1 0 0 0 11 2 4 0 0 5 0 290 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 13 0 8 0 0 0 0 0 0 0 0 100 4 0 0 7 13 3 8 0 1 0 0 260 0 0 0 100 5 0 0 3 219 104 18 0 1 0 0 301 0 0 0 100 6 0 0 0 11 2 6 0 0 2 0 294 0 0 0 100 7 0 0 17 318 158 114 0 0 0 0 272 0 0 0 100 March 2, 2026 at 06:58:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 132 0 2 1 0 1044 0 1 0 99 1 0 0 0 22 3 12 0 2 4 0 300 0 0 0 100 2 0 0 0 11 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 16 1 8 0 0 1 0 0 0 0 0 100 4 0 0 7 16 4 8 0 0 1 0 260 0 0 0 100 5 0 0 7 219 106 14 0 1 0 0 307 0 0 0 100 6 0 0 0 17 5 8 0 0 2 0 296 0 0 0 100 7 0 0 21 323 160 118 0 0 1 0 274 0 0 0 100 March 2, 2026 at 06:58:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2200 102 310 2 29 191 0 1044 0 2 0 98 1 0 0 0 100 2 200 0 36 264 0 301 0 1 0 99 2 0 0 0 93 7 172 0 44 235 0 0 0 1 0 99 3 0 0 0 195 96 186 0 39 252 0 0 0 1 0 99 4 0 0 7 92 3 181 0 39 228 0 260 0 1 0 99 5 0 0 3 294 103 177 2 24 236 0 300 0 1 0 99 6 0 0 0 181 2 351 1 44 195 0 294 0 1 0 99 7 0 0 17 388 151 285 0 35 227 0 271 0 1 0 99 March 2, 2026 at 06:58:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 27 0 2 2152 103 157 0 14 18 5 176 0 1 0 99 1 24 0 0 51 2 68 1 11 10 6 514 0 0 0 100 2 10 0 0 78 20 62 1 7 6 0 118 0 0 0 100 3 26 0 0 115 34 112 0 10 3 4 70 0 0 0 100 4 10 0 7 39 3 33 0 5 4 3 308 0 0 0 100 5 4 0 3 241 106 29 0 4 2 2 369 0 0 0 100 6 3247 0 113 29 2 67 4 4 28 17 1556 2 1 0 97 7 138 0 17 273 110 133 0 12 13 16 1783 0 0 0 99 March 2, 2026 at 06:58:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 108 0 0 0 0 10 0 1 0 99 1 0 0 0 11 2 8 0 0 4 0 305 0 0 0 100 2 0 0 0 13 4 6 0 0 0 0 4 0 0 0 100 3 0 0 0 114 50 110 0 0 0 0 0 0 0 0 100 4 0 0 7 13 3 10 0 0 0 0 267 0 0 0 100 5 0 0 3 223 111 8 0 0 0 0 301 0 0 0 100 6 0 0 0 20 4 20 0 0 7 0 310 0 0 0 100 7 0 0 17 215 104 40 2 0 1 0 1383 0 0 0 100 March 2, 2026 at 06:58:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 359 0 2 2172 101 214 7 31 9 0 2693 2 1 0 97 1 42 0 0 74 3 133 8 27 9 0 1847 2 0 0 98 2 35 0 0 65 5 203 4 29 8 0 1642 1 0 0 99 3 0 0 0 197 51 366 3 27 2 0 1587 1 0 0 99 4 97 0 7 75 3 234 5 21 3 0 1410 2 0 0 98 5 234 0 3 260 106 110 5 21 1 1 1541 1 0 0 98 6 186 0 0 67 8 88 8 20 8 1 1939 3 0 0 97 7 9 0 101 258 104 190 10 24 5 0 1918 1 0 0 98 March 2, 2026 at 06:58:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 142 0 2 0 0 1123 0 1 0 99 1 0 0 0 31 9 24 0 2 5 0 309 0 0 0 100 2 0 0 0 16 2 14 0 1 0 0 0 0 0 0 100 3 0 0 0 108 51 104 0 1 0 0 1 0 0 0 100 4 0 0 7 13 4 8 0 0 1 0 260 0 0 0 100 5 0 0 3 215 104 8 1 0 1 0 300 0 0 0 100 6 0 0 0 15 4 10 0 0 3 0 295 0 0 0 100 7 0 0 17 212 105 8 0 1 1 0 266 0 0 0 100 March 2, 2026 at 06:58:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2176 102 287 1 29 161 0 1139 0 1 0 98 1 0 0 0 171 7 323 0 33 162 0 340 0 1 0 99 2 0 0 0 76 0 143 2 27 156 0 93 0 1 0 99 3 0 0 0 207 101 197 1 26 192 0 0 0 1 0 99 4 0 0 7 129 25 195 0 28 171 0 303 0 1 0 99 5 0 0 12 272 104 138 0 23 173 0 302 0 1 0 99 6 0 0 14 74 3 127 1 27 132 3 365 0 1 0 99 7 0 0 24 277 108 118 0 16 118 0 287 0 1 0 99 March 2, 2026 at 06:58:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 103 146 1 1 0 0 1037 0 1 0 99 1 0 0 0 15 3 8 0 1 1 0 299 0 0 0 100 2 0 0 0 8 0 2 0 0 2 0 0 0 0 0 100 3 0 0 0 12 0 12 0 1 0 0 0 0 0 0 100 4 0 0 7 118 55 112 1 0 0 0 265 0 0 0 100 5 0 0 3 213 103 6 0 0 0 0 300 0 0 0 100 6 0 0 0 14 2 9 0 1 3 0 294 0 0 0 100 7 0 0 17 238 115 30 1 0 0 0 285 0 0 0 100 March 2, 2026 at 06:58:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2131 103 150 1 0 0 0 1036 0 1 0 99 1 0 0 0 32 4 14 0 1 0 0 312 0 0 0 100 2 0 0 0 21 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 26 1 6 0 1 0 0 21 0 0 0 100 4 0 0 7 134 53 120 0 1 0 0 267 0 0 0 100 5 0 0 3 239 111 8 0 0 0 0 302 0 0 0 100 6 0 0 112 23 4 25 0 0 1 0 311 0 0 0 100 7 0 0 17 245 111 26 0 0 0 0 277 0 0 0 100 March 2, 2026 at 06:58:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 142 1 0 0 0 1034 0 1 0 99 1 0 0 0 19 3 12 1 0 4 0 315 0 0 0 100 2 0 0 0 8 0 4 0 0 0 0 18 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 7 112 53 106 0 0 0 0 260 0 0 0 100 5 0 0 3 214 103 6 1 0 0 0 300 0 0 0 100 6 0 0 7 13 2 8 0 0 4 0 294 0 0 0 100 7 0 0 17 223 110 18 0 0 0 0 276 0 0 0 100 March 2, 2026 at 06:58:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 2904 104 1515 50 269 27 0 7063 6 3 0 90 1 2 0 0 759 12 1393 46 269 25 0 8067 7 2 0 90 2 1 0 0 636 4 1060 23 226 34 0 6181 5 2 0 93 3 1 0 0 765 18 1430 48 287 22 0 7400 6 2 0 92 4 1 0 0 725 25 1206 28 234 30 0 6365 6 2 0 92 5 3 0 3 833 105 1078 19 182 34 0 4617 5 2 0 94 6 0 0 7 668 17 1205 43 215 58 0 7915 6 2 0 92 7 2 0 367 667 108 930 18 147 14 0 4581 5 2 0 94 March 2, 2026 at 06:58:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2183 104 289 0 27 243 0 1034 0 2 0 98 1 0 0 0 186 1 365 0 38 237 0 295 0 1 0 99 2 0 0 0 101 3 179 0 28 207 0 11 0 1 0 99 3 0 0 0 204 96 224 0 34 274 0 0 0 1 0 99 4 0 0 0 110 6 208 0 34 277 0 5 0 1 0 99 5 0 0 3 284 103 161 0 33 212 0 300 0 1 0 99 6 0 0 7 171 47 249 0 36 234 0 554 0 1 0 99 7 0 0 17 292 111 159 0 24 185 0 266 0 1 0 99 March 2, 2026 at 06:58:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 118 1 3 0 0 1046 0 1 0 99 1 0 0 0 39 1 32 0 1 4 0 306 0 0 0 100 2 0 0 0 12 3 8 0 0 0 0 12 0 0 0 100 3 0 0 0 6 0 2 0 0 0 0 3 0 0 0 100 4 0 0 0 29 10 22 0 1 0 0 15 0 0 0 100 5 0 0 3 213 103 8 0 0 0 0 303 0 0 0 100 6 0 0 7 16 5 12 0 0 6 0 555 0 0 0 100 7 0 0 17 311 154 106 1 0 0 0 271 0 0 0 100 March 2, 2026 at 06:58:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2135 124 186 1 1 0 0 1035 0 1 0 99 1 0 0 0 17 1 14 0 1 1 0 304 0 0 0 100 2 0 0 0 12 3 8 0 0 0 0 13 0 0 0 100 3 0 0 0 11 1 9 0 1 0 0 24 0 0 0 100 4 1 0 0 22 6 14 1 0 0 0 12 0 0 0 100 5 0 0 3 220 108 6 1 0 0 0 300 0 0 0 100 6 0 0 7 27 7 28 0 0 1 0 570 0 0 0 100 7 0 0 17 272 131 72 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:58:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 0 2197 152 276 1 6 4 2 1084 0 1 0 99 1 0 0 0 38 1 26 0 7 6 0 311 0 0 0 100 2 0 0 0 33 3 19 0 2 2 0 35 0 0 0 100 3 2613 0 112 31 1 54 3 4 5 12 388 0 1 0 99 4 155 0 0 68 7 100 1 13 11 16 519 0 0 0 100 5 49 0 5 248 103 60 0 13 7 10 494 0 0 0 100 6 650 0 0 53 4 58 1 13 8 6 1323 1 0 0 98 7 10 0 24 243 104 51 0 8 3 8 592 0 0 0 100 March 2, 2026 at 06:58:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2161 152 236 1 0 0 0 1121 0 1 0 99 1 0 0 0 9 2 4 0 0 2 0 298 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 4 0 0 0 10 2 2 0 0 0 0 0 0 0 0 100 5 0 0 3 212 103 6 0 0 0 0 300 0 0 0 100 6 0 0 0 27 6 22 0 1 3 0 299 0 0 0 100 7 0 0 24 212 105 10 0 1 0 0 537 0 0 0 100 March 2, 2026 at 06:58:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 33 0 0 2283 122 671 9 53 129 0 2743 1 2 0 97 1 61 0 7 226 11 520 3 48 135 1 1755 2 1 0 97 2 232 0 0 170 5 448 4 60 156 1 1806 2 1 0 97 3 313 0 0 191 72 218 11 40 143 2 1793 3 1 0 96 4 80 0 0 157 8 386 11 56 112 0 1616 2 1 0 97 5 409 0 3 361 109 415 3 63 147 2 2150 2 1 0 97 6 0 0 0 193 16 409 5 51 117 0 2073 1 1 0 98 7 4 0 87 319 104 457 2 46 121 0 1961 1 1 0 98 March 2, 2026 at 06:58:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 103 136 1 3 0 0 1123 0 1 0 99 1 0 0 7 20 5 14 0 2 2 0 566 0 0 0 100 2 0 0 0 34 11 32 1 1 0 0 20 0 0 0 100 3 0 0 0 12 0 14 0 1 0 0 3 0 0 0 100 4 0 0 0 112 53 106 0 0 0 0 2 0 0 0 100 5 0 0 3 216 104 10 1 0 0 0 305 0 0 0 100 6 0 0 0 21 3 12 0 0 1 0 295 0 0 0 100 7 0 0 17 208 103 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:58:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2127 103 168 2 8 10 0 1148 0 1 0 99 1 0 0 7 26 3 29 3 2 1 1 645 0 0 0 100 2 0 0 0 40 8 34 1 5 4 0 37 0 0 0 100 3 0 0 0 17 0 24 0 12 15 0 11 0 0 0 100 4 0 0 0 118 51 120 0 6 8 0 9 0 0 0 100 5 0 0 12 230 110 23 0 4 11 0 306 0 1 0 99 6 0 0 0 34 5 40 1 4 9 0 318 0 0 0 100 7 0 0 24 230 105 35 0 5 5 0 375 0 0 0 100 March 2, 2026 at 06:58:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2108 103 143 0 1 0 0 1036 0 1 0 99 1 0 0 7 15 3 6 1 0 1 0 559 0 0 0 100 2 0 0 0 28 7 22 0 0 0 0 10 0 0 0 100 3 0 0 0 10 1 4 0 1 0 0 0 0 0 0 100 4 0 0 0 110 51 102 0 0 0 0 0 0 0 0 100 5 0 0 3 218 103 16 0 1 1 0 300 0 0 0 100 6 0 0 0 14 2 6 0 0 1 0 294 0 0 0 100 7 0 0 17 216 105 8 1 0 0 0 267 0 0 0 100 March 2, 2026 at 06:58:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2110 102 141 1 0 1 0 1034 0 1 0 99 1 24 0 14 33 5 10 0 1 4 0 567 0 0 0 100 2 0 0 0 54 10 26 0 0 1 0 12 0 0 0 100 3 0 0 0 28 2 5 0 2 1 0 0 0 0 0 100 4 24 0 0 132 53 106 0 0 1 0 5 0 0 0 100 5 0 0 7 232 103 10 0 1 1 0 300 0 0 0 100 6 0 0 0 37 5 16 0 1 3 0 297 0 0 0 100 7 0 0 21 226 103 4 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:58:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2112 102 140 1 0 0 0 1030 0 1 0 99 1 0 0 7 16 4 12 0 0 2 0 559 0 0 0 100 2 0 0 0 21 6 16 1 1 3 0 9 0 0 0 100 3 0 0 0 17 1 10 0 0 0 0 0 0 0 0 100 4 0 0 0 109 51 102 0 0 0 0 0 0 0 0 100 5 0 0 3 214 103 6 1 0 0 0 300 0 0 0 100 6 0 0 0 18 3 16 0 3 6 0 295 0 0 0 100 7 0 0 17 210 103 6 0 0 3 0 266 0 0 0 100 March 2, 2026 at 06:58:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 27 0 0 2646 105 1060 32 188 43 0 5428 4 3 0 93 1 6 0 7 531 3 931 21 194 24 0 5945 4 2 0 94 2 0 0 0 568 15 924 12 139 49 0 4204 4 1 0 94 3 33 0 0 567 26 998 23 199 23 0 5740 5 2 0 93 4 0 0 0 529 24 899 23 172 30 0 4552 4 1 0 95 5 0 0 3 672 103 808 12 129 31 0 3707 4 1 0 95 6 0 0 0 484 4 908 25 187 30 0 5406 5 1 0 94 7 0 0 283 630 103 823 18 114 23 0 3296 4 1 0 95 March 2, 2026 at 06:58:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2291 104 415 11 62 3 0 2189 1 1 0 97 1 0 0 7 211 3 335 8 60 3 0 1793 1 1 0 98 2 0 0 0 184 2 307 1 56 13 0 1539 2 0 0 98 3 0 0 0 185 1 317 14 55 19 0 2098 2 1 0 98 4 0 0 0 180 6 302 6 55 4 0 1234 1 0 0 98 5 0 0 3 347 113 210 0 37 2 0 1082 1 0 0 99 6 0 0 0 231 52 301 5 47 10 0 1676 1 0 0 99 7 0 0 101 328 105 199 3 31 14 0 1563 1 0 0 98 March 2, 2026 at 06:58:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 971 0 119 2131 104 204 3 6 7 14 1996 1 1 0 98 1 2379 0 7 56 2 76 2 15 8 15 727 1 1 0 98 2 59 0 2 45 1 53 0 12 6 9 482 0 0 0 100 3 25 0 0 53 1 69 0 15 3 6 227 0 0 0 100 4 16 0 0 48 5 41 0 5 6 6 49 0 0 0 100 5 6 0 2 234 102 27 0 7 8 3 25 0 0 0 100 6 9 0 0 136 53 121 0 6 3 1 355 0 0 0 100 7 0 0 18 233 105 15 1 1 5 0 599 0 0 0 100 March 2, 2026 at 06:58:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 144 1 2 0 0 1122 0 1 0 99 1 0 0 7 10 3 4 0 0 0 0 259 0 0 0 100 2 0 0 0 9 2 4 0 0 3 0 294 0 0 0 100 3 0 0 0 6 0 2 0 0 0 0 10 0 0 0 100 4 0 0 0 20 6 14 0 0 0 0 6 0 0 0 100 5 0 0 3 215 102 14 0 1 0 0 0 0 0 0 100 6 0 0 0 113 53 108 1 0 0 0 301 0 0 0 100 7 0 0 17 213 105 8 0 1 5 0 607 0 0 0 100 March 2, 2026 at 06:58:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2192 103 304 1 30 241 0 1119 0 2 0 98 1 0 0 7 108 3 212 0 39 309 0 260 0 1 0 99 2 0 0 0 180 1 343 1 29 210 0 294 0 1 0 99 3 0 0 0 197 102 194 0 32 275 0 10 0 1 0 99 4 0 0 0 108 5 213 0 38 273 0 5 0 1 0 99 5 0 0 3 292 102 180 0 28 229 0 0 0 0 0 100 6 0 0 0 182 46 279 0 42 261 0 302 0 1 0 99 7 0 0 17 310 104 210 1 33 239 0 554 0 1 0 99 March 2, 2026 at 06:58:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 146 1 1 0 0 1131 0 1 0 99 1 0 0 7 16 3 14 1 2 0 0 268 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 297 0 0 0 100 3 0 0 0 120 56 118 0 0 0 0 13 0 0 0 100 4 0 0 0 25 7 16 1 1 0 0 339 0 0 0 100 5 0 0 3 210 102 4 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 8 0 1 0 0 301 0 0 0 100 7 0 0 17 216 106 12 0 1 1 0 583 0 0 0 100 March 2, 2026 at 06:58:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 0 2207 103 306 11 36 0 0 2613 1 1 0 97 1 0 0 7 131 2 277 3 37 2 0 1913 1 0 0 99 2 221 0 0 84 1 159 5 25 2 0 1616 1 0 0 98 3 0 0 0 151 50 218 8 19 1 0 1110 2 0 0 97 4 438 0 2 69 1 130 10 19 4 0 1823 3 1 0 96 5 73 0 3 273 108 106 8 28 1 0 1300 2 0 0 98 6 146 0 0 109 12 169 13 29 3 0 1718 2 0 0 98 7 105 0 101 309 106 257 10 28 0 1 2221 1 1 0 98 March 2, 2026 at 06:58:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 139 1 7 0 0 1136 0 1 0 99 1 0 0 7 32 6 21 0 3 4 0 284 0 0 0 100 2 0 0 0 10 1 4 0 1 4 0 312 0 0 0 100 3 18 0 0 13 0 8 0 2 0 0 25 0 0 0 100 4 0 0 0 14 2 7 0 2 0 0 5 0 0 0 100 5 0 0 3 228 109 18 1 1 0 0 12 0 0 0 100 6 0 0 0 116 52 106 1 0 0 0 300 0 0 0 100 7 4 0 31 222 106 20 0 1 1 0 542 0 0 0 100 March 2, 2026 at 06:58:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 136 1 0 1 0 1128 0 1 0 99 1 0 0 7 13 3 6 0 1 1 0 260 0 0 0 100 2 0 0 0 13 2 4 1 0 1 0 294 0 0 0 100 3 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 4 0 0 0 13 2 4 0 0 1 0 0 0 0 0 100 5 0 0 7 223 108 16 0 0 1 0 6 0 0 0 100 6 0 0 0 117 55 108 0 0 1 0 303 0 0 0 100 7 0 0 21 219 104 16 0 2 0 0 605 0 0 0 100 March 2, 2026 at 06:58:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2200 104 283 2 41 153 0 1120 0 2 0 98 1 0 0 7 121 3 217 1 45 219 0 288 0 1 0 99 2 0 0 0 155 1 299 0 28 133 0 294 0 1 0 99 3 0 0 0 194 95 192 0 36 176 0 23 0 1 0 99 4 0 0 10 99 1 195 0 35 239 0 3 0 1 0 99 5 0 0 10 299 105 179 3 22 171 0 82 0 0 0 99 6 0 0 0 197 52 277 0 37 172 0 331 0 1 0 99 7 0 0 17 315 108 166 1 24 136 0 550 0 1 0 99 March 2, 2026 at 06:58:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2161 149 235 1 1 0 0 1039 0 1 0 99 1 0 0 7 21 3 12 0 2 0 0 260 0 0 0 100 2 0 0 0 16 1 17 0 3 4 0 297 0 0 0 100 3 0 0 0 22 7 18 0 0 1 0 10 0 0 0 100 4 0 0 0 9 1 2 0 1 0 0 0 0 0 0 100 5 0 0 3 213 102 6 0 0 0 0 0 0 0 0 100 6 0 0 7 19 6 14 0 1 0 0 302 0 0 0 100 7 0 0 17 212 104 6 1 0 2 0 582 0 0 0 100 March 2, 2026 at 06:58:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2133 124 167 1 2 0 0 1037 0 1 0 99 1 0 0 7 104 30 84 0 3 0 0 265 0 0 0 100 2 0 0 0 33 2 10 0 1 1 0 294 0 0 0 100 3 0 0 0 44 9 24 0 1 0 0 15 0 0 0 100 4 0 0 0 29 1 10 1 2 0 0 10 0 0 0 100 5 0 0 3 232 108 4 0 0 0 0 0 0 0 0 100 6 0 0 0 40 5 22 1 1 0 0 314 0 0 0 100 7 0 0 17 234 106 16 0 2 2 0 606 0 0 0 100 March 2, 2026 at 06:58:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2108 102 101 1 3 0 0 421 0 1 0 99 1 0 0 7 118 52 142 0 4 0 0 877 0 0 0 100 2 0 0 0 19 1 10 1 0 3 0 294 0 0 0 100 3 0 0 0 27 7 26 0 1 2 0 8 0 0 0 100 4 0 0 0 11 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 211 102 4 0 0 0 0 0 0 0 0 100 6 0 0 0 14 3 8 0 1 0 0 302 0 0 0 100 7 0 0 17 211 104 6 0 0 1 0 577 0 0 0 100 March 2, 2026 at 06:58:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 34 0 0 2851 104 1419 38 257 31 0 6720 7 3 0 90 1 5 0 7 786 7 1500 51 305 35 0 9278 7 3 0 91 2 1 0 0 705 2 1225 27 207 35 0 5984 6 2 0 92 3 3 0 0 665 8 1192 43 236 17 0 7842 6 2 0 92 4 36 0 0 638 5 1099 32 243 27 0 5854 6 2 0 92 5 1 0 3 798 106 972 19 176 28 0 4772 4 2 0 94 6 7 0 0 652 39 1179 28 237 29 1 7264 6 2 0 92 7 2 0 367 702 107 943 20 122 12 0 4703 4 2 0 94 March 2, 2026 at 06:59:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2198 105 297 0 33 283 0 5 0 1 0 99 1 0 0 7 99 4 221 0 39 252 0 1299 0 1 0 99 2 0 0 0 184 1 366 0 38 224 0 294 0 1 0 99 3 0 0 0 186 95 186 0 37 269 0 0 0 1 0 99 4 0 0 0 106 5 198 0 39 268 0 0 0 1 0 99 5 0 0 3 287 102 171 0 29 202 0 0 0 1 0 99 6 0 0 0 199 50 304 0 44 282 0 312 0 1 0 99 7 0 0 17 296 104 192 1 33 245 0 610 0 1 0 99 March 2, 2026 at 06:59:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 41 0 0 2161 111 149 1 9 3 9 170 0 1 0 99 1 2598 0 119 41 3 105 3 12 13 13 1853 1 1 0 98 2 745 0 0 52 1 69 1 10 8 19 1279 1 0 0 98 3 59 0 2 50 0 61 0 14 10 7 223 0 0 0 100 4 24 0 0 146 53 156 0 9 8 9 58 0 0 0 100 5 4 0 3 240 102 33 0 7 2 2 50 0 0 0 100 6 7 0 0 42 4 32 1 5 4 4 333 0 0 0 100 7 0 0 17 259 104 41 0 3 5 0 580 0 0 0 100 March 2, 2026 at 06:59:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2122 108 132 1 1 0 0 11 0 1 0 99 1 0 0 7 14 3 42 1 1 0 0 1389 0 0 0 100 2 0 0 0 8 1 2 1 0 2 0 294 0 0 0 100 3 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 4 0 0 0 112 52 108 0 0 0 0 7 0 0 0 100 5 0 0 3 219 107 6 0 0 0 0 0 0 0 0 100 6 1 0 0 30 6 36 0 1 0 0 328 0 0 0 100 7 0 0 17 215 105 12 0 0 4 0 540 0 0 0 100 March 2, 2026 at 06:59:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 106 118 0 0 0 0 320 0 1 0 99 1 0 0 7 17 4 42 1 0 1 0 1390 0 0 0 100 2 0 0 0 9 1 6 0 0 6 0 312 0 0 0 100 3 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 4 0 0 0 110 52 104 0 1 0 0 0 0 0 0 100 5 0 0 3 212 102 8 0 0 0 0 5 0 0 0 100 6 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 7 0 0 17 220 108 16 1 0 3 0 536 0 0 0 100 March 2, 2026 at 06:59:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 103 116 0 0 1 0 4 0 1 0 99 1 0 0 7 13 4 36 1 0 1 0 1381 0 0 0 100 2 0 0 0 12 2 6 0 0 5 0 297 0 0 0 100 3 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 4 0 0 0 114 52 108 0 1 0 0 0 0 0 0 100 5 0 0 3 210 102 4 0 0 1 0 0 0 0 0 100 6 0 0 0 19 5 12 0 0 1 0 313 0 0 0 100 7 0 0 17 224 108 24 1 1 3 0 585 0 0 0 100 March 2, 2026 at 06:59:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 125 0 0 2282 103 445 8 70 166 1 1642 2 1 0 97 1 3 0 7 227 5 460 16 71 129 0 2739 2 1 0 97 2 0 0 0 227 3 437 7 63 103 0 1604 2 1 0 98 3 140 0 0 300 88 488 4 73 137 0 1974 1 1 0 98 4 184 0 0 200 7 485 5 75 143 0 1732 1 1 0 98 5 281 0 3 360 103 273 4 42 129 0 1750 2 1 0 97 6 123 0 0 141 3 258 5 51 164 1 1687 2 1 0 97 7 236 0 115 456 153 427 11 60 135 0 2590 3 1 0 96 March 2, 2026 at 06:59:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2123 109 104 1 3 0 0 25 0 1 0 99 1 0 0 7 33 3 54 2 0 0 0 1389 0 0 0 99 2 0 0 0 8 1 2 1 0 0 0 294 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 5 0 0 3 219 102 14 0 0 0 0 3 0 0 0 100 6 0 0 0 13 3 8 0 0 0 0 302 0 0 0 100 7 0 0 17 312 155 108 0 0 0 0 641 0 0 0 100 March 2, 2026 at 06:59:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2124 105 114 0 14 10 0 41 0 1 0 99 1 1 0 7 75 9 100 1 4 4 0 1331 0 0 0 99 2 0 0 0 22 1 22 0 3 3 0 306 0 0 0 100 3 0 0 0 17 1 17 0 1 7 0 4 0 0 0 100 4 0 0 0 22 1 26 0 3 12 2 152 0 0 0 100 5 0 0 3 232 109 17 0 2 5 0 26 0 0 0 100 6 0 0 0 33 4 34 0 4 4 0 333 0 0 0 100 7 0 0 25 326 154 132 0 8 13 0 577 0 1 0 99 March 2, 2026 at 06:59:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 117 0 0 0 0 0 0 1 0 99 1 0 0 14 27 9 50 1 1 0 0 1307 0 0 0 99 2 0 0 0 10 1 4 0 1 1 0 294 0 0 0 100 3 0 0 0 16 2 14 0 1 0 0 1 0 0 0 100 4 0 0 0 11 1 4 0 1 0 0 0 0 0 0 100 5 0 0 3 213 102 4 0 0 0 0 0 0 0 0 100 6 0 0 0 14 3 8 0 1 0 0 302 0 0 0 100 7 0 0 17 313 155 108 0 0 2 0 556 0 0 0 100 March 2, 2026 at 06:59:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2108 101 113 0 0 0 0 0 0 1 0 99 1 0 0 7 44 10 52 0 0 0 0 1303 0 0 0 99 2 0 0 7 24 1 4 0 1 6 0 294 0 0 0 100 3 0 0 0 27 1 4 0 1 0 0 1 0 0 0 100 4 0 0 0 27 2 4 0 2 0 0 0 0 0 0 100 5 0 0 3 227 102 4 0 0 0 0 0 0 0 0 100 6 23 0 0 31 3 8 1 0 0 0 305 0 0 0 100 7 0 0 17 332 156 110 1 0 1 0 524 0 0 0 100 March 2, 2026 at 06:59:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2109 101 116 0 1 2 0 0 0 1 0 99 1 0 0 7 27 10 52 1 0 2 0 1306 0 0 0 99 2 0 0 0 12 1 6 1 0 1 0 294 0 0 0 100 3 0 0 0 12 1 8 0 1 2 0 0 0 0 0 100 4 0 0 0 16 1 12 0 1 0 0 0 0 0 0 100 5 0 0 3 211 102 4 0 0 0 0 0 0 0 0 100 6 0 0 0 17 3 14 0 0 3 0 3 0 0 0 100 7 0 0 17 314 154 108 1 1 1 0 906 0 0 0 100 March 2, 2026 at 06:59:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 0 2883 103 1467 41 237 22 0 5832 6 3 0 91 1 23 0 7 811 7 1456 49 265 14 0 7905 7 3 0 91 2 1 0 0 758 25 1284 31 212 31 0 6750 6 2 0 92 3 2 0 0 675 2 1294 38 255 31 0 7405 6 2 0 92 4 45 0 0 636 2 1122 32 230 27 0 6235 6 2 0 92 5 2 0 3 791 107 963 20 181 23 1 4306 5 1 0 94 6 5 0 0 635 3 1129 31 221 34 0 6143 6 2 0 93 7 4 0 381 740 134 967 15 144 49 0 5685 6 2 0 92 March 2, 2026 at 06:59:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2112 102 118 0 0 0 0 12 0 1 0 99 1 0 0 7 13 3 40 1 0 2 0 1301 0 0 0 100 2 0 0 0 108 51 104 0 0 1 0 297 0 0 0 100 3 0 0 0 13 2 8 0 1 0 0 24 0 0 0 100 4 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 5 0 0 3 233 115 18 0 0 0 0 10 0 0 0 100 6 2 0 0 24 5 20 0 0 1 0 19 0 0 0 100 7 0 0 17 219 107 16 0 1 1 0 831 0 0 0 100 March 2, 2026 at 06:59:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 112 0 0 0 0 10 0 1 0 99 1 0 0 7 14 3 38 0 0 0 0 1296 0 0 0 100 2 0 0 0 108 51 104 0 0 7 0 295 0 0 0 100 3 0 0 0 9 1 4 0 0 2 0 0 0 0 0 100 4 0 0 0 12 1 12 0 2 1 0 0 0 0 0 100 5 0 0 3 222 108 14 0 0 0 0 6 0 0 0 100 6 0 0 0 13 3 8 0 0 0 0 2 0 0 0 100 7 0 0 17 222 110 18 0 0 7 0 878 0 0 0 100 March 2, 2026 at 06:59:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 112 0 0 1 0 10 0 1 0 99 1 0 0 7 14 4 36 1 0 2 0 1296 0 0 0 100 2 0 0 0 113 52 104 1 0 1 0 294 0 0 0 100 3 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 4 0 0 0 15 2 6 0 0 1 0 0 0 0 0 100 5 0 0 7 224 106 22 0 1 1 0 5 0 0 0 100 6 0 0 0 17 5 8 0 0 1 0 4 0 0 0 100 7 0 0 21 216 105 10 2 1 3 0 895 0 0 0 100 March 2, 2026 at 06:59:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2633 0 113 2208 101 317 2 34 269 14 410 1 2 0 97 1 140 0 7 142 4 272 1 54 235 17 1529 0 1 0 99 2 33 0 2 249 53 360 1 43 272 9 502 0 1 0 99 3 15 0 0 225 101 206 0 42 209 2 143 0 1 0 99 4 645 0 0 126 1 222 1 51 267 4 908 1 1 0 98 5 17 0 3 420 106 410 0 49 233 2 384 0 1 0 99 6 0 0 0 116 1 202 0 37 270 0 35 0 1 0 99 7 3 0 17 318 107 197 0 23 242 1 982 0 1 0 99 March 2, 2026 at 06:59:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 92 0 2 0 0 10 0 1 0 99 1 0 0 7 19 3 44 1 0 0 0 1379 0 0 0 100 2 0 0 0 120 57 116 0 0 5 0 304 0 0 0 100 3 0 0 0 26 1 18 1 0 0 0 3 0 0 0 100 4 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 212 102 6 0 0 0 0 0 0 0 0 100 6 0 0 0 16 2 16 0 1 0 0 2 0 0 0 100 7 0 0 17 214 105 8 2 0 9 0 813 0 0 0 100 March 2, 2026 at 06:59:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 159 0 0 2272 107 437 18 40 2 0 2171 3 1 0 96 1 80 0 7 143 3 296 12 44 3 0 2891 2 1 0 97 2 257 0 0 99 20 131 6 23 9 0 1798 2 1 0 97 3 346 0 0 187 35 300 16 37 8 0 1649 2 1 0 98 4 2 0 0 94 2 162 10 35 5 0 1617 1 0 0 98 5 201 0 3 331 110 269 6 35 5 0 1715 1 0 0 98 6 59 0 0 83 4 158 11 24 4 0 883 3 0 0 97 7 22 0 115 277 105 288 1 31 9 0 2297 1 0 0 99 March 2, 2026 at 06:59:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 104 0 0 0 0 0 0 1 0 99 1 0 0 7 21 4 44 1 0 0 0 1389 0 0 0 100 2 0 0 0 10 1 2 1 0 3 0 294 0 0 0 100 3 0 0 0 109 51 104 0 1 0 0 0 0 0 0 100 4 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 5 0 0 3 210 102 4 0 0 0 0 0 0 0 0 100 6 0 0 0 23 8 18 0 1 0 0 11 0 0 0 100 7 0 0 17 213 105 8 1 0 1 0 945 0 0 0 100 March 2, 2026 at 06:59:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2120 102 121 0 6 2 0 17 0 1 0 99 1 0 0 7 27 3 55 1 7 11 0 1398 0 0 0 100 2 0 0 0 15 1 8 0 2 7 0 300 0 0 0 100 3 0 0 7 134 55 137 0 5 11 0 31 0 0 0 100 4 0 0 0 18 1 13 0 5 3 0 31 0 0 0 100 5 0 0 3 225 104 19 0 2 2 0 75 0 0 0 100 6 0 0 8 32 6 33 1 2 11 1 95 0 1 0 99 7 1 0 17 228 105 35 1 6 13 0 810 0 0 0 100 March 2, 2026 at 06:59:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2175 101 231 0 26 156 0 0 0 1 0 99 1 0 0 7 73 5 166 0 34 151 0 1301 0 1 0 99 2 0 0 0 70 1 133 0 23 116 0 294 0 0 0 100 3 0 0 0 212 105 196 1 30 160 0 9 0 1 0 99 4 0 0 7 145 33 223 0 36 181 0 1 0 0 0 100 5 0 0 3 341 102 269 0 23 127 0 0 0 1 0 99 6 0 0 0 77 2 145 0 27 177 0 2 0 0 0 100 7 0 0 17 266 105 110 0 20 109 0 908 0 0 0 100 March 2, 2026 at 06:59:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 112 2110 102 113 0 1 0 0 12 0 1 0 99 1 0 0 7 31 4 38 1 0 0 0 1298 0 0 0 100 2 0 0 0 24 1 2 0 0 1 0 294 0 0 0 100 3 0 0 0 42 6 20 0 0 0 0 6 0 0 0 100 4 0 0 0 133 54 110 0 0 0 0 3 0 0 0 100 5 0 0 10 227 102 6 0 1 0 0 0 0 0 0 100 6 0 0 0 26 1 4 0 0 0 0 0 0 0 0 100 7 0 0 17 232 106 10 1 0 1 0 875 0 0 0 100 March 2, 2026 at 06:59:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2111 102 92 0 2 0 0 1 0 1 0 99 1 0 0 7 55 7 84 1 3 1 0 1318 0 0 0 99 2 0 0 0 15 1 16 1 1 2 0 297 0 0 0 100 3 0 0 0 45 12 42 0 0 0 0 50 0 0 0 100 4 0 0 0 113 53 106 0 0 0 0 3 0 0 0 100 5 0 0 3 223 111 6 0 0 0 0 0 0 0 0 100 6 0 0 0 16 3 12 0 0 0 0 8 0 0 0 100 7 0 0 17 220 106 16 1 1 2 0 879 0 0 0 100 March 2, 2026 at 06:59:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2874 103 1484 44 241 17 0 6608 6 3 0 91 1 41 0 7 737 6 1390 48 279 31 0 8445 7 2 0 90 2 21 0 0 627 3 1009 21 187 59 0 5835 5 2 0 93 3 6 0 0 718 5 1298 43 252 32 0 7862 6 2 0 92 4 1 0 0 706 34 1199 23 223 16 0 5290 6 2 0 92 5 1 0 3 774 106 917 18 167 27 0 4384 5 1 0 93 6 5 0 0 590 4 1121 20 232 46 0 7028 6 2 0 92 7 18 0 353 697 124 918 17 148 28 0 4923 4 2 0 94 March 2, 2026 at 06:59:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 104 0 0 1 0 0 0 1 0 99 1 0 0 7 16 5 38 1 0 1 0 1298 0 0 0 100 2 0 0 0 14 3 6 0 1 4 0 294 0 0 0 100 3 0 0 0 21 3 10 0 1 1 0 0 0 0 0 100 4 0 0 0 17 3 8 0 0 1 0 10 0 0 0 100 5 0 0 7 210 102 2 0 1 0 0 0 0 0 0 100 6 0 0 0 25 9 16 0 0 1 0 9 0 0 0 100 7 0 0 21 312 154 106 1 0 7 0 885 0 0 0 100 March 2, 2026 at 06:59:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 48 0 0 2203 102 262 0 33 222 6 110 0 1 0 99 1 730 0 119 107 4 264 3 48 217 9 1579 0 1 0 98 2 111 0 0 121 2 225 1 38 256 17 398 0 1 0 99 3 20 0 2 216 81 245 0 50 240 7 151 0 1 0 99 4 8 0 0 118 1 214 0 46 251 4 99 0 1 0 99 5 5 0 3 383 101 338 1 41 213 1 26 0 1 0 99 6 646 0 0 131 8 204 3 41 233 7 910 1 1 0 98 7 1912 0 17 411 154 286 2 37 243 1 1138 0 1 0 98 March 2, 2026 at 06:59:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 104 0 1 0 0 0 0 1 0 99 1 0 0 7 15 5 42 1 1 1 0 1385 0 0 0 100 2 0 0 0 18 2 10 1 0 4 0 294 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 12 1 8 0 0 0 0 10 0 0 0 100 5 0 0 3 212 101 10 0 1 0 0 0 0 0 0 100 6 0 0 0 21 6 14 1 0 0 0 7 0 0 0 100 7 0 0 17 311 154 106 1 0 4 0 909 0 0 0 100 March 2, 2026 at 06:59:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 102 116 0 1 0 0 5 0 1 0 99 1 0 0 7 32 6 62 1 3 1 0 1400 0 0 0 99 2 0 0 0 13 3 8 0 1 1 0 295 0 0 0 100 3 0 0 0 13 1 12 1 0 0 0 12 0 0 0 100 4 0 0 0 10 1 6 0 0 0 0 10 0 0 0 100 5 0 0 3 212 106 0 0 0 0 0 0 0 0 0 100 6 0 0 0 31 10 28 0 0 0 0 334 0 0 0 100 7 0 0 17 314 154 108 1 0 2 0 866 0 0 0 100 March 2, 2026 at 06:59:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 106 110 0 2 0 0 5 0 1 0 99 1 0 0 7 21 4 46 1 0 0 0 1382 0 0 0 100 2 0 0 0 11 3 6 0 0 4 0 294 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 5 0 0 3 219 101 14 0 2 0 0 0 0 0 0 100 6 0 0 0 16 3 10 0 2 0 0 13 0 0 0 100 7 0 0 17 311 154 106 1 0 5 0 844 0 0 0 100 March 2, 2026 at 06:59:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 116 0 0 2209 106 306 6 27 4 0 1656 2 1 0 97 1 49 0 9 55 3 106 3 11 2 0 2176 2 1 0 97 2 156 0 0 93 5 207 11 28 6 0 1667 2 0 0 98 3 336 0 14 93 2 208 15 34 7 0 1843 3 1 0 96 4 48 0 0 129 3 241 10 34 4 0 1594 1 0 0 98 5 0 0 11 331 125 195 12 37 4 0 1428 1 0 0 99 6 50 0 0 100 2 261 3 36 4 0 1678 1 0 0 99 7 5 0 100 311 134 244 3 30 1 0 2205 1 0 0 99 March 2, 2026 at 06:59:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 0 2178 101 246 0 30 170 0 10 0 1 0 99 1 0 0 0 81 2 153 3 32 125 0 1145 0 1 0 99 2 0 0 0 66 4 112 1 25 164 0 310 0 0 0 99 3 0 0 0 180 90 169 0 27 132 0 2 0 0 0 100 4 0 0 0 86 2 160 0 26 147 0 11 0 0 0 99 5 0 0 10 474 153 439 0 22 145 0 267 0 0 0 99 6 0 0 0 103 2 200 0 41 179 0 3 0 0 0 100 7 0 0 31 300 111 166 1 23 122 0 961 0 1 0 99 March 2, 2026 at 06:59:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2194 0 9 2257 106 339 27 45 131 13 1444 5 2 0 93 1 1550 0 0 205 3 400 71 56 88 14 2870 5 2 0 94 2 1523 0 0 193 3 349 75 50 57 16 1318 7 1 0 92 3 659 0 0 163 1 254 22 53 50 11 1246 4 1 0 96 4 1509 0 7 150 2 259 28 46 96 13 976 4 2 0 94 5 2328 0 36 428 152 337 45 35 125 14 1833 5 2 0 93 6 6907 0 17 133 3 223 19 38 141 16 2013 5 2 0 93 7 2114 0 142 371 112 303 48 38 88 22 1805 5 1 0 94 March 2, 2026 at 06:59:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 0 2179 104 202 5 14 3 0 483 2 1 0 97 1 15 0 2 101 2 159 4 20 1 0 1646 5 1 0 95 2 5 0 0 59 5 45 3 10 8 0 226 6 0 0 94 3 39 0 0 98 14 106 6 17 6 0 1088 6 0 0 94 4 63 0 0 86 3 110 3 17 1 0 699 3 0 0 97 5 0 0 10 363 147 185 1 15 0 0 940 1 0 0 98 6 20 0 7 71 2 86 8 14 7 0 339 4 0 0 95 7 8 0 115 255 105 81 4 13 7 0 945 2 0 0 97 March 2, 2026 at 06:59:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 108 0 0 1 0 295 0 1 0 99 1 4 0 0 22 2 44 2 0 1 0 1138 0 0 0 100 2 0 0 0 12 2 10 0 1 0 0 18 0 0 0 100 3 0 0 0 24 8 16 0 0 0 0 309 0 0 0 100 4 0 0 0 10 1 4 0 1 0 0 0 0 0 0 100 5 0 0 17 312 153 107 0 0 0 0 262 0 0 0 100 6 0 0 0 13 1 6 0 1 0 0 0 0 0 0 100 7 0 0 17 210 103 6 0 1 3 0 536 0 0 0 100 March 2, 2026 at 06:59:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 112 1 2 0 0 294 0 1 0 99 1 0 0 0 13 2 34 1 0 2 0 1128 0 0 0 100 2 0 0 0 26 3 22 0 3 1 0 0 0 0 0 100 3 0 0 0 28 9 18 1 1 1 0 309 0 0 0 100 4 0 0 0 14 2 4 0 0 1 0 0 0 0 0 100 5 0 0 17 312 153 106 0 0 1 0 260 0 0 0 100 6 0 0 0 17 5 8 0 0 1 0 4 0 0 0 100 7 0 0 17 209 103 4 0 0 2 0 567 0 0 0 100 March 2, 2026 at 06:59:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 110 0 0 3 0 294 0 1 0 99 1 0 0 0 9 1 34 1 0 0 0 1127 0 0 0 100 2 0 0 0 60 22 56 0 1 0 0 0 0 0 0 100 3 0 0 0 31 10 32 0 1 1 0 310 0 0 0 100 4 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 5 0 0 10 268 132 60 0 0 0 0 260 0 0 0 100 6 0 0 0 12 2 8 0 0 0 0 0 0 0 0 100 7 0 0 17 211 103 10 0 1 1 0 516 0 0 0 100 March 2, 2026 at 06:59:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 63 0 42 2149 102 193 1 28 166 10 488 0 1 0 99 1 30 0 3 78 3 146 3 21 24 15 1005 0 0 0 99 2 28 0 5 159 51 214 2 22 33 9 84 0 0 0 100 3 609 0 9 78 9 122 6 21 26 16 583 1 1 0 97 4 28 0 10 47 1 94 4 22 16 6 168 0 0 0 100 5 7 0 13 239 102 48 1 16 2041 3 83 0 1 0 99 6 1104 0 9 51 3 95 1 25 3107 12 558 0 1 0 99 7 25 0 27 239 104 61 2 19 3127 9 687 0 1 0 99 March 2, 2026 at 06:59:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 42 2120 102 136 0 3 11 6 304 0 1 0 99 1 143 0 8 29 1 59 1 4 15 4 797 0 1 0 99 2 285 0 0 130 51 121 2 2 13 3 92 0 0 0 100 3 9 0 0 41 6 29 0 5 6 2 312 0 0 0 100 4 5 0 5 30 1 37 1 7 2 5 45 0 0 0 100 5 3 0 3 230 108 15 0 2 2 0 8 0 0 0 100 6 11 0 14 33 4 29 1 3 2 1 290 0 0 0 100 7 29 0 17 226 103 18 0 2 7 3 550 0 0 0 100 March 2, 2026 at 06:59:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 42 2161 102 111 1 1 6 0 294 0 2 0 98 1 0 0 343 23 1 44 1 0 2 0 753 0 1 0 99 2 0 0 7 171 51 112 0 1 0 0 0 0 0 0 100 3 0 0 0 68 3 6 1 0 0 0 300 0 0 0 100 4 0 0 0 68 2 6 0 0 0 0 0 0 0 0 100 5 0 0 4 265 101 4 0 1 2 0 0 0 0 0 100 6 0 0 7 70 3 8 0 1 0 0 261 0 0 0 100 7 0 0 17 264 103 4 0 0 5 0 584 0 0 0 100 March 2, 2026 at 06:59:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 102 108 0 0 0 0 294 0 1 0 99 1 0 0 0 7 1 32 0 0 1 0 751 0 0 0 100 2 0 0 0 117 51 112 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 8 0 1 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 209 102 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 1 0 559 0 0 0 100 March 2, 2026 at 06:59:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 102 112 0 0 8 0 294 0 1 0 99 1 0 0 0 11 1 36 1 1 1 0 752 0 0 0 100 2 0 0 0 115 51 110 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 8 0 0 1 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 209 101 2 0 0 0 0 0 0 0 0 100 6 0 0 7 20 4 22 0 1 2 0 261 0 0 0 100 7 0 0 17 211 103 10 0 0 6 0 622 0 0 0 100 March 2, 2026 at 06:59:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 118 0 1 7 0 298 0 1 0 99 1 3 0 0 21 3 56 0 1 16 0 836 0 1 0 99 2 848 0 2 156 66 158 0 5 49 0 733 0 1 0 99 3 502 0 1 17 3 16 0 2 21 0 476 0 0 0 100 4 322 0 1 26 5 184 0 2 6 0 448 0 0 0 99 5 0 0 2 221 110 12 0 2 0 0 9 0 0 0 100 6 0 0 7 12 2 8 0 0 0 0 259 0 0 0 100 7 0 0 18 213 103 12 1 1 3 0 520 0 0 0 100 March 2, 2026 at 06:59:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 114 1 0 1 0 295 0 1 0 99 1 0 0 0 12 1 40 1 0 0 0 753 0 0 0 100 2 0 0 0 155 71 150 0 0 0 0 20 0 0 0 100 3 0 0 0 13 3 8 1 0 0 0 300 0 0 0 100 4 0 0 0 15 4 12 0 0 0 0 7 0 0 0 100 5 0 0 2 214 107 0 0 0 0 0 0 0 0 0 100 6 0 0 7 14 3 12 0 1 0 0 269 0 0 0 100 7 0 0 18 213 104 10 0 0 3 0 569 0 0 0 100 March 2, 2026 at 06:59:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2116 103 120 0 1 0 0 295 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 155 71 150 0 0 0 0 20 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 11 2 4 0 0 0 0 0 0 0 0 100 5 0 0 2 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 18 210 103 6 0 1 6 0 519 0 0 0 100 March 2, 2026 at 06:59:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 102 112 0 1 8 0 294 0 1 0 99 1 0 0 0 15 2 42 0 1 0 0 745 0 0 0 100 2 0 0 0 160 72 150 0 1 1 0 20 0 0 0 100 3 0 0 0 14 4 6 0 0 1 0 300 0 0 0 100 4 0 0 0 14 3 6 0 1 1 0 0 0 0 0 100 5 0 0 7 208 101 0 0 0 1 0 0 0 0 0 100 6 0 0 7 16 5 8 0 0 1 0 262 0 0 0 100 7 0 0 21 209 103 6 0 1 8 0 610 0 0 0 100 March 2, 2026 at 06:59:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2146 102 178 0 12 80 0 294 0 1 0 99 1 0 0 0 44 1 103 1 12 92 0 743 0 0 0 99 2 0 0 0 188 68 223 0 13 51 0 17 0 0 0 100 3 0 0 0 120 62 100 0 17 128 0 303 0 0 0 100 4 0 0 0 51 2 92 0 12 81 0 0 0 1 0 99 5 0 0 3 292 101 171 0 13 84 0 0 0 0 0 100 6 0 0 7 48 3 79 0 15 47 0 259 0 0 0 100 7 0 0 17 247 103 79 1 8 91 0 519 0 0 0 100 March 2, 2026 at 06:59:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 112 1 1 1 0 294 0 1 0 99 1 0 0 0 16 2 42 1 0 0 0 751 0 0 0 100 2 0 0 0 118 51 116 0 1 0 0 0 0 0 0 100 3 0 0 0 53 23 48 1 0 0 0 321 0 0 0 100 4 0 0 0 12 2 6 0 0 0 0 4 0 0 0 100 5 0 0 3 212 104 2 0 0 0 0 0 0 0 0 100 6 0 0 7 13 3 10 0 0 0 0 263 0 0 0 100 7 0 0 17 209 103 4 1 0 5 0 618 0 0 0 100 March 2, 2026 at 06:59:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 116 0 0 2 0 294 0 1 0 99 1 0 0 0 14 3 40 1 0 0 0 750 0 0 0 100 2 0 0 0 109 51 104 0 0 0 0 0 0 0 0 100 3 0 0 0 57 23 58 0 1 0 0 320 0 0 0 100 4 0 0 0 13 2 12 0 0 0 0 10 0 0 0 100 5 0 0 3 212 106 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 2 10 0 0 0 0 267 0 0 0 100 7 0 0 17 211 103 8 0 0 1 0 571 0 0 0 100 March 2, 2026 at 06:59:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 114 0 0 0 0 294 0 1 0 99 1 0 0 0 9 1 32 0 0 0 0 744 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 51 23 46 0 0 0 0 320 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 1 0 0 261 0 0 0 100 7 0 0 17 208 103 4 0 0 1 0 555 0 0 0 100 March 2, 2026 at 06:59:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 102 114 0 0 0 0 294 0 1 0 99 1 0 0 0 9 1 32 2 0 0 0 745 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 53 23 48 0 0 0 0 320 0 0 0 100 4 0 0 0 14 2 14 0 1 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 258 0 0 0 100 7 0 0 17 208 103 4 0 0 0 0 528 0 0 0 100 March 2, 2026 at 06:59:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 118 1 0 3 0 294 0 1 0 99 1 0 0 0 9 1 34 1 0 2 0 743 0 0 0 100 2 0 0 0 108 51 104 0 0 0 0 0 0 0 0 100 3 0 0 0 52 23 46 1 0 0 0 320 0 0 0 100 4 0 0 0 13 3 8 0 0 0 0 1 0 0 0 100 5 0 0 3 212 101 10 0 1 0 0 0 0 0 0 100 6 0 0 7 13 3 10 0 1 1 0 261 0 0 0 100 7 0 0 17 211 103 10 0 0 4 0 611 0 0 0 100 March 2, 2026 at 06:59:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 103 118 0 1 1 0 306 0 1 0 99 1 0 0 0 7 1 32 0 0 1 0 744 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 51 23 46 0 0 0 0 320 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 2 0 17 210 104 6 0 0 0 0 577 0 0 0 100 March 2, 2026 at 06:59:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 120 0 1 0 0 295 0 1 0 99 1 0 0 0 10 1 36 1 0 1 0 750 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 54 24 50 0 0 0 0 341 0 0 0 100 4 0 0 0 17 4 16 0 0 0 0 13 0 0 0 100 5 0 0 3 214 106 2 0 0 1 0 0 0 0 0 100 6 0 0 7 19 3 22 0 1 1 0 268 0 0 0 100 7 0 0 17 213 104 8 0 0 3 0 532 0 0 0 100 March 2, 2026 at 06:59:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 103 118 0 0 12 0 295 0 1 0 99 1 0 0 0 9 1 32 0 0 0 0 744 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 51 23 46 0 0 0 0 320 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 2 8 0 0 0 0 259 0 0 0 100 7 0 0 17 213 103 14 0 1 12 0 546 0 0 0 100 March 2, 2026 at 06:59:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 118 1 1 0 0 294 0 1 0 99 1 0 0 0 12 2 34 1 0 2 0 743 0 0 0 100 2 0 0 0 109 52 102 0 0 1 0 0 0 0 0 100 3 0 0 0 54 24 46 1 0 1 0 320 0 0 0 100 4 0 0 0 13 3 6 0 0 1 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 1 0 0 0 0 0 100 6 0 0 7 15 5 8 0 0 1 0 262 0 0 0 100 7 0 0 17 208 103 4 0 0 5 0 570 0 0 0 100 March 2, 2026 at 06:59:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 128 0 1 1 0 294 0 1 0 99 1 0 0 0 8 1 34 0 0 0 0 744 0 0 0 100 2 0 0 0 108 51 104 0 0 3 0 0 0 0 0 100 3 0 0 0 51 23 46 0 0 0 0 320 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 209 103 0 0 0 0 0 0 0 0 0 100 6 0 0 7 11 2 8 0 0 3 0 259 0 0 0 100 7 0 0 17 213 103 12 0 0 1 0 563 0 0 0 100 March 2, 2026 at 06:59:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 116 0 0 2 0 294 0 1 0 99 1 0 0 0 13 1 46 1 1 1 0 744 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 51 23 46 0 0 0 0 320 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 210 103 4 2 0 3 0 564 0 0 0 100 March 2, 2026 at 06:59:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 118 0 0 1 0 294 0 1 0 99 1 0 0 0 10 1 36 1 0 2 0 749 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 52 23 48 0 0 0 0 320 0 0 0 100 4 0 0 0 18 4 18 0 0 0 0 15 0 0 0 100 5 0 0 3 214 108 0 0 0 1 0 0 0 0 0 100 6 0 0 7 12 2 10 0 0 0 0 266 0 0 0 100 7 0 0 17 212 103 10 0 1 2 0 564 0 0 0 100 March 2, 2026 at 06:59:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 114 1 0 4 0 294 0 1 0 99 1 0 0 0 26 8 50 0 1 0 0 751 0 0 0 100 2 0 0 0 112 51 112 0 1 0 0 0 0 0 0 100 3 0 0 0 38 16 30 1 0 0 0 312 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 1 0 0 261 0 0 0 100 7 0 0 17 208 103 4 0 0 1 0 564 0 0 0 100 March 2, 2026 at 06:59:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 102 116 0 0 2 0 293 0 1 0 99 1 0 0 0 48 21 72 1 0 0 0 766 0 0 0 100 2 0 0 0 109 51 104 0 1 0 0 0 0 0 0 100 3 0 0 0 16 3 16 0 1 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 4 0 572 0 0 0 100 March 2, 2026 at 07:00:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 118 0 0 0 0 294 0 1 0 99 1 0 0 0 47 21 72 1 0 0 0 764 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 7 0 0 17 211 103 8 1 0 3 0 562 0 0 0 100 March 2, 2026 at 07:00:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 116 0 0 3 0 295 0 1 0 99 1 0 0 0 48 21 72 1 0 1 0 763 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 300 0 0 0 100 4 0 0 0 16 3 16 0 1 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 209 103 4 1 0 5 0 568 0 0 0 100 March 2, 2026 at 07:00:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 118 1 0 6 0 295 0 1 0 99 1 0 0 0 51 21 78 0 0 1 0 769 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 1 0 0 0 300 0 0 0 100 4 0 0 0 19 4 18 0 0 1 0 13 0 0 0 100 5 0 0 3 217 106 10 0 1 0 0 0 0 0 0 100 6 0 0 7 14 3 12 0 0 0 0 268 0 0 0 100 7 0 0 17 213 104 10 0 0 3 0 597 0 0 0 100 March 2, 2026 at 07:00:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 103 116 0 0 3 0 295 0 1 0 99 1 0 0 0 54 22 78 1 0 0 0 772 0 0 0 100 2 0 0 0 109 51 106 0 0 0 0 18 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 2 0 549 0 0 0 100 March 2, 2026 at 07:00:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 116 0 0 3 0 294 0 1 0 99 1 0 0 0 51 22 72 2 0 1 0 766 0 0 0 100 2 0 0 0 109 52 104 0 1 0 0 0 0 0 0 100 3 0 0 0 13 4 6 0 0 1 0 300 0 0 0 100 4 0 0 0 13 3 6 0 0 1 0 0 0 0 0 100 5 0 0 3 209 101 2 0 0 3 0 0 0 0 0 100 6 0 0 7 19 5 20 0 1 2 0 262 0 0 0 100 7 0 0 17 209 103 4 1 0 5 0 602 0 0 0 100 March 2, 2026 at 07:00:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 120 0 0 4 0 294 0 1 0 99 1 0 0 0 47 21 72 0 0 0 0 763 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 2 8 0 0 0 0 259 0 0 0 100 7 0 0 17 215 103 18 0 1 4 0 506 0 0 0 100 March 2, 2026 at 07:00:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 116 1 1 0 0 305 0 1 0 99 1 0 0 0 48 21 72 1 0 0 0 765 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 12 3 6 1 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 211 104 8 1 0 2 0 643 0 0 0 100 March 2, 2026 at 07:00:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 102 126 0 1 1 0 294 0 1 0 99 1 0 0 0 50 21 76 1 0 1 0 769 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 14 4 10 0 0 0 0 323 0 0 0 100 4 0 0 0 19 5 18 0 0 0 0 14 0 0 0 100 5 0 0 3 213 107 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 2 10 0 0 0 0 266 0 0 0 100 7 0 0 17 213 103 10 0 0 0 0 553 0 0 0 100 March 2, 2026 at 07:00:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 116 0 0 0 0 294 0 1 0 99 1 0 0 0 55 21 82 1 1 0 0 763 0 0 0 100 2 0 0 0 108 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 1 0 0 261 0 0 0 100 7 0 0 17 208 103 4 0 0 3 0 548 0 0 0 100 March 2, 2026 at 07:00:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 102 114 0 0 7 0 294 0 1 0 99 1 0 0 0 49 21 74 0 0 0 0 765 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 0 0 582 0 0 0 100 March 2, 2026 at 07:00:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 118 1 0 0 0 294 0 1 0 99 1 0 0 0 50 21 74 1 0 0 0 763 0 0 0 100 2 0 0 0 112 51 112 0 1 0 0 0 0 0 0 100 3 0 0 0 12 3 6 1 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 210 103 8 0 0 2 0 575 0 0 0 100 March 2, 2026 at 07:00:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 118 0 1 5 0 295 0 1 0 99 1 0 0 0 48 21 72 1 0 0 0 764 0 0 0 100 2 0 0 0 109 51 104 0 0 0 0 0 0 0 0 100 3 0 0 0 16 3 16 0 1 1 0 300 0 0 0 100 4 0 0 0 13 4 8 0 0 0 0 2 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 4 0 0 0 0 259 0 0 0 100 7 0 0 17 209 103 4 1 0 0 0 514 0 0 0 100 March 2, 2026 at 07:00:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 103 122 0 1 4 0 295 0 1 0 99 1 0 0 0 50 21 76 1 0 0 0 768 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 14 4 10 0 0 0 0 321 0 0 0 100 4 0 0 0 17 4 16 0 0 0 0 13 0 0 0 100 5 0 0 3 212 106 0 0 0 0 0 0 0 0 0 100 6 0 0 7 14 3 12 0 0 0 0 268 0 0 0 100 7 0 0 17 213 104 8 0 0 2 0 565 0 0 0 100 March 2, 2026 at 07:00:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 116 0 0 0 0 295 0 1 0 99 1 0 0 0 49 21 74 0 0 0 0 766 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 0 0 1 0 300 0 0 0 100 4 0 0 0 14 2 16 0 1 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 3 0 568 0 0 0 100 March 2, 2026 at 07:00:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 102 116 1 0 1 0 294 0 1 0 99 1 0 0 0 50 22 72 1 0 2 0 764 0 0 0 100 2 0 0 0 109 52 104 0 1 0 0 0 0 0 0 100 3 0 0 0 14 4 6 1 0 1 0 300 0 0 0 100 4 0 0 0 15 3 8 0 0 1 0 0 0 0 0 100 5 0 0 3 212 101 10 0 1 1 0 0 0 0 0 100 6 0 0 7 15 5 8 0 0 1 0 262 0 0 0 100 7 1 0 17 211 103 4 2 0 6 0 611 0 0 0 100 March 2, 2026 at 07:00:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 118 0 0 3 0 294 0 1 0 99 1 0 0 0 45 20 70 0 0 1 0 762 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 1 0 0 259 0 0 0 100 7 0 0 17 210 103 8 0 0 1 0 559 0 0 0 100 March 2, 2026 at 07:00:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 114 0 0 1 0 294 0 1 0 99 1 0 0 0 38 16 60 1 0 1 0 758 0 0 0 100 2 0 0 0 118 56 114 0 1 0 0 6 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 209 101 2 0 0 1 0 0 0 0 0 100 6 0 0 7 17 3 20 0 1 0 0 261 0 0 0 100 7 0 0 17 208 103 4 0 0 4 0 571 0 0 0 100 March 2, 2026 at 07:00:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 118 0 1 2 0 294 0 1 0 99 1 0 0 0 9 1 36 1 0 0 0 750 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 12 3 8 0 0 0 0 300 0 0 0 100 4 0 0 0 17 4 16 0 0 0 0 13 0 0 0 100 5 0 0 3 213 107 0 0 0 0 0 0 0 0 0 100 6 0 0 7 14 2 12 0 0 0 0 266 0 0 0 100 7 0 0 17 216 103 16 0 1 1 0 598 0 0 0 100 March 2, 2026 at 07:00:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 116 1 0 12 0 294 0 1 0 99 1 0 0 0 10 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 148 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 12 3 6 1 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 1 0 0 261 0 0 0 100 7 0 0 17 208 103 4 0 0 12 0 576 0 0 0 100 March 2, 2026 at 07:00:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 102 124 0 1 2 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 1 0 743 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 211 103 8 1 1 6 0 571 0 0 0 100 March 2, 2026 at 07:00:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 120 0 0 6 0 294 0 1 0 99 1 0 0 0 14 1 44 1 1 3 0 745 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 210 103 8 0 0 2 0 517 0 0 0 100 March 2, 2026 at 07:00:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 103 118 0 1 1 0 306 0 1 0 99 1 0 0 0 7 1 32 0 0 0 0 743 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 210 104 6 0 0 3 0 606 0 0 0 100 March 2, 2026 at 07:00:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 118 1 0 1 0 295 0 1 0 99 1 0 0 0 12 1 38 1 0 1 0 749 0 0 0 100 2 0 0 0 152 71 152 0 1 0 0 20 0 0 0 100 3 0 0 0 13 3 8 1 0 0 0 300 0 0 0 100 4 0 0 0 17 4 16 0 0 1 0 13 0 0 0 100 5 0 0 3 213 107 0 0 0 0 0 0 0 0 0 100 6 0 0 7 14 3 12 0 0 0 0 268 0 0 0 100 7 0 0 17 213 104 10 0 1 2 0 579 0 0 0 100 March 2, 2026 at 07:00:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 116 0 0 0 0 295 0 1 0 99 1 0 0 0 10 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 149 71 144 0 0 0 0 20 0 0 0 100 3 0 0 0 16 3 16 0 1 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 0 0 572 0 0 0 100 March 2, 2026 at 07:00:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2111 102 118 0 0 2 0 294 0 1 0 99 1 0 0 0 10 2 32 0 0 1 0 744 0 0 0 100 2 0 0 0 150 72 142 0 0 1 0 20 0 0 0 100 3 0 0 0 14 4 6 0 0 1 0 300 0 0 0 100 4 0 0 0 14 3 6 0 0 1 0 0 0 0 0 100 5 0 0 7 208 101 2 0 1 0 0 0 0 0 0 100 6 0 0 7 16 5 8 0 0 1 0 262 0 0 0 100 7 0 0 21 209 103 4 0 0 2 0 515 0 0 0 100 March 2, 2026 at 07:00:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 103 118 0 0 8 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 13 3 8 0 0 1 0 300 0 0 0 100 4 0 0 0 16 2 18 0 1 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 211 103 8 1 0 0 0 563 0 0 0 100 March 2, 2026 at 07:00:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 114 1 0 3 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 12 3 6 1 0 0 0 300 0 0 0 100 4 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 5 0 0 3 212 101 10 0 1 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 209 103 4 1 0 8 0 617 0 0 0 100 March 2, 2026 at 07:00:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 102 118 0 1 3 0 294 0 1 0 99 1 0 0 0 10 1 36 1 0 0 0 750 0 0 0 100 2 0 0 0 147 71 142 0 0 0 0 20 0 0 0 100 3 0 0 0 12 3 8 0 0 0 0 300 0 0 0 100 4 0 0 0 21 6 18 0 0 0 0 17 0 0 0 100 5 0 0 3 215 107 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 2 10 0 0 0 0 264 0 0 0 100 7 0 0 17 211 103 6 0 0 1 0 531 0 0 0 100 March 2, 2026 at 07:00:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 114 0 0 0 0 294 0 1 0 99 1 0 0 0 11 1 34 0 0 0 0 743 0 0 0 100 2 0 0 0 131 63 126 0 0 0 0 20 0 0 0 100 3 0 0 0 26 10 22 0 1 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 209 101 2 0 0 1 0 0 0 0 0 100 6 0 0 7 17 3 18 0 2 1 0 261 0 0 0 100 7 0 0 17 208 103 4 0 0 1 0 577 0 0 0 100 March 2, 2026 at 07:00:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 102 118 0 1 0 0 294 0 1 0 99 1 0 0 0 11 2 34 2 0 1 0 744 0 0 0 100 2 0 0 0 51 23 46 0 0 1 0 20 0 0 0 100 3 0 0 0 113 54 108 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 1 1 0 0 0 0 0 100 5 0 0 3 210 102 4 0 1 1 0 0 0 0 0 100 6 0 0 7 14 3 10 0 0 0 0 259 0 0 0 100 7 0 0 17 215 104 16 0 1 5 0 528 0 0 0 100 March 2, 2026 at 07:00:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 118 1 0 2 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 745 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 114 53 108 1 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 211 103 8 1 0 1 0 570 0 0 0 100 March 2, 2026 at 07:00:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2113 103 130 0 1 2 0 295 0 1 0 99 1 0 0 0 8 1 32 1 0 1 0 743 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 13 4 8 0 0 0 0 2 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 211 103 8 1 0 1 0 644 0 0 0 100 March 2, 2026 at 07:00:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 103 120 0 0 2 0 295 0 1 0 99 1 0 0 0 15 1 46 2 1 1 0 749 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 114 54 110 0 0 0 0 321 0 0 0 100 4 0 0 0 18 4 18 0 0 1 0 15 0 0 0 100 5 0 0 3 214 106 0 0 0 0 0 0 0 0 0 100 6 0 0 7 14 3 12 0 0 0 0 268 0 0 0 100 7 0 0 17 213 104 10 0 1 3 0 497 0 0 0 100 March 2, 2026 at 07:00:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 103 116 0 0 1 0 295 0 1 0 99 1 0 0 0 14 2 38 1 0 1 0 753 0 0 0 100 2 0 0 0 49 21 46 0 0 0 0 38 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 208 103 4 0 0 5 0 566 0 0 0 100 March 2, 2026 at 07:00:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 116 1 0 6 0 294 0 1 0 99 1 0 0 0 13 2 36 0 0 2 0 744 0 0 0 100 2 0 0 0 55 22 54 0 1 1 0 20 0 0 0 100 3 0 0 0 114 54 108 1 1 0 0 300 0 0 0 100 4 0 0 0 13 3 6 0 0 1 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 1 0 0 0 0 0 100 6 0 0 7 15 5 8 0 0 1 0 262 0 0 0 100 7 0 0 17 208 103 4 0 0 3 0 596 0 0 0 100 March 2, 2026 at 07:00:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 103 118 0 0 6 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 49 21 44 0 0 0 0 20 0 0 0 100 3 0 0 0 116 53 116 0 1 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 210 103 8 0 0 2 0 533 0 0 0 100 March 2, 2026 at 07:00:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 114 0 0 4 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 261 0 0 0 100 7 0 0 17 211 104 8 1 0 0 0 602 0 0 0 100 March 2, 2026 at 07:00:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 122 0 2 2 0 294 0 1 0 99 1 0 0 0 9 1 36 0 0 0 0 749 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 117 53 112 0 0 0 0 300 0 0 0 100 4 0 0 0 21 4 24 0 1 0 0 12 0 0 0 100 5 0 0 3 212 106 0 0 0 0 0 0 0 0 0 100 6 0 0 7 12 2 10 0 0 0 0 264 0 0 0 100 7 0 0 17 211 103 8 0 0 0 0 521 0 0 0 100 March 2, 2026 at 07:00:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 114 0 0 10 0 294 0 1 0 99 1 0 0 0 10 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 113 53 106 1 0 0 0 300 0 0 0 100 4 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 5 0 0 3 212 101 10 0 1 1 0 0 0 0 0 100 6 0 0 7 12 3 8 0 1 0 0 260 0 0 0 100 7 0 0 17 208 103 4 0 0 7 0 583 0 0 0 100 March 2, 2026 at 07:00:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 102 114 1 0 3 0 294 0 1 0 99 1 0 0 0 10 1 34 1 0 0 0 744 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 209 103 6 1 0 4 0 562 0 0 0 100 March 2, 2026 at 07:00:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 118 0 0 2 0 294 0 1 0 99 1 0 0 0 7 1 32 0 0 0 0 744 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 209 101 2 0 0 1 0 0 0 0 0 100 6 0 0 7 17 3 20 0 1 0 0 261 0 0 0 100 7 0 0 17 210 103 8 0 0 1 0 610 0 0 0 100 March 2, 2026 at 07:00:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 103 116 0 0 5 0 295 0 1 0 99 1 0 0 0 12 3 36 1 0 0 0 748 0 0 0 100 2 0 0 0 49 21 46 0 0 0 0 22 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 3 209 102 2 0 0 0 0 2 0 0 0 100 6 0 0 7 12 2 8 0 0 0 0 259 0 0 0 100 7 0 0 17 213 103 14 0 1 2 0 566 0 0 0 100 March 2, 2026 at 07:00:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 120 0 1 4 0 295 0 1 0 99 1 0 0 0 10 1 36 1 0 0 0 749 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 113 53 108 1 0 0 0 300 0 0 0 100 4 0 0 0 16 4 14 0 0 0 0 12 0 0 0 100 5 0 0 3 212 106 0 0 0 0 0 0 0 0 0 100 6 0 0 7 14 3 12 0 0 0 0 266 0 0 0 100 7 0 0 17 213 104 8 0 0 1 0 569 0 0 0 100 March 2, 2026 at 07:00:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2116 103 128 1 1 3 0 295 0 1 0 99 1 0 0 0 9 1 32 0 0 0 0 744 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 111 53 106 0 0 0 0 300 0 0 0 100 4 0 0 0 13 4 8 0 0 0 0 2 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 211 103 6 1 1 2 0 558 0 0 0 100 March 2, 2026 at 07:00:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 118 0 0 7 0 294 0 1 0 99 1 0 0 0 15 2 42 1 1 2 0 745 0 0 0 100 2 0 0 0 49 22 42 0 0 1 0 20 0 0 0 100 3 0 0 0 113 54 108 0 1 0 0 300 0 0 0 100 4 0 0 0 15 4 8 0 0 1 0 1 0 0 0 100 5 0 0 3 207 101 0 0 0 1 0 0 0 0 0 100 6 0 0 7 15 5 8 0 0 1 0 262 0 0 0 100 7 0 0 17 208 103 4 0 0 4 0 579 0 0 0 100 March 2, 2026 at 07:00:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 103 118 0 0 3 0 294 0 1 0 99 1 0 0 0 8 1 32 1 0 0 0 744 0 0 0 100 2 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 3 0 0 0 113 53 108 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 7 10 2 6 0 0 0 0 259 0 0 0 100 7 0 0 17 211 103 8 1 0 3 0 513 0 0 0 100 March 2, 2026 at 07:00:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 102 118 0 0 5 0 294 0 1 0 99 1 29 0 0 21 1 56 0 2 1 0 856 1 0 0 99 2 1 0 0 31 8 38 1 3 1 0 95 0 0 0 100 3 18 0 0 122 53 120 1 0 0 0 345 0 0 0 100 4 1293 0 2 19 2 18 1 0 1 0 115 0 0 0 99 5 0 0 3 259 149 10 0 2 0 0 28 0 0 0 100 6 1 0 7 15 3 14 0 2 0 0 273 0 0 0 100 7 0 0 17 214 103 16 0 1 2 0 575 0 0 0 100 March 2, 2026 at 07:00:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 102 142 1 2 1 0 294 0 1 0 99 1 2 0 0 27 5 56 1 0 0 0 778 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 118 53 120 0 1 0 0 300 0 0 0 100 4 0 0 0 16 2 10 0 1 0 0 0 0 0 0 100 5 0 0 3 300 191 2 0 0 3 0 0 0 0 0 100 6 40 0 7 25 2 30 1 1 0 0 308 0 0 0 100 7 0 0 17 233 103 50 1 1 4 0 615 0 0 0 100