March 2, 2026 at 06:53:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 790 0 79 4387 151 6227 78 353 1392 51 7902 6 11 0 83 1 1173 0 58 1277 28 4098 28 449 1480 51 8958 17 8 0 75 2 1170 0 159 1022 23 3600 24 371 1453 50 8339 5 6 0 89 3 703 0 136 1462 519 3798 17 342 1470 79 10697 3 10 0 87 4 796 0 70 1294 21 3161 22 420 1495 75 5928 3 7 0 90 5 894 0 612 3280 2508 2639 23 323 1511 15 5659 5 8 0 87 6 919 0 34 1231 18 4420 24 471 1473 82 8573 12 7 0 82 7 1097 0 259 2107 26 5399 39 437 1364 44 4454 3 8 0 89 March 2, 2026 at 06:53:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3924 0 67 2620 157 957 17 191 656 48 1924 8 6 0 86 1 2949 0 18 594 4 1248 10 189 993 62 1422 3 5 0 91 2 4656 0 21 444 5 637 19 158 595 56 1957 9 20 0 71 3 6795 0 25 752 373 936 33 220 837 84 3662 12 12 0 76 4 6433 0 85 444 41 856 15 191 964 73 2034 9 8 0 83 5 6385 0 28 525 38 664 9 151 1071 44 2858 6 32 0 63 6 5718 0 51 405 2 964 10 211 930 88 2394 5 5 0 90 7 7887 0 29 340 0 763 17 202 756 63 2950 8 6 0 86 March 2, 2026 at 06:53:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2388 203 333 0 81 495 0 258 0 1 0 99 1 0 0 0 428 1 894 0 86 444 0 1 0 1 0 99 2 30 0 0 94 1 281 0 90 476 0 1057 0 1 0 99 3 0 0 0 428 333 246 0 87 556 0 294 0 1 0 98 4 0 0 17 348 123 303 2 100 532 0 131 0 1 0 99 5 0 0 0 161 32 300 0 87 479 0 0 0 1 0 99 6 0 0 0 94 1 240 0 91 422 0 435 0 1 0 99 7 40 0 0 96 1 238 0 87 394 0 310 0 1 0 99 March 2, 2026 at 06:53:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2400 204 311 0 89 670 0 261 0 4 0 96 1 0 0 0 468 1 959 0 101 700 0 0 0 1 0 99 2 27 0 0 149 28 333 0 98 721 0 1039 0 2 0 98 3 0 0 0 434 331 269 1 82 820 0 294 0 2 0 98 4 0 0 4 308 104 255 0 79 799 0 0 0 2 0 98 5 0 0 0 148 23 304 0 92 686 0 0 0 1 0 99 6 0 0 14 102 2 259 0 91 669 0 566 0 1 0 99 7 0 0 0 96 1 238 0 84 633 0 300 0 1 0 99 March 2, 2026 at 06:53:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2417 253 350 1 30 197 0 260 0 1 0 99 1 0 0 0 177 2 344 0 35 148 0 6 0 0 0 100 2 0 0 0 74 2 142 1 37 139 0 722 0 0 0 99 3 0 0 0 186 114 182 0 35 200 0 615 0 1 0 99 4 0 0 4 278 103 148 0 35 176 0 0 0 0 0 100 5 0 0 0 72 6 135 0 34 164 0 9 0 0 0 100 6 0 0 14 89 2 180 0 38 168 0 568 0 1 0 99 7 0 0 0 71 1 142 0 29 172 0 300 0 0 0 100 March 2, 2026 at 06:53:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2411 239 282 2 31 151 0 261 0 2 0 98 1 0 0 0 97 11 156 2 36 216 1 0 0 2 0 98 2 0 0 0 77 0 149 1 24 226 1 0 0 2 0 98 3 0 0 0 224 146 176 1 30 218 0 1331 0 2 0 98 4 0 0 4 325 109 213 0 45 217 0 0 0 1 0 99 5 0 0 0 206 0 423 0 35 152 0 0 0 0 0 100 6 0 0 14 80 3 161 1 35 258 0 565 0 2 0 98 7 0 0 0 67 1 130 1 30 207 0 300 0 2 0 98 March 2, 2026 at 06:53:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4190 0 23 2483 203 463 11 58 76 35 1861 3 3 0 94 1 1109 0 11 215 23 377 10 57 114 21 653 2 1 0 97 2 1511 0 9 168 2 331 5 62 104 34 858 1 1 0 98 3 3876 0 6 229 9 470 8 59 170 31 2674 2 6 0 92 4 995 0 44 380 106 356 1 57 114 25 674 1 1 0 98 5 1678 0 15 157 11 300 1 44 86 23 714 2 3 0 95 6 307 0 23 203 27 371 2 49 73 22 1487 1 1 0 99 7 334 0 3 140 2 282 1 32 83 15 1116 1 1 0 98 March 2, 2026 at 06:53:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 10 2320 207 122 0 4 0 0 329 0 1 0 99 1 5 0 5 21 4 14 0 2 0 0 11 0 0 0 100 2 0 0 0 15 1 8 0 0 4 0 9 0 0 0 100 3 0 0 0 17 3 40 1 2 0 0 1415 0 0 0 100 4 0 0 18 231 104 18 0 4 0 0 6 0 0 0 100 5 0 0 7 12 1 6 0 2 0 0 1 0 0 0 100 6 0 0 14 43 17 38 0 1 3 0 575 0 1 0 99 7 0 0 0 84 36 76 0 1 0 0 303 0 0 0 100 March 2, 2026 at 06:53:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2324 210 126 0 2 0 0 270 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 7 0 0 13 3 38 0 0 1 0 1410 0 0 0 100 4 0 0 4 220 103 16 0 1 0 0 0 0 0 0 100 5 0 0 0 10 1 5 0 2 0 0 0 0 0 0 100 6 0 0 14 9 2 8 0 1 0 0 567 0 0 0 100 7 0 0 0 107 51 102 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2323 209 128 0 0 0 0 271 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 1 14 3 42 1 0 0 0 1415 0 0 0 100 4 0 0 4 320 155 116 0 2 0 0 9 0 0 0 100 5 0 0 0 24 6 20 0 1 0 0 10 0 0 0 100 6 0 0 14 9 2 8 0 1 0 0 566 0 0 0 100 7 0 0 0 14 3 8 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 10 2369 209 187 2 15 56 1 296 0 1 0 99 1 25 0 7 67 2 112 0 23 53 1 48 0 1 0 99 2 9 0 0 49 1 79 0 20 41 8 65 0 0 0 100 3 287 0 16 133 68 148 2 19 78 3 1527 0 1 0 99 4 8 0 6 374 153 225 0 25 65 3 48 0 0 0 100 5 29 0 0 121 5 214 0 16 32 3 26 0 0 0 100 6 13 0 27 104 4 150 0 18 49 3 590 0 0 0 100 7 21 0 0 61 2 105 1 13 47 3 331 0 0 0 100 March 2, 2026 at 06:53:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2314 204 116 0 1 0 0 261 0 1 0 99 1 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 14 1 6 0 0 0 0 1 0 0 0 100 3 0 0 0 17 3 41 1 2 0 0 1356 0 0 0 100 4 0 0 4 313 153 104 0 0 0 0 0 0 0 0 100 5 0 0 0 10 0 4 0 0 0 0 0 0 0 0 100 6 0 0 14 19 3 20 0 1 0 0 566 0 0 0 100 7 0 0 7 8 1 4 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2312 203 117 0 2 0 0 259 0 1 0 99 1 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 14 3 39 1 0 0 0 1353 0 0 0 100 4 0 0 4 313 153 104 0 0 0 0 0 0 0 0 100 5 0 0 0 8 0 0 0 0 0 0 0 0 0 0 100 6 0 0 14 13 3 10 0 1 0 0 565 0 0 0 100 7 0 0 0 15 1 14 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2312 204 116 0 0 0 0 261 0 0 0 100 1 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 10 0 4 0 0 0 0 0 0 0 0 100 3 0 0 7 13 3 38 0 0 0 0 1351 0 0 0 100 4 0 0 4 315 154 108 0 0 0 0 1 0 0 0 100 5 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 6 0 0 14 11 3 8 0 0 0 0 567 0 0 0 100 7 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2312 203 126 0 1 1 0 259 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 15 3 42 1 0 1 0 1358 0 0 0 100 4 0 0 4 315 153 112 0 0 0 0 10 0 0 0 100 5 0 0 0 18 7 8 0 0 0 0 7 0 0 0 100 6 0 0 14 10 3 8 0 0 0 0 565 0 0 0 100 7 0 0 0 12 1 8 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:53:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2862 0 11 2669 203 793 18 83 92 6 1636 4 2 0 94 1 213 0 8 368 5 680 22 94 139 6 1864 2 1 0 96 2 278 0 0 342 3 597 10 54 90 1 1324 2 1 0 97 3 2558 0 2 480 83 770 21 79 144 2 3051 2 2 0 96 4 714 0 102 549 136 578 9 61 101 7 1192 2 1 0 97 5 62 0 0 328 3 595 7 55 124 2 1074 2 1 0 97 6 217 0 14 296 3 575 11 54 79 3 2265 2 1 0 97 7 237 0 0 203 1 363 6 31 85 4 1069 1 1 0 98 March 2, 2026 at 06:53:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2312 202 120 1 2 0 0 11 0 1 0 99 1 0 0 7 16 4 8 0 1 4 0 271 0 0 0 100 2 0 0 0 14 2 4 0 1 1 0 2 0 0 0 100 3 0 0 0 122 55 140 1 0 2 0 1416 0 0 0 100 4 0 0 21 217 104 12 0 0 1 0 15 0 0 0 100 5 0 0 0 14 2 2 1 0 1 0 1 0 0 0 100 6 38 0 14 30 9 28 0 1 2 0 590 0 0 0 100 7 2 0 0 20 5 10 0 0 1 0 326 0 0 0 100 March 2, 2026 at 06:53:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 204 116 0 1 0 0 2 0 0 0 100 1 0 0 7 16 3 16 0 5 0 0 260 0 0 0 100 2 0 0 0 13 1 10 0 2 0 0 1 0 0 0 100 3 0 0 0 118 53 148 1 2 0 0 1407 0 0 0 100 4 0 0 3 212 103 5 0 2 0 0 0 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 14 23 9 20 1 0 0 0 574 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 0 0 0 0 1 0 1 0 99 1 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 1 0 0 113 53 138 0 0 0 0 1422 0 0 0 100 4 0 0 4 216 103 14 0 1 0 0 0 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 14 22 9 20 0 0 0 0 575 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 21 2328 203 139 0 9 1 2 34 0 1 0 99 1 4 0 9 22 3 20 1 5 2 0 284 0 0 0 100 2 5 0 0 20 0 20 0 6 2 3 42 0 0 0 100 3 291 0 6 97 38 132 1 5 11 2 1541 0 0 0 99 4 3 0 7 259 121 54 1 5 1 0 10 0 0 0 100 5 11 0 3 40 10 51 2 12 3 6 68 0 0 0 100 6 28 0 16 49 12 50 1 6 1 5 641 0 0 0 100 7 15 0 10 28 1 34 0 8 4 4 358 0 0 0 99 March 2, 2026 at 06:53:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 201 113 0 0 0 0 0 0 1 0 99 1 0 0 7 18 4 10 0 0 0 0 280 0 0 0 100 2 0 0 0 9 0 2 0 0 1 0 0 0 0 0 100 3 0 0 0 15 3 38 1 0 0 0 1368 0 0 0 100 4 0 0 11 317 154 112 0 1 2 0 0 0 0 0 100 5 0 0 0 16 1 18 0 2 3 0 0 0 0 0 100 6 0 0 14 16 4 18 0 1 2 0 584 0 0 0 100 7 0 0 0 13 2 10 0 0 0 0 309 0 0 0 100 March 2, 2026 at 06:53:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2307 202 115 0 0 0 0 2 0 1 0 99 1 0 0 7 12 3 6 0 0 0 0 259 0 0 0 100 2 0 0 0 12 1 6 0 0 0 0 1 0 0 0 100 3 0 0 0 16 3 38 2 0 1 0 1364 0 0 0 100 4 0 0 3 300 146 90 0 0 0 0 1 0 0 0 100 5 0 0 0 26 8 22 0 2 0 0 0 0 0 0 100 6 0 0 14 17 3 18 1 1 0 0 566 0 0 0 100 7 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2305 201 112 0 0 0 0 0 0 1 0 99 1 0 0 7 11 3 6 0 0 0 0 259 0 0 0 100 2 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 36 1 0 0 0 1360 0 0 0 100 4 0 0 4 212 103 4 0 0 0 0 0 0 0 0 100 5 0 0 0 106 50 100 0 0 0 0 0 0 0 0 100 6 0 0 14 11 3 8 0 0 0 0 567 0 0 0 100 7 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:53:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 202 112 0 0 0 0 2 0 1 0 99 1 0 0 7 10 3 6 1 0 0 0 259 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1364 0 0 0 100 4 0 0 4 211 103 4 0 0 0 0 0 0 0 0 100 5 0 0 0 107 51 102 0 0 0 0 1 0 0 0 100 6 0 0 14 12 3 10 0 0 0 0 565 0 0 0 100 7 0 0 0 12 1 12 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:53:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 375 0 3 3273 204 2059 64 226 95 2 7203 13 4 0 83 1 2730 0 15 812 3 1639 59 185 171 7 6963 16 3 0 80 2 398 0 1 1057 0 2128 62 198 112 2 7942 12 4 0 84 3 2589 0 24 1024 9 2147 82 215 162 5 8623 13 4 0 83 4 820 0 382 933 107 1593 51 183 137 6 8408 16 4 0 81 5 179 0 0 885 47 1633 43 145 177 2 6312 13 3 0 84 6 128 0 14 939 5 1857 63 178 88 3 7530 12 3 0 85 7 281 0 0 805 3 1529 63 153 149 2 6776 13 3 0 84 March 2, 2026 at 06:53:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 57 0 9 5274 210 6050 95 609 402 0 23811 38 12 0 50 1 36 0 0 2948 10 5896 101 598 394 0 22925 46 10 0 44 2 37 0 0 2969 9 6096 90 608 377 0 22061 38 10 0 51 3 27 0 0 2728 60 5506 96 534 444 0 22384 47 10 0 43 4 24 0 1335 2655 109 5464 97 533 367 0 21225 42 10 0 48 5 19 0 0 2671 10 5473 80 495 408 0 21910 40 9 0 50 6 24 0 14 2364 11 4718 79 456 347 0 19363 43 8 0 49 7 11 0 0 2100 3 4171 51 388 418 0 19858 42 8 0 49 March 2, 2026 at 06:53:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 7 5282 206 6186 101 664 355 0 20848 36 11 0 52 1 15 0 12 2686 13 5293 94 575 499 0 23732 45 10 0 45 2 13 0 0 2994 13 6091 93 554 404 0 24694 41 10 0 49 3 11 0 0 2508 13 5136 102 526 398 0 21637 46 9 0 45 4 14 0 1393 2458 116 4948 91 463 408 0 21162 41 10 0 49 5 9 0 0 2223 7 4489 71 393 358 0 20041 45 9 0 46 6 23 0 14 2609 8 5423 103 526 378 0 19681 41 9 0 50 7 26 0 0 2411 10 4927 80 428 464 0 22705 42 9 0 49 March 2, 2026 at 06:53:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 3 5130 203 5852 118 584 436 0 22891 43 11 0 46 1 14 0 0 2550 15 5050 127 527 563 0 22749 46 10 0 44 2 10 0 7 2957 11 5982 98 530 315 0 21321 43 9 0 48 3 9 0 0 2602 13 5214 107 523 644 0 23794 44 10 0 45 4 5 0 1293 2753 110 5666 95 542 328 0 20230 41 10 0 49 5 1 0 12 2300 7 4595 105 454 492 0 19736 40 9 0 51 6 13 0 0 2873 12 5987 96 545 408 0 22564 39 9 0 51 7 2 0 14 2464 8 4978 87 456 524 0 21889 42 9 0 48 March 2, 2026 at 06:53:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 3 4776 211 5056 97 542 275 0 20441 46 11 0 43 1 10 0 0 2737 15 5464 106 574 334 0 19173 45 9 0 45 2 4 0 0 2567 6 5211 100 507 290 0 19258 44 9 0 47 3 4 0 0 3026 13 6285 96 586 455 0 21345 39 10 0 51 4 14 0 1313 2513 108 5063 69 458 293 0 20299 42 10 0 48 5 11 0 0 2399 8 4867 108 408 387 0 20643 42 9 0 48 6 6 0 0 2694 8 5511 84 532 345 0 20624 40 9 0 50 7 2 0 0 2347 11 4664 94 415 449 0 18769 39 8 0 53 March 2, 2026 at 06:53:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 3 5011 210 5478 129 585 277 0 18546 40 11 0 49 1 11 0 0 2270 6 4404 123 506 363 0 18401 46 9 0 45 2 10 0 0 2271 8 4485 104 487 231 0 17944 43 9 0 48 3 17 0 0 2656 4 5262 126 499 387 0 19080 41 10 0 49 4 6 0 1369 2688 117 5334 107 524 286 0 18115 37 10 0 53 5 2 0 0 2278 17 4357 105 432 297 0 15968 43 8 0 49 6 2 0 0 2340 11 4694 98 446 243 0 17308 43 9 0 48 7 2 0 0 2032 18 3893 67 352 395 0 17231 38 8 0 53 March 2, 2026 at 06:53:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 3 4854 207 5170 119 619 482 0 22436 43 11 0 46 1 11 0 0 3223 9 6572 119 705 549 0 23476 39 11 0 51 2 3 0 0 2891 11 5698 91 551 461 0 21621 38 10 0 53 3 10 0 0 2825 56 5710 102 570 453 0 22265 42 10 0 48 4 8 0 1376 2594 114 5222 97 509 520 0 20743 47 10 0 44 5 5 0 7 2606 12 5238 105 470 479 0 20268 39 9 0 52 6 23 0 14 2533 9 5247 75 483 441 0 21265 45 9 0 46 7 6 0 0 2324 14 4587 98 416 537 0 20791 43 9 0 48 March 2, 2026 at 06:53:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 17 5002 210 5555 99 595 336 0 21765 46 11 0 43 1 4 0 0 2890 8 5936 146 619 391 0 23343 43 11 0 47 2 3 0 0 2805 10 5569 103 555 396 0 20771 41 9 0 50 3 4 0 7 2710 12 5558 112 540 487 0 23193 43 10 0 47 4 9 0 1375 2317 112 4654 98 471 304 0 20762 48 10 0 42 5 0 0 0 2578 11 5271 61 450 331 0 19665 40 9 0 51 6 4 0 0 2733 11 5497 114 498 364 0 20911 40 9 0 51 7 1 0 0 2522 6 5127 80 439 648 0 22346 40 9 0 51 March 2, 2026 at 06:53:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 17 5019 214 5550 128 584 379 0 22421 44 11 0 45 1 3 0 0 2730 7 5421 151 593 350 0 21088 42 10 0 48 2 3 0 0 2699 12 5437 106 503 248 0 19612 40 10 0 51 3 4 0 0 2806 16 5704 107 515 388 0 22031 39 10 0 51 4 4 0 1333 2680 113 5389 106 486 378 0 20966 42 10 0 48 5 15 0 17 2161 8 4271 99 415 325 0 17962 43 8 0 49 6 3 0 0 2328 8 4731 106 466 268 0 19701 45 9 0 46 7 5 0 0 2279 4 4668 91 392 313 0 17365 42 8 0 49 March 2, 2026 at 06:53:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 72 0 17 3713 207 3029 38 311 140 0 10873 18 5 0 77 1 98 0 0 1210 12 2427 34 262 248 1 10438 18 5 0 77 2 58 0 0 1162 2 2405 22 242 203 0 11485 19 4 0 76 3 4 0 0 1179 8 2329 30 224 310 0 12444 20 5 0 76 4 22 0 607 1043 103 1858 33 185 97 0 8172 21 4 0 75 5 53 0 7 1064 11 2196 19 196 301 0 9039 17 4 0 79 6 157 0 0 1179 7 2437 26 217 103 1 7696 20 4 0 77 7 11 0 0 1019 26 1991 17 190 214 0 8534 18 4 0 78 March 2, 2026 at 06:53:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2369 256 230 0 0 0 0 285 0 1 0 99 1 0 0 0 16 4 12 0 0 1 0 616 0 0 0 100 2 0 0 0 15 1 8 0 0 0 0 8 0 0 0 100 3 0 0 0 15 2 42 2 1 2 0 1439 0 0 0 100 4 0 0 4 218 104 18 0 0 0 0 20 0 0 0 100 5 0 0 7 17 8 4 0 0 0 0 260 0 0 0 100 6 0 0 0 8 1 6 0 1 0 0 1 0 0 0 100 7 0 0 0 21 4 20 0 1 0 0 18 0 0 0 100 March 2, 2026 at 06:53:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2400 253 299 0 10 51 0 268 0 1 0 99 1 0 0 0 51 3 86 1 11 58 0 594 0 0 0 100 2 0 0 0 39 1 67 0 12 55 0 0 0 0 0 100 3 0 0 0 99 46 122 1 15 54 0 1429 0 0 0 99 4 0 0 3 240 103 65 0 12 54 0 1 0 0 0 100 5 0 0 7 86 3 154 1 13 50 0 260 0 0 0 100 6 0 0 0 46 1 81 0 14 60 0 0 0 0 0 100 7 0 0 0 49 6 73 0 12 42 0 8 0 0 0 100 March 2, 2026 at 06:53:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2355 252 218 0 1 1 0 266 0 0 0 99 1 0 0 0 20 4 20 0 1 1 0 595 0 0 0 100 2 0 0 0 11 2 2 0 0 1 0 0 0 0 0 100 3 0 0 0 15 4 36 0 0 1 0 1431 0 0 0 100 4 0 0 7 211 103 4 0 1 1 0 2 0 0 0 100 5 0 0 7 11 3 4 0 0 1 0 260 0 0 0 100 6 0 0 0 12 3 4 0 0 1 0 1 0 0 0 100 7 0 0 0 26 9 18 0 0 1 0 7 0 0 0 100 March 2, 2026 at 06:53:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 35 2366 253 219 0 6 2 0 285 0 1 0 99 1 9 0 5 38 4 35 2 8 3 3 611 0 0 0 100 2 19 0 7 28 2 36 0 8 2 0 40 0 1 0 99 3 26 0 0 32 2 54 2 7 11 2 1494 0 0 0 99 4 294 0 13 222 102 30 1 13 20 4 143 0 0 0 100 5 4 0 15 27 5 34 0 11 1 6 299 0 0 0 100 6 3 0 6 19 1 16 1 4 4 1 37 0 0 0 100 7 9 0 4 30 4 23 0 3 2 4 25 0 0 0 100 March 2, 2026 at 06:53:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2360 252 205 0 2 0 0 266 0 1 0 99 1 0 0 0 31 3 24 0 2 0 0 595 0 0 0 100 2 0 0 0 15 1 14 0 2 0 0 0 0 0 0 100 3 0 0 0 13 3 36 1 0 0 0 1375 0 0 0 100 4 0 0 4 212 103 2 0 1 0 0 0 0 0 0 100 5 0 0 7 12 2 8 0 1 0 0 259 0 0 0 100 6 0 0 7 11 1 4 0 1 0 0 0 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:53:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2360 253 219 0 1 0 0 268 0 1 0 99 1 0 0 0 23 3 12 1 1 0 0 594 0 0 0 100 2 0 0 0 18 1 16 0 2 0 0 14 0 0 0 100 3 0 0 0 21 3 48 2 1 1 0 1370 0 0 0 100 4 0 0 4 220 105 10 0 0 0 0 8 0 0 0 100 5 0 0 7 21 10 8 1 1 1 0 267 0 0 0 100 6 0 0 0 11 1 4 0 1 0 0 0 0 0 0 100 7 0 0 7 15 1 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:53:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2364 254 200 0 3 0 0 267 0 1 0 99 1 0 0 0 42 4 38 0 4 2 0 615 0 0 0 100 2 0 0 0 13 1 8 0 0 3 0 0 0 0 0 100 3 0 0 0 11 2 34 1 0 3 0 1369 0 0 0 100 4 0 0 3 208 102 0 0 0 0 0 0 0 0 0 100 5 0 0 7 9 2 4 0 0 0 0 259 0 0 0 100 6 0 0 0 9 1 4 0 0 2 0 0 0 0 0 100 7 0 0 0 13 1 8 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:53:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2360 253 216 0 0 0 0 268 0 1 0 99 1 0 0 0 14 2 10 0 1 0 0 593 0 0 0 100 2 0 0 0 13 2 8 0 1 0 0 1 0 0 0 100 3 0 0 0 15 2 38 2 1 0 0 1369 0 0 0 100 4 0 0 4 212 102 10 0 1 0 0 0 0 0 0 100 5 0 0 7 8 2 4 0 0 0 0 259 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 9 2 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:53:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 759 0 3 3243 229 1664 51 293 103 7 7523 15 4 0 82 1 457 0 14 924 8 1628 40 292 75 5 9219 12 3 0 85 2 463 0 0 783 9 1299 29 240 108 2 7407 12 3 0 85 3 3199 0 8 840 3 1535 38 277 148 10 10031 13 4 0 83 4 2966 0 721 897 103 1379 38 269 110 10 7832 12 4 0 84 5 975 0 53 670 6 1114 25 222 89 8 7087 10 3 0 88 6 567 0 7 782 6 1384 37 270 120 5 7667 11 3 0 87 7 526 0 0 666 6 1157 32 185 146 7 7422 10 2 0 87 March 2, 2026 at 06:53:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 205 0 3 4004 203 2909 73 529 195 0 14163 24 7 0 70 1 386 0 0 1703 10 3008 73 599 239 0 16918 26 6 0 68 2 313 0 14 1614 8 2706 53 481 258 0 15036 27 5 0 68 3 436 0 0 1526 11 2614 77 503 263 0 18097 25 6 0 69 4 247 0 1418 1501 116 2564 53 502 197 0 15473 21 6 0 73 5 132 0 0 1336 15 2175 32 396 205 0 12808 19 4 0 76 6 301 0 7 1366 5 2385 54 500 250 0 16170 21 5 0 74 7 190 0 0 1183 8 1965 39 341 198 0 12978 18 4 0 79 March 2, 2026 at 06:53:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 72 0 3 4099 213 3060 82 583 173 0 15996 26 7 0 67 1 94 0 7 1846 4 3252 92 623 243 0 17706 26 6 0 68 2 88 0 0 1660 17 2704 53 495 148 0 15729 21 5 0 73 3 121 0 14 1574 15 2675 77 553 364 0 18269 22 6 0 73 4 14 0 1418 1480 107 2539 71 537 178 0 16105 22 6 0 72 5 37 0 0 1389 8 2323 47 395 244 0 16214 24 5 0 71 6 81 0 0 1598 8 2826 71 531 147 0 15633 20 5 0 76 7 84 0 0 1330 18 2257 62 388 269 0 15835 21 5 0 74 March 2, 2026 at 06:54:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 3 4210 212 3226 75 629 181 0 16117 26 7 0 67 1 33 0 54 1874 12 3341 89 718 399 0 18274 24 6 0 69 2 84 0 0 1751 6 2980 70 534 332 0 15953 26 6 0 68 3 45 0 14 1851 87 3170 106 693 234 0 19922 25 6 0 69 4 45 0 1417 1681 111 2941 63 640 217 0 17081 21 6 0 72 5 51 0 0 1470 10 2514 54 469 329 0 15935 20 5 0 75 6 29 0 0 1574 9 2796 79 607 342 0 16707 23 5 0 72 7 10 0 0 1382 2 2371 50 429 215 0 13773 19 4 0 76 March 2, 2026 at 06:54:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 4259 209 3423 85 708 183 0 16064 24 7 0 69 1 0 0 0 2044 16 3611 91 740 290 0 19619 25 7 0 69 2 0 0 0 1799 8 3102 74 566 302 0 17716 23 6 0 71 3 0 0 14 1888 14 3455 84 689 249 0 20950 25 6 0 68 4 0 0 1429 1649 116 2892 59 626 178 0 17742 22 6 0 72 5 0 0 0 1435 11 2392 42 506 339 0 15772 21 5 0 74 6 0 0 0 1574 13 2831 63 600 324 0 18016 23 5 0 71 7 29 0 0 1361 11 2405 43 447 313 0 16191 23 5 0 72 March 2, 2026 at 06:54:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 3 4728 208 4322 105 867 263 0 20781 27 8 0 64 1 23 0 7 2386 10 4291 106 906 311 0 23656 28 8 0 65 2 13 0 0 2126 10 3692 81 688 337 0 20967 25 7 0 68 3 9 0 0 2156 11 4053 104 837 358 0 24797 26 7 0 66 4 11 0 1431 2125 118 3846 77 806 312 0 21159 24 7 0 69 5 6 0 0 1872 13 3307 41 610 350 0 18798 20 6 0 75 6 4 0 0 1979 6 3728 80 755 336 0 21518 24 6 0 70 7 8 0 0 1726 13 3207 57 573 378 0 19905 22 6 0 72 March 2, 2026 at 06:54:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 136 0 3 2344 201 143 1 14 13 1 207 0 1 0 99 1 64 0 7 43 3 63 1 12 0 0 453 0 0 0 100 2 25 0 0 49 1 83 1 9 16 0 324 1 0 0 99 3 1 0 0 40 3 66 0 7 5 0 207 0 0 0 99 4 14 0 46 329 156 144 0 4 6 0 742 0 0 0 99 5 0 0 0 41 3 42 1 6 1 0 544 0 0 0 100 6 8 0 0 40 5 55 1 8 10 0 208 0 0 0 100 7 0 0 0 48 1 78 2 6 5 0 1219 0 0 0 100 March 2, 2026 at 06:54:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 102 0 0 0 0 0 0 1 0 99 1 0 0 7 18 4 18 0 0 0 0 273 0 0 0 100 2 0 0 0 21 2 18 0 1 0 0 307 0 0 0 100 3 0 0 0 23 8 20 0 0 0 0 12 0 0 0 100 4 0 0 18 319 157 114 1 2 0 0 568 0 0 0 100 5 0 0 0 15 6 4 0 0 0 0 298 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 7 0 0 0 11 1 36 1 0 0 0 1130 0 0 0 100 March 2, 2026 at 06:54:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2350 201 187 0 11 43 0 1 0 1 0 99 1 0 0 7 67 3 123 0 20 65 0 261 0 0 0 100 2 0 0 0 52 2 80 0 14 54 0 300 0 0 0 100 3 0 0 0 126 68 107 0 15 56 0 6 0 0 0 99 4 0 0 18 367 156 215 0 18 62 0 566 0 0 0 100 5 0 0 0 42 1 69 0 11 45 0 294 0 0 0 100 6 0 0 0 106 2 197 0 14 50 0 18 0 0 0 100 7 0 0 0 49 2 118 0 9 58 0 1137 0 0 0 99 March 2, 2026 at 06:54:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 110 0 1 0 0 0 0 1 0 99 1 0 0 7 18 5 14 1 0 0 0 265 0 0 0 100 2 0 0 0 24 3 20 0 0 0 0 304 0 0 0 100 3 0 0 0 18 5 14 0 0 0 0 6 0 0 0 100 4 0 0 18 315 156 110 0 0 0 0 565 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 6 0 0 0 10 2 6 0 0 0 0 0 0 0 0 100 7 0 0 0 12 1 36 1 1 1 0 1129 0 0 0 100 March 2, 2026 at 06:54:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 19 2324 200 136 1 6 3 4 48 0 1 0 99 1 15 0 27 33 2 35 1 10 2 5 297 0 0 0 100 2 5 0 13 31 2 31 1 6 2 2 330 0 0 0 100 3 8 0 0 36 3 23 0 5 8 1 56 0 0 0 100 4 294 0 20 339 156 128 1 5 16 3 674 0 0 0 99 5 18 0 12 28 5 34 0 8 4 10 327 0 0 0 100 6 21 0 8 24 2 22 1 6 7 3 36 0 0 0 100 7 1 0 0 21 1 45 2 3 2 2 1092 0 0 0 100 March 2, 2026 at 06:54:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 102 0 0 0 0 0 0 0 0 100 1 0 0 7 19 2 21 0 3 0 0 259 0 0 0 100 2 0 0 0 23 2 16 0 0 0 0 300 0 0 0 100 3 0 0 7 9 1 6 0 1 0 0 2 0 0 0 100 4 0 0 18 317 156 110 1 0 0 0 566 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 294 0 0 0 100 6 0 0 0 10 2 2 0 0 0 0 0 0 0 0 100 7 0 0 0 11 1 32 1 0 1 0 1068 0 0 0 100 March 2, 2026 at 06:54:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 102 0 0 0 0 0 0 1 0 99 1 0 0 14 22 5 21 0 0 0 0 266 0 0 0 100 2 0 0 0 28 2 28 0 1 0 0 306 0 0 0 100 3 0 0 0 10 0 6 0 1 0 0 0 0 0 0 100 4 0 0 18 321 156 124 0 2 0 0 579 0 0 0 100 5 0 0 0 18 8 2 0 0 1 0 294 0 0 0 100 6 0 0 0 8 1 2 0 1 0 0 0 0 0 0 100 7 0 0 0 11 1 34 0 0 0 0 1069 0 0 0 100 March 2, 2026 at 06:54:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 200 100 0 0 0 0 0 0 1 0 99 1 0 0 14 16 3 12 1 0 2 0 259 0 0 0 100 2 0 0 0 23 3 18 0 0 1 0 300 0 0 0 100 3 0 0 0 12 2 10 0 1 1 0 2 0 0 0 100 4 0 0 18 319 156 116 0 1 0 0 566 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 294 0 0 0 100 6 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 7 0 0 0 9 1 32 1 0 0 0 1069 0 0 0 100 March 2, 2026 at 06:54:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2303 200 100 0 0 1 0 0 0 1 0 99 1 0 0 7 17 4 10 0 0 1 0 259 0 0 0 100 2 0 0 0 24 3 14 1 0 1 0 300 0 0 0 100 3 0 0 0 16 2 14 0 1 1 0 0 0 0 0 100 4 0 0 21 320 158 116 0 1 0 0 567 0 0 0 100 5 0 0 0 10 2 2 0 0 1 0 294 0 0 0 100 6 0 0 0 10 2 2 0 0 1 0 1 0 0 0 100 7 0 0 0 15 4 36 1 0 2 0 1071 0 0 0 100 March 2, 2026 at 06:54:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 216 0 3 2733 201 897 39 171 29 7 4247 5 2 0 93 1 274 0 7 464 5 934 36 212 50 3 4924 5 2 0 94 2 333 0 0 407 3 741 20 168 59 1 3845 4 1 0 95 3 251 0 0 407 3 850 42 181 107 0 4485 5 2 0 94 4 5234 0 237 593 109 813 32 172 55 13 5429 6 2 0 92 5 910 0 1 372 8 736 15 144 68 9 3922 4 1 0 95 6 260 0 0 435 4 898 23 168 67 7 4487 4 1 0 94 7 164 0 0 459 42 787 23 117 126 7 4744 4 2 0 95 March 2, 2026 at 06:54:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37 0 3 2358 246 194 0 1 0 0 10 0 0 0 99 1 0 0 7 12 3 8 0 1 0 0 263 0 0 0 100 2 0 0 0 20 2 14 0 0 0 0 300 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 4 0 0 18 213 105 8 0 0 0 0 566 0 0 0 100 5 0 0 0 11 2 4 0 0 0 0 294 0 0 0 100 6 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 7 0 0 0 29 12 52 0 0 1 0 1127 0 0 0 100 March 2, 2026 at 06:54:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2371 256 216 0 0 0 0 9 0 1 0 99 1 0 0 7 12 3 8 1 0 0 0 260 0 0 0 100 2 0 0 0 22 2 20 0 1 0 0 310 0 0 0 100 3 0 0 0 13 3 10 0 0 0 0 3 0 0 0 100 4 0 0 18 217 106 12 0 0 0 0 566 0 0 0 100 5 0 0 0 29 10 22 0 1 1 0 301 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 1 13 1 40 1 1 0 0 1132 0 0 0 100 March 2, 2026 at 06:54:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2411 259 289 0 11 47 0 14 0 1 0 99 1 0 0 7 53 4 82 0 9 61 0 281 0 0 0 100 2 0 0 0 59 6 87 1 11 46 0 306 0 0 0 100 3 0 0 0 102 49 96 0 13 90 0 0 0 0 0 100 4 0 0 18 256 105 92 0 13 54 0 567 0 0 0 100 5 0 0 0 55 2 98 0 11 45 0 294 0 0 0 100 6 0 0 0 89 0 170 0 14 65 0 0 0 0 0 100 7 0 0 0 27 1 65 1 6 25 0 1126 0 0 0 100 March 2, 2026 at 06:54:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 17 2378 255 239 0 7 1 6 52 0 1 0 99 1 5 0 7 32 2 30 0 6 5 4 306 0 0 0 100 2 16 0 7 35 4 45 1 8 1 7 346 0 0 0 99 3 4 0 2 33 3 31 0 3 5 4 54 0 0 0 100 4 280 0 33 226 105 32 2 6 22 3 706 0 0 0 100 5 5 0 2 30 5 25 0 2 1 0 318 0 0 0 100 6 23 0 2 17 0 17 0 2 3 1 22 0 0 0 100 7 2 0 2 17 1 44 1 5 1 0 1094 0 0 0 100 March 2, 2026 at 06:54:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 250 209 0 3 0 0 0 0 1 0 99 1 0 0 7 12 2 6 0 0 0 0 259 0 0 0 100 2 0 0 0 19 3 11 0 2 0 0 300 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 4 0 0 18 216 105 10 0 0 0 0 566 0 0 0 100 5 0 0 7 10 2 6 0 1 0 0 294 0 0 0 100 6 0 0 0 14 0 10 0 0 0 0 0 0 0 0 100 7 0 0 0 11 1 32 1 0 0 0 1068 0 0 0 100 March 2, 2026 at 06:54:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2353 250 207 0 1 0 0 0 0 1 0 99 1 0 0 7 16 2 8 1 1 0 0 259 0 0 0 100 2 0 0 0 19 3 13 0 2 0 0 300 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 2 0 0 0 100 4 0 0 18 214 105 8 0 0 0 0 565 0 0 0 100 5 0 0 0 12 2 6 0 0 0 0 294 0 0 0 100 6 0 0 0 10 0 6 0 2 0 0 0 0 0 0 100 7 0 0 0 15 1 44 0 1 1 0 1070 0 0 0 100 March 2, 2026 at 06:54:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2356 250 212 0 1 0 0 0 0 1 0 99 1 0 0 7 11 2 6 0 0 0 0 259 0 0 0 100 2 0 0 0 23 3 18 1 0 0 0 311 0 0 0 100 3 0 0 0 11 1 8 0 1 0 0 0 0 0 0 100 4 0 0 18 214 105 8 0 0 0 0 567 0 0 0 100 5 0 0 0 24 10 12 0 0 1 0 301 0 0 0 100 6 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 7 0 0 0 15 1 42 1 0 1 0 1077 0 0 0 100 March 2, 2026 at 06:54:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2360 250 218 0 1 0 0 0 0 1 0 99 1 0 0 7 11 2 8 0 0 2 0 259 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 3 0 0 0 13 3 10 0 0 1 0 2 0 0 0 100 4 0 0 18 217 106 12 1 0 0 0 566 0 0 0 100 5 0 0 0 12 2 10 0 1 1 0 294 0 0 0 100 6 0 0 0 6 0 2 0 0 1 0 0 0 0 0 100 7 0 0 0 10 1 34 1 0 0 0 1068 0 0 0 100 March 2, 2026 at 06:54:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 465 0 3 4149 213 3366 74 320 166 15 7560 20 7 0 73 1 380 0 0 1832 14 3216 114 340 217 7 7421 20 5 0 75 2 407 0 38 1595 13 2725 45 249 237 8 6595 15 5 0 80 3 322 0 0 1673 13 2898 68 270 214 4 6651 18 5 0 77 4 2262 0 1062 1520 121 2475 53 268 177 14 6900 15 10 0 76 5 717 0 0 1346 14 2201 33 189 272 15 5973 16 4 0 80 6 693 0 7 1429 7 2497 55 229 210 26 6253 15 5 0 80 7 247 0 2 1102 8 1923 27 137 206 11 6353 14 4 0 83 March 2, 2026 at 06:54:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 48 0 3 4590 215 4036 46 432 303 0 9530 25 8 0 67 1 30 0 0 2363 12 4166 76 454 250 0 10672 26 7 0 67 2 48 0 0 2112 16 3589 55 308 291 0 8734 22 6 0 72 3 13 0 0 2225 27 3883 53 351 307 0 9019 24 6 0 70 4 38 0 1420 1960 114 3391 43 304 293 0 8003 22 6 0 72 5 36 0 4 1697 20 2869 26 214 277 0 7366 20 5 0 75 6 25 0 14 1981 22 3443 37 313 249 0 8621 22 5 0 73 7 22 0 0 1493 12 2506 29 189 286 0 6357 18 4 0 78 March 2, 2026 at 06:54:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 41 0 3 4736 218 4331 88 467 287 1 9634 28 8 0 64 1 66 0 0 2433 18 4235 91 435 223 0 10911 27 7 0 66 2 32 0 7 2039 22 3370 48 311 286 0 8475 22 6 0 73 3 31 0 0 2435 26 4316 89 382 338 0 9638 26 7 0 68 4 17 0 1419 1862 123 3142 45 307 293 0 8134 21 6 0 73 5 35 0 0 1710 30 2859 28 225 225 0 6940 16 4 0 79 6 24 0 14 1903 19 3311 55 280 287 0 8037 22 5 0 73 7 18 0 0 1446 15 2351 19 154 328 0 6316 17 4 0 80 March 2, 2026 at 06:54:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 602 0 13 2591 248 603 9 59 21 19 872 2 2 0 96 1 2439 0 30 264 3 500 7 64 22 13 2589 4 1 0 95 2 282 0 21 222 5 381 8 52 17 12 1157 2 1 0 97 3 316 0 19 269 12 452 12 54 70 9 1424 3 1 0 95 4 2855 0 124 419 106 417 12 56 63 11 1493 2 2 0 97 5 1061 0 9 232 37 299 7 46 50 17 1194 1 1 0 98 6 75 0 26 202 9 349 8 41 17 8 1035 1 1 0 98 7 150 0 5 174 1 290 5 41 63 19 793 3 1 0 96 March 2, 2026 at 06:54:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2400 251 279 0 11 61 0 1 0 1 0 99 1 4 0 0 58 2 115 1 12 77 0 1428 0 0 0 100 2 0 0 7 44 3 69 0 12 53 0 307 0 0 0 100 3 37 0 0 114 57 103 0 19 50 0 8 0 0 0 100 4 0 0 3 252 104 86 0 16 50 0 294 0 0 0 100 5 0 0 0 56 3 92 0 10 48 0 300 0 0 0 100 6 0 0 14 90 1 166 0 14 33 0 266 0 0 0 100 7 0 0 7 35 0 63 0 8 46 0 0 0 0 0 100 March 2, 2026 at 06:54:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2356 250 204 0 1 0 0 0 0 0 0 100 1 0 0 0 19 2 42 1 0 1 0 1425 0 0 0 100 2 0 0 7 17 4 12 1 1 0 0 261 0 0 0 100 3 0 0 7 27 8 23 0 0 0 0 10 0 0 0 100 4 0 0 4 214 103 6 0 1 1 0 294 0 0 0 100 5 0 0 0 17 3 16 0 1 0 0 300 0 0 0 100 6 0 0 14 6 1 2 0 0 0 0 266 0 0 0 100 7 0 0 0 9 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2353 250 204 0 1 0 0 0 0 1 0 99 1 0 0 0 20 2 42 2 0 0 0 1427 0 0 0 100 2 0 0 7 15 4 10 0 0 0 0 261 0 0 0 100 3 0 0 0 24 7 16 0 0 0 0 8 0 0 0 100 4 0 0 4 211 103 4 0 0 0 0 294 0 0 0 100 5 0 0 0 14 3 6 0 0 0 0 300 0 0 0 100 6 0 0 14 12 1 14 0 2 0 0 266 0 0 0 100 7 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 183 0 29 2414 213 275 4 31 14 6 305 0 1 0 99 1 582 0 16 150 42 232 9 27 13 7 1841 1 1 0 98 2 199 0 7 111 3 178 5 28 10 12 553 0 0 0 99 3 459 0 2 111 9 156 5 23 31 6 472 1 1 0 98 4 5201 0 51 270 104 135 1 30 57 9 1289 2 2 0 96 5 1193 0 8 147 36 153 3 23 33 4 926 1 1 0 98 6 68 0 20 74 3 147 2 27 14 10 693 1 0 0 99 7 219 0 0 63 2 101 2 22 12 2 528 0 0 0 100 March 2, 2026 at 06:54:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 114 0 0 0 0 0 0 1 0 99 1 37 0 7 43 17 67 1 2 0 0 1434 0 0 0 99 2 0 0 7 99 43 100 0 1 0 0 275 0 0 0 100 3 0 0 0 20 4 16 0 0 0 0 7 0 0 0 100 4 0 0 4 215 103 8 0 1 0 0 302 0 0 0 100 5 0 0 0 18 10 4 0 0 0 0 300 0 0 0 100 6 0 0 14 10 2 6 0 1 0 0 266 0 0 0 100 7 0 0 0 15 0 16 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:54:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2350 200 201 0 14 79 0 0 0 1 0 99 1 0 0 7 84 7 166 1 21 77 0 1434 0 1 0 99 2 0 0 7 149 53 177 1 13 51 0 260 0 0 0 100 3 0 0 0 138 71 123 0 17 91 0 3 0 0 0 100 4 0 0 4 262 103 100 0 16 62 0 294 0 0 0 100 5 0 0 0 53 3 87 0 12 63 0 301 0 0 0 100 6 0 0 14 117 3 219 0 15 63 0 266 0 0 0 100 7 0 0 0 52 0 96 0 15 44 0 0 0 0 0 100 March 2, 2026 at 06:54:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2306 201 112 0 1 0 0 1 0 1 0 99 1 0 0 7 15 3 36 1 0 1 0 1425 0 0 0 99 2 0 0 7 117 55 108 0 0 1 0 261 0 0 0 100 3 0 0 0 27 9 18 0 0 1 0 9 0 0 0 100 4 0 0 7 212 103 4 0 0 1 0 294 0 0 0 100 5 0 0 0 15 4 6 0 0 1 0 301 0 0 0 100 6 0 0 14 14 4 8 0 0 1 0 267 0 0 0 100 7 0 0 0 11 1 2 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:54:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 24890 0 44 2556 202 474 15 77 34 43 1247 8 24 0 68 1 2485 0 13 250 4 363 11 61 45 36 1577 4 1 0 95 2 7500 0 144 203 21 389 6 61 61 47 2746 3 3 0 94 3 436 0 30 325 43 547 3 89 80 50 1072 1 1 0 98 4 3114 0 10 389 103 342 13 66 89 31 1600 2 2 0 96 5 3159 0 9 240 38 402 6 68 116 39 1830 1 2 0 97 6 225 0 37 185 3 370 5 73 73 47 1148 0 1 0 99 7 92 0 8 171 0 324 3 60 35 39 847 0 0 0 99 March 2, 2026 at 06:54:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 51 0 31 2314 204 69 0 3 2 0 7 0 1 0 99 1 0 0 0 63 2 52 0 3 3 0 300 0 0 0 100 2 0 0 7 22 4 40 1 0 2 0 1305 0 0 0 100 3 0 0 0 124 54 114 0 0 0 0 3 0 0 0 100 4 0 0 11 220 104 10 0 2 0 0 296 0 0 0 100 5 0 0 0 16 2 6 0 0 0 0 300 0 0 0 100 6 0 0 14 23 1 20 0 1 0 0 265 0 0 0 100 7 0 0 0 10 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2348 204 121 0 3 1 0 16 0 1 0 99 1 0 0 231 16 2 10 0 1 2 0 300 0 0 0 100 2 0 0 7 51 4 40 1 0 0 0 1299 0 0 0 99 3 0 0 0 166 59 126 0 0 0 0 16 0 0 0 100 4 0 0 4 250 104 8 0 0 0 0 295 0 0 0 100 5 0 0 0 52 8 6 0 1 0 0 300 0 0 0 100 6 0 0 14 53 1 18 0 0 0 0 276 0 0 0 100 7 0 0 0 44 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2358 205 188 0 6 59 0 9 0 1 0 99 1 0 0 0 57 3 95 2 13 48 0 321 0 0 0 100 2 0 0 7 51 5 112 1 15 59 0 1298 0 0 0 99 3 0 0 0 186 98 162 0 10 53 0 0 0 0 0 100 4 0 0 4 283 117 123 0 12 61 0 294 0 0 0 100 5 0 0 0 49 2 84 0 9 40 0 300 0 0 0 100 6 0 0 14 102 2 186 0 12 22 0 285 0 0 0 100 7 0 0 0 59 1 106 0 9 48 0 9 0 0 0 100 March 2, 2026 at 06:54:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 61 0 3 2351 205 163 0 9 9 4 111 0 1 0 99 1 12 0 0 43 2 43 0 11 4 3 408 0 0 0 100 2 7 0 7 46 5 67 1 8 4 2 1429 0 0 0 99 3 6 0 0 47 5 37 0 6 1 3 44 0 0 0 100 4 2642 0 117 255 117 83 2 5 8 16 687 1 1 0 98 5 87 0 0 126 38 146 1 14 17 11 518 0 0 0 100 6 27 0 15 41 1 45 0 10 15 6 390 0 0 0 100 7 651 0 0 41 0 39 1 5 7 6 232 1 0 0 98 March 2, 2026 at 06:54:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2318 205 116 1 1 0 0 15 0 1 0 99 1 0 0 0 19 2 16 0 1 0 0 307 0 0 0 100 2 0 0 7 20 5 46 1 2 0 0 1385 0 0 0 100 3 0 0 0 12 2 8 0 0 2 0 3 0 0 0 100 4 0 0 4 210 103 4 0 0 0 0 294 0 0 0 100 5 0 0 0 109 52 104 0 0 0 0 300 0 0 0 100 6 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 7 0 0 0 8 0 4 0 1 0 0 3 0 0 0 100 March 2, 2026 at 06:54:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2313 205 114 0 0 1 0 10 0 0 0 99 1 0 0 0 21 1 22 0 1 0 0 300 0 0 0 100 2 23 0 7 19 6 42 2 0 2 0 1385 0 0 0 100 3 0 0 0 12 2 8 0 1 0 0 0 0 0 0 100 4 0 0 4 210 103 4 0 0 0 0 294 0 0 0 100 5 0 0 0 109 52 104 0 0 0 0 300 0 0 0 100 6 0 0 14 7 2 2 0 0 0 0 266 0 0 0 100 7 23 0 0 6 0 2 0 1 0 0 5 0 0 0 100 March 2, 2026 at 06:54:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2315 204 116 1 0 0 0 16 0 1 0 99 1 0 0 0 20 1 14 1 0 0 0 300 0 0 0 100 2 0 0 7 20 4 50 1 2 1 0 1376 0 0 0 100 3 0 0 0 16 3 14 0 0 0 0 5 0 0 0 100 4 0 0 4 210 103 4 0 0 0 0 294 0 0 0 100 5 0 0 0 116 57 104 0 0 0 0 300 0 0 0 100 6 1 0 14 16 3 16 0 0 0 0 282 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 206 30 0 0 0 0 8 0 1 0 99 1 0 0 0 99 1 96 0 1 3 0 300 0 0 0 100 2 0 0 7 15 4 40 1 0 0 0 1377 0 0 0 100 3 0 0 0 14 3 10 0 0 1 0 0 0 0 0 100 4 0 0 4 211 103 6 0 0 0 0 294 0 0 0 100 5 0 0 0 113 52 110 1 0 2 0 300 0 0 0 100 6 0 0 14 8 2 6 0 0 0 0 266 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 204 46 0 3 1 0 8 0 1 0 99 1 0 0 0 85 2 76 0 0 1 0 300 0 0 0 100 2 0 0 7 21 6 42 1 1 2 0 1377 0 0 0 100 3 0 0 0 20 4 16 0 1 1 0 0 0 0 0 100 4 0 0 4 210 103 4 0 0 1 0 294 0 0 0 100 5 0 0 0 113 54 108 0 1 0 0 301 0 0 0 100 6 0 0 14 9 3 4 0 0 1 0 267 0 0 0 100 7 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:54:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 71 0 3 2419 207 332 1 18 5 0 513 1 1 0 98 1 245 0 0 114 1 206 3 26 8 0 832 1 1 0 99 2 100 0 7 88 5 354 4 16 10 0 2110 1 1 0 99 3 293 0 0 105 7 179 1 20 13 2 576 1 0 0 99 4 462 0 18 288 105 147 1 11 6 1 714 1 1 0 98 5 92 0 0 190 86 199 2 10 2 3 614 0 0 0 99 6 35 0 14 57 1 110 1 13 8 1 546 0 0 0 99 7 52 0 0 40 1 60 1 5 10 1 243 0 0 0 100 March 2, 2026 at 06:54:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 110 0 0 0 0 4 0 1 0 99 1 30 0 0 30 6 24 1 0 0 0 322 0 0 0 100 2 0 0 7 23 5 48 1 1 1 0 1409 0 0 0 100 3 0 0 0 16 3 12 0 2 0 0 15 0 0 0 100 4 1 0 18 217 105 12 0 1 0 0 302 0 0 0 100 5 2 0 0 112 52 106 0 1 0 0 310 0 0 0 100 6 11 0 14 15 3 8 0 0 0 0 301 0 0 0 100 7 8 0 0 10 0 4 0 1 0 0 11 0 0 0 100 March 2, 2026 at 06:54:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 114 1 1 0 0 10 0 1 0 99 1 0 0 0 28 7 22 1 0 0 0 306 0 0 0 100 2 0 0 7 15 4 40 1 0 0 0 1392 0 0 0 100 3 0 0 0 16 4 13 0 1 0 0 1 0 0 0 100 4 0 0 4 215 104 10 0 1 0 0 298 0 0 0 100 5 0 0 0 124 58 116 1 2 0 0 305 0 0 0 100 6 0 0 14 13 3 10 0 0 0 0 273 0 0 0 100 7 0 0 0 10 0 8 0 1 0 0 4 0 0 0 100 March 2, 2026 at 06:54:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2349 201 181 0 10 55 0 1 0 1 0 99 1 0 0 0 80 7 130 0 17 64 0 309 0 0 0 100 2 0 0 7 48 4 101 1 17 49 0 1391 0 0 0 99 3 0 0 0 119 64 102 0 16 58 0 0 0 0 0 100 4 0 0 4 263 103 115 0 21 68 0 294 0 0 0 99 5 0 0 0 147 52 176 0 7 37 0 300 0 0 0 100 6 0 0 14 115 2 223 0 18 53 0 266 0 0 0 100 7 0 0 0 45 0 82 0 14 49 0 0 0 0 0 100 March 2, 2026 at 06:54:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 765 0 20 2628 201 627 6 131 679 84 2614 2 2 0 96 1 975 0 155 346 7 659 5 132 80 90 3107 1 2 0 97 2 2193 0 26 316 5 584 8 116 465 76 4379 1 3 0 96 3 6786 0 258 340 3 699 7 136 165 116 4092 2 3 0 94 4 296 0 38 517 104 640 0 157 647 122 3684 1 2 0 97 5 407 0 29 414 76 668 1 134 110 80 2970 1 1 0 98 6 249 0 27 334 13 624 5 135 71 82 2812 1 1 0 98 7 107 0 21 234 0 419 2 88 205 61 3437 1 1 0 98 March 2, 2026 at 06:54:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 3 2331 201 111 0 2 2 1 8 0 1 0 99 1 8 0 7 42 1 31 1 4 7 1 336 0 0 0 100 2 9 0 7 40 4 63 1 3 4 4 1086 0 0 0 100 3 9 0 0 30 3 20 0 1 5 1 9 0 0 0 100 4 5 0 88 261 123 57 0 5 10 2 307 0 2 0 98 5 2 0 0 33 2 23 0 3 11 2 310 0 1 0 99 6 13 0 22 92 33 84 0 6 10 3 286 0 0 0 100 7 26 0 3 27 0 20 1 5 5 5 28 0 0 0 100 March 2, 2026 at 06:54:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2416 201 114 0 1 0 0 2 0 1 0 99 1 0 0 0 120 1 10 0 0 0 0 300 0 0 0 100 2 0 0 7 120 4 40 1 0 0 0 1020 0 1 0 99 3 0 0 0 116 3 6 0 0 0 0 0 0 0 0 100 4 0 0 53 310 103 6 0 0 2 0 294 0 2 0 98 5 0 0 678 19 2 6 1 0 2 0 300 0 1 0 99 6 0 0 14 212 51 104 0 1 0 0 266 0 0 0 100 7 0 0 7 113 0 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:54:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 108 0 1 0 0 0 0 0 0 100 1 0 0 0 17 1 10 0 0 0 0 300 0 0 0 100 2 0 0 7 16 4 40 0 0 0 0 1019 0 0 0 100 3 0 0 0 20 3 20 0 1 0 0 15 0 0 0 100 4 0 0 18 220 105 14 0 1 0 0 305 0 0 0 100 5 0 0 0 18 7 4 0 0 0 0 300 0 0 0 100 6 0 0 14 108 51 104 0 1 0 0 267 0 0 0 100 7 0 0 0 12 0 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 108 0 0 0 0 2 0 1 0 99 1 0 0 0 23 1 24 0 1 1 0 300 0 0 0 100 2 0 0 7 16 4 42 2 0 0 0 1017 0 0 0 100 3 0 0 0 14 4 10 0 0 1 0 0 0 0 0 100 4 0 0 4 211 103 6 0 0 2 0 294 0 0 0 100 5 0 0 0 12 2 10 0 0 2 0 300 0 0 0 100 6 0 0 14 106 51 104 0 0 0 0 266 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3164 0 243 2495 200 424 7 54 61 71 6936 2 5 0 93 1 660 0 21 244 2 395 3 72 51 57 1388 0 1 0 98 2 2798 0 23 254 5 393 1 60 33 40 2010 1 1 0 98 3 2804 0 26 208 6 273 6 49 43 37 820 1 2 0 98 4 4932 0 14 395 104 255 9 50 63 35 10226 3 5 0 92 5 69 0 5 185 12 210 1 38 25 31 655 0 0 0 99 6 91 0 33 259 44 305 0 42 29 23 714 0 0 0 99 7 5184 0 236 150 1 238 2 35 18 51 731 1 1 0 98 March 2, 2026 at 06:54:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4735 0 183 2583 201 244 7 45 393 35 9761 3 4 0 92 1 2515 0 12 201 3 231 6 48 389 48 7342 2 2 0 95 2 534 0 17 355 50 435 3 62 69 56 2063 0 1 0 98 3 3478 0 395 264 4 202 3 42 323 34 771 1 3 0 96 4 2741 0 7 415 102 198 2 52 116 32 1467 1 1 0 98 5 1610 0 383 264 8 205 2 47 202 32 1327 1 2 0 98 6 4196 0 372 218 2 214 3 48 342 46 6891 3 3 0 95 7 3176 0 0 288 0 160 1 36 331 30 6972 3 2 0 95 March 2, 2026 at 06:54:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2371 200 106 0 1 0 0 0 0 1 0 99 1 0 0 0 81 2 10 0 2 0 0 300 0 0 0 100 2 0 0 7 126 21 78 0 0 1 0 1391 0 0 0 99 3 0 0 28 144 35 78 0 2 2 0 0 0 1 0 99 4 0 0 4 278 103 4 0 0 0 0 1 0 0 0 100 5 0 0 448 16 3 8 0 0 2 0 594 0 1 0 99 6 0 0 14 73 1 2 0 0 0 0 266 0 0 0 100 7 0 0 0 73 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 110 0 0 0 0 2 0 0 0 100 1 0 0 0 16 2 10 0 0 0 0 300 0 0 0 100 2 0 0 7 14 3 40 2 1 0 0 1391 0 0 0 100 3 0 0 0 116 54 112 0 0 0 0 1 0 0 0 100 4 0 0 4 217 103 18 0 1 0 0 9 0 0 0 100 5 0 0 0 22 10 14 0 0 1 0 606 0 0 0 100 6 0 0 14 13 3 10 0 0 0 0 273 0 0 0 100 7 0 0 0 9 0 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2778 216 1124 2 148 1533 6 1 0 4 0 96 1 0 0 0 253 2 565 1 137 1706 1 321 0 4 0 96 2 0 0 7 229 5 534 3 122 1427 0 1391 0 4 0 96 3 0 0 0 562 288 625 2 141 1566 1 0 0 4 0 96 4 0 0 3 418 102 500 0 144 1417 1 0 0 4 0 96 5 0 0 0 219 3 481 1 112 1535 1 595 0 4 0 96 6 0 0 14 218 1 526 0 152 1649 2 266 0 4 0 96 7 0 0 0 215 0 479 2 104 1557 5 0 0 4 0 96 March 2, 2026 at 06:54:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2365 251 206 0 0 0 0 2 0 1 0 99 1 0 0 0 16 1 10 0 0 0 0 300 0 0 0 100 2 0 0 7 21 6 46 1 1 1 0 1393 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 0 0 0 0 100 4 0 0 4 212 102 6 0 0 0 0 0 0 0 0 100 5 0 0 11 15 4 10 6 1 0 0 594 0 1 0 99 6 0 0 14 6 1 2 1 0 0 0 266 0 0 0 100 7 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 501 0 16 2530 202 441 6 61 142 31 4587 6 4 0 90 1 988 0 17 469 4 957 6 119 103 32 3611 5 2 0 93 2 1496 0 17 500 10 962 7 87 61 19 4880 5 2 0 93 3 396 0 8 602 47 1135 3 122 78 18 3166 3 2 0 94 4 13427 0 146 670 105 996 7 96 132 35 4870 10 6 0 84 5 531 0 9 219 12 382 10 65 137 36 4124 6 3 0 91 6 2388 0 41 583 1 1270 4 128 96 42 4277 6 3 0 90 7 582 0 5 287 1 559 7 77 116 42 4403 7 3 0 90 March 2, 2026 at 06:54:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 106 0 0 0 0 2 0 0 0 100 1 0 0 0 20 1 15 0 1 0 0 300 0 0 0 100 2 40 0 7 30 10 54 2 1 0 0 1393 0 0 0 99 3 0 0 7 111 52 108 0 1 0 0 0 0 0 0 100 4 0 0 4 210 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 13 3 6 0 0 0 0 595 0 0 0 100 6 0 0 14 8 2 4 0 0 0 0 266 0 0 0 100 7 0 0 0 8 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:54:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2320 200 106 0 0 0 0 0 0 1 0 99 1 0 0 112 18 1 13 1 0 0 0 300 0 0 0 100 2 0 0 7 45 10 52 1 1 1 0 1390 0 0 0 100 3 0 0 0 129 52 110 0 0 0 0 0 0 0 0 100 4 1 0 4 230 104 10 0 1 0 0 13 0 0 0 100 5 0 0 0 45 15 14 0 0 0 0 601 0 0 0 100 6 0 0 14 31 2 16 0 1 0 0 279 0 0 0 100 7 0 0 0 29 0 14 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:55:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2483 202 464 2 93 1731 0 2 0 4 0 96 1 0 0 7 183 1 414 2 114 1611 0 300 0 3 0 97 2 0 0 7 196 10 452 2 90 1699 0 1390 0 3 0 96 3 0 0 0 472 229 517 1 108 1723 0 0 0 3 0 97 4 0 0 4 445 118 519 4 128 1724 0 1 0 2 0 98 5 0 0 0 392 9 833 2 112 1569 0 593 0 2 0 98 6 0 0 14 190 4 426 4 103 1550 0 273 0 3 0 97 7 0 0 0 186 0 407 3 89 1617 0 0 0 3 0 97 March 2, 2026 at 06:55:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 7 2608 201 670 5 23 9 0 1134 3 1 0 96 1 96 0 0 126 33 131 8 5 40 0 3343 5 2 0 93 2 16 0 7 316 10 594 5 21 19 0 2735 3 1 0 96 3 14 0 0 365 4 662 6 28 22 0 1288 2 1 0 97 4 62 0 133 261 120 50 4 3 33 0 2968 5 2 0 93 5 18 0 0 234 5 397 5 23 29 0 1559 3 1 0 96 6 2 0 14 327 8 593 7 25 16 0 1441 2 1 0 98 7 4 0 0 267 4 503 3 14 15 0 1213 1 1 0 98 March 2, 2026 at 06:55:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 106 0 1 0 0 2 0 0 0 100 1 0 0 0 107 51 102 0 0 0 0 300 0 0 0 100 2 0 0 7 25 4 48 2 0 1 0 1383 0 0 0 100 3 0 0 0 13 3 10 0 1 0 0 1 0 0 0 100 4 0 0 4 211 103 2 0 0 0 0 0 0 0 0 100 5 0 0 0 16 3 16 0 1 0 0 593 0 0 0 100 6 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 7 0 0 0 19 6 14 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:55:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 104 0 0 0 0 0 0 0 0 100 1 0 0 0 108 51 102 0 0 0 0 300 0 0 0 100 2 0 0 7 23 3 48 1 0 2 0 1385 0 0 0 100 3 0 0 0 12 3 8 0 0 0 0 0 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 1 0 0 0 100 5 0 0 0 17 5 12 0 1 0 0 597 0 0 0 100 6 0 0 14 12 2 14 0 1 0 0 266 0 0 0 100 7 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:55:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 106 0 0 0 0 2 0 0 0 100 1 0 0 0 109 51 104 0 0 0 0 300 0 0 0 100 2 0 0 7 22 3 48 0 0 1 0 1383 0 0 0 100 3 0 0 0 15 4 12 0 0 0 0 1 0 0 0 100 4 0 0 4 211 103 6 0 0 0 0 9 0 0 0 100 5 0 0 0 23 9 16 1 0 0 0 604 0 0 0 100 6 0 0 14 15 4 12 0 0 0 0 273 0 0 0 100 7 0 0 0 20 6 16 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:55:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2447 201 387 1 57 1214 0 76 0 3 0 97 1 0 0 0 213 36 375 2 74 1049 0 300 0 2 0 98 2 0 0 7 224 22 450 4 86 1208 0 1397 0 2 0 98 3 0 0 0 301 150 312 3 68 1177 1 0 0 3 0 97 4 0 0 4 348 103 317 2 77 1157 0 0 0 2 0 98 5 0 0 0 298 6 650 0 89 1108 0 610 0 2 0 98 6 0 0 14 148 2 310 2 71 1212 1 284 0 2 0 98 7 0 0 0 157 6 314 2 69 1044 0 18 0 2 0 98 March 2, 2026 at 06:55:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 201 112 0 1 1 0 2 0 1 0 99 1 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 2 0 0 7 60 21 84 1 1 0 0 1393 0 0 0 99 3 0 0 0 92 41 90 0 1 0 0 1 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 15 5 10 0 0 0 0 596 0 0 0 100 6 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 7 0 0 0 7 0 2 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:55:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 102 0 0 0 0 0 0 1 0 99 1 0 0 0 9 2 4 0 0 0 0 301 0 0 0 100 2 0 0 7 35 9 60 1 0 0 0 1395 0 0 0 99 3 0 0 0 112 53 108 0 0 0 0 1 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 19 7 14 0 0 0 0 600 0 0 0 100 6 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 108 0 0 0 0 2 0 0 0 100 1 0 0 0 12 1 12 0 1 0 0 300 0 0 0 100 2 0 0 7 36 9 60 2 0 1 0 1392 0 0 0 99 3 0 0 0 110 52 106 0 0 0 0 0 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 18 6 12 1 0 0 0 595 0 0 0 100 6 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 201 112 0 0 0 0 98 0 0 0 100 1 0 0 0 11 1 6 0 1 1 0 300 0 0 0 100 2 0 0 7 40 7 72 1 1 0 0 1393 0 0 0 100 3 0 0 0 111 52 108 0 0 0 0 0 0 0 0 100 4 0 0 4 209 102 4 0 0 0 0 7 0 0 0 100 5 0 0 0 34 14 29 0 0 3 0 593 0 0 0 100 6 0 0 14 12 2 9 0 1 0 0 308 0 0 0 100 7 0 0 0 22 5 20 0 0 0 0 10 0 0 0 100 March 2, 2026 at 06:55:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 201 106 0 0 0 0 2 0 1 0 99 1 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 2 0 0 7 26 4 52 2 0 1 0 1384 0 0 0 100 3 0 0 0 110 52 106 0 0 0 0 0 0 0 0 100 4 0 0 4 208 102 2 0 0 2 0 0 0 0 0 100 5 0 0 0 14 3 12 0 0 2 0 300 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 561 0 0 0 100 7 0 0 0 18 6 14 0 0 3 0 9 0 0 0 100 March 2, 2026 at 06:55:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 29 0 5 2340 200 156 0 16 8 7 168 0 1 0 99 1 8 0 0 45 2 48 0 10 5 3 442 0 0 0 100 2 28 0 7 58 4 85 1 8 5 7 1544 0 0 0 99 3 17 0 0 150 53 153 0 9 4 2 93 0 0 0 100 4 825 0 4 237 103 27 2 8 8 3 6503 2 1 0 97 5 28 0 0 47 8 34 0 5 2 3 340 0 0 0 100 6 2669 0 128 30 4 66 2 5 11 14 968 1 1 0 98 7 112 0 0 65 7 83 0 13 12 17 153 0 0 0 100 March 2, 2026 at 06:55:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 106 0 0 0 0 2 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 2 0 0 7 23 3 48 1 0 1 0 1464 0 0 0 100 3 0 0 0 119 53 118 0 0 0 0 1 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 18 6 12 1 0 0 0 303 0 0 0 100 6 0 0 14 9 3 6 0 0 0 0 559 0 0 0 100 7 0 0 0 17 6 12 0 0 0 0 10 0 0 0 100 March 2, 2026 at 06:55:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 58 0 3 5005 203 5614 43 208 105 0 12830 13 9 0 79 1 35 0 0 2471 9 4978 42 224 69 0 11764 10 7 0 84 2 363 0 0 2492 5 5661 34 145 77 0 19651 12 8 0 80 3 95 0 0 2328 26 4811 29 171 59 0 11746 12 6 0 81 4 33 0 3 1608 116 2824 16 139 65 0 7293 5 4 0 91 5 538 0 0 1473 8 3237 17 101 89 0 10360 9 6 0 85 6 344 0 0 1713 7 3662 8 122 91 1 9203 8 6 0 86 7 132 0 21 1231 17 2538 14 70 44 0 6932 5 4 0 91 March 2, 2026 at 06:55:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 27 0 3 6717 207 9461 43 310 126 0 24483 23 16 0 62 1 21 0 0 5003 10 10471 84 372 93 0 24389 21 15 0 64 2 16 0 0 3509 12 7056 28 237 103 0 17876 16 11 0 73 3 17 0 0 4162 15 8724 47 312 141 0 19601 16 12 0 72 4 8 0 3 2858 121 5334 40 245 49 0 11510 11 7 0 82 5 6 0 0 2153 18 4380 24 142 96 0 10877 10 6 0 84 6 31 0 0 3545 11 7329 30 219 105 0 14226 12 9 0 79 7 13 0 21 2063 15 4389 26 122 127 0 12991 11 7 0 81 March 2, 2026 at 06:55:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 3 7144 205 10046 90 446 589 0 24355 23 17 0 60 1 21 0 0 4907 11 10096 88 508 696 0 21833 20 14 0 66 2 15 0 0 3851 15 7779 63 370 571 0 18541 16 12 0 72 3 8 0 0 4366 124 8942 80 437 576 0 19000 15 13 0 73 4 22 0 209 2732 109 5188 43 333 647 0 13001 11 9 0 80 5 10 0 0 2107 10 4447 36 229 678 0 12369 11 8 0 81 6 17 0 0 3215 14 6739 51 358 639 0 14635 13 10 0 77 7 17 0 21 2536 10 5265 28 206 543 0 12334 11 8 0 81 March 2, 2026 at 06:55:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 18 0 3 4607 203 4955 38 217 89 0 14180 14 9 0 77 1 22 0 23 2844 11 5788 34 249 62 0 13463 13 8 0 79 2 11 0 0 2199 13 4546 29 159 94 0 10092 9 6 0 84 3 7 0 0 2692 8 5596 28 199 77 0 12088 10 7 0 83 4 8 0 4 2103 110 4044 25 160 74 0 11075 9 6 0 85 5 8 0 0 1772 9 3586 17 103 60 0 8914 8 5 0 87 6 12 0 7 2180 32 4482 18 156 77 0 9939 8 6 0 87 7 7 0 14 1200 11 2378 11 72 59 0 5515 5 3 0 92 March 2, 2026 at 06:55:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 100 0 0 0 0 0 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 27 9 22 0 2 0 0 8 0 0 0 100 3 0 0 0 11 1 6 0 1 0 0 0 0 0 0 100 4 0 0 4 216 105 38 1 0 0 0 1515 0 0 0 100 5 0 0 0 12 1 12 0 1 0 0 300 0 0 0 100 6 2 0 7 114 55 110 0 0 0 0 262 0 0 0 100 7 0 0 14 16 2 12 0 0 0 0 561 0 0 0 100 March 2, 2026 at 06:55:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 102 0 0 0 0 0 0 1 0 99 1 0 0 0 11 2 4 0 0 0 0 3 0 0 0 100 2 0 0 0 20 5 16 0 2 0 0 19 0 0 0 100 3 0 0 0 11 1 12 0 2 1 0 7 0 0 0 100 4 0 0 4 217 105 40 2 0 1 0 1522 0 0 0 100 5 0 0 0 11 1 6 1 1 1 0 303 0 0 0 100 6 0 0 7 128 58 130 1 1 0 0 270 0 0 0 100 7 0 0 14 16 2 14 0 0 0 0 562 0 0 0 100 March 2, 2026 at 06:55:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 61 0 17 2686 201 953 91 182 35 0 3263 5 3 0 93 1 12 0 0 240 1 483 30 99 28 0 3196 5 2 0 93 2 13 0 0 337 4 668 56 135 213 0 3500 5 2 0 93 3 1 0 0 355 2 752 48 137 56 0 3450 4 1 0 94 4 2 0 139 521 106 719 45 142 46 0 3738 5 2 0 93 5 26 0 0 303 8 589 37 101 54 0 3327 6 2 0 92 6 2 0 14 265 29 480 25 70 209 0 4322 5 2 0 93 7 34 0 14 251 29 424 32 64 84 0 3833 6 2 0 93 March 2, 2026 at 06:55:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2472 201 461 2 117 1752 0 1 0 4 0 96 1 0 0 7 198 2 454 4 114 1742 0 2 0 3 0 97 2 0 0 0 190 8 413 1 93 1818 0 10 0 4 0 96 3 0 0 0 382 188 803 2 123 1688 0 0 0 3 0 97 4 0 0 4 373 106 376 3 112 1705 0 300 0 4 0 96 5 0 0 0 181 1 379 4 94 1666 0 300 0 4 0 96 6 0 0 7 201 8 438 4 93 1735 0 1392 0 4 0 96 7 0 0 14 266 43 492 8 84 1662 1 559 0 4 0 96 March 2, 2026 at 06:55:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 119 2310 202 115 0 1 0 0 5 0 1 0 99 1 0 0 0 32 1 12 0 2 1 0 0 0 0 0 100 2 0 0 0 42 8 16 0 1 1 0 6 0 0 0 100 3 0 0 0 31 3 8 0 1 1 0 0 0 0 0 100 4 0 0 7 229 104 4 0 0 1 0 300 0 0 0 100 5 0 0 0 29 3 4 0 0 1 0 301 0 0 0 100 6 0 0 7 33 5 40 1 0 1 0 1393 0 0 0 100 7 0 0 14 134 53 112 0 2 1 0 561 0 0 0 100 March 2, 2026 at 06:55:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2304 200 110 0 0 0 0 0 0 1 0 99 1 0 0 0 9 1 4 0 1 0 0 2 0 0 0 100 2 0 0 0 24 8 18 0 0 0 0 10 0 0 0 100 3 0 0 0 15 3 8 0 0 0 0 1 0 0 0 100 4 0 0 4 213 104 4 1 0 0 0 300 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 6 0 0 7 14 4 38 1 0 0 0 1392 0 0 0 100 7 0 0 14 110 52 106 0 0 0 0 559 0 0 0 100 March 2, 2026 at 06:55:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 3 2476 203 386 6 16 223 0 1761 4 2 0 95 1 8 0 0 396 2 795 16 36 21 0 1854 3 1 0 96 2 2 0 0 349 12 654 4 19 27 0 2168 3 1 0 96 3 0 0 0 220 3 376 5 22 21 0 1877 4 1 0 94 4 17 0 130 249 105 70 5 13 226 0 3218 5 2 0 93 5 0 0 0 290 2 528 2 14 25 0 1756 2 1 0 97 6 0 0 7 333 26 618 5 16 14 0 2669 1 1 0 98 7 3 0 14 230 29 381 5 11 21 0 2357 3 1 0 96 March 2, 2026 at 06:55:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 206 122 0 0 0 0 9 0 1 0 99 1 0 0 0 13 3 6 0 1 0 0 2 0 0 0 100 2 0 0 0 17 2 16 0 1 0 0 13 0 0 0 100 3 0 0 0 22 3 24 0 1 0 0 6 0 0 0 100 4 0 0 4 221 108 16 0 0 0 0 312 0 0 0 100 5 0 0 0 16 6 4 1 1 0 0 301 0 0 0 100 6 0 0 7 113 54 138 1 0 0 0 1392 0 0 0 100 7 0 0 14 13 2 10 0 1 0 0 560 0 0 0 100 March 2, 2026 at 06:55:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2449 207 404 1 71 1206 0 7 0 3 0 97 1 0 0 0 162 1 353 1 81 1161 0 0 0 2 0 98 2 0 0 0 139 1 299 1 60 1075 0 1 0 2 0 98 3 0 0 0 330 156 363 0 96 1244 1 0 0 2 0 98 4 0 0 4 347 106 317 1 77 1157 0 305 0 2 0 98 5 0 0 0 132 1 270 2 67 1070 0 300 0 2 0 98 6 0 0 7 404 54 757 1 84 932 0 1393 0 2 0 98 7 0 0 14 141 4 295 1 60 1018 1 560 0 2 0 98 March 2, 2026 at 06:55:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2316 206 120 0 0 0 0 9 0 0 0 99 1 0 0 0 11 2 6 0 0 0 0 2 0 0 0 100 2 0 0 0 11 1 6 0 1 0 0 1 0 0 0 100 3 0 0 0 14 1 10 0 1 0 0 0 0 0 0 100 4 0 0 4 217 104 14 1 1 0 0 300 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 6 0 0 7 62 28 84 2 0 0 0 1391 0 0 0 100 7 0 0 14 63 29 60 0 1 0 0 560 0 0 0 100 March 2, 2026 at 06:55:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 208 128 0 1 0 0 19 0 0 0 99 1 0 0 0 12 2 6 0 0 0 0 1 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 12 1 10 0 0 0 0 75 0 0 0 100 4 0 0 4 217 106 10 0 1 0 0 305 0 0 0 100 5 0 0 0 14 1 17 0 2 0 0 307 0 0 0 100 6 0 0 7 19 6 46 0 1 0 0 1401 0 0 0 100 7 0 0 14 111 53 108 0 0 0 0 561 0 0 0 100 March 2, 2026 at 06:55:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2316 205 118 0 0 0 0 9 0 0 0 100 1 0 0 0 11 2 6 0 0 0 0 2 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 4 0 0 4 211 104 4 0 0 0 0 300 0 0 0 100 5 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 6 0 0 7 15 5 40 1 0 0 0 1392 0 0 0 100 7 0 0 14 109 53 106 0 0 0 0 559 0 0 0 100 March 2, 2026 at 06:55:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 3 2354 208 166 0 10 9 7 56 0 1 0 99 1 733 0 113 30 1 50 0 8 13 7 139 0 0 0 99 2 145 0 0 56 2 76 0 6 9 15 124 0 0 0 100 3 14 0 2 42 2 47 0 6 7 7 111 0 0 0 100 4 796 0 4 246 104 47 2 8 5 8 6877 2 1 0 97 5 13 0 0 48 6 45 0 10 9 4 457 0 0 0 100 6 6 0 7 102 29 145 4 10 3 8 1484 0 0 0 100 7 1892 0 14 101 29 104 2 7 6 6 923 0 1 0 99 March 2, 2026 at 06:55:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 206 120 0 0 0 0 9 0 1 0 99 1 0 0 0 11 2 6 0 0 0 0 2 0 0 0 100 2 0 0 0 9 0 6 0 0 0 0 0 0 0 0 100 3 0 0 0 11 1 8 0 0 0 0 0 0 0 0 100 4 0 0 4 215 105 8 1 0 1 0 300 0 0 0 100 5 0 0 0 8 1 4 0 0 2 0 300 0 0 0 100 6 0 0 7 116 54 142 2 0 2 0 1475 0 0 0 100 7 0 0 14 15 3 18 0 2 1 0 559 0 0 0 100 March 2, 2026 at 06:55:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 101 0 7 4128 208 3954 37 153 80 0 9340 9 6 0 85 1 472 0 0 1919 4 3909 24 146 59 0 8947 7 5 0 88 2 14 0 27 1403 2 2922 22 90 51 0 7127 6 4 0 90 3 85 0 0 1178 6 2437 36 105 60 0 8074 9 4 0 87 4 21 0 7 1105 105 1858 18 114 77 0 5813 5 3 0 92 5 139 0 0 1281 5 3227 12 57 25 0 12525 5 3 0 91 6 15 0 7 1310 45 2691 15 99 41 0 8235 6 4 0 91 7 186 0 14 1035 6 2161 14 56 39 0 6880 6 4 0 90 March 2, 2026 at 06:55:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 2 6877 207 9823 71 380 114 0 27501 24 16 0 59 1 15 0 0 5204 14 10684 71 411 111 0 21664 19 13 0 68 2 14 0 0 3847 17 7988 49 258 152 0 19292 17 11 0 72 3 17 0 0 4463 9 9323 66 320 67 0 21083 17 12 0 71 4 9 0 5 2712 124 4975 35 243 69 0 12025 12 7 0 81 5 9 0 0 2084 12 4424 26 140 117 0 12833 11 7 0 82 6 13 0 0 2992 8 6333 50 242 117 0 16416 13 9 0 78 7 14 0 21 2060 11 4268 23 125 44 0 11202 9 6 0 85 March 2, 2026 at 06:55:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 3 7064 203 10203 52 345 140 0 26959 24 16 0 60 1 10 0 0 5063 15 10543 57 396 105 0 22709 20 13 0 67 2 4 0 0 3688 12 7619 45 259 97 0 17847 16 11 0 74 3 10 0 0 4101 11 8558 58 304 82 0 20828 17 12 0 71 4 1 0 3 2769 117 5158 34 250 107 0 11913 12 7 0 81 5 6 0 0 2318 9 4899 25 155 89 0 11154 10 7 0 83 6 11 0 0 3104 14 6567 35 209 74 0 17049 14 9 0 76 7 5 0 21 2229 16 4555 15 108 67 0 13198 9 7 0 84 March 2, 2026 at 06:55:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 5079 205 5910 34 221 94 0 16426 16 10 0 74 1 0 0 0 3179 29 6458 32 252 59 0 14113 13 8 0 79 2 0 0 0 2251 7 4688 18 148 62 0 12380 11 7 0 82 3 4 0 0 2873 11 5872 36 186 52 0 12183 9 7 0 85 4 3 0 4 1767 112 3401 13 143 56 0 8543 8 5 0 87 5 0 0 0 1367 12 2859 11 86 62 0 8178 8 5 0 87 6 0 0 0 1774 10 3809 10 143 50 0 10137 8 6 0 87 7 0 0 21 1731 25 3490 19 90 38 0 8789 6 4 0 90 March 2, 2026 at 06:55:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2550 200 616 2 73 825 0 0 0 2 0 98 1 0 0 0 227 42 396 0 86 951 0 0 0 2 0 98 2 0 0 0 162 10 294 0 62 718 0 22 0 2 0 98 3 0 0 0 271 139 272 2 51 864 0 300 0 2 0 98 4 0 0 4 345 110 289 2 68 784 0 9 0 2 0 98 5 0 0 0 127 0 270 1 55 945 0 0 0 2 0 98 6 0 0 0 134 1 274 1 65 861 0 18 0 2 0 98 7 0 0 21 118 7 282 1 64 860 0 2339 0 2 0 98 March 2, 2026 at 06:55:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 3 2537 200 529 43 96 177 0 2890 7 2 0 90 1 12 0 21 428 3 908 69 194 41 1 3971 5 2 0 93 2 11 0 0 385 33 680 54 118 110 0 3415 5 2 0 93 3 4 0 21 398 5 730 58 146 45 0 3660 5 2 0 94 4 29 0 144 396 110 341 34 69 189 0 3529 6 2 0 92 5 3 0 0 286 17 494 29 79 45 0 2794 5 2 0 93 6 7 0 0 343 1 697 37 123 136 1 3485 5 2 0 93 7 43 0 13 369 6 775 52 152 47 0 5034 4 2 0 93 March 2, 2026 at 06:55:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 108 0 0 0 0 0 0 1 0 99 1 0 0 7 15 4 11 0 1 0 0 262 0 0 0 100 2 0 0 0 22 6 14 0 0 0 0 6 0 0 0 100 3 1 0 14 17 5 14 0 0 0 0 567 0 0 0 100 4 0 0 11 210 103 4 0 1 0 0 0 0 0 0 100 5 0 0 0 106 50 100 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 6 1 0 0 0 2 0 0 0 100 7 0 0 0 17 4 40 1 1 0 0 1727 0 0 0 100 March 2, 2026 at 06:55:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2325 200 118 0 1 0 0 0 0 1 0 99 1 0 0 119 13 3 9 1 1 0 0 262 0 0 0 100 2 0 0 0 38 7 16 0 0 0 0 10 0 0 0 100 3 0 0 14 30 5 12 0 0 0 0 566 0 0 0 100 4 0 0 4 227 103 4 0 0 0 0 0 0 0 0 100 5 0 0 0 122 50 102 0 1 0 0 0 0 0 0 100 6 0 0 0 27 3 6 0 0 0 0 5 0 0 0 100 7 0 0 0 32 3 40 1 1 1 0 1725 0 0 0 100 March 2, 2026 at 06:55:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2310 200 118 2 1 0 0 10 0 0 0 100 1 0 0 14 16 2 18 0 1 0 0 260 0 0 0 100 2 0 0 1 22 6 16 0 1 0 0 9 0 0 0 100 3 0 0 18 19 5 16 0 0 0 0 567 0 0 0 100 4 0 0 4 213 103 4 0 1 0 0 4 0 0 0 100 5 0 0 0 116 56 104 0 0 1 0 5 0 0 0 100 6 0 0 0 10 1 6 0 1 0 0 4 0 0 0 100 7 0 0 0 24 5 50 1 0 1 0 1727 0 0 0 100 March 2, 2026 at 06:55:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 3 2728 201 950 59 152 1605 0 1530 4 5 0 92 1 0 0 7 413 4 825 47 124 1462 0 2375 4 4 0 92 2 14 0 0 384 7 831 53 150 1675 1 1695 4 3 0 93 3 0 0 14 587 192 865 38 149 1859 0 2268 3 4 0 93 4 5 0 144 591 104 885 52 183 1800 0 1468 2 4 0 93 5 1 0 0 352 39 639 22 108 1561 1 1567 3 4 0 93 6 2 0 0 306 4 628 49 118 1729 0 2643 4 4 0 92 7 0 0 0 375 4 815 38 131 1509 1 3086 3 4 0 93 March 2, 2026 at 06:55:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 106 0 2 1 0 1 0 0 0 100 1 0 0 7 16 5 8 0 0 1 0 261 0 0 0 100 2 0 0 0 16 2 10 0 1 1 0 0 0 0 0 100 3 0 0 14 120 55 116 0 1 0 0 565 0 0 0 100 4 0 0 4 219 108 12 0 0 1 0 9 0 0 0 100 5 0 0 0 9 1 0 0 0 1 0 0 0 0 0 100 6 0 0 0 15 5 6 0 0 1 0 1 0 0 0 100 7 0 0 0 16 4 38 1 0 1 0 1723 0 0 0 100 March 2, 2026 at 06:55:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 784 0 3 2342 200 110 3 9 2 3 6508 2 1 0 97 1 20 0 7 103 20 106 1 11 4 4 375 0 0 0 100 2 1890 0 0 44 0 44 2 11 5 1 397 0 1 0 99 3 752 0 128 114 41 165 0 16 9 10 797 0 1 0 99 4 91 0 4 262 110 68 0 7 6 14 106 0 0 0 100 5 25 0 2 39 0 39 0 10 6 3 95 0 0 0 100 6 12 0 0 37 2 28 0 5 4 0 95 0 0 0 100 7 44 0 0 41 4 64 1 8 4 3 1795 0 0 0 100 March 2, 2026 at 06:55:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 84 0 2 0 0 0 0 0 0 100 1 0 0 7 135 52 128 0 0 0 0 260 0 0 0 100 2 0 0 0 12 1 8 0 1 0 0 6 0 0 0 100 3 0 0 14 17 5 14 1 0 0 0 568 0 0 0 100 4 0 0 4 220 108 14 0 0 0 0 9 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 7 0 0 0 14 3 38 1 0 1 0 1809 0 0 0 100 March 2, 2026 at 06:55:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 2954 204 1538 23 69 36 1 3680 3 3 0 94 1 28 0 7 804 46 1515 15 70 17 0 3436 3 2 0 95 2 154 0 0 412 0 801 9 31 30 0 4088 7 2 0 92 3 112 0 14 1066 8 2430 9 55 16 0 7153 4 3 0 94 4 521 0 4 568 114 683 7 42 27 0 3013 2 1 0 96 5 38 0 0 726 7 1794 11 34 24 0 8461 4 2 0 94 6 1 0 0 493 3 1037 7 42 23 0 2736 2 2 0 96 7 4 0 0 247 3 527 6 24 11 0 3584 1 1 0 97 March 2, 2026 at 06:55:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 20 0 3 6794 205 9497 136 547 1227 0 23515 23 17 0 60 1 8 0 0 4750 24 9955 151 601 1604 0 23179 20 16 0 65 2 35 0 7 4080 15 8403 143 450 1445 0 19804 16 13 0 71 3 6 0 0 4552 210 9118 119 510 1503 0 20737 17 14 0 69 4 11 0 18 3114 112 6026 80 436 1432 0 13467 13 11 0 76 5 5 0 1 2376 4 5043 50 302 1646 0 12434 11 10 0 79 6 7 0 0 3043 12 6590 96 398 1573 0 15209 13 10 0 77 7 4 0 0 2097 9 4428 46 258 1477 0 11582 9 9 0 82 March 2, 2026 at 06:55:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 3 6694 204 9304 65 362 116 0 26055 24 16 0 60 1 7 0 14 4740 23 9584 56 421 79 0 22281 19 12 0 69 2 6 0 0 3907 9 8139 71 288 126 0 19538 18 11 0 71 3 6 0 7 4305 12 9188 48 340 101 0 23770 19 13 0 69 4 6 0 4 3347 113 6457 28 248 113 0 15356 14 9 0 77 5 5 0 0 2203 12 4645 21 150 94 0 11481 11 7 0 83 6 2 0 0 2839 9 5887 38 212 90 0 13063 11 7 0 82 7 3 0 0 2123 16 4388 30 128 67 0 11848 10 6 0 84 March 2, 2026 at 06:55:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 3 5966 213 7652 59 324 126 0 18936 19 12 0 69 1 5 0 14 3854 11 7997 56 327 72 0 20304 16 11 0 73 2 3 0 0 2909 7 5854 33 197 108 0 15171 12 8 0 80 3 12 0 0 3475 28 7266 43 258 94 0 17066 14 10 0 76 4 25 0 11 2578 110 4947 29 206 110 0 12344 12 7 0 81 5 10 0 0 2332 6 4913 10 122 76 0 13936 13 8 0 79 6 2 0 0 2784 19 5953 27 195 155 0 13790 12 8 0 80 7 4 0 0 1726 6 3574 13 103 77 0 8862 8 5 0 87 March 2, 2026 at 06:55:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 61 0 3 2655 202 779 89 171 60 0 3170 5 2 0 93 1 50 0 14 362 5 737 85 157 71 0 5413 5 2 0 92 2 3 0 0 397 5 767 85 165 81 0 3514 4 2 0 94 3 0 0 0 423 42 735 71 112 83 1 3260 5 2 0 94 4 2 0 160 525 113 618 54 109 71 0 3404 5 3 0 92 5 1 0 0 203 3 340 40 67 68 0 3146 8 2 0 90 6 4 0 21 279 1 549 73 103 102 0 3255 5 2 0 93 7 0 0 0 346 3 615 57 112 96 0 3654 5 2 0 94 March 2, 2026 at 06:55:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 201 116 2 1 1 0 13 0 0 0 99 1 4 0 14 15 4 40 1 1 2 0 1703 0 0 0 100 2 0 0 0 127 59 122 0 0 0 0 306 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 4 0 0 11 216 105 8 0 1 0 0 260 0 0 0 100 5 0 0 0 23 10 12 0 0 1 0 313 0 0 0 100 6 0 0 0 26 3 23 0 1 0 0 7 0 0 0 100 7 0 0 7 20 3 20 0 2 0 0 8 0 0 0 100 March 2, 2026 at 06:55:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2550 212 585 2 115 1948 0 0 0 4 0 96 1 0 0 14 253 5 556 2 144 2117 0 1695 0 4 0 96 2 0 0 0 323 42 572 5 108 1795 0 303 0 4 0 96 3 0 0 0 483 247 490 1 118 1771 1 0 0 4 0 96 4 0 0 10 454 104 516 3 134 2221 0 260 0 4 0 96 5 0 0 0 245 3 480 4 101 1729 0 300 0 4 0 96 6 0 0 112 242 1 546 3 130 1787 0 0 0 3 0 97 7 0 0 0 470 7 970 0 133 1663 0 2 0 3 0 97 March 2, 2026 at 06:55:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2357 250 204 0 1 1 0 1 0 0 0 100 1 0 0 14 15 5 38 0 0 2 0 1695 0 0 0 100 2 0 0 0 24 8 14 0 0 1 0 303 0 0 0 100 3 0 0 0 11 1 2 0 1 1 0 0 0 0 0 100 4 0 0 14 219 104 20 0 2 0 0 260 0 0 0 100 5 0 0 0 13 3 4 0 0 1 0 300 0 0 0 100 6 0 0 7 22 3 14 0 0 1 0 1 0 0 0 100 7 0 0 0 18 5 8 0 0 1 0 3 0 0 0 100 March 2, 2026 at 06:55:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2382 246 198 5 0 28 0 2961 5 2 0 92 1 0 0 14 90 5 145 8 4 36 0 4444 6 2 0 92 2 0 0 0 372 8 672 8 38 19 0 1907 2 1 0 97 3 0 0 0 417 1 839 12 35 25 0 2090 2 1 0 97 4 0 0 136 344 106 254 3 14 30 0 2051 3 1 0 96 5 0 0 0 182 3 310 5 14 17 0 969 2 1 0 98 6 0 0 0 357 2 679 11 31 13 0 1807 2 1 0 97 7 0 0 0 350 5 674 5 19 11 0 1185 2 1 0 98 March 2, 2026 at 06:55:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2333 214 114 0 6 0 0 37 0 0 0 99 1 0 0 14 21 4 43 2 2 0 0 1422 1 0 0 99 2 0 0 0 24 2 22 0 1 1 0 765 0 0 0 100 3 0 0 0 21 2 27 1 3 1 0 332 0 0 0 100 4 0 0 25 222 105 24 1 5 0 0 284 0 0 0 100 5 0 0 0 60 2 66 0 4 0 0 28 0 0 0 100 6 0 0 0 15 1 10 0 2 0 0 71 0 0 0 100 7 0 0 0 96 41 91 0 2 0 0 29 0 0 0 100 March 2, 2026 at 06:55:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2379 261 236 2 0 0 0 44 0 1 0 99 1 0 0 14 15 3 38 1 0 0 0 1397 0 0 0 100 2 0 0 0 13 2 6 0 0 0 0 594 0 0 0 100 3 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 4 0 0 11 222 108 16 1 0 0 0 267 0 0 0 100 5 0 0 0 17 7 8 0 0 1 0 7 0 0 0 100 6 0 0 0 22 2 24 0 3 0 0 5 0 0 0 100 7 0 0 0 13 2 10 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:55:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2511 241 473 4 75 1136 1 9 0 3 0 97 1 0 0 14 173 2 399 3 79 1189 0 1396 0 3 0 97 2 0 0 0 322 5 678 2 92 1062 0 617 0 2 0 98 3 0 0 0 345 170 398 1 87 1257 0 300 0 2 0 98 4 0 0 11 364 104 347 2 81 1351 0 260 0 3 0 97 5 0 0 0 159 13 315 3 59 1142 0 0 0 2 0 98 6 0 0 0 181 3 363 1 84 1076 0 0 0 2 0 98 7 0 0 0 147 2 309 1 74 1249 0 0 0 2 0 98 March 2, 2026 at 06:55:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 205 46 0 2 0 0 5 0 1 0 99 1 0 0 14 9 3 36 0 0 0 0 1397 0 0 0 100 2 0 0 0 18 3 12 1 1 0 0 594 0 0 0 100 3 0 0 0 11 1 4 1 0 0 0 300 0 0 0 100 4 0 0 11 217 106 12 0 0 0 0 262 0 0 0 100 5 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 6 0 0 0 86 1 78 0 0 0 0 0 0 0 0 100 7 0 0 0 16 3 16 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:55:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2330 211 84 0 3 0 0 18 0 1 0 99 1 0 0 14 64 3 88 1 2 0 0 1395 0 0 0 100 2 0 0 0 13 2 10 0 0 0 0 669 0 0 0 100 3 0 0 0 12 2 8 0 0 0 0 306 0 0 0 100 4 0 0 11 215 105 8 0 0 0 0 260 0 0 0 100 5 0 0 0 113 52 110 0 1 0 0 13 0 0 0 100 6 0 0 0 18 2 12 0 1 0 0 1 0 0 0 100 7 0 0 0 13 3 8 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:55:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2318 207 116 0 0 0 0 7 0 0 0 99 1 0 0 14 10 3 36 1 0 0 0 1398 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 594 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 11 214 104 8 1 0 0 0 260 0 0 0 100 5 0 0 0 111 53 106 0 0 0 0 2 0 0 0 100 6 0 0 0 15 1 10 0 0 0 0 0 0 0 0 100 7 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:55:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2322 207 130 1 0 0 0 27 0 0 0 99 1 0 0 14 13 2 44 1 1 1 0 1395 0 0 0 100 2 0 0 0 15 2 10 0 0 0 0 595 0 0 0 100 3 0 0 0 9 1 6 0 0 0 0 300 0 0 0 100 4 0 0 11 213 104 8 0 0 0 0 260 0 0 0 100 5 0 0 0 78 37 66 0 0 0 0 8 0 0 0 100 6 0 0 0 58 21 56 0 1 0 0 5 0 0 0 100 7 0 0 0 14 3 10 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 714 0 116 2342 207 167 1 6 11 9 152 0 1 0 99 1 113 0 14 55 3 93 1 12 10 9 1513 0 0 0 99 2 20 0 2 49 2 53 1 11 7 7 749 0 0 0 100 3 24 0 0 47 2 52 1 11 6 4 529 0 0 0 100 4 54 0 11 246 104 49 0 7 10 8 322 0 0 0 100 5 784 0 0 41 6 25 1 1 2 2 6503 2 1 0 97 6 1897 0 0 142 51 131 2 7 5 1 319 0 1 0 99 7 9 0 0 33 3 26 0 8 1 2 36 0 0 0 100 March 2, 2026 at 06:56:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 103 0 7 6574 214 8987 92 358 92 0 24522 25 15 0 60 1 34 0 0 5057 11 10667 83 379 82 0 27948 23 15 0 62 2 107 0 7 4063 23 8622 52 285 174 0 26455 19 12 0 69 3 84 0 0 3835 13 7804 74 313 132 0 19907 14 10 0 76 4 4 0 21 2963 111 5643 35 237 50 0 13320 12 8 0 80 5 23 0 0 1497 8 3032 22 138 65 0 8739 8 5 0 87 6 496 0 0 2646 12 5583 50 241 108 0 15344 12 8 0 80 7 86 0 0 2598 14 5473 41 149 112 0 12077 11 7 0 82 March 2, 2026 at 06:56:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 3 6672 207 9396 66 357 96 0 25892 23 16 0 60 1 12 0 0 4613 10 9591 58 390 81 0 26659 21 15 0 64 2 7 0 7 3873 12 7959 63 260 83 0 18639 17 11 0 72 3 5 0 0 4248 19 8810 59 312 99 0 19214 16 11 0 73 4 4 0 17 3116 113 6054 32 273 85 0 16592 15 9 0 76 5 2 0 0 1704 16 3432 19 145 47 0 8205 8 5 0 88 6 6 0 0 2990 20 6307 36 232 93 0 14562 12 8 0 79 7 5 0 0 2564 14 5456 23 139 86 0 12393 11 7 0 82 March 2, 2026 at 06:56:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 3 6384 214 8902 69 357 102 0 24978 24 16 0 61 1 9 0 0 4371 10 8909 44 367 116 0 21645 19 13 0 68 2 9 0 7 3815 18 7891 30 246 68 0 17750 16 11 0 73 3 1 0 0 4209 14 8877 52 319 64 0 20551 17 12 0 71 4 2 0 17 2877 120 5595 30 244 84 0 14001 12 8 0 80 5 7 0 0 2132 7 4559 17 146 115 0 14443 13 8 0 79 6 4 0 0 3062 11 6437 34 224 76 0 16614 14 9 0 78 7 2 0 0 2550 14 5272 22 148 55 0 10040 8 6 0 86 March 2, 2026 at 06:56:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2420 201 349 2 11 2 0 455 0 1 0 99 1 1 0 0 108 3 188 1 15 3 0 366 1 0 0 99 2 8 0 7 83 5 111 3 11 2 0 636 0 0 0 99 3 0 0 0 137 2 263 4 13 2 0 626 0 0 0 99 4 0 0 18 348 156 180 2 13 0 0 786 0 0 0 99 5 0 0 0 70 9 158 4 7 2 0 986 1 0 0 99 6 7 0 0 96 9 193 4 8 2 0 2135 1 1 0 99 7 2 0 0 95 2 177 0 5 2 0 273 0 0 0 100 March 2, 2026 at 06:56:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2447 213 407 1 65 899 0 0 0 2 0 98 1 0 0 0 127 1 245 3 54 874 0 1 0 2 0 98 2 0 0 7 118 3 251 1 65 812 0 261 0 2 0 98 3 0 0 0 256 134 276 1 69 947 0 0 0 2 0 98 4 0 0 18 444 142 434 0 75 915 0 575 0 2 0 98 5 0 0 0 127 2 270 1 43 942 0 301 0 2 0 98 6 0 0 0 154 8 342 2 58 902 0 1524 0 2 0 98 7 0 0 0 177 3 351 2 55 834 0 9 0 2 0 98 March 2, 2026 at 06:56:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2357 251 208 0 0 0 0 0 0 0 0 100 1 0 0 0 14 0 14 0 2 0 0 0 0 0 0 100 2 0 0 0 15 3 8 0 1 0 0 3 0 0 0 100 3 0 0 0 13 1 8 0 2 0 0 0 0 0 0 100 4 0 0 18 210 104 4 1 0 0 0 565 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 6 0 0 0 25 9 48 1 0 0 0 1513 0 0 0 100 7 0 0 7 11 3 8 1 1 0 0 260 0 0 0 100 March 2, 2026 at 06:56:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2354 251 206 0 0 0 0 0 0 0 0 100 1 0 0 0 12 3 8 0 0 0 0 2 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 13 0 8 0 0 0 0 0 0 0 0 100 4 0 0 17 209 104 4 0 0 0 0 567 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 6 0 0 0 24 9 48 1 0 0 0 1516 0 0 0 99 7 0 0 7 12 4 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 251 206 0 0 0 0 0 0 1 0 99 1 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 2 0 0 0 14 1 14 0 1 0 0 2 0 0 0 100 3 0 0 0 13 0 8 0 0 0 0 0 0 0 0 100 4 0 0 18 209 104 4 0 0 0 0 565 0 0 0 100 5 0 0 0 10 1 4 1 0 0 0 300 0 0 0 100 6 0 0 0 23 8 46 2 0 1 0 1516 0 0 0 100 7 0 0 7 12 4 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2356 251 212 0 1 0 0 3 0 1 0 99 1 0 0 0 17 3 18 0 0 0 0 15 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 19 0 18 0 1 0 0 0 0 0 0 100 4 0 0 18 212 104 8 1 0 0 0 573 0 0 0 100 5 0 0 0 21 8 10 0 0 0 0 304 0 0 0 100 6 0 0 0 25 8 50 0 0 0 0 1522 0 0 0 99 7 0 0 7 15 4 12 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2360 251 214 0 0 1 0 0 0 1 0 99 1 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 18 213 104 10 1 0 1 0 567 0 0 0 100 5 0 0 0 12 2 8 0 0 0 0 300 0 0 0 100 6 0 0 0 25 9 50 1 0 3 0 1511 0 0 0 99 7 0 0 7 13 4 10 1 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2355 252 214 0 0 1 0 1 0 1 0 99 1 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 2 0 0 0 11 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 11 1 4 0 0 1 0 0 0 0 0 100 4 0 0 21 215 104 16 0 2 0 0 566 0 0 0 100 5 0 0 0 12 2 4 0 0 1 0 300 0 0 0 100 6 0 0 0 25 9 46 1 0 1 0 1515 0 0 0 100 7 0 0 7 17 6 10 0 0 1 0 261 0 0 0 100 March 2, 2026 at 06:56:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2358 251 212 0 0 0 0 0 0 1 0 99 1 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 18 213 105 8 0 1 0 0 567 0 0 0 100 5 0 0 0 16 1 16 1 1 0 0 300 0 0 0 100 6 0 0 0 23 8 46 2 0 1 0 1515 0 0 0 99 7 0 0 7 12 4 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 251 212 0 0 0 0 0 0 0 0 100 1 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 18 209 104 4 0 0 0 0 566 0 0 0 100 5 0 0 0 11 2 6 0 0 0 0 301 0 0 0 100 6 0 0 0 23 9 48 1 0 0 0 1513 0 0 0 100 7 0 0 7 12 4 8 0 0 0 0 260 0 0 0 100 March 2, 2026 at 06:56:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 89 0 7 6788 213 9401 75 357 125 0 24716 23 15 0 62 1 55 0 0 4940 16 10080 67 400 154 0 24152 19 13 0 68 2 22 0 0 3418 15 6921 57 260 115 0 18810 20 10 0 69 3 458 0 0 3986 16 8327 72 325 100 0 20529 16 11 0 73 4 74 0 21 2451 116 4624 38 258 122 0 12559 11 7 0 81 5 0 0 0 2470 12 5154 23 141 105 0 11834 11 7 0 82 6 48 0 0 2679 12 5903 41 246 95 0 16824 14 9 0 78 7 17 0 7 1855 16 4557 18 93 76 0 17500 10 6 0 84 March 2, 2026 at 06:56:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 3 6816 206 9604 105 447 555 0 24539 23 16 0 60 1 63 0 0 4895 12 10134 110 508 617 0 22812 19 14 0 68 2 17 0 0 4073 9 8384 56 326 564 0 21659 21 14 0 65 3 28 0 0 4181 143 8514 70 389 691 0 18456 15 11 0 73 4 8 0 4 2832 113 5416 52 344 599 0 14413 13 9 0 78 5 4 0 14 1828 11 3816 34 222 622 0 10794 9 7 0 84 6 16 0 0 3379 10 7329 133 337 585 0 14578 12 9 0 78 7 7 0 7 2365 12 5031 41 225 666 0 14000 12 9 0 80 March 2, 2026 at 06:56:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 3 6698 205 9323 48 378 146 0 24647 24 15 0 61 1 7 0 0 5010 19 10407 55 412 112 0 23072 20 13 0 67 2 5 0 0 3644 10 7656 36 237 178 0 21176 19 12 0 68 3 4 0 0 4238 19 8831 68 326 97 0 20203 16 11 0 73 4 3 0 11 2999 113 5741 33 269 148 0 14485 13 8 0 79 5 3 0 14 2071 10 4422 23 137 93 0 11761 11 7 0 82 6 3 0 0 2908 12 6089 24 243 152 0 16954 13 9 0 79 7 3 0 0 2351 12 4875 11 127 59 0 10462 9 6 0 85 March 2, 2026 at 06:56:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2477 202 432 0 15 11 0 694 1 1 0 98 1 0 0 0 169 6 316 2 12 12 0 1330 1 1 0 98 2 0 0 0 103 2 189 1 8 5 0 825 1 0 0 99 3 0 0 0 226 3 426 2 14 2 0 848 1 1 0 99 4 0 0 11 350 105 291 0 11 10 0 1477 1 1 0 98 5 0 0 14 127 3 335 2 6 7 0 1574 1 1 0 98 6 0 0 0 201 59 294 1 8 1 0 2269 0 1 0 99 7 0 0 0 371 2 742 0 2 3 0 462 1 0 0 99 March 2, 2026 at 06:56:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 110 0 2 1 0 3 0 1 0 99 1 0 0 0 10 2 6 0 0 0 0 0 0 0 0 100 2 0 0 0 19 3 14 0 0 0 0 296 0 0 0 100 3 0 0 0 10 0 10 0 1 0 0 0 0 0 0 100 4 0 0 11 220 105 10 1 1 0 0 260 0 0 0 100 5 0 0 14 8 2 6 0 0 0 0 269 0 0 0 100 6 0 0 0 132 61 154 1 1 0 0 1823 0 0 0 99 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 118 0 0 1 0 8 0 1 0 99 1 0 0 0 25 8 24 0 0 0 0 16 0 0 0 100 2 0 0 0 12 2 8 0 0 1 0 297 0 0 0 100 3 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 4 0 0 11 215 105 14 0 0 0 0 276 0 0 0 100 5 0 0 14 14 7 4 0 0 0 0 269 0 0 0 100 6 0 0 0 126 56 158 1 0 0 0 1848 0 0 0 99 7 0 0 0 12 0 12 0 0 0 0 9 0 0 0 100 March 2, 2026 at 06:56:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2404 201 303 1 49 439 0 0 0 2 0 98 1 0 0 0 157 8 310 1 50 464 0 9 0 1 0 99 2 0 0 0 115 3 227 1 39 513 0 296 0 1 0 99 3 0 0 0 230 106 238 0 44 452 0 0 0 1 0 99 4 0 0 11 314 106 224 1 49 473 0 260 0 1 0 99 5 0 0 14 102 1 207 2 40 383 0 266 0 1 0 99 6 0 0 0 183 38 321 2 47 513 0 1815 0 1 0 98 7 0 0 0 184 15 360 0 46 397 0 0 0 1 0 99 March 2, 2026 at 06:56:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2305 202 112 0 0 1 0 1 0 1 0 99 1 0 0 0 25 9 18 0 0 1 0 9 0 0 0 100 2 0 0 0 14 3 4 1 0 2 0 294 0 0 0 100 3 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 4 0 0 14 215 105 8 0 0 1 0 260 0 0 0 100 5 0 0 14 13 2 12 0 1 1 0 266 0 0 0 100 6 0 0 0 17 4 38 1 0 1 0 1815 0 0 0 100 7 0 0 0 110 52 104 0 1 0 0 1 0 0 0 100 March 2, 2026 at 06:56:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 110 0 0 0 0 0 0 1 0 99 1 0 0 0 23 8 19 0 1 0 0 21 0 0 0 100 2 0 0 0 13 3 7 0 0 0 0 279 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 11 215 106 8 1 0 0 0 261 0 0 0 100 5 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 6 0 0 0 17 4 40 2 0 0 0 1816 0 0 0 99 7 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 110 0 0 0 0 0 0 1 0 99 1 0 0 0 26 10 22 0 0 0 0 301 0 0 0 100 2 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 11 212 105 6 0 0 0 0 260 0 0 0 100 5 0 0 14 7 1 4 0 1 0 0 266 0 0 0 100 6 0 0 0 19 3 48 1 1 1 0 1815 0 0 0 100 7 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3673 0 7 3366 204 2007 999 101 175 11 5165 82 7 0 10 1 2352 0 0 1152 19 2160 1043 135 155 8 6999 83 7 0 11 2 8192 0 0 1034 14 2233 1009 146 222 6 7531 80 9 0 11 3 2504 0 0 1002 13 1739 859 130 192 6 6023 84 5 0 11 4 4573 0 1106 1145 113 2233 1074 128 240 10 6890 82 7 0 10 5 4001 0 14 934 10 1758 814 120 163 6 6767 83 6 0 11 6 3952 0 0 1026 12 2012 942 122 215 17 7531 83 6 0 11 7 3346 0 0 970 8 1781 864 110 146 12 5541 84 5 0 11 March 2, 2026 at 06:56:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 3 2310 203 108 0 0 8 0 8 0 1 0 99 1 1 0 0 16 3 16 0 2 2 0 302 0 0 0 100 2 0 0 0 17 2 16 0 3 0 0 10 0 0 0 100 3 0 0 0 121 56 117 0 1 1 0 14 0 0 0 100 4 8 0 10 213 105 8 0 0 0 0 269 0 0 0 100 5 4 0 14 14 2 11 0 5 2 0 302 0 0 0 100 6 0 0 0 24 3 53 1 4 2 0 1830 0 0 0 100 7 0 0 0 9 0 2 0 0 3 0 0 0 0 0 100 March 2, 2026 at 06:56:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 201 120 0 2 1 0 0 0 0 0 100 1 0 0 0 15 4 12 0 1 0 0 296 0 0 0 100 2 0 0 0 21 6 16 0 1 0 0 9 0 0 0 100 3 0 0 0 109 51 104 0 1 0 0 2 0 0 0 100 4 0 0 10 212 105 6 1 0 0 0 260 0 0 0 100 5 0 0 14 11 2 6 0 0 0 0 267 0 0 0 100 6 0 0 0 17 4 40 2 0 1 0 1827 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 201 114 0 0 0 0 1 0 0 0 100 1 0 0 0 21 4 24 0 2 0 0 296 0 0 0 100 2 1 0 0 25 9 18 0 0 0 0 11 0 0 0 100 3 0 0 0 107 50 102 0 1 0 0 0 0 0 0 100 4 0 0 10 212 105 6 0 0 0 0 260 0 0 0 100 5 0 0 14 10 3 6 0 0 0 0 269 0 0 0 100 6 0 0 0 18 5 42 1 1 0 0 1828 0 0 0 100 7 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 2326 201 111 8 2 265 0 3060 6 2 0 92 1 0 0 0 294 4 551 16 47 12 0 1888 3 1 0 96 2 0 0 0 374 7 723 28 54 4 0 1489 3 1 0 97 3 0 0 0 335 48 532 20 35 6 0 1163 4 1 0 95 4 0 0 108 406 105 405 14 31 175 0 1944 4 1 0 95 5 6 0 14 174 2 307 8 18 35 0 2746 5 1 0 93 6 0 0 0 356 6 700 25 42 5 0 3171 2 1 0 97 7 51 0 0 27 0 5 4 1 33 0 3043 6 2 0 92 March 2, 2026 at 06:56:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2565 201 550 5 25 43 0 2762 8 2 0 90 1 28 0 0 163 4 245 9 14 44 1 3300 5 2 0 93 2 0 0 0 318 13 533 9 27 30 0 1897 3 1 0 96 3 0 0 0 362 2 696 12 32 47 1 1946 2 1 0 97 4 3 0 173 368 150 222 5 18 25 0 2879 5 2 0 93 5 2 0 21 288 9 507 5 24 30 0 2617 9 1 0 90 6 8 0 0 307 5 578 5 22 24 0 3284 2 1 0 96 7 3 0 0 395 2 704 9 23 32 0 2527 8 1 0 91 March 2, 2026 at 06:56:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2500 214 549 3 123 1932 0 1134 0 5 0 95 1 0 0 0 205 3 465 2 132 1959 0 294 0 4 0 96 2 0 0 0 347 6 736 1 124 1877 1 9 0 4 0 96 3 0 0 0 417 197 460 5 126 1782 0 2 0 4 0 96 4 0 0 10 476 141 529 3 128 1968 0 261 0 4 0 96 5 0 0 14 265 4 593 1 130 1775 0 267 0 3 0 97 6 0 0 7 208 5 448 4 134 1865 0 599 0 3 0 97 7 0 0 0 191 0 428 2 92 1864 0 0 0 4 0 96 March 2, 2026 at 06:56:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35 0 121 2354 206 192 1 17 10 9 1334 0 1 0 99 1 15 0 0 180 51 166 0 14 7 4 433 0 0 0 100 2 10 0 0 69 8 38 0 6 4 3 91 0 0 0 100 3 19 0 0 57 1 39 0 8 3 6 83 0 0 0 100 4 65 0 14 258 105 43 0 8 3 3 346 0 0 0 100 5 1 0 14 53 4 28 0 5 3 2 347 0 0 0 100 6 2590 0 113 57 4 62 2 7 12 10 1008 1 1 0 98 7 824 0 0 64 2 56 2 10 10 13 6545 2 1 0 97 March 2, 2026 at 06:56:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2309 203 134 1 3 0 0 1217 0 1 0 99 1 0 0 0 131 55 124 0 4 1 0 294 0 0 0 100 2 0 0 0 22 6 16 1 1 1 0 6 0 0 0 100 3 0 0 0 13 1 8 0 2 1 0 2 0 0 0 100 4 0 0 11 224 107 22 0 1 0 0 261 0 0 0 100 5 0 0 14 9 2 4 0 1 0 0 266 0 0 0 100 6 0 0 0 16 3 10 1 1 0 0 600 0 0 0 100 7 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:56:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 281 0 3 5842 210 7306 64 272 122 0 19130 16 12 0 72 1 5 0 0 3358 24 6960 67 304 146 0 20748 20 11 0 70 2 56 0 0 2751 14 5600 43 206 104 0 14011 13 8 0 79 3 118 0 0 4045 13 8807 47 262 60 0 23070 13 9 0 78 4 26 0 4 2764 110 5264 27 216 70 0 12726 12 7 0 81 5 159 0 14 1543 8 3275 17 123 73 0 10248 10 6 0 84 6 21 0 7 2463 12 5335 38 206 122 0 15106 11 8 0 82 7 25 0 0 1860 4 4046 24 110 60 0 10110 10 6 0 85 March 2, 2026 at 06:56:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 3 6875 208 9642 80 421 123 0 22549 22 14 0 64 1 8 0 0 4894 13 10060 77 434 97 0 22677 19 13 0 68 2 6 0 0 3435 12 7150 56 267 123 0 19238 17 11 0 72 3 8 0 0 4845 16 9844 57 334 103 0 21826 17 12 0 71 4 8 0 4 2801 117 5300 35 262 129 0 14658 13 8 0 79 5 9 0 14 1966 21 4241 20 160 64 0 12545 12 7 0 81 6 2 0 7 3295 21 7043 34 259 97 0 19655 14 10 0 76 7 7 0 0 2203 8 4703 32 148 97 0 12035 10 7 0 83 March 2, 2026 at 06:56:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 3 6962 211 9980 137 515 810 0 23774 23 16 0 61 1 18 0 7 4995 16 10384 99 525 936 0 23661 19 14 0 67 2 24 0 0 3346 11 6859 63 344 924 0 20058 17 12 0 71 3 4 0 0 4077 140 8289 75 403 872 0 17553 15 12 0 74 4 9 0 4 2988 113 5856 54 346 873 0 15019 14 10 0 76 5 3 0 14 2518 11 5300 37 240 791 0 11758 11 8 0 81 6 5 0 0 3422 18 7128 56 339 907 0 15608 13 10 0 77 7 8 0 0 2219 14 4881 44 249 947 0 14736 13 9 0 78 March 2, 2026 at 06:56:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 3 3535 206 2601 88 231 80 0 8134 9 5 0 86 1 1 0 14 1195 41 2403 48 133 156 1 8168 10 4 0 86 2 2 0 14 925 9 1896 82 176 71 0 7068 8 4 0 89 3 2 0 0 1085 4 2215 78 182 85 0 6881 10 4 0 86 4 0 0 144 982 106 1680 89 222 66 1 6086 6 3 0 91 5 4 0 14 489 5 1025 82 154 103 2 4678 6 2 0 92 6 78 0 0 1113 6 2342 70 200 60 2 7401 8 4 0 88 7 7 0 10 448 10 846 28 102 87 3 4888 7 3 0 90 March 2, 2026 at 06:56:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 106 0 3 1 0 0 0 1 0 99 1 0 0 14 113 52 109 0 2 0 0 272 0 0 0 100 2 0 0 0 34 8 28 0 3 0 0 283 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 211 103 32 1 0 0 0 1133 0 0 0 100 5 0 0 14 10 3 6 0 0 0 0 266 0 0 0 100 6 0 0 0 14 3 8 0 0 0 0 602 0 0 0 100 7 0 0 0 8 1 2 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:56:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2325 200 110 0 0 1 0 7 0 1 0 99 1 0 0 7 136 54 122 1 3 0 0 556 0 0 0 100 2 0 0 112 36 8 37 0 2 0 0 16 0 0 0 100 3 0 0 0 30 3 8 0 1 0 0 6 0 0 0 100 4 0 0 4 229 104 34 2 0 0 0 1137 0 0 0 100 5 0 0 14 25 3 6 0 0 0 0 266 0 0 0 100 6 0 0 0 33 5 12 0 0 0 0 605 0 0 0 100 7 0 0 0 21 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 108 0 0 0 0 23 0 1 0 99 1 0 0 7 120 54 118 0 0 0 0 554 0 0 0 100 2 0 0 7 36 9 32 0 0 0 0 12 0 0 0 100 3 0 0 0 14 3 10 0 0 0 0 4 0 0 0 100 4 0 0 4 213 103 38 0 1 0 0 1139 0 0 0 100 5 0 0 14 15 8 6 0 0 0 0 266 0 0 0 100 6 0 0 0 14 2 10 0 0 0 0 606 0 0 0 100 7 0 0 0 12 0 8 1 0 0 0 5 0 0 0 100 March 2, 2026 at 06:56:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2905 224 1265 9 133 1893 0 1765 2 6 0 92 1 0 0 7 320 20 594 10 128 2069 0 3599 5 6 0 89 2 0 0 0 478 5 917 8 123 2124 0 1453 2 5 0 92 3 0 0 0 783 204 1212 5 154 2016 0 1530 2 5 0 93 4 0 0 133 690 107 1108 8 145 2074 0 3067 2 5 0 92 5 0 0 14 441 5 939 3 142 1924 1 1625 2 4 0 93 6 0 0 0 386 6 790 12 130 2130 0 3373 4 5 0 90 7 0 0 0 498 16 1032 10 135 2068 0 1571 5 4 0 91 March 2, 2026 at 06:56:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2343 239 114 0 2 1 0 1 0 1 0 99 1 0 0 7 16 5 10 0 0 1 0 553 0 0 0 100 2 0 0 0 88 1 84 0 1 1 0 0 0 0 0 100 3 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 4 0 0 4 222 108 44 1 0 1 0 1139 0 0 0 99 5 0 0 14 14 5 8 0 0 1 0 266 0 0 0 100 6 0 0 0 38 15 32 0 2 0 0 599 0 0 0 100 7 0 0 0 9 2 2 0 0 1 0 1 0 0 0 100 March 2, 2026 at 06:56:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 104 0 0 0 0 0 0 1 0 99 1 0 0 7 13 4 12 1 1 0 0 557 0 0 0 100 2 0 0 0 22 1 180 0 1 0 0 331 0 0 0 100 3 0 0 0 20 4 20 0 1 0 0 3 0 0 0 100 4 0 0 3 226 110 48 1 1 0 0 1140 0 0 0 99 5 0 0 14 11 4 8 0 0 0 0 266 0 0 0 100 6 0 0 0 111 53 106 0 0 0 0 602 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 March 2, 2026 at 06:56:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 104 0 1 0 0 0 0 1 0 99 1 0 0 7 12 4 8 0 0 0 0 554 0 0 0 100 2 0 0 0 19 1 14 0 0 0 0 6 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 3 0 0 0 100 4 0 0 4 224 109 46 1 0 0 0 1138 0 0 0 99 5 0 0 14 12 4 10 0 1 0 0 267 0 0 0 100 6 0 0 0 109 52 104 0 0 0 0 600 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2317 204 120 1 1 0 0 12 0 1 0 99 1 0 0 7 12 4 8 0 0 0 0 554 0 0 0 100 2 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 19 4 17 0 1 0 0 9 0 0 0 100 4 0 0 4 235 109 64 2 1 0 0 1151 0 0 0 100 5 0 0 14 19 10 12 0 1 0 0 268 0 0 0 100 6 0 0 0 119 53 118 2 0 0 0 690 0 0 0 100 7 0 0 0 15 2 12 0 1 0 0 8 0 0 0 100 March 2, 2026 at 06:56:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 205 118 0 0 0 0 8 0 0 0 99 1 0 0 7 15 5 14 0 1 2 0 554 0 0 0 100 2 0 0 0 9 0 4 0 0 3 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 4 0 0 4 216 104 40 0 0 4 0 1130 0 0 0 99 5 0 0 14 19 4 24 0 1 0 0 267 0 0 0 100 6 0 0 0 111 52 106 0 0 0 0 600 0 0 0 100 7 0 0 0 6 0 2 0 0 4 0 0 0 0 0 100 March 2, 2026 at 06:56:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 3 2343 205 140 0 8 6 3 67 0 1 0 99 1 867 0 7 45 5 46 1 5 11 3 764 0 0 0 99 2 10 0 0 37 0 28 0 5 6 2 47 0 0 0 100 3 1464 0 114 32 3 59 2 5 7 10 6605 2 1 0 97 4 1174 0 4 259 104 95 3 9 11 10 1540 0 1 0 99 5 21 0 16 43 4 54 0 9 12 8 407 0 0 0 100 6 5 0 0 143 53 147 0 11 6 2 709 0 0 0 100 7 28 0 0 34 0 32 0 5 5 7 47 0 0 0 100 March 2, 2026 at 06:56:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 206 120 0 0 0 0 6 0 1 0 99 1 0 0 7 13 4 8 0 0 0 0 555 0 0 0 100 2 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 212 103 34 1 0 0 0 1213 0 0 0 100 5 0 0 14 15 5 12 0 1 0 0 267 0 0 0 100 6 0 0 0 116 53 116 0 1 0 0 602 0 0 0 100 7 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:56:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 46 0 3 5137 206 6050 55 225 96 0 17259 15 10 0 75 1 45 0 0 2944 10 6231 55 252 116 0 16593 14 9 0 77 2 56 0 7 2407 11 4951 34 177 57 0 12058 11 7 0 82 3 206 0 0 2402 4 4875 38 193 44 0 11897 10 6 0 84 4 19 0 4 1690 108 2982 28 157 61 0 7445 6 4 0 90 5 6 0 14 832 12 1725 13 90 80 0 7078 5 3 0 92 6 19 0 0 2617 30 5803 21 126 40 0 16653 8 5 0 86 7 56 0 0 1344 2 2811 16 79 45 0 9516 11 4 0 85 March 2, 2026 at 06:56:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 10 6447 210 8694 81 388 136 0 26594 24 16 0 61 1 6 0 0 4877 11 10161 80 416 111 0 23632 20 13 0 66 2 9 0 0 3995 17 8269 61 304 114 0 20550 18 12 0 71 3 5 0 0 4110 9 8396 70 322 88 0 20025 16 11 0 73 4 5 0 4 2830 114 5371 39 265 99 0 13629 13 8 0 79 5 0 0 0 2473 21 5064 22 158 86 0 10865 9 6 0 84 6 7 0 14 2861 14 5897 29 210 115 0 14415 12 8 0 80 7 7 0 0 2481 11 5433 28 152 88 0 13717 12 8 0 80 March 2, 2026 at 06:56:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 10 4169 208 3928 21 191 779 0 9527 9 8 0 84 1 4 0 0 2000 5 4138 16 212 605 0 9149 8 7 0 85 2 10 0 0 1745 6 3662 18 146 739 0 7599 7 6 0 87 3 7 0 0 1873 154 3640 15 174 828 0 8226 7 6 0 87 4 8 0 4 1315 110 2394 19 166 716 0 6468 6 5 0 89 5 8 0 0 1224 16 2461 9 124 638 0 5159 4 4 0 92 6 0 0 14 1131 16 2309 13 149 749 0 6306 4 4 0 92 7 0 0 0 794 5 1704 3 93 589 0 4424 4 4 0 93 March 2, 2026 at 06:56:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2309 204 102 0 3 0 0 261 0 0 0 99 1 0 0 0 12 2 0 0 0 1 0 0 0 0 0 100 2 0 0 0 22 3 14 0 0 1 0 300 0 0 0 100 3 0 0 0 12 1 4 0 1 1 0 0 0 0 0 100 4 0 0 7 214 103 12 0 1 1 0 294 0 0 0 100 5 0 0 0 41 11 30 0 0 1 0 7 0 0 0 100 6 0 0 14 113 53 134 1 0 1 0 1480 0 0 0 100 7 0 0 0 12 3 4 0 0 1 0 301 0 0 0 100 March 2, 2026 at 06:56:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2307 203 112 0 1 0 0 260 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 19 2 12 1 1 1 0 300 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 4 211 104 4 0 0 1 0 295 0 0 0 100 5 0 0 0 21 8 18 0 1 0 0 9 0 0 0 100 6 0 0 14 90 43 114 1 0 0 0 1482 0 0 0 100 7 0 0 0 29 11 24 1 1 0 0 300 0 0 0 100 March 2, 2026 at 06:56:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2306 202 114 0 0 0 0 260 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 14 3 10 0 0 0 0 300 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 4 0 0 4 211 103 4 0 1 0 0 294 0 0 0 100 5 0 0 0 28 9 28 0 1 0 0 9 0 0 0 100 6 0 0 14 7 2 34 0 0 0 0 1480 0 0 0 100 7 0 0 0 108 51 102 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:56:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2316 204 130 2 0 0 0 275 0 0 0 99 1 0 0 0 9 0 4 0 0 0 0 5 0 0 0 100 2 0 0 0 14 3 8 0 1 0 0 300 0 0 0 100 3 0 0 0 13 2 10 0 1 0 0 4 0 0 0 100 4 0 0 4 211 104 4 0 0 0 0 295 0 0 0 100 5 0 0 0 36 15 26 1 1 0 0 13 0 0 0 100 6 0 0 14 15 3 46 1 1 0 0 1483 0 0 0 100 7 0 0 0 115 52 112 1 0 0 0 308 0 0 0 100 March 2, 2026 at 06:56:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2311 203 118 0 0 1 0 260 0 0 0 100 1 0 0 0 10 2 6 0 0 1 0 22 0 0 0 100 2 0 0 0 18 2 18 0 3 3 0 300 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 294 0 0 0 100 5 0 0 0 25 9 22 0 0 0 0 9 0 0 0 100 6 0 0 14 9 2 34 2 0 0 0 1480 0 0 0 100 7 0 0 0 108 51 104 0 0 1 0 300 0 0 0 100 March 2, 2026 at 06:56:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2309 202 116 0 0 0 0 260 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 17 2 10 1 0 0 0 300 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 294 0 0 0 100 5 0 0 0 24 9 18 0 0 0 0 9 0 0 0 100 6 0 0 14 13 3 40 2 1 0 0 1481 0 0 0 100 7 0 0 0 113 51 112 1 1 0 0 300 0 0 0 100 March 2, 2026 at 06:56:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2309 202 122 0 1 0 0 260 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 14 2 10 0 0 0 0 300 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 294 0 0 0 100 5 0 0 0 26 10 20 1 0 0 0 10 0 0 0 100 6 0 0 14 10 3 36 1 0 1 0 1482 0 0 0 100 7 0 0 0 109 51 104 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:56:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2310 203 116 1 0 0 0 261 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 16 3 10 0 0 0 0 301 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 294 0 0 0 100 5 0 0 0 22 8 16 0 0 0 0 8 0 0 0 100 6 0 0 14 9 3 36 0 0 0 0 1482 0 0 0 100 7 0 0 0 107 51 104 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:56:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2312 204 132 1 1 0 0 273 0 1 0 99 1 0 0 0 14 0 14 0 1 0 0 5 0 0 0 100 2 0 0 0 14 2 10 0 1 0 0 300 0 0 0 100 3 0 0 0 10 2 6 0 1 0 0 1 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 294 0 0 0 100 5 0 0 0 29 15 18 0 0 0 0 9 0 0 0 100 6 0 0 14 8 2 34 1 0 0 0 1479 0 0 0 99 7 0 0 0 112 51 108 0 0 0 0 307 0 0 0 100 March 2, 2026 at 06:57:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 10 5518 209 7147 56 313 278 0 22247 15 10 0 75 1 4 0 0 2904 5 6133 69 337 227 0 15326 12 9 0 79 2 1 0 1 2220 12 4500 53 236 245 0 11925 9 7 0 84 3 15 0 0 2715 98 5565 56 258 209 0 13116 11 8 0 82 4 1 0 4 2021 110 3671 35 223 205 0 7976 7 5 0 88 5 29 0 0 1123 9 2258 31 140 222 0 9257 11 5 0 84 6 3 0 0 1767 17 3860 32 200 252 0 10001 8 5 0 87 7 1 0 14 1417 27 2944 22 141 193 0 6933 6 4 0 90 March 2, 2026 at 06:57:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 17 6622 207 9177 66 350 146 0 24545 23 15 0 62 1 13 0 0 4392 12 8974 58 377 105 0 24047 21 13 0 66 2 11 0 0 3420 11 6960 49 236 80 0 17684 16 10 0 74 3 10 0 0 4267 19 8918 53 291 112 0 19128 15 10 0 74 4 7 0 4 2935 113 5741 32 240 129 0 17884 15 10 0 75 5 9 0 7 2412 13 5025 27 140 117 0 13186 12 8 0 80 6 3 0 0 3362 16 6988 44 239 78 0 13740 12 8 0 80 7 4 0 0 2677 13 5575 20 141 115 0 13525 11 7 0 82 March 2, 2026 at 06:57:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 3 6648 206 9381 62 376 137 0 24196 22 15 0 62 1 11 0 0 4398 6 9220 53 420 153 0 23726 20 13 0 67 2 11 0 0 3452 9 7177 38 261 156 0 19078 18 11 0 71 3 31 0 0 4606 11 9543 56 339 105 0 21188 17 11 0 72 4 8 0 4 3237 116 6223 28 260 85 0 16718 14 9 0 76 5 12 0 14 2115 14 4372 25 171 151 0 12673 11 7 0 82 6 0 0 7 3228 20 6680 53 273 121 0 15543 14 9 0 78 7 5 0 0 2210 14 4584 18 137 75 0 10684 9 6 0 85 March 2, 2026 at 06:57:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 3 4128 202 3869 21 151 79 0 9608 9 6 0 85 1 6 0 0 1702 4 3538 25 158 39 0 9094 8 5 0 87 2 2 0 0 1655 2 3290 23 113 27 0 7324 6 4 0 89 3 2 0 0 1671 7 3428 30 140 33 0 7731 6 4 0 90 4 1 0 3 1195 116 2092 9 99 93 0 6815 6 3 0 91 5 0 0 14 809 38 1588 7 56 19 0 4048 4 2 0 94 6 2 0 7 1000 9 2069 9 84 34 0 5728 5 3 0 92 7 0 0 0 656 2 1349 6 38 15 0 4281 4 2 0 94 March 2, 2026 at 06:57:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2312 202 100 2 3 0 0 15 0 0 0 100 1 0 0 0 30 2 22 0 0 0 0 7 0 0 0 100 2 0 0 0 14 1 8 1 0 0 0 300 0 0 0 100 3 0 0 0 13 1 6 0 1 0 0 0 0 0 0 100 4 0 0 4 218 105 40 0 3 1 0 1216 0 0 0 100 5 0 0 14 121 60 112 0 1 0 0 561 0 0 0 100 6 0 0 7 22 9 18 0 0 0 0 269 0 0 0 100 7 0 0 0 16 2 12 1 0 0 0 306 0 0 0 100 March 2, 2026 at 06:57:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2438 201 352 1 69 828 0 9 0 2 0 98 1 0 0 0 173 14 354 1 75 893 0 4 0 2 0 98 2 0 0 0 138 1 286 1 71 755 0 300 0 2 0 98 3 0 0 0 268 139 271 1 63 831 0 0 0 2 0 98 4 0 0 4 382 103 381 2 82 971 0 1226 0 2 0 98 5 0 0 14 193 41 307 0 51 700 0 583 0 2 0 98 6 0 0 7 305 15 607 0 89 859 0 277 0 2 0 98 7 0 0 0 133 1 298 0 65 983 0 303 0 2 0 98 March 2, 2026 at 06:57:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 102 0 2 0 0 0 0 0 0 100 1 0 0 0 111 53 106 0 0 0 0 3 0 0 0 100 2 0 0 0 14 1 10 0 0 0 0 300 0 0 0 100 3 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 4 0 0 4 222 103 40 1 0 0 0 1214 0 0 0 100 5 0 0 14 13 5 10 0 0 0 0 561 0 0 0 100 6 0 0 7 25 9 20 1 0 0 0 269 0 0 0 100 7 0 0 0 12 1 12 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:57:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 110 0 0 0 0 1 0 0 0 100 1 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 2 0 0 0 12 1 8 0 0 0 0 300 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 4 210 103 2 1 0 0 0 707 0 0 0 100 5 0 0 14 15 6 12 0 0 0 0 560 0 0 0 100 6 0 0 7 23 9 50 0 2 0 0 776 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:57:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 200 118 0 1 0 0 0 0 0 0 100 1 0 0 0 112 52 106 0 0 0 0 2 0 0 0 100 2 0 0 0 16 2 12 1 0 0 0 301 0 0 0 100 3 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 14 13 5 10 0 0 0 0 561 0 0 0 100 6 0 0 7 27 11 52 1 0 0 0 1485 0 0 0 100 7 0 0 0 10 1 4 1 1 0 0 300 0 0 0 100 March 2, 2026 at 06:57:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2313 202 124 1 0 0 0 16 0 0 0 100 1 0 0 0 116 51 116 0 1 0 0 5 0 0 0 100 2 0 0 0 12 1 8 0 0 0 0 300 0 0 0 100 3 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 14 21 11 10 0 0 0 0 559 0 0 0 100 6 0 0 7 26 10 50 2 0 1 0 1485 0 0 0 99 7 0 0 0 12 1 10 0 0 0 0 305 0 0 0 100 March 2, 2026 at 06:57:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1965 0 3 3018 202 1475 695 81 54 0 3565 56 5 0 39 1 51 0 0 747 24 1533 683 93 39 0 3586 58 4 0 39 2 18 0 7 786 5 1543 726 84 46 0 4176 57 4 0 39 3 15 0 0 671 12 1188 559 97 45 1 3333 58 3 0 39 4 24 0 703 740 113 1186 569 79 53 1 3256 58 3 0 39 5 76 0 0 665 6 1204 595 74 46 0 3415 58 3 0 38 6 3 0 14 836 16 1649 777 85 46 0 5487 57 4 0 39 7 29 0 7 695 4 1247 586 86 63 0 4027 58 3 0 39 March 2, 2026 at 06:57:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2549 203 623 219 65 24 0 1764 25 2 0 72 1 0 0 0 283 38 443 147 44 9 0 1237 25 1 0 74 2 1 0 0 177 6 383 147 54 32 0 1497 25 1 0 74 3 0 0 0 259 5 577 219 71 19 0 2109 24 2 0 74 4 0 0 203 410 113 410 169 46 27 0 1359 25 1 0 74 5 2 0 0 227 6 477 215 56 14 0 1609 25 1 0 74 6 0 0 14 264 7 569 220 58 28 0 3122 25 2 0 73 7 6 0 7 265 5 409 192 34 12 0 1694 26 1 0 73 March 2, 2026 at 06:57:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 100 0 0 0 0 0 0 1 0 99 1 0 0 0 123 59 118 0 0 0 0 12 0 0 0 100 2 0 0 0 12 0 8 0 0 0 0 0 0 0 0 100 3 0 0 0 17 2 16 1 2 0 0 302 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 20 3 16 0 0 0 0 296 0 0 0 100 6 2 0 14 14 5 38 1 0 0 0 1492 0 0 0 100 7 0 0 7 12 3 8 1 1 0 0 561 0 0 0 100 March 2, 2026 at 06:57:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2301 200 100 0 0 0 0 0 0 0 0 100 1 0 0 0 120 57 116 0 1 0 0 9 0 0 0 100 2 0 0 0 10 0 6 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 301 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 17 2 12 0 0 0 0 294 0 0 0 100 6 0 0 14 12 4 38 1 0 0 0 1493 0 0 0 100 7 0 0 7 12 4 6 0 0 0 0 559 0 0 0 100 March 2, 2026 at 06:57:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 202 114 1 0 0 0 16 0 0 0 100 1 0 0 0 131 59 129 0 2 0 0 13 0 0 0 100 2 0 0 0 11 0 8 0 0 0 0 0 0 0 0 100 3 0 0 0 12 1 8 0 0 0 0 300 0 0 0 100 4 0 0 3 214 103 12 0 1 0 0 1 0 0 0 100 5 0 0 0 22 8 8 0 0 0 0 295 0 0 0 100 6 0 0 14 12 4 38 1 0 1 0 1493 0 0 0 100 7 0 0 7 17 4 16 1 0 0 0 567 0 0 0 100 March 2, 2026 at 06:57:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2809 208 1102 29 161 1758 0 1333 3 5 0 92 1 2 0 0 580 29 1154 33 179 1849 0 1307 3 4 0 92 2 0 0 0 691 2 1358 24 161 1453 0 1256 3 4 0 93 3 0 0 0 771 201 1121 17 163 1789 0 2196 4 5 0 92 4 0 0 130 460 104 529 9 119 1924 0 2599 8 5 0 87 5 46 0 10 300 33 545 6 119 1589 1 3345 6 5 0 89 6 3 0 28 249 4 541 11 137 1608 2 4572 6 5 0 89 7 0 0 7 502 5 1004 29 148 1516 0 2144 3 4 0 93 March 2, 2026 at 06:57:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 200 98 0 2 0 0 0 0 0 0 100 1 0 0 7 14 4 10 0 1 0 0 3 0 0 0 100 2 0 0 0 32 1 22 0 0 0 0 0 0 0 0 100 3 0 0 0 11 1 4 1 1 0 0 299 0 0 0 100 4 0 0 4 211 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 108 51 102 0 0 0 0 294 0 0 0 100 6 0 0 14 26 9 49 2 2 1 0 1419 0 0 0 99 7 0 0 7 16 4 12 1 1 0 0 565 0 0 0 100 March 2, 2026 at 06:57:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2320 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 28 2 6 0 0 0 0 0 0 0 0 100 2 0 0 0 26 1 6 0 1 0 0 0 0 0 0 100 3 0 0 0 25 1 4 0 0 0 0 300 0 0 0 100 4 0 0 4 223 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 128 52 106 0 1 0 0 295 0 0 0 100 6 0 0 126 20 4 53 1 2 0 0 1400 0 0 0 99 7 0 0 7 44 11 24 0 0 0 0 575 0 0 0 100 March 2, 2026 at 06:57:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 12 3 6 0 0 0 0 2 0 0 0 100 2 0 0 0 16 2 10 0 1 0 0 1 0 0 0 100 3 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 4 0 0 4 208 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 108 51 102 0 0 0 0 294 0 0 0 100 6 0 0 21 16 4 42 1 0 0 0 1399 0 0 0 99 7 0 0 7 30 9 30 1 1 0 0 565 0 0 0 100 March 2, 2026 at 06:57:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2666 202 802 18 43 22 0 1951 6 2 0 93 1 0 0 0 283 4 499 7 35 28 0 1722 3 1 0 96 2 0 0 0 280 4 443 5 25 15 0 1264 2 1 0 98 3 0 0 0 286 4 548 10 27 30 0 2842 4 1 0 95 4 0 0 144 505 104 579 3 23 16 0 1179 1 1 0 98 5 2 0 0 90 26 60 5 2 36 0 3267 5 2 0 93 6 0 0 14 174 9 305 12 18 18 0 3701 4 2 0 94 7 0 0 7 361 36 623 4 19 11 0 1741 2 1 0 98 March 2, 2026 at 06:57:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2461 200 415 1 89 1354 0 0 0 3 0 97 1 0 0 0 358 18 719 1 112 1172 0 2 0 2 0 98 2 0 0 0 180 0 359 2 81 1218 0 0 0 2 0 98 3 1 0 0 330 159 382 2 88 1193 0 305 0 2 0 98 4 0 0 4 352 104 323 2 77 1251 0 6 0 2 0 98 5 0 0 0 133 1 273 2 58 1015 0 294 0 2 0 98 6 0 0 14 161 10 351 3 76 1145 0 1406 0 2 0 97 7 0 0 7 218 38 391 3 71 1092 0 561 0 2 0 98 March 2, 2026 at 06:57:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 62 0 7 2336 201 140 0 11 8 2 147 0 1 0 99 1 22 0 0 156 53 170 0 14 10 7 157 0 0 0 100 2 747 0 112 52 5 88 0 13 8 15 220 0 0 0 99 3 2688 0 0 58 3 74 5 11 10 18 7131 2 2 0 96 4 28 0 9 243 102 47 0 10 6 8 114 0 0 0 100 5 11 0 0 46 2 32 0 5 6 3 350 0 0 0 100 6 3 0 14 52 11 65 0 5 5 2 1525 0 0 0 99 7 1 0 7 40 4 23 0 3 5 1 573 0 0 0 100 March 2, 2026 at 06:57:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 111 53 106 0 0 0 0 2 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 295 0 0 0 100 6 0 0 14 24 10 50 1 0 0 0 1491 0 0 0 100 7 0 0 7 11 3 8 1 0 0 0 561 0 0 0 100 March 2, 2026 at 06:57:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 46 0 3 4613 203 4856 44 159 61 0 12543 12 8 0 80 1 34 0 0 2215 33 4485 39 189 51 0 11798 10 6 0 84 2 266 0 0 2156 6 4899 20 124 35 0 16525 9 5 0 86 3 33 0 0 2106 15 4325 27 151 75 0 11743 9 6 0 85 4 8 0 4 1490 106 2700 13 121 67 0 9429 11 5 0 84 5 8 0 0 1244 3 2681 16 86 41 0 6852 6 4 0 90 6 6 0 14 1718 16 3565 19 118 33 0 8910 6 4 0 89 7 80 0 7 1210 6 2606 12 73 52 0 7463 6 4 0 90 March 2, 2026 at 06:57:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 3 7051 208 9872 69 344 84 0 24471 23 15 0 62 1 20 0 7 4884 16 10018 61 418 121 0 25720 22 14 0 65 2 13 0 19 3748 10 7904 39 273 116 0 20098 18 11 0 71 3 5 0 0 4297 15 9008 63 339 97 0 21678 19 12 0 70 4 4 0 3 3096 115 5937 35 283 81 0 13944 12 8 0 79 5 1 0 0 2335 15 4761 18 151 106 0 10359 10 6 0 84 6 5 0 0 3258 19 6916 39 221 121 0 17560 13 9 0 78 7 3 0 14 1726 13 3544 24 131 67 0 10807 9 6 0 86 March 2, 2026 at 06:57:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 4592 207 4813 17 211 718 0 11145 11 9 0 81 1 7 0 7 2695 23 5818 21 270 686 0 13517 11 9 0 80 2 3 0 0 1962 5 4197 12 159 834 0 10622 9 7 0 84 3 12 0 0 2429 130 4854 23 218 694 0 9871 9 7 0 84 4 2 0 4 1361 109 2446 20 202 721 0 7655 7 6 0 88 5 0 0 0 1120 9 2324 9 121 682 0 4391 4 4 0 92 6 6 0 0 1433 5 3073 15 172 822 0 8169 6 5 0 90 7 3 0 14 1005 17 2071 12 122 597 0 4289 4 4 0 93 March 2, 2026 at 06:57:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 205 82 0 2 0 0 8 0 1 0 99 1 0 0 7 15 3 8 1 1 0 0 261 0 0 0 100 2 0 0 0 25 2 20 1 0 0 0 294 0 0 0 100 3 0 0 0 12 3 6 0 0 0 0 301 0 0 0 100 4 0 0 4 209 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 42 0 34 0 0 0 0 0 0 0 0 100 6 0 0 0 19 4 48 1 1 0 0 1520 0 0 0 100 7 0 0 14 108 52 106 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 206 114 0 0 0 0 10 0 0 0 99 1 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 2 0 0 0 22 2 16 0 0 0 0 294 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 3 211 104 4 0 0 0 0 2 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 16 4 40 1 1 1 0 1520 0 0 0 100 7 0 0 14 114 52 118 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:57:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2316 206 114 0 0 0 0 6 0 0 0 100 1 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 2 0 0 0 23 3 16 0 0 0 0 295 0 0 0 100 3 0 0 0 12 3 6 1 0 0 0 302 0 0 0 100 4 0 0 4 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 38 2 0 0 0 1520 0 0 0 100 7 0 0 14 108 52 106 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2316 205 116 0 1 0 0 8 0 1 0 99 1 0 0 7 9 2 6 0 1 0 0 260 0 0 0 100 2 0 0 0 21 2 16 0 0 0 0 294 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 4 0 0 3 215 104 8 0 0 0 0 8 0 0 0 100 5 0 0 0 14 5 8 0 1 0 0 10 0 0 0 100 6 0 0 0 14 4 36 1 0 1 0 1515 0 0 0 100 7 21 0 14 124 54 128 0 0 0 0 283 0 0 0 100 March 2, 2026 at 06:57:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 205 122 0 1 0 0 8 0 0 0 99 1 0 0 7 12 3 10 1 0 3 0 263 0 0 0 100 2 0 0 0 21 2 16 0 0 0 0 294 0 0 0 100 3 0 0 0 12 3 8 0 1 1 0 302 0 0 0 100 4 0 0 4 212 104 6 0 0 0 0 4 0 0 0 100 5 0 0 0 7 0 4 0 0 0 0 0 0 0 0 100 6 0 0 0 14 4 40 0 0 1 0 1515 0 0 0 100 7 0 0 14 111 52 110 0 0 2 0 266 0 0 0 100 March 2, 2026 at 06:57:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2316 206 114 0 0 1 0 9 0 0 0 99 1 4 0 7 17 6 10 0 0 1 0 265 0 0 0 100 2 0 0 0 27 4 18 0 0 1 0 295 0 0 0 100 3 0 0 0 12 3 4 0 0 1 0 300 0 0 0 100 4 0 0 7 210 103 4 0 1 0 0 1 0 0 0 100 5 0 0 0 10 2 2 0 0 1 0 1 0 0 0 100 6 0 0 0 15 4 36 1 0 1 0 1515 0 0 0 100 7 0 0 14 111 53 106 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:57:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2320 209 126 1 1 3 0 6 0 0 0 99 1 0 0 7 25 5 31 0 8 2 0 260 0 0 0 100 2 0 0 7 28 3 26 0 4 2 0 294 0 0 0 100 3 0 0 0 18 4 14 1 3 1 0 302 0 0 0 100 4 0 0 3 214 103 6 0 2 2 0 0 0 0 0 100 5 0 0 0 12 2 8 0 1 2 0 1 0 0 0 100 6 0 0 0 17 4 40 2 2 3 0 1515 0 0 0 100 7 0 0 14 111 53 108 0 0 1 0 266 0 0 0 100 March 2, 2026 at 06:57:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2317 207 116 0 0 0 0 8 0 0 0 100 1 0 0 7 18 4 14 0 1 0 0 267 0 0 0 100 2 0 0 0 37 4 36 0 1 0 0 299 0 0 0 100 3 0 0 7 13 3 10 0 2 0 0 301 0 0 0 100 4 0 0 4 208 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 36 1 0 1 0 1515 0 0 0 100 7 0 0 14 109 52 106 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:57:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2318 205 114 0 0 0 0 9 0 1 0 99 1 0 0 7 13 4 8 1 0 0 0 261 0 0 0 100 2 0 0 0 21 2 16 0 0 0 0 294 0 0 0 100 3 0 0 0 14 3 10 0 1 0 0 302 0 0 0 100 4 0 0 4 212 102 4 0 0 0 0 5 0 0 0 100 5 0 0 0 24 9 18 0 1 0 0 23 0 0 0 100 6 0 0 0 12 3 36 1 0 0 0 1515 0 0 0 100 7 0 0 14 113 52 114 0 1 0 0 273 0 0 0 100 March 2, 2026 at 06:57:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 4682 207 5139 62 236 201 0 13808 12 9 0 79 1 11 0 7 2533 13 5407 64 269 182 0 14266 12 8 0 80 2 19 0 0 1799 7 3563 38 158 177 0 9178 8 5 0 86 3 4 0 0 2386 65 4802 44 216 171 0 12020 13 6 0 81 4 2 0 4 1514 106 2640 21 178 178 0 6746 6 4 0 90 5 1 0 0 1481 3 3683 14 112 146 0 14016 7 4 0 89 6 26 0 0 1728 10 3631 27 161 195 0 8766 7 5 0 88 7 2 0 14 923 32 1911 14 95 143 0 5951 4 3 0 93 March 2, 2026 at 06:57:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 18 0 3 7095 208 10226 63 389 140 0 26603 24 16 0 60 1 6 0 0 5340 18 11260 60 415 115 0 28626 24 15 0 61 2 10 0 0 3643 8 7428 31 289 91 0 17744 16 10 0 73 3 4 0 0 4601 18 9530 60 341 94 0 21060 17 12 0 71 4 7 0 11 2614 116 4914 31 262 110 0 12771 12 7 0 80 5 2 0 0 1854 6 3925 24 148 103 0 10324 10 6 0 84 6 6 0 0 3019 13 6447 33 239 79 0 16045 13 9 0 78 7 2 0 14 1840 10 3833 25 129 71 0 11252 9 6 0 85 March 2, 2026 at 06:57:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 3 6584 205 9256 55 324 113 0 24483 22 15 0 63 1 4 0 0 4702 14 9884 40 361 114 0 23630 20 13 0 67 2 6 0 0 3523 8 7181 30 247 75 0 16011 14 9 0 77 3 5 0 0 4353 8 9135 41 272 154 0 21160 16 11 0 72 4 4 0 11 2911 109 5606 29 241 79 0 15922 14 9 0 77 5 6 0 0 2149 7 4493 11 141 82 0 13001 12 7 0 81 6 7 0 0 3732 15 8006 29 230 81 0 18674 17 11 0 73 7 10 0 14 1975 17 4122 17 124 113 0 11477 10 6 0 84 March 2, 2026 at 06:57:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 3 4117 203 4076 13 173 46 0 12473 12 8 0 81 1 1 0 0 2323 6 4896 21 191 53 0 11451 9 6 0 85 2 3 0 0 1840 3 3936 13 122 60 0 8446 8 5 0 86 3 4 0 0 2045 24 4228 16 141 50 0 9894 8 5 0 87 4 4 0 11 1360 111 2345 14 119 52 0 6167 6 3 0 91 5 4 0 0 699 4 1497 11 54 29 0 5140 5 3 0 92 6 1 0 0 1508 30 3058 8 105 53 0 7932 6 4 0 90 7 0 0 14 746 3 1504 5 59 33 0 3827 3 2 0 95 March 2, 2026 at 06:57:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 200 112 0 1 0 0 0 0 1 0 99 1 0 0 0 13 2 38 1 0 1 0 1504 0 0 0 100 2 0 0 0 13 1 6 0 1 0 0 0 0 0 0 100 3 0 0 0 17 3 14 0 1 0 0 300 0 0 0 100 4 0 0 11 237 113 36 0 1 0 0 280 0 0 0 100 5 0 0 0 17 7 4 0 0 0 0 1 0 0 0 100 6 0 0 0 113 50 110 0 1 0 0 12 0 0 0 100 7 0 0 14 15 3 16 0 0 0 0 573 0 0 0 100 March 2, 2026 at 06:57:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2451 201 413 2 78 894 0 5 0 3 0 97 1 0 0 0 153 3 339 2 75 1093 0 1518 0 3 0 97 2 0 0 0 126 0 272 1 62 879 0 0 0 2 0 98 3 0 0 0 289 156 287 3 77 864 0 301 0 2 0 98 4 0 0 10 403 123 401 2 83 912 0 277 0 2 0 98 5 0 0 0 138 1 298 1 62 865 0 3 0 2 0 98 6 0 0 0 287 35 518 2 79 915 0 3 0 2 0 98 7 0 0 14 218 6 429 2 64 875 0 578 0 2 0 98 March 2, 2026 at 06:57:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2305 201 114 0 1 0 0 1 0 1 0 99 1 0 0 0 13 3 34 1 0 2 0 1503 0 0 0 100 2 0 0 0 11 1 2 0 0 1 0 0 0 0 0 100 3 0 0 0 16 4 8 0 0 1 0 300 0 0 0 100 4 0 0 14 315 155 108 0 0 1 0 261 0 0 0 100 5 0 0 0 15 2 12 0 1 1 0 0 0 0 0 100 6 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 7 0 0 14 26 10 20 1 0 1 0 575 0 0 0 100 March 2, 2026 at 06:57:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 114 0 0 0 0 6 0 0 0 100 1 0 0 0 10 2 34 1 0 0 0 1503 0 0 0 100 2 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 3 0 0 0 15 3 12 0 2 0 0 309 0 0 0 100 4 0 0 11 315 156 108 1 0 0 0 262 0 0 0 100 5 0 0 0 13 3 8 0 0 0 0 2 0 0 0 100 6 0 0 0 12 1 10 0 1 0 0 0 0 0 0 100 7 0 0 14 22 9 20 0 0 0 0 589 0 0 0 100 March 2, 2026 at 06:57:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 12 3 36 1 0 0 0 1504 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 3 0 0 0 100 3 0 0 0 16 3 12 0 0 0 0 302 0 0 0 100 4 0 0 11 310 154 104 0 0 0 0 260 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 1 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 14 18 7 16 0 0 0 0 573 0 0 0 100 March 2, 2026 at 06:57:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 200 114 0 0 0 0 0 0 1 0 99 1 0 0 0 12 3 36 1 0 1 0 1504 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 17 2 13 1 0 0 0 300 0 0 0 100 4 0 0 11 318 156 112 0 0 0 0 268 0 0 0 100 5 4 0 0 20 10 10 0 0 0 0 5 0 0 0 100 6 0 0 0 17 3 16 0 0 0 0 14 0 0 0 100 7 0 0 14 33 9 38 1 1 0 0 584 0 0 0 100 March 2, 2026 at 06:57:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1341 0 3 2876 213 1165 541 72 54 1 3535 48 5 0 47 1 6 0 0 586 3 1176 539 78 70 0 4883 49 4 0 47 2 1 0 0 597 3 1127 533 95 58 0 3390 50 3 0 47 3 0 0 0 650 7 1199 580 73 39 0 3390 50 3 0 47 4 27 0 654 655 129 914 428 57 59 0 2683 50 3 0 47 5 25 0 0 631 14 1157 554 79 53 0 3264 50 3 0 47 6 22 0 0 780 16 1857 764 83 79 0 3820 49 4 0 47 7 11 0 21 655 10 1186 574 86 45 0 3861 50 3 0 47 March 2, 2026 at 06:57:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2606 206 589 217 96 24 0 2223 33 3 0 64 1 41 0 0 381 4 692 271 84 40 0 3673 32 2 0 66 2 1 0 0 372 4 683 266 98 59 0 2394 33 2 0 65 3 5 0 0 300 3 520 218 72 25 0 2182 34 2 0 65 4 2 0 458 443 108 538 198 85 35 0 2585 33 2 0 65 5 105 0 0 349 39 548 178 82 25 0 2385 33 2 0 65 6 58 0 0 482 13 1088 420 104 71 0 2391 32 2 0 66 7 10 0 14 409 9 717 320 99 57 0 3098 33 2 0 65 March 2, 2026 at 06:57:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 110 0 0 0 0 0 0 1 0 99 1 0 0 0 16 4 8 1 0 0 0 864 0 0 0 100 2 0 0 0 15 0 15 0 2 0 0 17 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 309 0 0 0 100 4 0 0 10 210 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 111 52 106 0 1 0 0 0 0 0 0 100 6 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 7 2 0 14 9 3 6 0 0 0 0 566 0 0 0 100 March 2, 2026 at 06:57:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2300 200 110 0 0 0 0 0 0 1 0 99 1 0 0 0 10 2 37 0 0 0 0 641 0 0 0 100 2 0 0 0 17 2 12 0 0 0 0 296 0 0 0 100 3 0 0 0 27 8 26 1 1 0 0 306 0 0 0 100 4 0 0 10 215 106 8 0 0 0 0 263 0 0 0 100 5 0 0 0 111 52 106 0 1 0 0 0 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 7 0 0 14 10 3 6 1 0 0 0 566 0 0 0 100 March 2, 2026 at 06:57:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 114 0 0 0 0 0 0 1 0 99 1 0 0 0 12 2 34 1 0 0 0 1222 0 0 0 100 2 0 0 0 11 1 4 0 0 0 0 294 0 0 0 100 3 0 0 0 24 9 20 0 0 0 0 307 0 0 0 100 4 0 0 10 214 104 8 0 0 0 0 265 0 0 0 100 5 0 0 0 118 59 106 0 0 1 0 0 0 0 0 100 6 0 0 0 14 2 16 0 1 0 0 18 0 0 0 100 7 0 0 14 15 3 16 0 1 0 0 573 0 0 0 100 March 2, 2026 at 06:57:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 10 2562 214 524 18 126 1819 0 3537 8 6 0 86 1 2 0 0 504 5 1032 45 179 1721 0 4178 9 5 0 86 2 0 0 0 347 7 662 21 127 2081 0 2389 4 5 0 91 3 0 0 0 761 194 1121 29 178 1621 1 2004 3 4 0 93 4 1 0 143 559 106 742 16 138 1906 0 1664 4 4 0 91 5 24 0 0 597 40 1070 39 142 1702 0 1494 3 4 0 93 6 0 0 14 321 2 637 12 129 2009 0 3396 8 5 0 88 7 3 0 14 717 7 1406 24 143 1531 0 1944 2 4 0 94 March 2, 2026 at 06:57:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2307 201 106 0 1 1 0 1 0 1 0 99 1 0 0 0 16 3 36 1 0 1 0 1129 0 0 0 100 2 0 0 0 24 8 14 0 0 1 0 300 0 0 0 100 3 0 0 0 22 3 14 0 2 1 0 300 0 0 0 100 4 0 0 14 218 105 12 0 3 0 0 261 0 0 0 100 5 0 0 7 120 53 116 0 2 1 0 0 0 0 0 100 6 0 0 0 12 1 2 0 0 1 0 0 0 0 0 100 7 0 0 14 17 4 10 0 0 1 0 567 0 0 0 100 March 2, 2026 at 06:57:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2322 200 104 0 0 0 0 0 0 0 0 100 1 0 0 0 26 2 34 1 0 0 0 1124 0 0 0 100 2 0 0 0 135 55 114 1 1 0 0 300 0 0 0 100 3 0 0 0 40 5 18 1 0 0 0 306 0 0 0 100 4 0 0 11 226 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 31 4 8 0 1 0 0 1 0 0 0 100 6 0 0 112 10 1 7 0 3 0 0 1 0 0 0 100 7 0 0 14 30 3 8 1 1 0 0 565 0 0 0 100 March 2, 2026 at 06:57:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 104 0 0 0 0 0 0 1 0 99 1 0 0 0 13 3 36 1 0 0 0 1126 0 0 0 100 2 0 0 0 122 57 116 0 1 0 0 301 0 0 0 100 3 0 0 0 20 3 14 0 0 0 0 301 0 0 0 100 4 0 0 11 211 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 12 2 6 0 1 0 0 0 0 0 0 100 6 0 0 7 13 0 12 0 1 0 0 0 0 0 0 100 7 0 0 14 13 3 8 0 0 0 0 567 0 0 0 100 March 2, 2026 at 06:57:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2505 201 451 11 31 22 0 2555 4 2 0 94 1 2 0 0 120 4 202 7 10 31 0 3494 4 2 0 94 2 0 0 0 410 33 689 8 32 18 0 1754 2 1 0 97 3 0 0 0 229 7 384 8 14 26 0 2291 6 1 0 93 4 0 0 137 533 129 618 13 36 39 0 2456 3 1 0 95 5 0 0 0 308 11 584 7 28 8 0 1760 3 1 0 96 6 0 0 0 327 4 606 13 32 34 0 1845 2 1 0 97 7 0 0 14 269 5 471 7 21 21 0 1963 2 1 0 97 March 2, 2026 at 06:57:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2482 207 422 2 76 1169 0 9 0 3 0 97 1 0 0 0 158 3 362 2 75 1094 0 1146 0 3 0 97 2 0 0 0 198 1 392 2 83 1252 0 294 0 3 0 97 3 0 0 0 403 219 387 2 82 1268 0 301 0 3 0 97 4 0 0 11 488 148 500 2 91 1254 0 260 0 3 0 97 5 0 0 0 376 5 782 1 97 1093 0 0 0 2 0 98 6 0 0 0 189 2 416 1 95 1288 0 0 0 2 0 98 7 0 0 14 180 3 375 2 70 1132 0 567 0 3 0 97 March 2, 2026 at 06:57:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2323 206 118 0 3 0 0 10 0 1 0 99 1 0 0 0 10 2 34 1 0 0 0 1125 0 0 0 100 2 0 0 0 25 2 18 0 0 0 0 296 0 0 0 100 3 0 0 0 90 42 82 1 0 0 0 300 0 0 0 100 4 0 0 11 233 115 28 0 1 0 0 261 0 0 0 100 5 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 1 0 0 1 0 0 0 100 7 0 0 14 26 6 22 1 0 0 0 569 0 0 0 100 March 2, 2026 at 06:57:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2322 208 124 0 0 0 0 12 0 0 0 99 1 0 0 0 17 3 46 1 1 1 0 1127 0 0 0 100 2 0 0 0 12 1 6 0 1 0 0 294 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 11 310 154 104 0 0 0 0 260 0 0 0 100 5 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 14 21 5 18 0 0 0 0 568 0 0 0 100 March 2, 2026 at 06:57:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3333 0 116 4228 211 4059 54 200 50 11 16326 12 8 0 79 1 147 0 0 1785 8 3570 46 189 54 8 9068 8 5 0 87 2 83 0 2 2089 5 4617 30 120 51 11 14872 9 5 0 86 3 50 0 0 1688 13 3476 44 150 45 7 9221 7 5 0 88 4 60 0 11 1076 131 1633 15 92 44 3 5893 5 3 0 92 5 183 0 0 1259 3 2835 12 72 38 10 7730 6 4 0 90 6 345 0 0 1082 2 2250 19 113 46 2 6158 4 3 0 92 7 7 0 14 502 7 960 7 43 39 1 6423 7 2 0 91 March 2, 2026 at 06:57:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 16 0 17 6523 207 8809 69 403 126 0 25172 22 15 0 63 1 17 0 0 4726 12 9897 66 407 91 0 24720 21 14 0 65 2 10 0 0 3379 7 6818 49 272 102 0 17219 16 10 0 73 3 19 0 0 4342 16 9149 59 359 106 0 22165 19 12 0 69 4 8 0 11 3018 120 5682 45 256 119 0 14720 13 8 0 78 5 27 0 0 1884 12 3838 28 145 50 0 10355 10 6 0 84 6 10 0 0 3452 16 7218 41 237 81 0 17090 15 10 0 76 7 6 0 0 2276 14 4795 23 144 69 0 9716 8 6 0 86 March 2, 2026 at 06:58:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 17 5102 206 5861 50 270 737 0 15543 14 11 0 76 1 4 0 0 3246 23 6663 48 327 708 0 14473 12 9 0 78 2 6 0 0 2450 9 5053 28 217 714 0 13211 12 9 0 79 3 11 0 0 2389 112 4776 44 257 765 0 10946 9 7 0 84 4 3 0 11 2113 115 3851 25 190 683 0 8188 7 6 0 87 5 4 0 0 1251 12 2578 13 119 616 0 6246 6 5 0 89 6 4 0 0 1867 15 3854 20 184 765 0 8397 7 6 0 86 7 10 0 0 1383 9 2970 15 109 725 0 7953 7 6 0 87 March 2, 2026 at 06:58:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2310 204 110 2 1 1 0 1778 0 1 0 99 1 0 0 0 111 52 104 0 0 1 0 0 0 0 0 100 2 0 0 0 51 2 40 0 0 1 0 0 0 0 0 100 3 0 0 0 10 1 0 0 0 1 0 0 0 0 0 100 4 0 0 14 219 108 12 0 0 1 0 855 0 0 0 100 5 0 0 0 10 1 4 0 2 0 0 0 0 0 0 100 6 0 0 0 26 9 16 0 0 1 0 9 0 0 0 100 7 0 0 0 9 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:58:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2305 203 113 1 0 0 0 832 0 1 0 99 1 0 0 0 15 4 40 0 2 1 0 945 0 0 0 100 2 0 0 0 88 38 84 0 2 0 0 2 0 0 0 100 3 0 0 0 31 10 32 0 2 0 0 0 0 0 0 100 4 0 0 11 217 107 10 1 0 0 0 854 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 6 0 0 0 21 8 16 0 0 0 0 9 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2309 203 116 0 0 0 0 567 0 1 0 99 1 0 0 0 13 3 38 1 0 1 0 1212 0 1 0 99 2 0 0 0 15 1 10 0 1 0 0 0 0 0 0 100 3 0 0 0 110 51 104 0 0 0 0 1 0 0 0 100 4 0 0 11 219 107 18 0 1 0 0 854 0 0 0 100 5 0 0 0 9 2 2 0 0 0 0 0 0 0 0 100 6 0 0 0 19 7 14 0 0 0 0 8 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2310 202 124 3 1 0 0 577 0 0 0 99 1 0 0 0 14 3 40 1 1 1 0 1217 0 0 0 99 2 0 0 0 13 2 8 0 0 0 0 2 0 0 0 100 3 0 0 0 111 52 108 0 0 0 0 4 0 0 0 100 4 0 0 11 217 107 10 1 0 0 0 854 0 0 0 100 5 0 0 0 15 7 4 0 0 1 0 1 0 0 0 100 6 0 0 0 26 8 20 0 0 0 0 14 0 0 0 100 7 21 0 0 15 3 12 0 0 0 0 11 0 0 0 100 March 2, 2026 at 06:58:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2314 203 118 1 0 0 0 576 0 1 0 99 1 0 0 0 11 2 36 1 0 0 0 1206 0 0 0 99 2 0 0 0 12 1 8 0 1 0 0 0 0 0 0 100 3 0 0 0 108 51 104 0 0 2 0 1 0 0 0 100 4 0 0 11 221 108 16 0 0 0 0 854 0 0 0 100 5 0 0 0 16 0 18 0 1 1 0 18 0 0 0 100 6 0 0 0 21 8 16 0 0 0 0 9 0 0 0 100 7 0 0 0 8 0 6 0 0 4 0 0 0 0 0 100 March 2, 2026 at 06:58:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2304 202 116 0 0 0 0 565 0 0 0 99 1 0 0 0 10 2 36 0 0 1 0 1205 0 0 0 99 2 0 0 0 15 2 8 0 0 0 0 2 0 0 0 100 3 0 0 0 105 50 102 0 1 0 0 0 0 0 0 100 4 0 0 11 219 108 14 1 0 0 0 858 0 0 0 100 5 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 6 0 0 0 25 7 24 1 1 0 0 8 0 0 0 100 7 0 0 0 10 2 6 0 0 0 0 4 0 0 0 100 March 2, 2026 at 06:58:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2306 202 112 0 0 0 0 566 0 0 0 100 1 0 0 0 13 3 38 1 0 0 0 1207 0 0 0 99 2 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 3 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 4 0 0 11 216 107 10 0 0 0 0 854 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 21 8 16 0 0 0 0 9 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2307 203 114 0 0 0 0 567 0 0 0 99 1 0 0 0 13 3 38 1 0 0 0 1207 0 0 0 99 2 0 0 0 13 2 8 0 1 0 0 2 0 0 0 100 3 0 0 0 106 50 100 0 0 0 0 0 0 0 0 100 4 0 0 11 217 107 10 1 0 0 0 854 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 23 8 18 0 0 0 0 9 0 0 0 100 7 0 0 0 10 0 10 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2320 204 138 1 1 0 0 584 0 1 0 99 1 0 0 0 15 3 42 1 0 0 0 1237 0 0 0 99 2 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 3 0 0 0 106 50 102 0 0 0 0 0 0 0 0 100 4 0 0 11 218 108 12 0 0 0 0 855 0 0 0 100 5 0 0 0 17 8 2 0 0 0 0 0 0 0 0 100 6 0 0 0 25 8 20 0 0 0 0 12 0 0 0 100 7 0 0 0 10 0 6 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 39 0 17 4027 204 3568 40 168 141 0 9884 9 6 0 85 1 2 0 0 1603 3 3230 46 203 154 0 10323 11 5 0 84 2 1 0 0 1264 2 2540 29 144 142 0 8144 7 4 0 89 3 0 0 0 2039 104 4671 28 180 91 0 16252 8 5 0 86 4 0 0 11 1275 111 2193 25 139 172 0 6351 5 4 0 91 5 3 0 0 1319 7 2677 19 106 122 0 4982 4 3 0 92 6 0 0 0 1371 10 2920 21 139 175 0 7272 7 4 0 89 7 2 0 0 849 3 1769 14 87 90 0 4005 4 3 0 94 March 2, 2026 at 06:58:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 7 6345 212 8458 52 303 157 0 24044 24 15 0 61 1 36 0 0 4465 11 9195 58 331 114 0 22267 19 13 0 68 2 13 0 14 3657 7 7305 46 251 105 0 18747 15 10 0 74 3 11 0 7 4017 18 8404 55 315 111 0 20135 16 11 0 73 4 8 0 7 3025 114 5997 29 246 168 0 16470 16 10 0 74 5 25 0 0 2136 7 4590 24 148 97 0 12844 12 7 0 81 6 7 0 0 3640 13 7530 36 222 118 0 16347 13 9 0 78 7 7 0 0 2320 25 4806 27 132 70 0 10129 9 6 0 84 March 2, 2026 at 06:58:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 3 6524 206 8897 56 372 124 0 23845 22 15 0 63 1 13 0 0 4709 7 9763 71 376 132 0 23388 19 13 0 68 2 7 0 0 3670 10 7656 46 259 124 0 20369 19 12 0 69 3 2 0 14 4184 14 8623 57 321 96 0 18019 15 10 0 75 4 8 0 11 2937 112 5626 33 257 105 0 15884 15 9 0 76 5 6 0 0 1979 17 4278 32 150 111 0 12007 12 7 0 81 6 5 0 0 3465 16 7198 28 240 120 0 15825 12 9 0 79 7 2 0 0 2225 7 4635 27 127 117 0 12888 11 7 0 82 March 2, 2026 at 06:58:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 3 5201 204 6275 46 256 94 0 15556 16 10 0 74 1 9 0 0 3158 6 6476 40 272 74 0 14930 13 9 0 79 2 4 0 0 2335 9 4722 18 161 94 0 10987 10 7 0 83 3 2 0 14 2356 13 4903 36 214 88 0 13921 11 7 0 82 4 6 0 11 2014 121 3711 19 168 79 0 8589 7 5 0 88 5 3 0 0 1518 10 3193 21 92 85 0 10192 9 5 0 86 6 2 0 0 1940 15 4089 18 156 89 0 10191 8 6 0 86 7 2 0 0 1207 28 2382 14 86 47 0 5842 5 3 0 92 March 2, 2026 at 06:58:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 202 113 1 1 0 0 4 0 0 0 100 1 0 0 0 13 1 8 0 0 0 0 8 0 0 0 100 2 0 0 0 11 1 4 0 1 0 0 2 0 0 0 100 3 0 0 14 10 3 8 0 0 0 0 266 0 0 0 100 4 0 0 11 214 106 10 1 1 0 0 559 0 0 0 100 5 0 0 0 17 7 36 1 1 1 0 1207 0 0 0 100 6 0 0 0 36 8 36 1 1 0 0 308 0 0 0 100 7 0 0 0 117 52 117 0 2 0 0 308 0 0 0 100 March 2, 2026 at 06:58:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2453 202 424 2 81 1059 0 11 0 2 0 98 1 0 0 0 131 1 279 3 79 966 0 24 0 2 0 98 2 0 0 0 161 1 328 3 66 864 0 0 0 2 0 98 3 0 0 14 328 171 334 2 71 928 0 270 0 2 0 98 4 0 0 11 345 106 296 2 68 1011 0 564 0 2 0 98 5 0 0 0 305 1 665 3 64 913 1 1210 0 2 0 98 6 0 0 0 185 8 384 4 80 1090 0 310 0 2 0 98 7 0 0 0 254 54 437 3 70 964 0 314 0 2 0 98 March 2, 2026 at 06:58:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 204 118 1 1 0 0 3 0 0 0 99 1 0 0 0 12 2 8 0 1 0 0 6 0 0 0 100 2 0 0 0 9 1 4 0 1 0 0 2 0 0 0 100 3 0 0 14 27 11 24 0 1 0 0 282 0 0 0 100 4 0 0 10 218 107 10 1 0 0 0 560 0 0 0 100 5 0 0 0 9 1 32 1 0 1 0 1205 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 100 46 94 0 1 0 0 301 0 0 0 100 March 2, 2026 at 06:58:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 200 120 0 1 0 0 0 0 0 0 100 1 0 0 0 11 2 4 0 0 0 0 1 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 14 80 38 76 0 1 0 0 273 0 0 0 100 4 0 0 11 257 127 52 0 1 0 0 561 0 0 0 100 5 0 0 0 7 1 32 0 0 0 0 1207 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 12 2 8 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:58:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 14 1 12 0 1 0 0 1 0 0 0 100 2 0 0 0 11 1 6 0 2 0 0 2 0 0 0 100 3 2 0 14 25 11 22 0 0 0 0 277 0 0 0 100 4 0 0 11 314 156 108 1 0 0 0 559 0 0 0 100 5 0 0 0 8 1 32 1 0 0 0 1206 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:58:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 111 1 1 0 0 0 0 1 0 99 1 0 0 0 9 0 6 0 0 0 0 7 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 14 22 9 20 0 0 0 0 275 0 0 0 100 4 0 0 11 316 157 110 0 0 0 0 562 0 0 0 100 5 0 0 0 14 7 32 1 0 0 0 1206 0 0 0 100 6 0 0 0 13 2 8 0 0 0 0 299 0 0 0 100 7 0 0 0 21 4 21 1 2 0 0 313 0 0 0 100 March 2, 2026 at 06:58:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 3 2725 202 887 366 58 37 0 2085 39 3 0 58 1 22 0 0 425 0 727 362 39 49 0 2046 39 2 0 59 2 265 0 7 554 2 1145 535 52 39 0 3047 39 3 0 59 3 8 0 0 473 9 957 422 56 50 0 2498 39 2 0 58 4 527 0 452 641 135 1197 440 59 45 0 3790 38 4 0 58 5 1585 0 0 462 9 846 411 45 50 1 3217 39 3 0 58 6 24 0 0 522 10 996 476 44 38 0 2434 39 2 0 58 7 1 0 0 459 7 809 377 52 50 0 2420 39 2 0 59 March 2, 2026 at 06:58:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 3 2705 204 886 379 106 31 0 2999 43 3 0 53 1 2 0 0 468 20 889 378 87 33 0 2679 43 2 0 54 2 3 0 7 506 29 889 406 75 19 0 2714 44 2 0 54 3 7 0 0 387 5 793 339 95 40 0 3178 44 2 0 54 4 2 0 353 546 110 902 362 110 25 0 3504 43 3 0 54 5 4 0 0 400 3 869 369 116 34 0 4057 44 3 0 54 6 1 0 0 426 5 754 362 87 32 0 2021 45 2 0 53 7 6 0 0 453 7 831 394 95 24 0 3005 44 2 0 54 March 2, 2026 at 06:58:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 102 0 0 0 0 0 0 1 0 99 1 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 2 0 0 7 116 53 112 1 1 0 0 262 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 303 0 0 0 100 4 3 0 17 213 106 8 0 0 0 0 580 0 0 0 100 5 0 0 0 15 2 40 1 2 0 0 1219 0 0 0 100 6 0 0 0 10 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 10 2 6 0 1 0 0 300 0 0 0 100 March 2, 2026 at 06:58:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 102 0 0 0 0 1 0 1 0 99 1 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 2 0 0 7 118 53 114 0 0 0 0 261 0 0 0 100 3 0 0 0 23 8 18 0 1 0 0 303 0 0 0 100 4 0 0 17 220 107 20 0 1 0 0 568 0 0 0 100 5 0 0 0 16 1 40 1 0 0 0 1218 0 0 0 100 6 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 7 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 March 2, 2026 at 06:58:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 106 0 0 0 0 2 0 1 0 99 1 0 0 0 11 1 8 0 0 0 0 8 0 0 0 100 2 0 0 7 115 53 112 0 1 0 0 262 0 0 0 100 3 0 0 0 23 8 18 1 0 0 0 300 0 0 0 100 4 0 0 17 216 106 10 1 1 0 0 565 0 0 0 100 5 0 0 0 32 9 52 1 1 0 0 1218 0 0 0 100 6 0 0 0 10 0 6 0 1 0 0 6 0 0 0 100 7 0 0 0 23 5 24 4 1 0 0 315 0 0 0 100 March 2, 2026 at 06:58:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5380 0 13 2442 204 299 27 76 38 14 2631 29 3 0 68 1 2595 0 3 179 4 312 38 91 63 17 3004 28 2 0 71 2 5702 0 3 397 33 755 92 190 177 10 3650 21 3 0 76 3 4555 0 9 307 10 610 77 178 92 18 3258 23 3 0 74 4 11300 0 89 625 112 962 109 265 205 21 3831 23 5 0 72 5 9376 0 7 419 8 1051 194 297 188 25 4136 23 7 0 70 6 10462 0 31 413 1 1027 166 294 276 18 3190 21 5 0 74 7 9868 0 0 373 4 927 150 279 232 15 3388 18 5 0 77 March 2, 2026 at 06:58:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5086 0 3 3203 216 2000 328 607 3319 1 6507 59 12 0 29 1 811 0 7 492 2 879 165 265 1976 1 4773 76 7 0 16 2 3471 0 0 627 4 1242 180 384 2900 1 4939 67 9 0 24 3 5054 0 7 1059 213 2032 250 552 2468 2 5580 46 9 0 45 4 8862 0 563 1120 112 2327 350 660 3254 1 5675 36 12 0 52 5 9595 0 0 974 10 2458 431 687 3386 4 5516 34 12 0 55 6 4132 0 0 823 9 1745 260 474 2109 2 5601 44 7 0 48 7 4052 0 0 859 10 1905 313 519 3046 4 4756 36 10 0 55 March 2, 2026 at 06:58:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 10 2534 204 537 72 134 197 1 3263 5 3 0 92 1 6 0 8 347 3 782 86 182 215 0 2266 4 3 0 93 2 2 0 7 349 2 735 86 166 189 2 2419 4 2 0 95 3 16 0 7 449 131 665 71 135 228 0 2610 4 2 0 94 4 7 0 144 545 135 653 66 115 232 2 2860 4 2 0 94 5 4 0 0 196 1 368 52 101 210 4 3088 5 2 0 93 6 1 0 0 528 20 1130 94 205 256 2 3779 3 2 0 95 7 31 0 14 254 7 524 76 119 241 2 2915 5 2 0 93 March 2, 2026 at 06:58:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 202 107 1 0 1 0 300 0 1 0 99 1 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 12 1 4 0 1 0 0 0 0 0 0 100 3 0 0 7 12 2 8 0 1 0 0 260 0 0 0 100 4 0 0 18 315 155 108 0 1 0 0 268 0 0 0 100 5 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 24 3 44 3 0 3 0 1716 0 0 0 100 7 0 0 7 26 9 22 0 1 0 0 10 0 0 0 99 March 2, 2026 at 06:58:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 201 109 0 0 0 0 301 0 0 0 99 1 0 0 0 36 3 20 0 1 0 0 8 0 0 0 100 2 0 0 0 30 3 10 0 0 0 0 6 0 0 0 100 3 0 0 7 32 2 14 0 3 0 0 265 0 0 0 100 4 0 0 18 268 125 46 0 1 0 0 267 0 0 0 100 5 0 0 0 90 36 64 0 2 0 0 0 0 0 0 100 6 0 0 0 35 3 48 0 1 0 0 1724 0 0 0 99 7 0 0 112 32 10 29 0 1 0 0 7 0 0 0 100 March 2, 2026 at 06:58:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 201 104 0 1 0 0 300 0 1 0 99 1 0 0 0 8 0 2 0 1 0 0 0 0 0 0 100 2 0 0 0 13 0 12 0 1 0 0 0 0 0 0 100 3 0 0 7 18 2 12 1 0 0 0 260 0 0 0 100 4 0 0 18 214 105 8 0 1 0 0 268 0 0 0 100 5 0 0 0 108 50 100 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 38 1 0 0 0 1716 0 0 0 100 7 0 0 7 27 9 22 0 0 0 0 6 0 0 0 100 March 2, 2026 at 06:58:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 7 2483 206 502 1 104 1657 0 371 0 4 0 96 1 1 0 0 230 20 487 2 110 2034 0 76 0 4 0 96 2 0 0 0 197 6 444 2 106 1808 0 825 0 3 0 97 3 0 0 7 390 204 407 1 92 2020 0 274 0 4 0 96 4 4 0 21 582 105 841 2 136 1731 0 421 0 3 0 97 5 0 0 0 204 14 425 1 94 1894 0 41 0 3 0 96 6 25 0 0 187 6 450 3 123 1902 1 2552 0 4 0 96 7 11 0 0 197 7 421 1 89 1647 0 36 0 3 0 97 March 2, 2026 at 06:58:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2318 209 128 1 0 0 0 309 0 0 0 99 1 0 0 0 12 2 4 0 1 0 0 0 0 0 0 100 2 0 0 0 11 1 6 0 0 1 0 0 0 0 0 100 3 0 0 7 15 3 17 0 2 0 0 260 0 0 0 100 4 0 0 18 217 106 12 0 0 0 0 268 0 0 0 100 5 0 0 0 109 52 104 0 0 0 0 1 0 0 0 100 6 0 0 0 17 4 38 2 0 1 0 1718 0 0 0 100 7 0 0 0 16 4 10 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2323 209 130 0 0 0 0 307 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 19 5 14 0 0 0 0 9 0 0 0 100 3 0 0 7 10 2 8 0 0 1 0 260 0 0 0 100 4 0 0 18 220 106 18 0 1 0 0 268 0 0 0 100 5 0 0 0 105 50 101 0 1 0 0 0 0 0 0 100 6 0 0 0 13 4 38 0 0 1 0 1717 0 0 0 100 7 0 0 0 13 3 10 0 1 0 0 1 0 0 0 100 March 2, 2026 at 06:58:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 208 128 0 0 0 0 306 0 1 0 99 1 0 0 0 11 1 6 0 0 0 0 6 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 11 2 10 1 0 0 0 266 0 0 0 100 4 0 0 18 211 105 6 0 0 0 0 268 0 0 0 100 5 0 0 0 54 27 42 0 1 0 0 1 0 0 0 100 6 0 0 0 81 35 110 1 1 0 0 1730 0 0 0 100 7 0 0 0 15 3 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 3 2327 211 140 0 0 0 0 335 0 1 0 99 1 0 0 0 11 1 10 0 1 0 0 30 0 0 0 100 2 0 0 0 15 2 10 1 2 0 0 29 0 0 0 100 3 0 0 7 10 3 6 0 0 0 0 261 0 0 0 100 4 0 0 18 212 104 6 1 0 1 0 266 0 0 0 100 5 0 0 0 12 1 12 0 1 0 0 22 0 0 0 100 6 0 0 0 116 53 144 1 1 1 0 1716 0 0 0 100 7 0 0 0 19 3 16 0 0 0 0 7 0 0 0 100 March 2, 2026 at 06:58:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2316 204 114 1 2 4 0 306 0 1 0 99 1 0 0 0 6 0 2 0 1 0 0 1 0 0 0 100 2 0 0 0 9 0 2 0 0 1 0 3 0 0 0 100 3 0 0 7 9 2 6 0 1 0 0 260 0 0 0 100 4 0 0 18 216 106 14 0 0 2 0 269 0 0 0 100 5 0 0 0 12 2 8 0 0 2 0 13 0 0 0 100 6 0 0 0 129 58 156 1 2 2 0 1727 0 0 0 99 7 0 0 0 37 3 39 0 2 0 0 6 0 0 0 100 March 2, 2026 at 06:58:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 114 0 0 0 0 300 0 0 0 99 1 22 0 0 8 1 2 0 0 0 0 5 0 0 0 100 2 1 0 0 19 6 14 0 0 0 0 17 0 0 0 100 3 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 4 0 0 18 211 105 6 0 0 0 0 271 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 128 61 152 1 0 0 0 1713 0 0 0 99 7 0 0 0 12 2 8 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 203 126 0 2 0 0 301 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 9 2 4 1 0 0 0 260 0 0 0 100 4 0 0 18 211 105 6 0 0 0 0 268 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 124 59 148 1 0 0 0 1714 0 0 0 99 7 0 0 0 14 2 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 122 0 0 0 0 299 0 1 0 99 1 0 0 0 14 0 14 0 1 0 0 5 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 5 0 0 0 100 3 0 0 7 11 2 10 0 0 0 0 265 0 0 0 100 4 0 0 18 211 105 6 0 0 0 0 267 0 0 0 100 5 0 0 0 13 7 2 0 0 2 0 0 0 0 0 100 6 0 0 0 132 61 160 1 0 0 0 1727 0 0 0 99 7 0 0 0 14 2 12 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2339 232 171 1 2 0 0 301 0 1 0 99 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 3 0 0 7 9 2 6 0 0 0 0 260 0 0 0 100 4 0 0 18 211 105 6 0 0 0 0 268 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 44 19 66 1 0 0 0 1712 0 0 0 100 7 0 0 0 36 12 32 0 3 0 0 0 0 0 0 100 March 2, 2026 at 06:58:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2337 227 166 0 2 5 0 307 0 1 0 99 1 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 2 0 0 0 21 4 18 0 1 1 0 6 0 0 0 100 3 0 0 7 10 3 4 0 0 1 0 260 0 0 0 100 4 0 0 18 212 104 10 0 0 3 0 266 0 0 0 100 5 0 0 0 14 3 8 0 0 1 0 12 0 0 0 100 6 0 0 0 35 13 60 1 0 4 0 1719 0 0 0 99 7 0 0 0 73 29 71 0 4 1 0 3 0 0 0 100 March 2, 2026 at 06:58:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2330 223 150 0 2 0 0 300 0 1 0 99 1 0 0 0 67 30 66 0 2 0 0 2 0 0 0 100 2 0 0 0 16 3 172 0 0 0 0 334 0 0 0 100 3 0 0 7 14 2 14 1 1 0 0 260 0 0 0 100 4 0 0 18 211 105 6 0 0 0 0 268 0 0 0 100 5 0 0 0 14 2 8 1 3 0 0 1 0 0 0 100 6 0 0 0 24 9 48 1 0 0 0 1714 0 0 0 99 7 0 0 0 19 3 14 0 1 0 0 3 0 0 0 100 March 2, 2026 at 06:58:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 203 108 0 0 0 0 300 0 1 0 99 1 0 0 0 49 20 44 0 1 0 0 0 0 0 0 100 2 0 0 0 25 8 22 0 1 0 0 11 0 0 0 100 3 0 0 7 9 2 6 0 0 0 0 262 0 0 0 100 4 0 0 18 213 106 8 0 0 0 0 268 0 0 0 100 5 0 0 0 60 25 54 0 1 0 0 1 0 0 0 100 6 0 0 0 24 9 48 1 0 0 0 1714 0 0 0 100 7 0 0 0 12 2 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 203 115 1 1 0 0 300 0 1 0 99 1 0 0 0 17 1 14 0 0 0 0 6 0 0 0 100 2 0 0 0 107 50 102 0 1 0 0 0 0 0 0 100 3 0 0 7 16 2 15 0 1 0 0 265 0 0 0 100 4 0 0 18 216 105 16 0 1 0 0 268 0 0 0 100 5 0 0 0 14 7 2 0 0 0 0 1 0 0 0 100 6 0 0 0 32 11 58 2 0 0 0 1723 0 0 0 99 7 0 0 0 15 2 10 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 18 0 7 6028 208 7982 94 317 148 0 23965 22 14 0 64 1 19 0 0 4101 11 8316 83 379 115 0 20458 18 12 0 70 2 3 0 0 3361 21 6714 37 223 80 0 15283 14 9 0 78 3 34 0 7 4562 10 9934 74 318 64 0 28231 17 11 0 72 4 8 0 7 2758 113 5248 31 213 108 0 12374 12 8 0 81 5 11 0 14 1943 9 4206 23 118 107 0 11904 11 7 0 82 6 11 0 0 2535 21 5227 43 200 70 0 14199 14 7 0 80 7 141 0 0 1938 7 3979 18 113 49 0 9889 8 5 0 87 March 2, 2026 at 06:58:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 3 6863 209 9812 91 464 720 0 27582 27 18 0 55 1 16 0 0 5110 12 10744 105 540 741 0 26148 22 15 0 63 2 12 0 0 3822 5 7391 81 361 669 0 14762 13 10 0 77 3 3 0 7 4238 136 8621 92 418 681 0 20449 16 12 0 72 4 20 0 4 2845 114 5310 57 319 725 0 12449 12 8 0 79 5 20 0 0 2391 19 5123 32 211 665 0 11915 11 8 0 81 6 9 0 14 3735 11 7949 76 358 728 0 18047 16 11 0 73 7 3 0 0 1878 21 3922 66 246 635 0 10573 8 6 0 86 March 2, 2026 at 06:58:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 7 6563 210 9042 46 362 168 0 21876 21 14 0 66 1 30 0 0 5143 10 10560 49 370 109 0 23410 20 13 0 67 2 10 0 0 3383 13 6979 32 242 106 0 18701 17 10 0 73 3 6 0 0 4094 15 8519 48 288 89 0 19770 16 11 0 73 4 11 0 28 3099 113 6009 41 244 118 0 18763 16 10 0 75 5 6 0 0 2334 11 4943 18 169 83 0 11177 9 6 0 84 6 5 0 0 3020 17 6548 33 226 136 0 17638 16 10 0 74 7 1 0 0 2464 16 5020 18 134 89 0 11876 10 7 0 83 March 2, 2026 at 06:58:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2673 219 760 6 52 6 0 2333 2 2 0 96 1 1 0 0 601 32 1045 4 47 13 0 2028 2 1 0 97 2 5 0 0 429 5 834 3 37 5 0 2186 1 1 0 98 3 1 0 0 357 2 791 1 21 21 0 2269 2 1 0 97 4 0 0 25 514 114 650 4 25 11 0 3228 2 1 0 97 5 1 0 0 163 2 427 1 7 15 0 1280 1 1 0 98 6 1 0 0 304 3 617 4 22 3 0 1053 1 1 0 98 7 0 0 0 201 2 383 1 17 13 0 1252 1 1 0 98 March 2, 2026 at 06:58:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 106 0 0 0 0 0 0 0 0 100 1 0 0 0 113 51 112 0 0 0 0 12 0 0 0 100 2 0 0 0 16 3 10 1 2 0 0 600 0 0 0 100 3 0 0 0 22 6 18 0 0 0 0 10 0 0 0 100 4 0 0 25 227 112 56 1 1 0 0 1949 0 0 0 99 5 1 0 0 17 7 4 0 0 0 0 1 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 0 19 1 16 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 106 0 0 1 0 0 0 0 0 100 1 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 2 0 0 0 13 3 8 0 0 0 0 599 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 25 235 115 58 2 1 0 0 1948 0 0 0 99 5 0 0 0 13 1 14 0 2 0 0 3 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 7 0 0 0 16 1 12 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2387 201 277 0 33 453 0 3 0 2 0 98 1 0 0 0 300 47 522 0 46 393 0 6 0 1 0 99 2 0 0 0 87 4 166 0 27 455 0 608 0 1 0 99 3 0 0 0 229 117 234 0 53 508 0 12 0 1 0 99 4 0 0 28 334 115 277 2 44 508 0 1952 0 2 0 98 5 0 0 0 90 2 166 0 30 361 0 0 0 1 0 99 6 0 0 0 110 1 239 0 53 575 0 0 0 1 0 99 7 0 0 0 103 7 176 0 24 357 0 0 0 1 0 99 March 2, 2026 at 06:58:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 104 0 0 0 0 0 0 0 0 100 1 0 0 0 15 1 10 0 1 0 0 0 0 0 0 100 2 0 0 0 14 3 8 1 0 0 0 600 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 25 227 113 52 1 0 0 0 1948 0 0 0 99 5 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 7 0 0 0 108 51 104 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:58:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 112 0 1 0 0 0 0 0 0 100 1 0 0 0 11 2 4 0 0 0 0 1 0 0 0 100 2 0 0 0 14 3 8 1 0 0 0 601 0 0 0 100 3 4 0 0 17 6 12 0 0 0 0 8 0 0 0 100 4 0 0 25 231 115 56 1 0 1 0 1946 0 0 0 99 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 7 0 0 0 113 51 114 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 120 0 1 0 0 0 0 0 0 100 1 0 0 0 21 5 20 0 0 0 0 39 0 0 0 100 2 0 0 0 13 3 8 0 0 0 0 600 0 0 0 100 3 0 0 0 12 1 8 0 0 0 0 5 0 0 0 100 4 0 0 25 232 114 58 3 0 1 0 1953 0 0 0 99 5 0 0 0 17 8 4 0 0 0 0 1 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 7 0 0 0 113 51 110 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:58:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 18 0 3 2759 202 774 54 121 16 1 2937 25 3 0 72 1 6 0 0 453 6 640 49 129 20 0 3152 26 2 0 72 2 561 0 1 464 7 637 48 116 15 0 4021 27 2 0 71 3 6 0 0 479 19 689 60 120 24 0 3746 23 2 0 74 4 7 0 647 637 121 790 45 122 26 0 5617 17 3 0 80 5 1088 0 7 448 7 645 32 112 26 1 3764 18 2 0 80 6 4 0 0 442 6 664 30 118 16 0 3161 19 2 0 80 7 0 0 0 532 12 852 63 94 18 0 3168 13 2 0 85 March 2, 2026 at 06:58:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2799 215 750 33 126 19 0 3080 28 3 0 69 1 0 0 0 514 7 728 36 135 14 0 3197 38 2 0 60 2 0 0 0 523 10 726 33 116 9 0 4146 23 2 0 75 3 0 0 0 510 6 758 31 130 28 0 4110 24 2 0 74 4 0 0 633 572 110 672 13 128 12 0 5038 15 3 0 82 5 3 0 7 469 14 678 16 121 23 0 3380 13 2 0 86 6 0 0 0 500 10 738 28 136 5 0 3818 20 2 0 78 7 7 0 14 461 12 647 21 100 11 0 2761 14 2 0 84 March 2, 2026 at 06:58:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 3 2668 204 582 23 97 8 0 2519 21 2 0 77 1 0 0 0 450 12 661 27 117 22 0 3212 24 2 0 74 2 0 0 0 398 10 535 28 93 12 0 2544 25 2 0 73 3 4 0 0 411 9 671 30 118 18 0 4860 18 2 0 80 4 0 0 423 507 109 530 14 105 8 0 2810 19 2 0 79 5 0 0 7 412 7 638 20 92 21 0 3309 15 1 0 84 6 0 0 0 381 11 553 27 109 12 0 2787 20 1 0 79 7 5 0 14 404 16 620 18 80 24 0 2595 11 1 0 88 March 2, 2026 at 06:58:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 106 0 1 0 0 5 0 1 0 99 1 0 0 0 18 2 18 0 3 0 0 18 0 0 0 100 2 0 0 0 15 3 8 0 1 0 0 603 0 0 0 100 3 0 0 0 25 6 54 1 1 0 0 1137 0 0 0 99 4 0 0 3 220 104 15 0 3 0 0 303 0 0 0 100 5 1 0 7 11 3 6 1 0 0 0 268 0 0 0 100 6 6 0 0 10 2 7 0 1 0 0 29 0 0 0 100 7 2 0 14 109 52 108 1 2 0 0 281 0 0 0 100 March 2, 2026 at 06:58:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 729 0 116 2345 205 95 1 11 9 14 127 0 1 0 99 1 95 0 0 149 2 156 0 5 7 12 118 0 0 0 100 2 748 0 2 44 3 40 2 7 5 7 7121 2 1 0 97 3 24 0 0 57 8 93 1 8 5 3 1346 0 0 0 99 4 8 0 3 243 104 34 0 4 5 4 383 0 0 0 100 5 1941 0 7 50 8 49 2 8 5 5 609 0 1 0 99 6 16 0 0 42 1 55 0 10 7 10 117 0 0 0 100 7 15 0 14 142 49 144 1 11 6 3 414 0 0 0 100 March 2, 2026 at 06:59:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2355 250 102 0 0 0 0 3 0 0 0 100 1 0 0 0 109 0 104 0 0 0 0 0 0 0 0 100 2 0 0 0 14 3 6 1 0 0 0 601 0 0 0 100 3 0 0 0 30 10 56 1 1 1 0 1217 0 0 0 100 4 0 0 3 215 104 14 0 1 0 0 297 0 0 0 100 5 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 7 0 0 14 20 4 20 0 1 0 0 270 0 0 0 100 March 2, 2026 at 06:59:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 7 2691 220 867 30 64 1 0 1362 3 1 0 96 1 1 0 0 199 30 268 9 19 382 0 2083 4 1 0 94 2 9 0 0 274 5 501 21 47 39 0 2782 4 1 0 95 3 0 0 0 194 14 343 11 26 36 0 3702 5 2 0 93 4 25 0 105 425 104 420 28 41 28 0 2172 3 1 0 95 5 0 0 7 38 3 18 6 3 417 0 3228 6 2 0 93 6 0 0 0 332 4 613 19 47 6 0 1363 3 1 0 96 7 0 0 14 222 3 390 14 29 11 0 1615 4 1 0 95 March 2, 2026 at 06:59:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2323 201 130 0 11 17 0 73 0 1 0 99 1 0 0 7 37 6 34 1 5 13 0 56 1 0 0 99 2 0 0 0 27 3 17 0 2 4 0 678 0 0 0 100 3 1 0 0 28 2 57 3 6 10 0 1137 0 1 0 99 4 0 0 40 320 153 115 0 6 6 0 308 0 2 0 98 5 0 0 21 35 4 39 2 6 12 0 286 0 0 0 100 6 0 0 0 25 3 19 1 3 4 0 62 0 0 0 100 7 3 0 14 37 2 33 0 5 9 0 384 0 0 0 100 March 2, 2026 at 06:59:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 110 0 0 0 0 1 0 0 0 100 1 0 0 0 122 56 116 0 1 0 0 10 0 0 0 100 2 0 0 7 16 3 12 0 2 0 0 601 0 0 0 100 3 0 0 0 14 2 36 0 0 0 0 1112 0 0 0 99 4 0 0 4 217 106 8 0 1 0 0 296 0 0 0 100 5 0 0 7 13 2 9 0 2 0 0 260 0 0 0 100 6 0 0 0 17 2 14 0 1 0 0 0 0 0 0 100 7 0 0 14 9 2 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 201 114 0 0 0 0 1 0 1 0 99 1 0 0 0 136 54 118 0 1 0 0 15 0 0 0 100 2 0 0 0 43 8 20 1 1 0 0 608 0 0 0 100 3 0 0 0 35 2 46 1 1 0 0 1117 0 1 0 99 4 0 0 4 228 103 6 0 0 0 0 301 0 0 0 100 5 0 0 119 18 9 11 0 1 1 0 261 0 0 0 100 6 0 0 0 28 3 6 0 0 0 0 2 0 0 0 100 7 0 0 14 28 2 10 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 116 0 0 0 0 10 0 0 0 100 1 0 0 0 110 51 104 0 0 0 0 1 0 0 0 100 2 0 0 0 27 8 20 1 1 0 0 608 0 0 0 100 3 0 0 0 12 2 36 1 0 2 0 1114 0 0 0 99 4 0 0 4 213 104 4 0 0 0 0 295 0 0 0 100 5 0 0 14 14 4 10 0 0 0 0 278 0 0 0 100 6 0 0 0 12 2 6 0 1 0 0 0 0 0 0 100 7 0 0 14 13 2 14 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:59:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2507 202 536 3 104 1740 0 73 0 4 0 96 1 1 0 0 291 45 526 4 109 1677 0 74 0 3 0 97 2 0 0 0 384 6 817 1 105 1533 1 640 0 3 0 97 3 0 0 0 404 198 503 2 119 1773 1 1180 0 4 0 96 4 0 0 4 388 109 431 1 114 1776 1 1136 0 4 0 96 5 0 0 7 211 9 459 2 96 1505 0 280 0 2 0 97 6 0 0 0 173 3 393 1 118 1536 0 39 0 3 0 97 7 0 0 14 185 2 415 2 95 1798 0 1179 0 3 0 96 March 2, 2026 at 06:59:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2334 230 164 0 3 0 0 0 0 0 0 100 1 0 0 0 20 6 14 1 0 0 0 9 0 0 0 100 2 0 0 0 15 3 8 0 0 0 0 600 0 0 0 100 3 0 0 0 16 1 38 1 0 0 0 1114 0 0 0 100 4 0 0 4 255 125 48 0 1 0 0 295 0 0 0 100 5 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 7 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2329 222 146 0 2 1 0 2 0 0 0 100 1 0 0 0 80 35 76 0 1 0 0 8 0 0 0 100 2 0 0 0 19 3 16 1 1 0 0 599 0 0 0 100 3 0 0 0 8 1 34 1 1 1 0 1112 0 0 0 100 4 0 0 4 219 104 12 0 2 0 0 294 0 0 0 100 5 0 0 7 10 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 11 3 6 0 0 0 0 2 0 0 0 100 7 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2339 232 170 0 2 0 0 3 0 1 0 99 1 0 0 0 72 29 72 0 1 0 0 27 0 0 0 100 2 0 0 0 16 3 10 1 0 0 0 600 0 0 0 100 3 0 0 0 19 1 50 0 1 2 0 1118 0 0 0 100 4 0 0 4 222 104 18 0 0 0 0 301 0 0 0 100 5 0 0 7 21 11 10 0 1 0 0 262 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 7 0 0 14 11 2 8 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2330 223 146 0 1 0 0 6 0 0 0 100 1 0 0 0 75 32 70 0 1 1 0 18 0 0 0 100 2 0 0 0 22 4 20 0 2 0 0 608 0 0 0 100 3 0 0 0 8 1 32 1 0 0 0 1113 0 0 0 100 4 0 0 4 232 109 28 0 2 0 0 304 0 0 0 100 5 0 0 7 10 2 4 1 0 0 0 260 0 0 0 100 6 0 0 0 15 3 14 0 1 0 0 16 0 0 0 100 7 0 0 14 9 2 4 1 1 0 0 290 0 0 0 100 March 2, 2026 at 06:59:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2309 201 104 0 0 1 0 1 0 0 0 100 1 0 0 0 114 51 112 0 1 2 0 7 0 0 0 100 2 0 0 0 20 5 12 0 1 1 0 610 0 0 0 100 3 21 0 0 18 4 40 1 1 3 0 1118 0 0 0 100 4 0 0 7 245 112 46 0 2 1 0 309 0 0 0 100 5 0 0 7 12 3 6 0 1 2 0 263 0 0 0 100 6 0 0 0 15 3 10 0 0 2 0 0 0 0 0 100 7 0 0 14 9 2 4 0 0 1 0 269 0 0 0 100 March 2, 2026 at 06:59:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 201 106 0 1 0 0 4 0 0 0 100 1 0 0 0 61 25 54 0 3 0 0 0 0 0 0 100 2 0 0 0 65 28 58 1 2 0 0 600 0 0 0 100 3 0 0 0 11 1 34 1 0 1 0 1108 0 0 0 100 4 0 0 4 232 113 26 0 0 0 0 309 0 0 0 100 5 0 0 7 16 3 18 0 1 0 0 260 0 0 0 100 6 0 0 0 15 3 10 0 1 0 0 2 0 0 0 100 7 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 106 0 0 0 0 1 0 0 0 100 1 0 0 0 45 20 40 0 0 0 0 0 0 0 0 100 2 0 0 0 65 28 58 1 1 0 0 600 0 0 0 100 3 0 0 0 8 1 32 1 0 0 0 1107 0 0 0 100 4 0 0 4 239 117 34 0 1 0 0 304 0 0 0 100 5 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 15 1 10 0 0 0 0 0 0 0 0 100 7 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 0 2 0 0 2 0 0 0 100 1 0 0 0 18 4 18 0 0 0 0 16 0 0 0 100 2 0 0 0 13 3 8 0 0 0 0 601 0 0 0 100 3 0 0 0 12 1 38 0 0 0 0 1113 0 0 0 100 4 0 0 4 271 132 66 0 1 0 0 311 0 0 0 100 5 0 0 7 19 8 8 1 0 0 0 261 0 0 0 100 6 0 0 0 78 32 78 0 2 0 0 2 0 0 0 100 7 0 0 14 8 1 6 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 21 0 0 0 100 2 0 0 0 14 3 6 0 0 0 0 600 0 0 0 100 3 0 0 0 10 1 34 1 0 0 0 1110 0 0 0 100 4 0 0 4 232 113 26 0 1 0 0 305 0 0 0 100 5 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 109 51 104 0 0 0 0 0 0 0 0 100 7 0 0 14 10 1 14 0 2 0 0 266 0 0 0 100 March 2, 2026 at 06:59:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 202 116 0 0 0 0 3 0 0 0 100 1 0 0 0 12 2 8 0 0 1 0 5 0 0 0 100 2 0 0 0 18 3 16 1 0 2 0 606 0 0 0 100 3 0 0 0 12 2 38 1 1 1 0 1109 0 0 0 99 4 0 0 4 231 111 26 1 0 4 0 306 0 0 0 100 5 0 0 7 10 3 6 0 0 0 0 261 0 0 0 100 6 0 0 0 114 52 112 0 1 0 0 2 0 0 0 100 7 0 0 14 6 1 4 0 0 1 0 288 0 0 0 100 March 2, 2026 at 06:59:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 200 120 0 1 0 0 0 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 16 3 10 1 0 0 0 601 0 0 0 100 3 0 0 0 10 1 34 1 0 0 0 1110 0 0 0 100 4 0 0 4 232 113 26 0 0 0 0 305 0 0 0 100 5 0 0 7 9 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 7 0 0 14 7 1 4 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:59:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 204 120 0 0 0 0 5 0 0 0 99 1 0 0 0 15 2 16 0 1 0 0 1 0 0 0 100 2 0 0 0 101 46 96 0 1 0 0 599 0 0 0 100 3 0 0 0 8 1 32 1 0 1 0 1108 0 0 0 100 4 0 0 4 228 111 22 0 0 0 0 304 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 261 0 0 0 100 6 0 0 0 23 9 18 0 1 0 0 2 0 0 0 100 7 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 116 0 0 0 0 1 0 0 0 100 1 0 0 0 17 3 18 0 0 0 0 17 0 0 0 100 2 0 0 0 113 53 109 0 2 0 0 600 0 0 0 100 3 0 0 0 13 1 38 1 0 1 0 1112 0 0 0 100 4 0 0 4 232 112 26 0 0 0 0 311 0 0 0 100 5 0 0 7 19 12 6 0 0 0 0 261 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 14 10 1 8 0 0 0 0 266 0 0 0 100 March 2, 2026 at 06:59:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 197 0 3 6570 206 8750 75 354 137 0 21886 22 14 0 64 1 42 0 7 4958 8 10843 83 405 113 0 30850 21 14 0 65 2 67 0 0 3358 16 6893 59 260 77 0 20096 16 10 0 73 3 33 0 0 4523 7 9409 100 370 109 0 20277 16 11 0 73 4 8 0 4 2697 117 5169 41 252 140 0 14697 13 8 0 78 5 7 0 0 2076 9 4284 35 131 95 0 11173 11 7 0 82 6 312 0 0 2366 9 5003 33 193 76 0 14754 12 8 0 80 7 11 0 14 2155 25 4375 31 113 100 0 11107 12 6 0 82 March 2, 2026 at 06:59:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 40 0 21 6774 208 9420 111 503 730 0 25418 24 17 0 59 1 18 0 7 4912 13 9911 104 553 672 0 22441 19 14 0 67 2 11 0 0 3939 14 8138 63 350 652 0 19066 17 12 0 70 3 20 0 0 4194 158 8454 97 447 779 0 19758 17 13 0 70 4 45 0 7 3069 111 5929 58 374 722 0 13965 14 10 0 76 5 8 0 0 2504 15 5292 44 254 655 0 11598 11 8 0 81 6 13 0 0 3066 13 6373 33 356 671 0 15443 12 10 0 79 7 17 0 0 1984 12 4203 45 220 646 0 11788 10 8 0 82 March 2, 2026 at 06:59:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 3 6355 210 8579 60 347 173 0 24759 24 16 0 60 1 10 0 7 4679 16 9884 60 374 117 0 23824 20 13 0 66 2 4 0 0 3441 14 7081 27 238 99 0 16976 15 10 0 75 3 5 0 0 4407 5 9236 53 307 105 0 19765 16 11 0 73 4 6 0 3 3021 123 5871 41 262 97 0 15396 15 9 0 76 5 6 0 0 1934 8 3999 16 142 124 0 12243 11 7 0 82 6 18 0 0 2773 17 5809 33 227 80 0 14798 13 8 0 78 7 10 0 14 2476 16 5116 28 156 79 0 11646 10 7 0 83 March 2, 2026 at 06:59:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2635 208 813 1 34 10 0 2084 2 2 0 96 1 4 0 0 475 3 1007 7 48 2 0 3511 2 2 0 96 2 1 0 0 291 2 551 3 29 3 0 1344 1 1 0 98 3 2 0 7 502 6 1025 4 33 1 0 2227 1 1 0 98 4 0 0 4 480 116 577 3 24 19 0 2402 2 1 0 96 5 1 0 0 236 2 463 5 18 8 0 1188 1 1 0 98 6 1 0 0 230 4 440 4 18 4 0 1272 1 1 0 98 7 1 0 14 268 44 439 2 16 2 0 1337 1 1 0 99 March 2, 2026 at 06:59:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2354 250 206 0 0 0 0 0 0 0 0 100 1 0 0 0 20 2 52 1 2 0 0 1127 0 0 0 100 2 0 0 0 17 4 10 0 1 0 0 305 0 0 0 100 3 0 0 7 21 6 18 0 0 0 0 562 0 0 0 100 4 0 0 3 230 111 24 1 1 0 0 316 0 0 0 100 5 0 0 0 12 6 4 0 1 0 0 1 0 0 0 100 6 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 7 0 0 14 21 3 18 0 0 0 0 267 0 0 0 100 March 2, 2026 at 06:59:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 220 142 0 1 0 0 0 0 0 0 100 1 0 0 0 8 1 32 1 0 0 0 1117 0 0 0 100 2 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 3 0 0 7 13 4 8 0 0 0 0 553 0 0 0 100 4 0 0 4 292 143 86 0 1 0 0 315 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 7 0 0 14 16 2 14 0 0 0 0 269 0 0 0 100 March 2, 2026 at 06:59:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2523 209 551 0 54 436 0 0 0 1 0 99 1 0 0 0 118 2 275 1 57 550 0 1125 0 1 0 99 2 0 0 0 157 26 263 1 42 435 0 303 0 1 0 99 3 0 0 7 240 130 234 1 51 468 0 560 0 1 0 99 4 0 0 4 360 133 254 1 48 489 0 314 0 1 0 99 5 0 0 0 104 2 219 0 42 435 0 1 0 1 0 99 6 0 0 0 113 0 240 0 53 510 0 3 0 1 0 99 7 0 0 14 104 3 217 0 45 462 0 271 0 1 0 99 March 2, 2026 at 06:59:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 204 108 0 0 0 0 0 0 0 0 100 1 0 0 0 8 1 32 1 0 0 0 1118 0 0 0 100 2 0 0 0 19 5 14 0 1 0 0 304 0 0 0 100 3 0 0 7 17 4 18 0 1 0 0 553 0 0 0 100 4 0 0 4 229 112 22 0 0 0 0 310 0 0 0 100 5 0 0 0 6 0 2 0 0 0 0 1 0 0 0 100 6 0 0 0 89 41 86 0 2 0 0 0 0 0 0 100 7 0 0 14 25 7 22 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:59:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 102 0 0 0 0 0 0 0 0 100 1 0 0 0 8 1 32 1 0 1 0 1116 0 0 0 100 2 0 0 0 15 3 8 0 0 0 0 304 0 0 0 100 3 0 0 7 14 4 12 0 1 1 0 554 0 0 0 100 4 0 0 4 228 111 20 1 1 1 0 309 0 0 0 100 5 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 6 1 0 0 18 2 14 0 0 0 0 2 0 0 0 100 7 0 0 14 109 53 106 0 0 0 0 268 0 0 0 100 March 2, 2026 at 06:59:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 106 0 0 0 0 0 0 0 0 100 1 0 0 0 16 3 46 1 0 0 0 1133 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 3 0 0 7 17 4 16 0 0 0 0 559 0 0 0 100 4 0 0 4 294 141 94 0 2 0 0 316 0 0 0 100 5 0 0 0 14 8 2 0 0 0 0 1 0 0 0 100 6 0 0 0 14 0 10 0 0 0 0 0 0 0 0 100 7 0 0 14 51 22 50 0 1 0 0 266 0 0 0 100 March 2, 2026 at 06:59:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 330 0 3 2779 202 768 60 132 23 1 3687 23 4 0 74 1 0 0 0 511 8 764 61 142 21 0 4971 31 3 0 66 2 4 0 0 518 7 842 84 136 17 0 3948 26 3 0 72 3 10 0 7 543 30 810 69 153 27 1 4881 26 3 0 72 4 1 0 549 661 118 820 60 155 16 0 4040 28 3 0 70 5 18 0 0 459 8 676 20 117 12 0 3617 16 2 0 82 6 278 0 0 500 5 740 35 136 20 0 4064 20 2 0 77 7 744 0 14 454 10 664 35 105 18 0 3572 13 2 0 85 March 2, 2026 at 06:59:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 28 2740 206 652 33 103 13 0 3682 28 3 0 69 1 0 0 0 535 11 821 31 142 20 0 4681 27 3 0 70 2 0 0 0 452 10 625 26 125 13 0 3150 24 2 0 74 3 5 0 0 449 8 710 30 145 26 0 4653 23 2 0 75 4 0 0 427 663 114 790 22 146 14 0 4125 18 3 0 79 5 0 0 0 477 6 774 22 113 22 0 3761 19 2 0 79 6 0 0 0 445 11 669 31 126 20 0 3354 24 2 0 74 7 0 0 0 465 19 688 25 98 18 0 2886 12 2 0 86 March 2, 2026 at 06:59:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2680 204 618 25 85 11 0 2499 16 2 0 82 1 3 0 7 370 8 544 31 96 12 0 2970 25 2 0 74 2 0 0 14 389 9 614 31 105 30 0 4025 20 2 0 78 3 0 0 0 322 18 418 26 87 4 0 2995 27 2 0 72 4 0 0 340 583 134 634 20 102 13 0 3627 15 2 0 83 5 0 0 0 369 6 532 18 93 14 0 2531 13 1 0 86 6 0 0 0 321 5 464 20 82 25 0 2581 15 1 0 84 7 0 0 0 291 3 443 10 66 8 0 2101 11 1 0 88 March 2, 2026 at 06:59:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2325 206 122 0 4 0 0 20 0 1 0 99 1 0 0 7 22 5 14 0 2 0 0 274 0 0 0 100 2 2 0 14 29 4 54 1 2 0 0 1409 0 0 0 100 3 0 0 0 16 3 11 0 3 3 0 608 0 0 0 100 4 7 0 17 259 125 52 0 3 2 0 310 0 0 0 100 5 0 0 0 76 30 74 0 2 0 0 8 0 0 0 100 6 0 0 0 13 1 7 0 3 0 0 2 0 0 0 100 7 0 0 0 11 0 8 0 1 0 0 8 0 0 0 100 March 2, 2026 at 06:59:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 748 0 5 2351 207 94 2 11 11 9 6546 2 1 0 96 1 56 0 7 187 35 200 1 14 4 4 409 0 0 0 100 2 26 0 14 49 4 79 2 6 6 3 1619 0 0 0 99 3 30 0 0 57 6 65 1 12 7 10 724 0 0 0 100 4 1879 0 3 255 104 46 2 11 3 2 627 0 1 0 99 5 13 0 0 82 27 72 0 7 7 2 63 0 0 0 100 6 722 0 114 20 1 51 0 7 8 13 115 0 0 0 99 7 80 0 0 47 0 66 0 9 4 14 89 0 0 0 100 March 2, 2026 at 06:59:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2329 212 130 1 0 0 0 22 0 1 0 99 1 0 0 7 52 23 48 0 1 0 0 281 0 0 0 100 2 0 0 14 14 4 38 1 0 1 0 1475 0 0 0 100 3 0 0 0 13 3 10 0 1 0 0 597 0 0 0 100 4 0 0 3 219 104 12 0 0 0 0 301 0 0 0 100 5 0 0 0 71 30 68 0 1 0 0 18 0 0 0 100 6 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 7 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:59:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2764 209 1013 39 109 45 1 2922 4 2 0 94 1 0 0 7 277 2 494 19 44 168 0 2658 6 1 0 92 2 0 0 14 326 5 674 21 61 104 0 4051 4 2 0 94 3 40 0 0 255 5 476 27 63 123 4 3522 5 2 0 93 4 14 0 136 658 109 916 29 98 33 0 2662 3 3 0 94 5 0 0 0 196 46 254 7 20 214 1 3127 6 2 0 92 6 0 0 12 238 2 431 12 45 120 1 2729 4 1 0 94 7 2 0 0 163 0 279 11 28 125 0 2739 5 1 0 94 March 2, 2026 at 06:59:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 107 0 3 0 0 11 0 1 0 99 1 0 0 7 19 3 10 0 2 0 0 260 0 0 0 100 2 2 0 14 15 4 40 1 0 0 0 1386 0 0 0 100 3 0 0 0 16 4 10 0 0 0 0 594 0 0 0 100 4 0 0 4 213 103 4 0 1 0 0 300 0 0 0 100 5 0 0 0 125 56 116 0 1 0 0 10 0 0 0 100 6 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 7 0 0 7 11 2 6 0 1 0 0 5 0 0 0 100 March 2, 2026 at 06:59:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2308 201 75 0 5 0 0 0 0 1 0 99 1 0 0 7 76 3 52 1 1 0 0 261 0 0 0 100 2 0 0 14 28 3 38 1 0 1 0 1383 0 0 0 100 3 0 0 0 30 4 8 0 0 0 0 594 0 0 0 100 4 0 0 4 240 107 16 0 2 1 0 308 0 0 0 100 5 0 0 0 134 56 113 1 1 0 0 6 0 0 0 100 6 0 0 0 24 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 28 0 6 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2306 201 104 0 1 0 0 0 0 1 0 99 1 0 0 7 35 5 38 1 3 0 0 298 0 0 0 100 2 0 0 14 101 45 127 1 4 0 0 1382 0 0 0 100 3 0 0 0 22 4 16 0 0 0 0 599 0 0 0 100 4 0 0 4 227 108 20 0 1 0 0 307 0 0 0 100 5 0 0 0 36 16 22 0 1 0 0 10 0 0 0 100 6 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 12 1 6 0 0 0 0 1 0 0 0 100 March 2, 2026 at 06:59:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2313 202 43 0 7 0 0 53 0 1 0 99 1 0 0 7 88 2 80 0 1 1 0 271 0 0 0 100 2 0 0 14 25 3 54 1 1 0 0 1402 0 0 0 99 3 0 0 0 28 6 33 0 2 3 0 648 0 0 0 100 4 0 0 4 320 156 121 1 2 0 0 366 0 0 0 100 5 0 0 0 31 7 35 2 2 4 0 836 0 0 0 99 6 0 0 0 25 2 35 0 7 0 0 159 0 0 0 100 7 0 0 0 16 1 17 1 3 0 0 827 0 0 0 100 March 2, 2026 at 06:59:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2499 207 498 4 107 1657 0 9 0 4 0 96 1 0 0 7 226 3 480 2 117 1706 0 260 0 4 0 96 2 0 0 14 212 4 476 4 101 1638 0 1383 0 4 0 96 3 0 0 0 371 196 437 4 90 1721 0 593 0 4 0 96 4 0 0 4 578 152 749 5 137 1872 1 300 0 3 0 97 5 0 0 0 185 3 399 3 98 1649 0 0 0 4 0 96 6 0 0 0 194 3 418 3 102 1620 0 0 0 4 0 96 7 0 0 0 236 1 518 2 102 1555 0 0 0 3 0 97 March 2, 2026 at 06:59:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 207 84 0 2 0 0 6 0 1 0 99 1 0 0 7 78 33 72 1 2 0 0 261 0 0 0 100 2 0 0 14 25 3 58 1 2 0 0 1381 0 0 0 100 3 0 0 0 20 5 12 1 0 0 0 596 0 0 0 100 4 0 0 4 217 107 10 0 0 0 0 308 0 0 0 100 5 0 0 0 46 20 38 0 0 0 0 0 0 0 0 100 6 0 0 0 40 1 32 0 0 0 0 0 0 0 0 100 7 0 0 0 8 1 4 0 0 0 0 2 0 0 0 100 March 2, 2026 at 06:59:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2318 208 116 1 0 0 0 10 0 1 0 99 1 0 0 7 110 52 106 0 0 0 0 260 0 0 0 100 2 0 0 14 19 4 46 1 0 1 0 1388 0 0 0 100 3 0 0 0 19 4 14 1 1 0 0 595 0 0 0 100 4 0 0 4 212 104 6 0 1 0 0 301 0 0 0 100 5 0 0 0 6 0 2 0 0 0 0 1 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:59:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2324 208 122 0 1 0 0 23 0 1 0 99 1 1 0 7 129 56 132 1 1 0 0 288 0 0 0 100 2 0 0 14 20 3 50 1 1 0 0 1393 0 0 0 100 3 0 0 0 26 3 23 1 0 0 0 600 0 0 0 100 4 0 0 4 226 107 24 2 1 0 0 311 0 0 0 100 5 0 0 0 15 7 2 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 1 0 0 0 100 7 0 0 0 10 0 8 0 1 0 0 24 0 0 0 100 March 2, 2026 at 06:59:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 202 112 0 1 0 0 13 0 1 0 99 1 0 0 7 124 59 122 0 0 0 0 275 0 0 0 100 2 0 0 14 15 3 40 1 1 0 0 1383 0 0 0 100 3 0 0 0 18 3 14 0 1 0 0 595 0 0 0 100 4 0 0 4 221 107 12 0 2 0 0 304 0 0 0 100 5 0 0 0 11 0 12 0 1 1 0 3 0 0 0 100 6 0 0 0 10 1 8 0 0 0 0 7 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 3 0 0 0 100 March 2, 2026 at 06:59:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 114 0 0 0 0 0 0 1 0 99 1 0 0 7 124 59 120 2 1 0 0 267 0 0 0 100 2 0 0 14 14 3 40 1 0 1 0 1381 0 0 0 100 3 0 0 0 15 4 10 1 0 4 0 594 0 0 0 100 4 0 0 4 218 106 14 0 0 1 0 307 0 0 0 100 5 0 0 0 8 1 4 0 0 1 0 1 0 0 0 100 6 21 0 0 16 4 12 0 0 1 0 10 0 0 0 100 7 0 0 0 7 0 4 0 1 0 0 5 0 0 0 100 March 2, 2026 at 06:59:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 112 0 0 0 0 0 0 1 0 99 1 0 0 7 120 58 116 0 0 0 0 269 0 0 0 100 2 0 0 14 18 4 44 1 0 0 0 1375 0 0 0 100 3 0 0 0 13 4 8 0 0 0 0 595 0 0 0 100 4 0 0 4 209 103 2 0 0 0 0 300 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 7 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:59:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 201 113 0 1 0 0 0 0 1 0 99 1 0 0 7 120 58 116 0 0 0 0 269 0 0 0 100 2 0 0 14 14 3 38 1 0 0 0 1374 0 0 0 100 3 0 0 0 15 4 10 0 1 0 0 593 0 0 0 100 4 0 0 4 217 106 8 1 0 0 0 307 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 11 1 6 0 1 0 0 0 0 0 0 100 7 0 0 0 11 0 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 114 0 0 0 0 0 0 1 0 99 1 0 0 7 98 45 96 0 0 0 0 282 0 0 0 100 2 0 0 14 42 18 70 0 1 0 0 1375 0 0 0 100 3 0 0 0 18 4 14 0 0 0 0 599 0 0 0 100 4 0 0 4 211 103 6 0 0 0 0 307 0 0 0 100 5 0 0 0 12 6 0 0 0 0 0 0 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 13 2 10 0 1 0 0 2 0 0 0 100 March 2, 2026 at 06:59:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2313 202 128 1 1 0 0 5 0 1 0 99 1 0 0 7 25 9 20 2 0 0 0 273 0 0 0 100 2 0 0 14 112 53 138 1 0 0 0 1373 0 0 0 100 3 0 0 0 18 5 14 0 1 1 0 598 0 0 0 100 4 0 0 4 216 106 10 0 1 0 0 307 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 10 1 8 0 0 0 0 7 0 0 0 100 7 0 0 0 8 0 4 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:59:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2307 201 114 0 0 1 0 0 0 1 0 99 1 0 0 7 33 11 32 0 1 1 0 272 0 0 0 100 2 0 0 14 116 54 138 1 0 2 0 1374 0 0 0 99 3 0 0 0 17 5 10 0 0 3 0 594 0 0 0 100 4 0 0 7 215 104 12 0 1 2 0 301 0 0 0 100 5 0 0 0 9 1 2 0 0 2 0 0 0 0 0 100 6 0 0 0 13 3 6 0 0 2 0 0 0 0 0 100 7 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 March 2, 2026 at 06:59:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 114 0 1 0 0 11 0 1 0 99 1 0 0 7 20 8 16 0 0 0 0 269 0 0 0 100 2 0 0 14 58 26 82 1 0 0 0 1374 0 0 0 100 3 0 0 0 70 32 66 0 1 0 0 596 0 0 0 100 4 0 0 4 216 106 8 1 0 0 0 305 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 8 1 4 0 0 0 0 5 0 0 0 100 March 2, 2026 at 06:59:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 112 0 0 0 0 0 0 0 0 100 1 0 0 7 23 8 18 1 0 0 0 269 0 0 0 100 2 0 0 14 17 3 48 1 1 0 0 1374 0 0 0 100 3 0 0 0 54 23 50 0 0 0 0 599 0 0 0 100 4 3 0 4 215 106 8 0 0 0 0 306 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 69 31 66 0 1 0 0 0 0 0 0 100 7 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 06:59:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 3 2325 201 123 0 3 0 0 822 0 1 0 99 1 3 0 7 34 11 38 1 1 0 0 295 0 0 0 100 2 0 0 14 22 3 54 1 1 2 0 1420 0 0 0 100 3 73 0 0 33 4 38 2 4 12 0 1930 2 0 0 98 4 15 0 4 229 108 25 0 3 0 0 361 0 0 0 100 5 0 0 0 17 8 6 0 1 0 0 1 0 0 0 100 6 3 0 0 427 52 1169 1 2 0 0 6102 1 1 0 98 7 0 0 0 10 0 6 0 0 0 0 5 0 0 0 100 March 2, 2026 at 06:59:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 71 0 7 6805 207 9615 84 390 164 0 26819 24 16 0 60 1 238 0 7 5174 21 10581 93 448 92 0 21591 18 12 0 69 2 41 0 14 3366 16 6886 48 270 110 0 17628 16 10 0 74 3 8 0 0 4192 17 8873 68 329 110 0 21970 20 11 0 69 4 4 0 7 2806 122 5181 40 252 106 0 12498 12 7 0 81 5 12 0 0 2057 12 4184 25 149 68 0 11521 10 6 0 84 6 11 0 0 3529 17 7707 42 244 113 0 20440 16 11 0 73 7 35 0 0 2061 10 4396 25 123 80 0 12322 11 7 0 83 March 2, 2026 at 06:59:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 3 6597 208 8942 89 444 718 0 23581 23 16 0 61 1 23 0 7 4746 11 9802 91 525 818 0 23439 21 14 0 65 2 6 0 0 3475 12 7161 71 373 640 0 18135 17 12 0 71 3 8 0 0 4379 145 9213 111 434 684 0 20450 17 13 0 70 4 4 0 18 3222 118 6285 41 362 731 0 14543 12 9 0 79 5 8 0 0 2262 18 4781 44 232 750 0 15403 13 9 0 78 6 27 0 0 3598 13 7584 50 342 819 0 15506 12 10 0 78 7 2 0 0 2261 10 4797 70 254 579 0 10207 9 7 0 85 March 2, 2026 at 06:59:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 20 0 7 6803 208 9763 56 381 131 0 27272 25 16 0 58 1 8 0 2 4588 15 9359 67 429 110 0 22270 20 12 0 68 2 16 0 0 4172 8 8689 37 271 130 0 19218 18 12 0 71 3 10 0 7 3882 18 8141 43 323 130 0 19914 17 11 0 73 4 6 0 7 2820 116 5381 32 232 111 0 14107 13 8 0 78 5 0 0 14 2217 12 4655 23 143 118 0 14049 11 7 0 82 6 4 0 0 2582 10 5381 24 224 88 0 14269 12 8 0 80 7 7 0 0 2504 17 5108 20 120 86 0 10112 9 6 0 85 March 2, 2026 at 06:59:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 102 0 3 0 0 0 0 0 0 100 1 0 0 0 10 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 15 5 8 1 0 0 0 260 0 0 0 100 4 0 0 4 215 106 8 0 0 0 0 4 0 0 0 100 5 0 0 14 75 33 99 1 2 0 0 1985 0 0 0 99 6 0 0 0 62 27 56 0 1 0 0 0 0 0 0 100 7 0 0 0 11 0 6 0 1 0 0 0 0 0 0 100 March 2, 2026 at 06:59:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2313 201 118 0 2 0 0 0 0 1 0 99 1 0 0 0 17 4 16 0 0 0 0 313 0 0 0 100 2 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 3 0 0 7 20 4 16 0 0 0 0 265 0 0 0 100 4 0 0 4 214 104 10 0 0 0 0 11 0 0 0 100 5 0 0 14 39 17 58 1 0 1 0 1993 0 0 0 99 6 0 0 0 109 50 104 0 2 0 0 0 0 0 0 100 7 0 0 0 15 1 12 0 1 0 0 1 0 0 0 100 March 2, 2026 at 07:00:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 206 118 0 3 0 0 0 0 1 0 99 1 0 0 0 17 2 18 1 2 0 0 300 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 18 6 14 0 0 0 0 266 0 0 0 100 4 0 0 4 216 106 10 0 1 0 0 10 0 0 0 100 5 0 0 14 30 12 56 2 0 1 0 1990 0 0 0 99 6 0 0 0 104 45 99 0 3 0 0 7 0 0 0 100 7 0 0 0 9 0 6 0 0 1 0 3 0 0 0 100 March 2, 2026 at 07:00:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2432 250 365 0 31 395 0 0 0 1 0 99 1 0 0 0 88 4 172 0 41 377 0 300 0 1 0 99 2 0 0 0 79 2 161 0 46 429 0 0 0 1 0 99 3 0 0 7 183 94 187 0 40 442 0 260 0 1 0 99 4 0 0 4 285 103 176 0 43 428 0 0 0 1 0 99 5 0 0 14 184 10 381 1 42 391 0 1987 0 1 0 99 6 0 0 0 92 1 188 0 47 482 0 0 0 1 0 99 7 0 0 0 82 1 163 0 30 410 0 0 0 1 0 99 March 2, 2026 at 07:00:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2325 220 148 0 2 0 0 0 0 1 0 99 1 0 0 0 15 3 10 0 2 0 0 300 0 0 0 100 2 0 0 0 12 0 12 0 1 0 0 0 0 0 0 100 3 0 0 7 15 5 10 1 0 0 0 261 0 0 0 100 4 0 0 4 215 106 8 0 0 0 0 4 0 0 0 100 5 0 0 14 26 11 52 1 0 0 0 1987 0 0 0 99 6 0 0 0 69 30 64 0 1 0 0 0 0 0 0 100 7 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 112 0 1 0 0 0 0 0 0 100 1 0 0 0 14 4 8 0 0 0 0 301 0 0 0 100 2 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 3 0 0 7 18 4 20 0 1 0 0 261 0 0 0 100 4 0 0 4 215 106 8 0 0 0 0 4 0 0 0 100 5 0 0 14 27 11 52 2 0 1 0 1985 0 0 0 99 6 0 0 0 20 7 12 0 0 0 0 0 0 0 0 100 7 0 0 0 93 43 90 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:00:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 3 2338 200 211 24 19 6 1 607 2 1 0 97 1 0 0 0 44 7 70 6 16 1 0 645 2 0 0 98 2 0 0 0 24 0 44 11 13 1 0 352 2 0 0 98 3 429 0 7 54 5 116 25 12 7 1 621 2 0 0 98 4 93 0 32 234 106 90 14 18 6 0 588 2 0 0 98 5 0 0 14 70 18 129 6 17 2 0 2275 2 0 0 97 6 0 0 0 22 0 67 6 7 3 0 166 2 0 0 98 7 1354 0 0 125 50 151 7 14 4 2 467 2 1 0 98 March 2, 2026 at 07:00:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 4 2740 212 760 41 130 34 0 3411 24 3 0 73 1 0 0 0 448 11 703 43 132 30 0 4339 32 3 0 66 2 4 0 0 410 6 671 34 110 37 0 3493 30 2 0 67 3 9 0 7 507 12 852 50 165 36 0 4669 23 2 0 74 4 0 0 198 629 115 690 36 134 29 0 3438 23 2 0 75 5 3 0 14 609 18 1136 42 129 26 0 5837 10 2 0 88 6 23 0 0 470 5 806 24 117 45 0 3551 17 2 0 81 7 5 0 0 412 9 672 20 79 33 0 3057 17 2 0 81 March 2, 2026 at 07:00:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2793 205 789 39 131 22 0 3587 27 3 0 70 1 0 0 0 461 10 704 34 127 41 0 3428 31 2 0 66 2 0 0 0 451 9 668 34 111 34 0 2828 31 2 0 67 3 0 0 0 526 20 818 35 141 43 0 4296 27 2 0 70 4 0 0 347 594 111 665 28 136 20 0 4088 18 2 0 80 5 0 0 14 603 10 1104 67 130 36 0 5472 13 2 0 85 6 3 0 0 418 4 707 19 124 25 0 3951 17 2 0 82 7 0 0 0 417 9 599 19 87 27 0 3386 12 2 0 86 March 2, 2026 at 07:00:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2626 204 556 24 87 15 0 2184 26 2 0 72 1 0 0 1 318 7 479 28 95 25 0 2992 21 2 0 77 2 3 0 0 325 20 477 12 81 24 0 2213 17 2 0 82 3 0 0 0 359 12 579 31 106 23 0 2987 21 2 0 77 4 0 0 213 480 109 485 21 99 20 0 2412 17 2 0 82 5 0 0 21 448 9 821 42 98 31 0 4894 6 2 0 93 6 0 0 0 310 6 484 21 98 15 0 2928 13 1 0 85 7 0 0 0 291 12 427 9 63 22 0 1783 12 1 0 87 March 2, 2026 at 07:00:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2320 205 122 0 2 0 0 22 0 0 0 99 1 0 0 0 20 3 16 1 0 0 0 317 0 0 0 100 2 0 0 0 107 46 102 0 1 0 0 32 0 0 0 100 3 0 0 0 17 1 18 0 1 0 0 8 0 0 0 100 4 1 0 17 229 109 24 0 6 4 0 10 0 0 0 100 5 3 0 21 20 6 45 1 1 2 0 2220 0 0 0 99 6 7 0 0 11 1 3 0 1 1 0 46 0 0 0 100 7 0 0 0 12 1 7 0 3 0 0 2 0 0 0 100 March 2, 2026 at 07:00:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 2355 207 144 1 12 4 2 95 0 1 0 99 1 16 0 0 52 5 46 0 9 5 2 377 0 0 0 100 2 10 0 0 33 1 12 0 5 5 0 21 0 0 0 100 3 10 0 0 42 1 39 2 8 2 1 111 0 0 0 100 4 1894 0 3 291 123 95 2 7 4 8 437 0 1 0 99 5 728 0 134 51 10 109 2 11 16 8 2208 0 1 0 99 6 838 0 0 108 31 133 1 11 11 17 6860 2 1 0 97 7 57 0 2 56 1 64 0 12 10 5 107 0 0 0 100 March 2, 2026 at 07:00:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 208 120 0 0 0 0 14 0 1 0 99 1 0 0 0 15 3 14 0 2 0 0 305 0 0 0 100 2 0 0 0 10 0 6 0 0 0 0 7 0 0 0 100 3 0 0 0 10 2 6 0 1 1 0 4 0 0 0 100 4 0 0 3 213 105 6 0 0 0 0 2 0 0 0 100 5 0 0 21 19 5 44 2 0 1 0 2035 0 0 0 99 6 0 0 0 110 51 107 0 2 0 0 294 0 0 0 100 7 0 0 0 10 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 29 2647 208 757 26 66 10 1 1476 3 2 0 95 1 0 0 0 324 9 563 17 50 17 0 1628 4 1 0 95 2 0 0 0 292 3 558 25 63 14 0 1255 4 1 0 96 3 0 0 10 387 6 750 24 68 26 0 1563 3 2 0 96 4 31 0 130 373 105 322 15 26 63 1 3182 8 2 0 90 5 5 0 21 71 8 77 10 5 50 2 5638 12 2 0 86 6 1 0 0 152 44 130 9 5 66 0 4033 9 2 0 89 7 28 0 0 261 2 445 16 44 33 0 1934 4 1 0 95 March 2, 2026 at 07:00:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 113 0 0 0 0 0 0 1 0 99 1 0 0 7 16 3 10 1 1 0 0 300 0 0 0 100 2 0 0 0 20 6 14 0 0 0 0 9 0 0 0 100 3 0 0 0 11 2 6 0 1 0 0 1 0 0 0 100 4 0 0 4 214 105 4 0 0 0 0 2 0 0 0 100 5 2 0 21 116 56 142 1 0 0 0 1943 0 0 0 100 6 0 0 0 11 1 6 0 0 0 0 295 0 0 0 100 7 0 0 0 18 2 18 0 1 0 0 3 0 0 0 100 March 2, 2026 at 07:00:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2306 200 111 0 0 0 0 0 0 1 0 99 1 0 0 0 32 3 10 0 0 0 0 300 0 0 0 100 2 0 0 0 36 6 14 0 1 0 0 9 0 0 0 100 3 0 0 0 25 2 2 0 0 0 0 0 0 0 0 100 4 0 0 4 229 104 4 0 0 0 0 1 0 0 0 100 5 0 0 21 130 55 142 0 1 0 0 1939 0 0 0 99 6 0 0 0 26 1 4 1 1 0 0 294 0 0 0 100 7 0 0 0 28 2 8 0 0 0 0 5 0 0 0 100 March 2, 2026 at 07:00:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2309 200 124 0 1 1 0 0 0 1 0 99 1 1 0 0 25 6 22 0 0 0 0 315 0 0 0 100 2 0 0 0 20 6 12 0 0 0 0 9 0 0 0 100 3 0 0 0 13 1 10 0 1 0 0 5 0 0 0 100 4 1 0 4 216 105 10 0 0 0 0 8 0 0 0 100 5 0 0 21 124 64 142 2 0 0 0 1940 0 0 0 99 6 0 0 0 10 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 15 0 12 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2315 201 126 0 4 1 0 51 0 0 0 99 1 0 0 0 40 7 55 0 5 1 0 1243 0 0 0 100 2 0 0 0 32 7 34 0 2 1 0 46 0 0 0 100 3 0 0 0 18 3 24 0 4 1 0 82 0 0 0 100 4 0 0 4 219 104 25 0 6 0 0 59 0 0 0 100 5 0 0 21 70 32 100 3 3 0 0 1962 0 0 0 99 6 0 0 0 64 25 73 0 6 0 0 340 0 0 0 100 7 0 0 0 21 3 19 1 1 1 0 833 0 0 0 100 March 2, 2026 at 07:00:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2507 205 485 3 97 1587 0 5 0 4 0 96 1 0 0 0 300 8 631 2 118 1694 1 300 0 3 0 97 2 0 0 0 186 0 409 3 102 1563 0 0 0 3 0 97 3 0 0 0 412 205 458 3 128 1778 0 0 0 4 0 96 4 0 0 3 429 112 477 3 123 1880 1 7 0 3 0 96 5 1 0 21 201 5 465 7 91 1653 0 1959 0 4 0 96 6 0 0 0 379 23 775 2 124 1750 0 295 0 3 0 97 7 0 0 0 249 19 503 3 105 1620 0 0 0 2 0 98 March 2, 2026 at 07:00:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2321 206 118 1 3 1 0 9 0 0 0 99 1 0 0 0 116 53 110 0 1 0 0 300 0 0 0 100 2 0 0 0 15 0 14 0 2 2 0 0 0 0 0 100 3 0 0 0 38 13 20 0 0 0 0 0 0 0 0 100 4 0 0 4 220 103 20 0 2 6 0 0 0 0 0 100 5 0 0 21 22 6 54 0 0 2 0 1942 0 0 0 100 6 0 0 0 22 2 32 0 1 2 0 294 0 0 0 100 7 0 0 0 16 2 18 0 2 0 0 2 0 0 0 100 March 2, 2026 at 07:00:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 205 122 0 0 0 0 8 0 0 0 99 1 0 0 0 113 53 108 0 0 0 0 300 0 0 0 100 2 0 0 0 9 0 4 0 2 0 0 0 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 215 104 12 0 1 0 0 2 0 0 0 100 5 0 0 21 16 5 42 2 0 0 0 1937 0 0 0 99 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2321 207 126 0 0 0 0 21 0 0 0 99 1 0 0 0 63 25 64 0 1 0 0 318 0 0 0 100 2 0 0 0 16 2 14 0 1 0 0 8 0 0 0 100 3 0 0 0 15 1 16 1 1 0 0 36 0 0 0 100 4 0 0 4 212 103 8 0 1 0 0 9 0 0 0 100 5 0 0 21 83 40 102 2 1 3 0 1941 0 0 0 99 6 0 0 0 10 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 15 3 12 0 0 0 0 3 0 0 0 100 March 2, 2026 at 07:00:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 108 0 0 0 0 0 0 0 0 100 1 0 0 0 20 4 14 1 2 0 0 305 0 0 0 100 2 0 0 0 27 9 20 1 0 0 0 15 0 0 0 100 3 0 0 0 10 2 6 0 1 2 0 4 0 0 0 100 4 0 0 3 216 104 12 0 1 0 0 9 0 0 0 100 5 0 0 21 70 33 94 1 0 0 0 1937 0 0 0 99 6 0 0 0 59 24 62 0 3 0 0 294 0 0 0 100 7 0 0 0 7 0 4 0 0 0 0 3 0 0 0 100 March 2, 2026 at 07:00:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2336 226 162 0 1 1 0 5 0 1 0 99 1 0 0 0 28 9 22 0 2 1 0 300 0 0 0 100 2 0 0 0 23 7 18 0 0 5 0 9 0 0 0 100 3 0 0 0 10 2 4 0 1 1 0 0 0 0 0 100 4 0 0 4 210 103 4 0 0 5 0 0 0 0 0 100 5 0 0 21 18 7 44 1 0 3 0 1941 0 0 0 100 6 0 0 0 54 22 48 0 1 0 0 295 0 0 0 100 7 21 0 0 25 6 26 0 2 3 0 13 0 0 0 100 March 2, 2026 at 07:00:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 110 0 0 0 0 5 0 1 0 99 1 0 0 0 114 53 110 0 1 1 0 311 0 0 0 100 2 0 0 0 17 5 12 0 0 0 0 8 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 4 0 0 4 211 104 4 0 0 0 0 2 0 0 0 100 5 0 0 21 14 5 40 2 0 0 0 1934 0 0 0 99 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:00:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 200 120 0 1 0 0 0 0 1 0 99 1 0 0 0 113 53 108 0 0 0 0 300 0 0 0 100 2 0 0 0 19 6 14 0 0 0 0 6 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 4 0 0 4 211 104 4 0 0 0 0 1 0 0 0 100 5 0 0 21 13 5 40 1 0 0 0 1932 0 0 0 99 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 16 3 12 0 0 0 0 6 0 0 0 100 March 2, 2026 at 07:00:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 114 1 2 0 0 0 0 1 0 99 1 0 0 0 66 25 64 1 1 0 0 329 0 0 0 100 2 0 0 0 22 7 16 1 1 0 0 10 0 0 0 100 3 0 0 0 13 3 10 0 0 0 0 4 0 0 0 100 4 0 0 4 215 105 10 0 0 0 0 10 0 0 0 100 5 0 0 21 21 12 42 1 0 0 0 1935 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 73 30 73 0 2 0 0 9 0 0 0 100 March 2, 2026 at 07:00:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2333 230 164 0 2 0 0 0 0 1 0 99 1 0 0 0 22 4 18 1 0 0 0 308 0 0 0 100 2 0 0 0 22 7 14 0 0 0 0 14 0 0 0 100 3 0 0 0 7 1 4 0 1 0 0 0 0 0 0 100 4 0 0 4 214 104 10 0 1 1 0 9 0 0 0 100 5 0 0 21 13 5 40 1 0 0 0 1934 0 0 0 99 6 0 0 0 10 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 56 22 52 0 2 0 0 5 0 0 0 100 March 2, 2026 at 07:00:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2353 245 198 0 2 0 0 0 0 1 0 99 1 0 0 0 28 8 22 0 1 0 0 300 0 0 0 100 2 0 0 0 15 0 18 0 1 2 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 224 110 18 0 0 0 0 11 0 0 0 100 5 0 0 21 16 6 44 2 0 0 0 1934 0 0 0 99 6 0 0 0 13 3 8 0 1 0 0 295 0 0 0 100 7 0 0 0 12 0 10 0 1 3 0 0 0 0 0 100 March 2, 2026 at 07:00:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 108 0 0 0 0 0 0 1 0 99 1 0 0 0 113 53 108 0 0 0 0 300 0 0 0 100 2 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 12 1 12 0 1 1 0 0 0 0 0 100 4 0 0 4 221 109 14 0 0 0 0 6 0 0 0 100 5 0 0 21 15 6 42 1 0 0 0 1937 0 0 0 99 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 16 4 12 0 1 0 0 7 0 0 0 100 March 2, 2026 at 07:00:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 200 108 0 0 0 0 0 0 1 0 99 1 0 0 0 114 53 108 1 1 0 0 300 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 4 225 111 18 0 0 0 0 12 0 0 0 100 5 0 0 21 14 5 40 2 0 0 0 1932 0 0 0 99 6 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 35 0 3 2724 201 1519 3 4 0 0 7712 2 1 0 97 1 12 0 0 126 52 125 4 3 15 0 2015 3 1 0 96 2 19 0 0 109 1 186 1 6 1 0 1741 0 0 0 99 3 4 0 0 27 1 38 0 7 1 0 357 0 0 0 100 4 140 0 3 238 109 49 0 2 0 0 116 0 0 0 100 5 170 0 21 33 11 72 1 5 0 0 1981 0 0 0 99 6 42 0 0 21 2 24 1 4 0 0 353 0 0 0 100 7 123 0 0 30 4 34 0 1 1 0 58 0 0 0 100 March 2, 2026 at 07:00:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 74 0 3 6602 206 9099 71 353 176 0 25089 23 16 0 61 1 47 0 0 4801 11 9798 90 416 103 0 22153 20 13 0 68 2 12 0 0 3346 4 7003 42 236 161 0 19390 19 11 0 70 3 14 0 0 4605 24 9394 78 308 79 0 19771 16 11 0 73 4 8 0 3 2824 122 5346 46 273 137 0 13955 13 8 0 79 5 20 0 21 2176 10 4618 35 146 79 0 13990 12 8 0 80 6 10 0 0 3228 10 6880 41 246 119 0 15968 13 9 0 78 7 14 0 0 2095 21 4335 18 143 55 0 11122 9 6 0 85 March 2, 2026 at 07:00:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 7 6532 210 8969 80 447 741 0 23896 23 16 0 61 1 71 0 0 4801 13 10032 90 504 659 0 24717 20 14 0 65 2 12 0 0 4201 9 8668 58 333 762 0 21115 18 13 0 69 3 3 0 0 4085 134 8451 75 426 747 0 20610 17 13 0 70 4 23 0 14 3014 122 5766 60 349 740 0 13256 11 9 0 80 5 9 0 14 2249 20 4751 93 228 503 0 10644 10 7 0 83 6 12 0 0 2989 12 6205 49 325 765 0 14000 13 9 0 78 7 6 0 0 2307 7 4815 36 203 684 0 11644 11 8 0 81 March 2, 2026 at 07:00:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 7 6717 206 9526 85 351 138 0 25708 24 16 0 60 1 3 0 3 4810 10 10215 72 379 123 0 25675 23 14 0 63 2 5 0 0 3943 18 8151 49 266 109 0 22063 19 12 0 69 3 2 0 0 4537 24 9301 66 357 104 0 19792 16 11 0 74 4 1 0 14 2861 123 5356 38 272 103 0 14393 13 8 0 78 5 1 0 14 1903 8 3932 16 133 105 0 10723 10 6 0 84 6 2 0 0 2695 10 5618 35 216 119 0 13183 11 7 0 82 7 2 0 0 2092 5 4474 17 102 65 0 10155 9 6 0 85 March 2, 2026 at 07:00:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2344 204 151 3 9 0 0 232 0 1 0 99 1 0 0 0 49 1 89 0 2 0 0 152 0 0 0 100 2 0 0 0 43 3 99 1 1 0 0 1258 0 0 0 99 3 0 0 0 47 2 55 0 1 3 0 351 0 0 0 100 4 0 0 11 245 109 54 0 4 1 0 975 0 0 0 100 5 0 0 14 111 52 110 0 2 0 0 291 0 0 0 100 6 0 0 0 22 5 24 0 2 0 0 19 0 0 0 100 7 0 0 0 30 1 54 1 3 3 0 114 0 0 0 100 March 2, 2026 at 07:00:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2313 204 120 1 1 0 0 13 0 1 0 99 1 0 0 0 15 2 10 0 1 0 0 6 0 0 0 100 2 0 0 0 12 1 34 1 1 1 0 1117 0 0 0 100 3 0 0 0 15 2 12 1 0 0 0 310 0 0 0 100 4 0 0 11 220 108 14 1 0 0 0 854 0 0 0 100 5 0 0 14 115 59 106 0 0 0 0 269 0 0 0 100 6 0 0 0 32 9 27 0 3 0 0 14 0 0 0 100 7 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:00:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 203 110 0 1 1 0 5 0 1 0 99 1 0 0 0 24 5 26 0 2 0 0 15 0 0 0 100 2 0 0 0 14 1 38 1 0 0 0 1135 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 321 0 0 0 100 4 0 0 11 218 107 14 0 0 1 0 857 0 0 0 100 5 0 0 14 96 46 92 0 1 0 0 266 0 0 0 100 6 0 0 0 26 8 24 0 1 0 0 14 0 0 0 100 7 0 0 0 23 5 22 0 2 0 0 7 0 0 0 100 March 2, 2026 at 07:00:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2401 203 306 0 40 436 0 2 0 1 0 99 1 0 0 0 201 2 400 0 49 402 0 0 0 1 0 99 2 0 0 0 94 1 214 1 41 453 0 1117 0 1 0 99 3 0 0 0 212 106 219 1 43 458 0 300 0 1 0 99 4 0 0 10 317 108 232 1 44 488 0 854 0 1 0 99 5 0 0 14 94 2 179 0 34 401 0 268 0 1 0 99 6 0 0 0 112 8 213 0 39 452 0 11 0 1 0 99 7 0 0 0 178 50 261 0 32 426 0 0 0 1 0 99 March 2, 2026 at 07:00:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 204 110 0 0 0 0 7 0 0 0 100 1 0 0 0 10 2 6 0 1 0 0 11 0 0 0 100 2 0 0 0 12 1 36 1 1 1 0 1117 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 11 217 107 12 0 0 0 0 853 0 0 0 100 5 0 0 14 17 3 14 0 0 0 0 267 0 0 0 100 6 0 0 0 21 6 14 1 0 0 0 9 0 0 0 100 7 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 102 0 0 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 2 0 0 0 13 1 38 0 1 1 0 1118 0 0 0 100 3 0 0 0 12 1 12 0 1 0 0 299 0 0 0 100 4 0 0 11 217 107 12 1 0 0 0 854 0 0 0 100 5 0 0 14 17 3 14 0 0 0 0 268 0 0 0 100 6 0 0 0 18 5 12 0 1 0 0 9 0 0 0 100 7 0 0 0 106 50 100 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1594 0 3 2342 208 168 9 14 10 1 597 2 1 0 97 1 0 0 0 50 2 189 18 21 4 0 549 3 0 0 97 2 4 0 0 43 1 110 4 22 2 0 1463 2 0 0 97 3 7 0 0 41 2 87 3 10 2 1 568 3 0 0 97 4 517 0 53 257 108 103 26 20 5 0 1535 2 1 0 97 5 3 0 14 50 8 187 9 29 5 0 901 2 0 0 98 6 0 0 0 55 9 167 16 10 3 0 819 3 0 0 97 7 0 0 0 137 50 148 2 10 2 0 272 2 0 0 98 March 2, 2026 at 07:00:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 3 2762 214 769 34 109 18 0 3261 23 3 0 74 1 2 0 0 434 8 678 35 120 26 0 3679 27 2 0 71 2 4 0 0 497 6 826 32 127 17 0 4530 23 2 0 75 3 26 0 0 484 7 788 37 149 25 0 4695 23 2 0 75 4 2 0 276 582 114 702 28 142 23 0 5612 20 2 0 78 5 1 0 14 449 20 696 22 109 18 0 3337 18 2 0 80 6 0 0 0 387 7 641 31 127 19 0 3551 21 2 0 77 7 22 0 0 442 13 675 24 104 17 0 3344 19 2 0 79 March 2, 2026 at 07:00:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2734 205 687 33 105 15 0 3349 33 3 0 64 1 0 0 0 478 12 800 30 140 49 0 4732 25 2 0 73 2 0 0 0 440 7 656 28 111 20 0 3109 30 2 0 68 3 0 0 0 520 14 814 30 140 35 0 5052 24 2 0 74 4 0 0 374 586 119 652 23 130 16 0 4256 14 2 0 84 5 2 0 14 461 13 727 18 104 40 0 3727 16 2 0 82 6 0 0 0 445 7 739 18 117 17 0 3878 18 2 0 80 7 0 0 0 437 4 711 16 89 30 0 4160 15 2 0 84 March 2, 2026 at 07:00:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2594 209 494 18 81 8 0 2026 19 2 0 79 1 0 0 0 359 13 539 18 92 12 0 3618 22 2 0 77 2 0 0 0 321 10 606 20 73 12 0 2427 20 1 0 79 3 0 0 0 375 6 614 35 112 12 0 3570 19 1 0 79 4 3 0 262 503 115 527 26 106 7 0 2965 10 2 0 88 5 2 0 14 296 4 473 11 77 8 0 3355 13 1 0 86 6 0 0 0 329 13 494 14 86 13 0 2631 11 1 0 88 7 0 0 0 259 6 400 13 63 11 0 2038 12 1 0 87 March 2, 2026 at 07:00:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 2356 250 205 0 1 2 0 11 0 1 0 99 1 0 0 0 32 7 64 1 3 1 0 1139 0 0 0 100 2 1 0 0 14 2 10 0 2 3 0 14 0 0 0 100 3 0 0 0 18 3 14 0 1 0 0 622 0 0 0 100 4 0 0 10 218 107 14 0 0 0 0 273 0 0 0 100 5 2 0 14 13 3 14 0 0 0 0 568 0 0 0 100 6 2 0 0 12 3 8 0 0 2 0 11 0 0 0 100 7 0 0 0 7 0 4 0 2 0 0 2 0 0 0 100 March 2, 2026 at 07:00:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2358 250 216 1 2 0 0 13 0 0 0 100 1 0 0 0 38 8 68 0 1 1 0 1137 0 0 0 100 2 0 0 0 24 7 20 0 2 0 0 9 0 0 0 100 3 0 0 0 20 2 15 2 0 0 0 606 0 0 0 100 4 0 0 10 212 105 6 0 0 0 0 261 0 0 0 100 5 0 0 14 20 9 10 0 0 0 0 560 0 0 0 100 6 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 7 0 0 0 11 1 8 0 1 0 0 5 0 0 0 100 March 2, 2026 at 07:00:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2322 220 142 0 0 0 0 0 0 1 0 99 1 0 0 0 80 33 103 1 1 0 0 1123 0 0 0 100 2 0 0 0 39 11 40 0 2 0 0 19 0 0 0 100 3 0 0 0 13 2 8 0 1 0 0 603 0 0 0 100 4 0 0 10 211 104 6 0 1 0 0 263 0 0 0 100 5 0 0 14 10 3 8 0 0 0 0 560 0 0 0 100 6 0 0 0 11 3 6 0 0 0 0 5 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2647 202 731 23 75 37 0 2510 4 2 0 94 1 0 0 0 444 44 795 29 69 150 1 3744 4 2 0 95 2 20 0 32 270 9 489 23 45 133 0 3928 10 2 0 88 3 0 0 0 234 3 410 11 41 98 0 3137 5 2 0 94 4 0 0 151 579 109 771 28 67 47 0 2686 6 1 0 92 5 17 0 14 270 7 481 24 48 154 0 4278 9 2 0 89 6 0 0 7 222 3 381 11 44 122 0 2636 4 2 0 93 7 26 0 14 235 2 414 14 29 126 0 3501 10 2 0 88 March 2, 2026 at 07:00:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 80 0 3 2352 201 160 0 18 10 12 188 0 1 0 99 1 119 0 2 54 2 95 2 11 12 10 4368 1 1 0 99 2 21 0 0 54 7 57 0 11 7 8 122 0 0 0 100 3 37 0 7 54 3 59 0 8 1 9 645 0 0 0 100 4 20 0 11 245 105 26 0 7 2 1 331 0 0 0 100 5 8 0 14 137 54 127 0 5 4 4 539 0 0 0 100 6 0 0 0 41 2 29 0 9 2 1 123 0 0 0 100 7 2605 0 114 32 2 50 2 5 5 7 406 1 1 0 98 March 2, 2026 at 07:00:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 36 0 3 2328 201 118 0 1 0 0 6 0 1 0 99 1 638 0 0 62 18 69 1 1 0 0 4376 2 1 0 98 2 6 0 0 103 38 84 1 2 0 0 13 0 0 0 100 3 8 0 0 43 3 28 2 0 0 0 664 0 0 0 100 4 6 0 11 241 108 24 0 3 0 0 263 0 0 0 100 5 0 0 14 27 2 8 0 1 0 0 267 0 0 0 100 6 0 0 0 33 6 12 0 0 0 0 303 0 0 0 100 7 0 0 112 11 2 7 0 0 0 0 2 0 0 0 100 March 2, 2026 at 07:00:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 202 116 1 2 0 0 13 0 1 0 99 1 0 0 0 16 2 38 1 0 1 0 1117 0 0 0 100 2 0 0 0 122 57 116 0 0 0 0 9 0 0 0 100 3 0 0 0 19 4 16 0 0 0 0 605 0 0 0 100 4 0 0 11 218 104 9 0 2 0 0 260 0 0 0 100 5 0 0 14 14 7 6 0 0 0 0 266 0 0 0 100 6 0 0 0 8 1 2 0 0 0 0 294 0 0 0 100 7 0 0 7 12 1 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:00:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 200 124 0 3 0 0 38 0 0 0 99 1 0 0 0 30 3 69 3 3 1 0 1178 0 0 0 100 2 0 0 14 127 58 129 0 3 4 0 374 0 0 0 100 3 2 0 0 28 5 37 0 5 0 0 666 0 0 0 100 4 0 0 11 222 104 23 1 5 1 0 330 0 0 0 100 5 0 0 0 22 3 16 1 2 1 0 817 0 0 0 100 6 0 0 0 16 2 15 1 3 2 0 1134 0 0 0 100 7 0 0 0 18 3 17 2 1 0 0 53 0 0 0 100 March 2, 2026 at 07:00:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2508 200 553 0 108 1554 0 0 0 4 0 96 1 0 0 0 293 4 672 2 126 1839 1 1114 0 4 0 96 2 0 0 14 387 45 766 0 117 1720 0 266 0 3 0 97 3 0 0 0 408 199 469 1 115 1775 0 600 0 4 0 96 4 0 0 14 401 107 440 0 126 1898 0 260 0 4 0 96 5 0 0 0 186 7 389 1 96 1665 0 0 0 3 0 97 6 0 0 0 213 2 477 0 116 1693 0 294 0 3 0 97 7 0 0 0 197 8 416 0 95 1753 0 9 0 4 0 96 March 2, 2026 at 07:00:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 3 2309 202 106 0 1 0 0 6 0 1 0 99 1 0 0 0 15 2 38 1 1 0 0 1124 0 0 0 100 2 0 0 14 29 7 24 0 1 0 0 266 0 0 0 100 3 0 0 0 21 6 14 2 0 0 0 605 0 0 0 100 4 0 0 11 211 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 100 47 96 0 1 0 0 1 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 7 0 0 0 25 9 18 0 0 0 0 10 0 0 0 100 March 2, 2026 at 07:00:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 102 0 0 0 0 0 0 0 0 100 1 0 0 0 10 2 34 0 0 0 0 1112 0 0 0 100 2 0 0 14 109 52 106 0 0 0 0 266 0 0 0 100 3 0 0 0 13 3 8 0 0 0 0 601 0 0 0 100 4 0 0 11 214 105 8 0 0 0 0 261 0 0 0 100 5 0 0 0 21 1 22 0 3 0 0 0 0 0 0 100 6 0 0 0 8 1 2 0 0 0 0 294 0 0 0 100 7 0 0 0 19 7 14 0 0 0 0 9 0 0 0 100 March 2, 2026 at 07:00:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2318 203 132 1 1 0 0 25 0 0 0 99 1 0 0 0 17 3 42 1 1 0 0 1143 0 0 0 100 2 0 0 14 113 53 110 0 1 0 0 270 0 0 0 100 3 0 0 0 20 5 18 0 0 0 0 609 0 0 0 100 4 0 0 11 212 105 6 1 0 0 0 261 0 0 0 100 5 0 0 0 26 8 16 0 0 0 0 1 0 0 0 100 6 0 0 0 12 1 12 0 1 0 0 294 0 0 0 100 7 0 0 0 31 10 28 1 0 0 0 31 0 0 0 100 March 2, 2026 at 07:00:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 200 108 0 0 0 0 7 0 0 0 100 1 0 0 0 12 3 36 1 0 0 0 1115 0 0 0 100 2 0 0 14 57 23 52 0 2 0 0 271 0 0 0 100 3 0 0 0 15 4 10 0 0 0 0 621 0 0 0 100 4 0 0 11 210 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 63 26 58 0 1 1 0 3 0 0 0 100 6 0 0 0 19 6 16 0 1 0 0 297 0 0 0 100 7 0 0 0 22 8 20 0 1 0 0 13 0 0 0 100 March 2, 2026 at 07:00:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 3 2312 202 110 0 0 0 0 6 0 0 0 100 1 0 0 0 17 4 42 1 1 1 0 1118 0 0 0 100 2 0 0 14 18 2 16 0 0 3 0 266 0 0 0 100 3 0 0 0 22 6 16 2 0 0 0 603 0 0 0 100 4 0 0 11 213 104 10 0 0 1 0 260 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 114 52 110 0 1 3 0 295 0 0 0 100 7 0 0 0 26 8 26 0 1 0 0 8 0 0 0 100 March 2, 2026 at 07:00:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 200 112 0 1 0 0 1 0 1 0 99 1 0 0 0 12 3 36 1 0 0 0 1108 0 0 0 100 2 0 0 14 14 2 8 1 0 0 0 266 0 0 0 100 3 0 0 0 17 5 12 0 0 0 0 603 0 0 0 100 4 0 0 11 210 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 100 46 95 0 1 0 0 294 0 0 0 100 7 0 0 0 35 13 30 1 1 0 0 10 0 0 0 100 March 2, 2026 at 07:00:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 102 0 0 0 0 0 0 0 0 100 1 0 0 0 10 2 34 1 0 1 0 1109 0 0 0 100 2 0 0 14 9 2 6 0 0 0 0 266 0 0 0 100 3 0 0 0 17 5 12 0 0 0 0 605 0 0 0 100 4 0 0 11 211 104 4 1 0 0 0 260 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 16 1 10 1 0 0 0 294 0 0 0 100 7 0 0 0 121 58 116 0 0 0 0 11 0 0 0 100 March 2, 2026 at 07:00:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2312 202 128 2 2 0 0 12 0 1 0 99 1 0 0 0 18 2 48 0 1 0 0 1115 0 0 0 100 2 0 0 14 9 2 4 0 0 0 0 266 0 0 0 100 3 2 0 0 18 4 18 0 1 0 0 607 0 0 0 100 4 0 0 11 210 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 15 8 4 0 0 0 0 0 0 0 0 100 6 0 0 0 13 1 6 0 0 0 0 294 0 0 0 100 7 0 0 0 124 57 118 0 0 0 0 9 0 0 0 100 March 2, 2026 at 07:01:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 114 0 0 0 0 18 0 1 0 99 1 0 0 0 15 2 40 1 1 2 0 1108 0 0 0 100 2 0 0 14 17 2 24 0 1 0 0 281 0 0 0 100 3 0 0 0 21 6 12 2 0 0 0 606 0 0 0 100 4 0 0 11 210 104 4 0 0 0 0 260 0 0 0 100 5 0 0 0 9 1 6 0 0 1 0 3 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 297 0 0 0 100 7 0 0 0 128 60 126 1 0 0 0 15 0 0 0 100 March 2, 2026 at 07:01:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 200 108 0 0 1 0 0 0 1 0 99 1 0 0 0 17 5 40 1 0 1 0 1107 0 0 0 100 2 0 0 14 11 3 6 0 0 4 0 266 0 0 0 100 3 0 0 0 14 3 8 0 0 1 0 600 0 0 0 100 4 0 0 11 213 104 10 0 0 3 0 260 0 0 0 100 5 0 0 0 10 2 4 0 0 1 0 0 0 0 0 100 6 0 0 0 10 2 4 0 0 4 0 294 0 0 0 100 7 0 0 0 123 59 118 0 1 0 0 11 0 0 0 100 March 2, 2026 at 07:01:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 200 110 0 0 0 0 0 0 1 0 99 1 0 0 0 12 3 36 1 0 0 0 1109 0 0 0 100 2 0 0 14 11 2 8 0 0 0 0 266 0 0 0 100 3 0 0 0 20 4 20 0 1 0 0 602 0 0 0 100 4 0 0 11 211 104 4 1 0 0 0 260 0 0 0 100 5 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 7 0 0 0 121 58 116 0 0 0 0 11 0 0 0 100 March 2, 2026 at 07:01:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 12 3 36 1 0 0 0 1107 0 0 0 100 2 0 0 14 9 2 4 0 0 0 0 266 0 0 0 100 3 0 0 0 14 2 8 0 0 1 0 601 0 0 0 100 4 0 0 11 216 105 16 0 1 0 0 261 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 294 0 0 0 100 7 0 0 0 119 57 116 0 1 0 0 9 0 0 0 100 March 2, 2026 at 07:01:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 2458 202 351 1 7 2 0 405 0 1 0 99 1 9 0 0 660 5 1967 1 9 3 0 10297 2 1 0 96 2 0 0 14 61 2 100 3 4 11 0 2453 5 1 0 95 3 101 0 0 86 5 144 2 7 1 0 1621 1 0 0 99 4 345 0 11 304 105 195 4 7 12 0 1069 1 1 0 98 5 1 0 0 47 9 67 0 4 2 0 84 0 0 0 100 6 0 0 0 25 1 37 0 4 2 0 360 0 0 0 100 7 139 0 0 213 59 328 2 4 5 0 699 1 1 0 99 March 2, 2026 at 07:01:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 15 0 7 6828 210 9473 79 353 114 0 26645 25 16 0 60 1 15 0 0 3931 17 7986 91 376 123 0 21385 18 12 0 71 2 12 0 14 2915 15 5871 48 227 99 0 16600 14 9 0 77 3 14 0 0 4565 33 9340 65 329 111 0 20646 16 11 0 73 4 12 0 7 2930 118 5611 45 269 117 0 14764 14 9 0 78 5 10 0 7 2882 9 5990 30 167 113 0 15810 15 9 0 76 6 31 0 0 3515 5 7337 40 251 76 0 16567 14 9 0 76 7 11 0 0 2830 11 5804 28 157 67 0 10268 9 6 0 85 March 2, 2026 at 07:01:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 3 6551 207 9068 103 491 657 0 24854 23 16 0 61 1 16 0 0 4311 11 9027 82 499 760 0 24040 21 14 0 65 2 15 0 0 4031 12 8411 75 376 799 0 19249 17 13 0 70 3 15 0 14 4229 150 8568 110 469 772 0 21383 17 12 0 71 4 13 0 3 3331 117 6432 49 342 757 0 14952 14 10 0 76 5 9 0 7 2442 6 5198 33 250 695 0 12982 12 9 0 80 6 3 0 0 3082 20 6376 47 327 720 0 12237 10 8 0 82 7 8 0 0 2479 12 5275 45 234 688 0 11468 10 8 0 82 March 2, 2026 at 07:01:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 5 6751 210 9090 64 390 126 0 24064 23 15 0 63 1 9 0 14 4587 14 9733 77 427 119 0 24969 21 14 0 66 2 8 0 0 3396 15 6976 54 281 140 0 16044 15 10 0 75 3 8 0 0 4246 20 8845 72 336 111 0 21531 17 12 0 71 4 8 0 4 3448 112 6847 25 256 149 0 14651 13 9 0 78 5 2 0 7 2087 12 4396 10 128 73 0 12535 11 7 0 81 6 6 0 0 2695 13 5712 29 225 123 0 14862 13 8 0 78 7 4 0 0 1762 6 3658 15 121 65 0 9449 9 6 0 86 March 2, 2026 at 07:01:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 106 0 3 0 0 296 0 0 0 99 1 0 0 14 19 6 14 1 1 0 0 574 0 0 0 100 2 0 0 0 126 57 126 0 1 1 0 6 0 0 0 100 3 0 0 0 10 2 34 1 0 0 0 1117 0 0 0 100 4 0 0 4 221 105 12 0 0 0 0 300 0 0 0 100 5 0 0 7 10 4 4 0 0 0 0 260 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 201 118 0 0 0 0 299 0 0 0 100 1 0 0 14 18 5 20 0 0 0 0 604 0 0 0 100 2 0 0 0 130 60 126 0 2 1 0 16 0 0 0 100 3 0 0 0 21 3 54 1 2 0 0 1128 0 0 0 100 4 0 0 4 214 105 6 1 0 0 0 300 0 0 0 100 5 0 0 7 14 8 4 0 0 0 0 260 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 0 11 1 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 112 0 0 0 0 296 0 0 0 99 1 0 0 14 12 4 8 1 0 0 0 570 0 0 0 100 2 0 0 0 126 59 122 0 0 0 0 14 0 0 0 100 3 0 0 0 10 2 36 0 0 1 0 1120 0 0 0 100 4 0 0 4 213 105 6 0 0 0 0 300 0 0 0 100 5 0 0 7 11 2 10 1 0 0 0 267 0 0 0 100 6 0 0 0 9 0 6 0 1 1 0 3 0 0 0 100 7 0 0 0 13 2 8 0 1 0 0 5 0 0 0 100 March 2, 2026 at 07:01:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2382 201 276 0 40 434 0 294 0 2 0 98 1 0 0 14 94 3 196 0 50 475 0 566 0 1 0 99 2 0 0 0 205 58 298 0 41 467 0 9 0 1 0 99 3 0 0 0 192 98 211 1 40 527 0 1117 0 2 0 98 4 0 0 7 403 105 404 0 54 443 0 300 0 1 0 99 5 0 0 7 89 3 167 0 30 408 0 260 0 1 0 99 6 0 0 0 93 1 182 1 36 436 0 0 0 1 0 99 7 0 0 0 78 2 160 0 38 356 0 0 0 1 0 99 March 2, 2026 at 07:01:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 0 0 0 0 296 0 1 0 99 1 0 0 14 16 6 12 1 0 0 0 570 0 0 0 100 2 0 0 0 123 58 118 0 0 0 0 6 0 0 0 100 3 0 0 0 10 2 34 1 0 0 0 1116 0 0 0 100 4 0 0 4 215 105 8 0 0 0 0 300 0 0 0 100 5 0 0 7 16 3 18 0 1 0 0 261 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 110 1 0 0 0 294 0 1 0 99 1 0 0 14 7 2 4 0 0 0 0 567 0 0 0 100 2 0 0 0 123 58 118 0 0 0 0 9 0 0 0 100 3 0 0 0 10 2 34 1 0 0 0 1117 0 0 0 100 4 0 0 3 215 106 8 0 0 0 0 301 0 0 0 100 5 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 3 2359 202 204 5 21 3 0 586 3 1 0 96 1 6 0 14 49 6 254 5 28 2 0 1322 2 0 0 97 2 0 0 0 186 58 255 9 12 3 0 431 4 0 0 96 3 2 0 0 50 3 130 18 19 3 0 1742 4 1 0 96 4 1076 0 60 247 106 94 16 21 11 2 1012 3 1 0 96 5 9 0 7 68 9 183 37 29 3 1 1058 2 0 0 97 6 772 0 0 43 1 54 7 11 7 0 603 2 1 0 97 7 0 0 0 60 3 94 18 18 3 0 979 2 0 0 98 March 2, 2026 at 07:01:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 4 2729 206 696 33 115 19 0 3686 19 2 0 78 1 2 0 14 443 6 726 35 145 28 0 4132 27 2 0 71 2 0 0 7 423 8 674 34 114 23 0 4022 27 2 0 71 3 1 0 0 442 9 765 30 128 23 0 5523 25 2 0 73 4 3 0 212 614 118 726 33 121 22 0 3515 22 2 0 76 5 2 0 0 412 8 678 24 98 24 0 4018 19 2 0 79 6 29 0 0 443 15 699 20 112 20 0 4149 21 2 0 77 7 2 0 0 429 12 719 21 103 16 0 3552 14 2 0 84 March 2, 2026 at 07:01:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2743 205 771 30 129 12 0 2972 22 2 0 75 1 0 0 14 459 6 749 33 131 27 0 4116 27 2 0 71 2 2 0 7 377 5 647 24 106 25 0 4801 22 2 0 76 3 0 0 0 364 10 621 30 121 10 0 4726 27 2 0 72 4 0 0 115 571 114 650 23 116 31 0 3492 26 2 0 72 5 0 0 0 426 16 746 19 108 31 0 4102 16 2 0 82 6 0 0 0 440 12 752 22 148 16 0 4361 21 2 0 78 7 0 0 0 409 7 729 22 101 19 0 3725 12 2 0 86 March 2, 2026 at 07:01:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2668 205 596 27 87 28 0 2953 16 2 0 83 1 3 0 0 337 7 515 20 81 23 0 2857 23 2 0 75 2 0 0 21 264 10 410 19 71 11 0 3456 22 1 0 77 3 0 0 0 256 10 371 28 69 19 0 3109 28 2 0 71 4 2 0 157 554 130 588 19 93 38 0 2903 13 2 0 85 5 0 0 0 332 9 534 16 85 29 0 2640 7 1 0 92 6 0 0 0 265 4 442 21 78 7 0 2603 15 1 0 84 7 0 0 0 261 4 436 11 64 19 0 2405 8 1 0 91 March 2, 2026 at 07:01:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3 2317 206 129 2 2 0 0 324 0 1 0 99 1 0 0 0 19 3 20 0 2 0 0 7 0 0 0 100 2 2 0 21 19 6 17 1 1 0 0 1111 0 0 0 100 3 0 0 0 9 1 33 1 1 0 0 1145 0 0 0 100 4 0 0 3 309 149 105 0 2 0 0 10 0 0 0 100 5 6 0 0 21 7 16 0 1 0 0 9 0 0 0 100 6 0 0 0 15 2 12 0 2 0 0 18 0 0 0 100 7 0 0 0 8 0 4 0 1 0 0 9 0 0 0 100 March 2, 2026 at 07:01:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2326 210 132 0 1 0 0 319 0 1 0 99 1 0 0 0 17 3 18 0 0 0 0 19 0 0 0 100 2 0 0 21 14 5 12 0 0 0 0 826 0 0 0 100 3 0 0 0 15 3 42 1 0 0 0 1425 0 0 0 100 4 0 0 3 216 102 8 0 0 0 0 0 0 0 0 100 5 0 0 0 115 57 102 0 0 0 0 0 0 0 0 100 6 0 0 0 10 1 6 0 1 0 0 0 0 0 0 100 7 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:01:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2325 210 128 0 0 0 0 318 0 1 0 99 1 0 0 0 11 1 8 0 1 0 0 9 0 0 0 100 2 0 0 21 21 5 24 1 3 0 0 830 0 0 0 100 3 0 0 0 10 2 34 0 0 1 0 1417 0 0 0 100 4 0 0 3 219 104 12 0 0 0 0 2 0 0 0 100 5 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 6 0 0 0 13 2 12 0 0 0 0 7 0 0 0 100 7 0 0 0 6 0 2 0 0 1 0 3 0 0 0 100 March 2, 2026 at 07:01:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 44 2358 209 173 1 12 1074 4 391 0 2 0 98 1 45 0 10 71 4 124 6 27 65 11 259 0 3 0 97 2 778 0 27 87 15 135 3 24 27 3 1018 1 0 0 98 3 49 0 4 78 6 160 2 24 93 11 1640 0 1 0 99 4 1115 0 19 283 103 123 2 21 77 11 405 0 1 0 99 5 47 0 16 145 51 160 1 17 1198 3 108 0 1 0 99 6 72 0 22 49 4 77 3 14 1082 5 122 0 1 0 99 7 42 0 0 71 1 128 2 31 36 11 225 0 0 0 100 March 2, 2026 at 07:01:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 45 2320 202 102 0 2 5 1 357 0 1 0 99 1 13 0 7 49 1 51 0 4 4 3 38 0 1 0 99 2 8 0 21 131 55 123 1 2 5 2 832 0 0 0 100 3 18 0 0 70 24 89 2 1 3 2 1130 0 0 0 100 4 5 0 3 232 103 24 0 2 1 2 7 0 0 0 100 5 23 0 7 25 2 21 0 3 1 5 11 0 0 0 100 6 8 0 0 28 3 23 0 3 8 3 24 0 0 0 100 7 1 0 0 21 0 12 0 2 3 1 19 0 0 0 100 March 2, 2026 at 07:01:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2357 201 109 1 4 1 0 300 0 1 0 99 1 0 0 343 23 1 14 0 1 2 0 0 0 0 0 100 2 0 0 21 167 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 102 22 74 0 0 1 0 1059 0 0 0 100 4 0 0 3 276 103 10 0 1 0 0 1 0 0 0 100 5 0 0 10 65 1 6 3 1 0 0 0 0 1 0 99 6 0 0 7 63 2 6 0 1 0 0 0 0 0 0 100 7 0 0 0 58 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 24 2307 202 118 0 0 0 0 302 0 1 0 99 1 0 0 0 18 3 14 0 0 0 0 11 0 0 0 100 2 0 0 21 118 55 113 1 1 0 0 826 0 0 0 100 3 0 0 0 55 22 76 2 0 0 0 1057 0 0 0 100 4 0 0 3 215 102 4 0 1 0 0 8 0 0 0 100 5 0 0 0 20 7 6 0 1 0 0 1 0 0 0 100 6 0 0 1 16 1 12 0 1 0 0 0 0 0 0 100 7 0 0 0 20 2 16 0 1 0 0 7 0 0 0 100 March 2, 2026 at 07:01:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 112 0 0 0 0 300 0 0 0 100 1 0 0 0 11 3 7 0 1 0 0 1 0 0 0 100 2 0 0 21 115 55 112 0 1 0 0 824 0 0 0 100 3 0 0 0 50 22 74 1 0 0 0 1056 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 8 1 2 1 0 0 0 1 0 0 0 100 March 2, 2026 at 07:01:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 120 0 1 0 0 302 0 0 0 100 1 0 0 0 12 2 6 0 0 0 0 5 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 826 0 0 0 100 3 0 0 0 54 23 82 0 1 0 0 1056 0 0 0 100 4 0 0 3 210 102 6 0 0 0 0 2 0 0 0 100 5 0 0 0 12 4 4 0 0 0 0 0 0 0 0 100 6 0 0 0 12 2 8 0 1 0 0 1 0 0 0 100 7 0 0 0 11 0 12 0 1 0 0 4 0 0 0 100 March 2, 2026 at 07:01:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 201 122 1 1 0 0 300 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 824 0 0 0 100 3 0 0 0 52 23 76 1 0 0 0 1056 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 9 0 4 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:01:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 114 0 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 825 0 0 0 100 3 0 0 0 52 23 76 1 0 0 0 1056 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 203 124 2 1 0 0 309 0 0 0 99 1 0 0 0 20 3 20 0 2 0 0 9 0 0 0 100 2 0 0 21 115 55 114 0 1 0 0 827 0 0 0 100 3 0 0 0 53 23 78 1 0 1 0 1056 0 0 0 100 4 0 0 3 208 102 2 0 0 0 0 3 0 0 0 100 5 0 0 0 13 7 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 14 1 10 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:01:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 114 0 0 0 0 302 0 0 0 100 1 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 2 0 0 21 120 55 122 1 1 0 0 824 0 0 0 100 3 0 0 0 51 23 76 0 0 0 0 1056 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2308 201 114 1 0 1 0 300 0 1 0 99 1 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 2 0 0 21 116 56 110 0 0 1 0 825 0 0 0 100 3 0 0 0 58 25 80 1 0 1 0 1056 0 0 0 100 4 0 0 7 210 102 6 0 1 0 0 0 0 0 0 100 5 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 6 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 7 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:01:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 203 116 0 0 1 0 302 0 0 0 100 1 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 55 114 1 0 0 0 825 0 0 0 100 3 0 0 0 58 24 88 0 1 2 0 1056 0 0 0 100 4 0 0 3 212 103 6 0 2 1 0 0 0 0 0 100 5 0 0 0 12 3 8 0 1 1 0 1 0 0 0 100 6 0 0 0 13 3 10 0 1 0 0 0 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 116 0 0 0 0 301 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 54 23 78 1 1 0 0 1056 0 0 0 100 4 0 0 3 214 103 12 0 1 0 0 1 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2314 204 130 1 0 0 0 319 0 1 0 99 1 0 0 0 11 2 8 0 0 0 0 8 0 0 0 100 2 0 0 21 119 55 116 1 0 0 0 831 0 0 0 100 3 0 0 0 53 23 78 1 0 0 0 1055 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 16 7 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 112 1 0 0 0 300 0 1 0 99 1 0 0 0 11 2 8 0 0 0 0 9 0 0 0 100 2 0 0 21 115 55 112 0 1 0 0 824 0 0 0 100 3 0 0 0 50 21 74 1 0 0 0 1092 0 0 0 100 4 0 0 3 216 105 10 0 2 0 0 4 0 0 0 100 5 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:01:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 118 0 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 825 0 0 0 100 3 0 0 0 15 4 40 1 0 0 0 1036 0 0 0 100 4 0 0 3 249 122 44 0 0 0 0 20 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 15 2 16 0 1 0 0 1 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 114 0 0 0 0 301 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 202 116 0 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 826 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 7 0 0 0 12 0 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:01:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2319 203 136 2 1 0 0 315 0 1 0 99 1 0 0 0 9 1 6 0 0 0 0 5 0 0 0 100 2 0 0 21 118 55 116 0 0 0 0 830 0 0 0 100 3 0 0 0 12 3 38 0 0 1 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 15 7 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 10 0 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 202 114 0 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 824 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1035 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2310 202 118 0 1 0 0 301 0 0 0 100 1 0 0 0 15 2 12 0 1 1 0 0 0 0 0 100 2 0 0 21 116 56 110 0 0 1 0 826 0 0 0 100 3 0 0 0 18 5 40 1 0 1 0 1036 0 0 0 100 4 0 0 7 250 122 44 0 0 1 0 20 0 0 0 100 5 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 6 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 7 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:01:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 114 0 0 0 0 302 0 0 0 100 1 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 2 0 0 21 120 55 122 1 1 0 0 824 0 0 0 100 3 0 0 0 12 3 36 1 0 1 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 March 2, 2026 at 07:01:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2299 201 112 1 0 0 0 299 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 56 116 0 0 0 0 831 0 0 0 100 3 0 0 0 12 3 38 0 0 0 0 1038 0 0 0 100 4 0 0 3 248 122 42 0 0 0 0 21 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2317 204 128 1 0 0 0 315 0 1 0 99 1 1 0 0 12 2 8 0 0 0 0 7 0 0 0 100 2 0 0 21 120 55 118 2 1 0 0 830 0 0 0 100 3 0 0 0 20 3 51 2 2 0 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 14 7 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 203 116 0 0 0 0 301 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 110 0 0 0 0 826 0 0 0 100 3 0 0 0 13 3 38 0 0 0 0 1035 0 0 0 100 4 0 0 3 252 122 50 0 1 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 6 0 1 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:01:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 118 0 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 1 0 0 0 824 0 0 0 100 3 0 0 0 15 4 40 1 0 1 0 1037 0 0 0 100 4 0 0 3 249 122 44 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 201 112 1 0 0 0 300 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1034 0 0 0 100 4 0 0 3 249 122 42 0 0 0 0 20 0 0 0 100 5 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 118 0 0 0 0 302 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 825 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 13 1 14 0 1 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 203 122 0 0 0 0 307 0 0 0 100 1 0 0 0 9 1 6 0 0 0 0 8 0 0 0 100 2 0 0 21 119 55 122 0 1 0 0 838 0 0 0 100 3 0 0 0 13 3 38 1 0 1 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 14 6 2 0 0 0 0 0 0 0 0 100 6 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 10 0 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 114 0 0 0 0 302 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 826 0 0 0 100 3 0 0 0 13 3 36 2 0 2 0 1035 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 7 0 0 0 10 0 10 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:01:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2311 201 124 0 2 0 0 300 0 1 0 99 1 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 2 0 0 21 116 56 110 0 0 1 0 824 0 0 0 100 3 0 0 0 17 5 40 0 0 1 0 1037 0 0 0 100 4 0 0 7 250 122 44 0 0 1 0 20 0 0 0 100 5 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 6 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 7 0 0 0 12 1 4 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:01:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 1 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 825 0 0 0 100 3 0 0 0 12 3 36 1 0 1 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 201 114 0 0 0 0 300 0 0 0 99 1 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 2 0 0 21 116 56 114 0 0 0 0 827 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1036 0 0 0 100 4 0 0 3 249 123 42 0 0 0 0 21 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 202 122 0 0 0 0 307 0 1 0 99 1 0 0 0 15 3 12 0 0 0 0 31 0 0 0 100 2 0 0 21 128 57 134 1 1 0 0 838 0 0 0 100 3 0 0 0 12 3 38 0 0 1 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 15 8 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 10 0 6 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:01:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2303 201 112 0 0 0 0 300 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 1 0 0 825 0 0 0 100 3 0 0 0 15 4 38 2 0 0 0 1057 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:01:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 118 1 0 0 0 302 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 55 114 1 0 0 0 825 0 0 0 100 3 0 0 0 19 4 50 0 1 0 0 1036 0 0 0 100 4 0 0 3 249 122 44 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 114 0 0 0 0 300 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 116 56 114 0 0 0 0 826 0 0 0 100 3 0 0 0 14 3 38 1 0 0 0 1036 0 0 0 100 4 0 0 3 252 122 50 0 1 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 202 114 0 0 0 0 302 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 1 0 0 0 825 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1035 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:01:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 201 118 0 0 0 0 305 0 0 0 99 1 0 0 0 9 1 6 0 0 0 0 7 0 0 0 100 2 0 0 21 123 57 126 0 0 1 0 841 0 0 0 100 3 0 0 0 13 3 38 1 0 0 0 1037 0 0 0 100 4 0 0 3 249 122 42 0 0 0 0 20 0 0 0 100 5 0 0 0 20 7 12 0 1 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 1 0 0 0 302 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 825 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 13 1 14 0 1 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 114 0 0 1 0 300 0 0 0 100 1 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 2 0 0 21 115 56 112 0 0 0 0 825 0 0 0 100 3 0 0 0 17 5 40 1 0 2 0 1036 0 0 0 100 4 0 0 3 249 122 44 0 0 1 0 20 0 0 0 100 5 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 6 0 0 0 10 2 4 0 0 1 0 0 0 0 0 100 7 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:02:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2304 202 114 0 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 56 114 1 0 0 0 826 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 7 0 0 0 12 0 12 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:02:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2311 201 124 0 1 0 0 300 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 826 0 0 0 100 3 0 0 0 11 3 36 0 0 1 0 1036 0 0 0 100 4 0 0 3 249 123 42 0 0 0 0 21 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 120 1 0 0 0 307 0 0 0 99 1 0 0 0 11 2 8 0 0 0 0 8 0 0 0 100 2 0 0 21 123 57 124 1 0 0 0 837 0 0 0 100 3 0 0 0 13 3 38 1 0 1 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 14 7 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 114 0 0 0 0 300 0 1 0 99 1 0 0 0 16 2 18 0 1 0 0 9 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 13 3 40 0 0 0 0 1053 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:02:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 118 0 0 0 0 302 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 2 0 0 21 122 56 124 1 1 0 0 826 0 0 0 100 3 0 0 0 15 4 40 1 0 0 0 1036 0 0 0 100 4 0 0 3 250 122 44 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 11 2 6 1 0 0 0 1 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 112 0 0 0 0 300 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 1 0 0 0 302 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 55 114 1 0 0 0 825 0 0 0 100 3 0 0 0 17 3 46 1 1 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 201 120 0 0 0 0 305 0 1 0 99 1 0 0 0 9 1 6 0 0 0 0 7 0 0 0 100 2 0 0 21 123 57 126 0 0 0 0 842 0 0 0 100 3 0 0 0 15 3 40 1 0 1 0 1036 0 0 0 100 4 0 0 3 252 122 52 0 1 0 0 20 0 0 0 100 5 0 0 0 16 8 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 202 114 0 0 0 0 302 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 116 56 114 1 0 0 0 827 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1036 0 0 0 100 4 0 0 3 248 122 40 1 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2308 201 112 0 0 1 0 300 0 0 0 100 1 0 0 0 10 2 2 0 0 1 0 0 0 0 0 100 2 0 0 21 116 56 110 0 0 1 0 824 0 0 0 100 3 0 0 0 18 5 40 1 0 1 0 1036 0 0 0 100 4 0 0 7 252 122 48 0 1 0 0 20 0 0 0 100 5 0 0 0 15 2 12 0 1 1 0 0 0 0 0 100 6 0 0 0 11 2 4 0 0 1 0 0 0 0 0 100 7 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:02:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 114 1 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 826 0 0 0 100 3 0 0 0 12 3 36 1 0 1 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 11 2 6 0 0 0 0 1 0 0 0 100 6 0 0 0 13 1 14 0 1 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2302 201 112 0 0 0 0 300 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 824 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1035 0 0 0 100 4 0 0 3 249 123 42 0 0 0 0 21 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 122 0 0 0 0 307 0 1 0 99 1 0 0 0 11 2 8 0 0 0 0 8 0 0 0 100 2 0 0 21 122 57 124 1 0 1 0 840 0 0 0 100 3 0 0 0 12 3 38 0 0 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 16 9 4 0 0 0 0 1 0 0 0 100 6 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 7 0 0 0 13 0 14 0 1 1 0 0 0 0 0 100 March 2, 2026 at 07:02:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2312 201 122 0 1 0 0 300 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 1 0 0 824 0 0 0 100 3 0 0 0 14 4 38 1 0 0 0 1057 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:02:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 202 118 1 0 0 0 302 0 0 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 850 0 0 0 100 3 0 0 0 15 4 40 1 0 1 0 1036 0 0 0 100 4 0 0 3 250 122 44 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 116 0 0 0 0 300 0 1 0 99 1 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 2 0 0 21 115 55 112 1 0 0 0 824 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 116 0 0 0 0 302 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 2 0 0 21 122 56 124 1 1 0 0 826 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1035 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2306 201 120 0 0 0 0 305 0 0 0 99 1 0 0 0 9 1 6 0 0 0 0 7 0 0 0 100 2 3 0 21 124 57 128 0 0 0 0 842 0 0 0 100 3 0 0 0 13 3 38 1 0 1 0 1037 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 16 8 2 0 0 1 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 11 0 8 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2309 202 114 1 0 0 0 302 0 1 0 99 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 55 114 1 0 0 0 825 0 0 0 100 3 0 0 0 16 3 46 0 1 0 0 1036 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 112 0 0 1 0 300 0 0 0 99 1 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 2 0 0 21 115 56 110 0 0 1 0 825 0 0 0 100 3 0 0 0 19 5 44 1 1 1 0 1036 0 0 0 100 4 0 0 3 254 122 54 0 1 1 0 20 0 0 0 100 5 0 0 0 9 2 2 0 0 1 0 0 0 0 0 100 6 0 0 0 10 2 4 0 0 1 0 0 0 0 0 100 7 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:02:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 114 0 0 0 0 302 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 117 56 114 1 0 0 0 826 0 0 0 100 3 0 0 0 12 3 36 1 0 0 0 1034 0 0 0 100 4 0 0 3 247 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2307 201 112 0 0 0 0 300 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 114 55 112 0 0 0 0 825 0 0 0 100 3 0 0 0 11 3 36 0 0 0 0 1037 0 0 0 100 4 0 0 3 251 123 44 0 0 0 0 21 0 0 0 100 5 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2308 202 122 1 0 0 0 307 0 0 0 99 1 0 0 0 12 2 8 0 0 0 0 8 0 0 0 100 2 0 0 21 39 15 40 1 0 0 0 838 0 0 0 100 3 0 0 0 94 43 121 1 1 1 0 1036 0 0 0 100 4 0 0 3 245 121 40 0 0 0 0 20 0 0 0 100 5 0 0 0 17 8 6 0 0 0 0 1 0 0 0 100 6 0 0 0 13 1 14 0 1 0 0 0 0 0 0 100 7 0 0 0 10 0 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 112 0 0 0 0 300 0 0 0 100 1 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 2 0 0 21 14 5 10 0 0 0 0 825 0 0 0 100 3 0 0 0 111 52 135 1 0 1 0 1036 0 0 0 100 4 0 0 3 248 122 40 0 0 0 0 20 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 8 1 6 0 1 0 0 0 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 March 2, 2026 at 07:02:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 24 0 3 2322 202 144 0 0 0 0 433 0 1 0 99 1 0 0 0 17 1 22 0 2 0 0 95 0 0 0 100 2 1288 0 24 26 6 30 2 0 0 0 862 0 0 0 99 3 5 0 0 122 53 157 1 4 0 0 1100 0 0 0 100 4 0 0 3 246 120 42 0 1 1 0 33 0 0 0 100 5 4 0 1 72 63 10 0 0 0 0 17 0 0 0 100 6 4 0 0 15 2 12 1 1 0 0 79 0 0 0 99 7 0 0 0 17 0 24 0 1 0 0 0 0 0 0 100 March 2, 2026 at 07:02:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2585 201 678 0 1 4 0 300 0 1 0 99 1 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 2 0 0 21 16 5 12 0 0 0 0 824 0 0 0 100 3 0 0 0 51 22 76 1 0 1 0 1037 0 0 0 100 4 2563 0 3 267 102 118 1 0 28 0 453 1 1 0 98 5 0 0 0 416 408 4 0 0 49 0 0 0 0 0 100 6 0 0 0 74 33 72 0 1 0 0 11 0 0 0 100 7 0 0 0 284 0 546 0 0 26 0 0 0 1 0 99 March 2, 2026 at 07:02:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 3113 232 1732 1 2 17 0 302 0 1 0 99 1 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 2 0 0 21 15 5 12 1 0 0 0 825 0 0 0 100 3 0 0 0 14 3 36 1 0 0 0 1038 0 0 0 100 4 0 0 3 245 102 68 1 0 27 0 325 0 1 0 99 5 0 0 0 1093 1081 8 0 1 122 0 0 0 1 0 99 6 0 0 0 178 21 282 2 3 69 0 1024 1 2 0 98 7 0 0 0 770 0 1540 0 0 96 0 0 0 2 0 98 March 2, 2026 at 07:02:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2423 251 346 0 0 2 0 300 0 1 0 99 1 0 0 0 12 1 12 0 1 0 0 10 0 0 0 100 2 0 0 21 14 5 10 0 0 0 0 826 0 0 0 100 3 0 0 0 13 3 38 0 1 1 0 1035 0 0 0 100 4 0 0 3 209 103 0 0 0 0 0 0 0 0 0 100 5 0 0 0 169 160 4 0 0 5 0 0 0 0 0 100 6 0 0 0 46 4 63 0 3 2 0 122 0 0 0 100 7 0 0 0 86 2 154 0 2 4 0 23 0 0 0 100 March 2, 2026 at 07:02:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2397 247 289 0 2 1 0 302 0 1 0 99 1 0 0 0 35 7 40 0 2 1 0 63 0 0 0 100 2 0 0 21 20 5 22 1 1 0 0 825 0 0 0 100 3 0 0 0 13 2 36 1 0 1 0 1038 0 0 0 100 4 0 0 3 207 102 0 0 0 0 0 0 0 0 0 100 5 0 0 0 143 134 4 0 1 9 0 0 0 0 0 100 6 0 0 0 19 4 14 0 1 0 0 11 0 0 0 100 7 1 0 0 56 1 96 0 1 3 0 16 0 0 0 100 March 2, 2026 at 07:02:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2412 201 326 0 10 49 0 300 0 1 0 99 1 0 0 0 154 54 188 0 13 55 0 11 0 0 0 100 2 0 0 21 46 6 74 0 9 52 0 826 0 0 0 100 3 0 0 0 120 62 129 2 9 47 0 1037 0 1 0 99 4 0 0 3 321 102 223 0 11 47 0 116 0 0 0 99 5 0 0 0 222 171 90 0 10 59 0 0 0 0 0 100 6 0 0 0 54 2 92 0 16 56 0 0 0 0 0 100 7 0 0 0 117 2 217 0 11 38 0 0 0 0 0 100 March 2, 2026 at 07:02:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2357 203 215 1 1 0 0 302 0 0 0 99 1 0 0 0 125 51 134 0 1 0 0 81 0 0 0 100 2 0 0 21 18 5 16 1 0 0 0 828 0 0 0 100 3 0 0 0 19 4 50 0 1 0 0 1038 0 0 0 100 4 0 0 3 216 105 10 0 0 0 0 11 0 0 0 100 5 0 0 0 130 120 6 0 1 1 0 0 0 0 0 100 6 0 0 0 13 3 10 0 1 0 0 0 0 0 0 100 7 0 0 0 59 2 102 0 1 2 0 0 0 0 0 100 March 2, 2026 at 07:02:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2305 201 116 0 0 0 0 300 0 0 0 100 1 3 0 0 114 53 108 0 0 0 0 8 0 0 0 100 2 0 0 21 14 5 10 0 0 0 0 824 0 0 0 100 3 0 0 0 12 2 38 1 1 0 0 1037 0 0 0 100 4 0 0 3 214 103 12 0 1 0 0 1 0 0 0 100 5 0 0 0 12 4 4 0 1 0 0 0 0 0 0 100 6 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 11 1 6 0 0 0 0 0 0 0 0 100 March 2, 2026 at 07:02:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2310 202 116 0 0 0 0 302 0 0 0 100 1 0 0 0 123 56 120 0 0 0 0 21 0 0 0 100 2 0 0 21 20 5 20 2 0 0 0 835 0 0 0 100 3 0 0 0 10 2 36 0 0 1 0 1037 0 0 0 100 4 0 0 3 222 104 20 0 0 0 0 40 0 0 0 100 5 0 0 0 28 19 6 0 0 0 0 1 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 0 10 1 7 0 0 1 0 0 0 0 0 100 March 2, 2026 at 07:02:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2346 201 197 0 0 1 0 300 0 1 0 99 1 0 0 0 129 52 138 0 0 0 0 90 0 0 0 100 2 0 0 21 15 5 14 0 1 0 0 828 0 0 0 100 3 0 0 0 15 3 42 2 0 0 0 1075 0 0 0 100 4 0 0 3 214 104 8 0 0 0 0 11 0 0 0 100 5 0 0 0 146 133 14 0 1 5 0 0 0 0 0 100 6 0 0 0 9 1 6 0 1 0 0 0 0 0 0 100 7 0 0 0 53 2 88 0 0 3 0 1 0 0 0 100 March 2, 2026 at 07:02:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2361 202 216 1 12 58 0 302 0 1 0 99 1 0 0 0 174 54 226 0 13 50 0 33 0 0 0 100 2 0 0 21 82 5 145 1 16 31 0 828 0 0 0 100 3 7 0 0 168 116 282 0 20 50 0 1040 0 0 0 99 4 1 0 3 313 102 211 0 15 53 0 39 0 0 0 100 5 0 0 0 154 86 121 0 12 54 0 0 0 0 0 100 6 0 0 0 74 2 137 0 19 80 0 1 0 0 0 100 7 0 0 0 61 1 110 0 13 38 0 0 0 0 0 100