April 2, 2026 at 04:30:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 999 0 266 2383 132 5733 54 311 1641 24 6453 1 5 0 94 1 1316 0 69 464 8 5369 17 313 1652 34 12855 5 6 0 89 2 1000 0 91 303 14 5654 13 414 1415 47 12119 4 3 0 93 3 1105 0 78 657 274 5611 13 536 1412 29 10524 1 3 0 95 4 1058 0 46 583 255 4993 12 253 1527 39 10301 2 3 0 95 5 738 0 207 5387 5061 3446 21 244 2511 40 6927 1 7 0 92 6 940 0 75 346 19 4525 13 338 1392 27 8573 5 3 0 92 7 1215 0 408 204 13 6649 20 302 1646 12 9149 7 4 0 89 April 2, 2026 at 04:30:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4734 0 48 2231 109 515 3 95 461 52 5133 6 22 0 72 1 9152 0 92 364 1 589 3 100 493 60 6538 8 4 0 88 2 12552 0 33 383 2 568 8 71 776 56 6405 14 5 0 81 3 3656 0 36 207 20 372 3 66 464 40 2987 5 8 0 87 4 4082 0 739 365 85 581 1 88 558 76 3425 1 2 0 97 5 3096 0 21 521 31 534 1 62 273 49 3713 3 2 0 95 6 3256 0 14 112 2 241 4 43 205 23 2316 12 3 0 85 7 3545 0 87 361 94 489 1 60 574 44 1812 0 2 0 97 April 2, 2026 at 04:30:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2176 117 834 5 123 2900 0 294 0 10 0 90 1 0 0 0 49 1 592 4 116 2889 0 0 0 9 0 91 2 0 0 0 49 0 615 5 110 3056 0 0 0 9 0 91 3 0 0 0 449 406 829 7 127 2822 0 300 0 10 0 90 4 32 0 25 770 545 1734 3 216 2294 0 1595 0 2 0 98 5 0 0 0 59 1 597 7 110 2851 1 0 0 9 0 91 6 47 0 0 280 4 1414 0 205 2419 2 327 0 3 0 97 7 0 0 2 251 105 504 6 89 1897 0 9 0 10 0 90 April 2, 2026 at 04:30:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2117 102 106 0 0 1 0 296 0 0 0 100 1 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 300 0 0 0 100 4 27 0 17 310 154 134 0 0 0 0 1312 0 0 0 100 5 0 0 0 15 1 10 0 1 0 0 0 0 0 0 100 6 0 0 20 16 3 10 5 3 0 0 559 0 1 0 99 7 0 0 3 211 102 4 0 1 0 0 0 0 0 0 100 April 2, 2026 at 04:30:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 116 0 1 0 0 294 0 0 0 100 1 0 0 0 11 2 4 0 1 1 0 0 0 0 0 100 2 2 0 0 15 1 16 0 1 1 0 13 0 0 0 100 3 0 0 0 12 3 4 0 0 1 0 300 0 0 0 100 4 0 0 17 315 154 144 0 0 1 0 1320 0 0 0 100 5 0 0 0 17 6 6 0 0 1 0 0 0 0 0 100 6 0 0 7 13 4 6 0 0 1 0 558 0 0 0 100 7 3 0 3 222 105 18 0 0 1 0 18 0 0 0 100 April 2, 2026 at 04:30:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2112 103 114 0 0 0 0 297 0 0 0 100 1 0 0 0 11 2 6 0 0 0 0 5 0 0 0 100 2 0 0 2 10 2 6 0 0 0 0 4 0 0 0 100 3 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 4 7 0 17 217 106 40 1 0 1 0 1315 0 0 0 100 5 0 0 0 64 27 60 0 1 0 0 0 0 0 0 100 6 0 0 7 55 24 52 0 1 0 0 558 0 0 0 100 7 0 0 3 212 103 6 0 1 0 0 0 0 0 0 100 April 2, 2026 at 04:30:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14419 0 8 3315 114 16880 3369 4537 30953 333 99256 17 34 0 49 1 14063 0 2 1575 4 16865 3559 4340 33187 337 94227 16 33 0 51 2 17071 0 7 1543 9 14467 3090 3857 35651 379 92976 18 34 0 48 3 55299 0 0 1350 163 15602 3285 3844 39484 357 97033 19 39 0 43 4 13047 0 758 1737 270 14953 2865 4053 37777 358 88611 16 34 0 50 5 14717 0 1 1221 9 15992 3195 3969 39681 349 96749 16 34 0 49 6 14697 0 7 1560 34 16246 3228 3929 37961 351 95959 14 36 0 50 7 14892 0 4 1443 112 15503 2853 3545 39528 371 90798 15 35 0 49 April 2, 2026 at 04:30:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1108 0 0 4021 116 28310 4303 5057 21542 171 166023 36 63 0 1 1 1098 0 0 1987 24 28747 4634 5003 22473 183 166245 36 63 0 1 2 1047 0 0 2014 22 30501 4896 5207 22359 170 182488 36 63 0 1 3 1341 0 0 2752 689 31738 4878 5292 21485 226 183825 35 64 0 1 4 815 0 1439 2780 791 30998 4922 4802 25549 204 178956 40 60 0 1 5 702 0 0 2282 22 33788 5294 5377 21910 201 190538 37 62 0 1 6 417 0 7 2182 33 29623 4888 4851 23178 283 170743 41 58 0 1 7 644 0 3 2321 124 31745 5105 5138 24813 193 179431 36 63 0 1 April 2, 2026 at 04:30:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 76 0 2563 4262 123 32421 4406 4921 18854 329 172660 36 64 0 0 1 484 0 9 2761 34 35270 4419 5277 18181 312 173311 37 63 0 0 2 228 0 25 2633 10 34919 4537 5212 18105 293 169784 38 62 0 0 3 302 0 17 3413 713 35397 4401 5256 18716 320 179160 39 60 0 0 4 215 0 1401 3153 808 30529 4041 4805 16705 295 162004 37 62 0 0 5 515 0 0 2554 19 33847 4239 4973 17754 239 175112 38 61 0 0 6 398 0 2359 2253 15 34869 3930 4608 16749 214 169767 39 60 0 1 7 1 0 14 2653 117 31154 3804 4394 21534 307 157844 37 62 0 0 April 2, 2026 at 04:30:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 57 0 0 3957 124 33127 4015 5181 18501 258 160698 36 64 0 1 1 0 0 98 1858 24 33374 4116 4937 21959 221 158008 37 62 0 0 2 0 0 7 1930 26 37722 4199 5255 19390 265 169086 38 62 0 1 3 10 0 12 2818 892 33607 4435 4951 23069 247 160431 40 59 0 1 4 0 0 1416 2603 988 32594 3785 4793 20290 264 154224 38 62 0 1 5 0 0 0 1943 36 33224 4087 4846 24238 141 159727 37 63 0 1 6 13 0 0 1981 17 33052 4256 4892 20041 195 159505 38 62 0 1 7 0 0 3 2119 124 33552 4133 5058 17115 258 159815 36 64 0 1 April 2, 2026 at 04:30:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 132 0 0 3741 122 34216 3630 4516 18057 104 157080 34 65 0 1 1 0 0 0 1618 18 29830 3711 4201 17515 90 148322 36 64 0 0 2 136 0 7 1581 19 29645 3489 4210 17176 122 147972 38 62 0 0 3 0 0 13 2259 622 34518 3601 4546 17693 94 156002 37 63 0 1 4 33 0 1414 2225 712 31612 3854 4390 17468 60 152337 39 61 0 0 5 0 0 0 1680 22 32482 3786 4324 18879 85 154203 39 60 0 1 6 33 0 0 1718 35 31216 3814 4463 16269 90 160560 38 61 0 1 7 33 0 3 2037 127 31797 3835 4424 17163 90 157284 36 63 0 0 April 2, 2026 at 04:30:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 3211 4147 126 31682 4411 4854 20199 85 160368 40 60 0 1 1 0 0 7 2431 31 34283 4409 5145 16225 65 174868 38 61 0 1 2 2 0 7 2578 32 38771 4550 5719 20911 131 190831 38 62 0 1 3 3 0 13 2938 707 36695 4208 5736 18042 70 181117 35 64 0 1 4 2 0 1410 3153 819 36977 4647 5472 20876 54 182553 39 61 0 1 5 2 0 0 2428 30 33757 4145 5412 21921 82 172670 36 64 0 1 6 1 0 0 2215 24 31500 3650 4944 15433 81 164052 39 60 0 1 7 1 0 3 2584 129 35760 4390 5349 17619 157 178243 37 63 0 1 April 2, 2026 at 04:30:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 50 0 93 3013 113 21781 1948 2959 14471 31 97878 27 43 0 30 1 3 0 0 981 17 23859 1880 3388 14649 68 106936 28 43 0 30 2 9 0 7 1021 13 22480 1888 3124 16032 65 106188 24 45 0 31 3 3 0 13 1442 552 24683 1698 3109 14951 25 106749 25 42 0 32 4 2 0 996 1548 651 22981 1642 2958 18639 17 100186 26 45 0 30 5 37 0 0 980 29 23841 1771 3308 12394 60 105726 26 43 0 32 6 7 0 0 1042 37 23865 2048 3397 12545 49 105740 25 42 0 33 7 6 0 3 1282 123 24113 2094 3340 14247 34 105924 25 44 0 32 April 2, 2026 at 04:30:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2141 109 499 2 60 2110 38 10 0 1 0 99 1 0 0 0 129 1 372 2 39 1735 40 0 0 1 0 99 2 0 0 7 150 2 335 0 52 1612 37 259 0 1 0 99 3 1 0 14 191 77 416 0 52 1604 18 280 0 1 0 99 4 0 0 2 388 182 387 1 60 2270 38 2 0 1 0 99 5 0 0 0 158 1 380 1 48 1663 25 1169 0 1 0 99 6 0 0 0 229 55 634 3 70 2030 41 894 0 1 0 99 7 0 0 4 349 101 369 1 54 1970 26 0 0 1 0 99 April 2, 2026 at 04:30:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2120 108 134 0 1 0 0 10 0 0 0 100 1 0 0 0 13 2 6 0 1 1 0 3 0 0 0 100 2 0 0 7 15 3 8 0 1 1 0 259 0 0 0 100 3 0 0 14 9 2 2 0 0 1 0 266 0 0 0 100 4 0 0 7 210 102 2 0 1 1 0 0 0 0 0 100 5 0 0 0 13 4 32 1 0 1 0 1168 0 0 0 100 6 0 0 0 121 57 112 0 0 1 0 595 0 0 0 100 7 0 0 7 215 102 8 0 2 1 0 306 0 0 0 100 April 2, 2026 at 04:30:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2119 109 130 0 0 0 0 13 0 0 0 100 1 0 0 0 7 1 4 0 1 0 0 0 0 0 0 100 2 0 0 7 11 2 8 0 0 2 0 259 0 0 0 100 3 0 0 14 8 1 4 0 1 0 0 266 0 0 0 100 4 0 0 3 211 103 6 0 1 0 0 5 0 0 0 100 5 0 0 0 8 1 32 1 0 1 0 1169 0 0 0 100 6 0 0 0 114 54 110 0 1 0 0 594 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 300 0 0 0 100 April 2, 2026 at 04:30:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 103 0 14 2180 110 2167 45 117 154 3 7212 7 3 0 89 1 41231 0 0 107 5 2285 40 117 109 7 6054 6 6 0 88 2 1835 0 7 439 3 1740 19 62 171 10 6649 7 3 0 90 3 122 0 15 628 3 2092 22 83 129 11 6181 4 2 0 94 4 718 0 235 781 102 1938 19 66 104 8 5620 5 2 0 93 5 67 0 0 231 2 1748 16 56 164 9 6715 6 2 0 92 6 116 0 6 637 48 1733 6 48 64 3 4145 2 1 0 97 7 22 0 16 277 106 1621 17 49 107 3 6397 6 9 0 85 April 2, 2026 at 04:30:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 0 2578 112 14901 626 1402 5386 19 39022 27 18 0 55 1 27 0 0 461 16 13967 340 1257 5371 16 35785 25 18 0 57 2 27 0 14 469 5 13148 441 1158 5022 13 36896 30 18 0 52 3 33 0 0 748 309 12789 473 978 5125 12 35076 26 16 0 58 4 27 0 1417 738 391 12098 342 880 4885 16 34943 29 17 0 54 5 17 0 0 373 9 11696 189 824 5044 13 30100 24 16 0 60 6 20 0 13 416 6 10750 231 758 4615 10 31883 29 18 0 52 7 20 0 70 586 108 10755 213 737 5005 11 31278 30 17 0 53 April 2, 2026 at 04:30:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 20 0 17 2637 110 14950 570 1762 6729 26 37405 25 20 0 55 1 21 0 0 446 13 14554 497 1609 6995 29 35968 24 20 0 56 2 10 0 7 476 11 13451 407 1376 6498 16 34246 26 21 0 53 3 9 0 0 924 492 12465 342 1171 6114 21 32281 27 20 0 53 4 18 0 1415 922 589 13272 573 1174 6895 26 35130 26 20 0 54 5 23 0 7 468 16 12160 594 1057 5947 19 33702 32 19 0 49 6 9 0 0 499 6 12149 396 1054 6386 16 32438 28 18 0 54 7 5 0 3 649 108 10686 276 993 6384 25 29292 28 20 0 52 April 2, 2026 at 04:31:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 14 2583 108 14265 587 1548 6633 18 36424 24 20 0 56 1 9 0 0 496 11 14277 593 1390 6901 10 35113 25 18 0 57 2 14 0 7 445 13 13181 340 1212 6618 14 35528 28 20 0 52 3 14 0 0 829 418 12004 349 1057 6084 21 32546 28 21 0 51 4 10 0 1416 818 515 11153 274 945 5969 24 33676 32 22 0 47 5 13 0 0 458 17 11212 422 946 5666 29 33018 32 20 0 48 6 12 0 7 411 14 11352 224 923 6739 16 29606 23 20 0 57 7 13 0 3 663 108 11088 313 865 6702 15 28328 25 17 0 58 April 2, 2026 at 04:31:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 0 2638 114 15105 808 1563 6660 14 37635 29 18 0 53 1 25 0 14 427 6 13568 417 1363 6677 22 34325 25 21 0 54 2 13 0 0 424 8 13312 368 1203 6049 16 32236 24 20 0 57 3 4 0 7 820 324 12592 482 1023 6321 15 34190 32 19 0 50 4 5 0 1458 754 442 11301 266 908 6311 18 32675 29 22 0 49 5 6 0 0 426 16 11718 236 923 6390 16 29041 22 19 0 59 6 11 0 0 463 12 11849 510 889 6156 24 31751 26 19 0 55 7 5 0 3 607 111 9986 233 806 6029 24 28782 29 20 0 51 April 2, 2026 at 04:31:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 0 2549 112 13397 497 1526 6221 11 32708 26 21 0 54 1 11 0 10 470 8 13765 528 1389 6490 8 33307 26 18 0 56 2 7 0 0 447 9 13139 391 1273 5716 14 33161 25 20 0 54 3 12 0 7 810 357 12062 467 1074 6408 15 31058 26 20 0 54 4 10 0 1446 774 453 10712 288 878 6116 7 30699 27 24 0 49 5 10 0 3 408 15 10670 237 826 5960 13 28910 28 20 0 51 6 11 0 0 451 5 10695 393 847 5940 11 30559 32 19 0 49 7 5 0 33 654 117 11313 357 886 6503 7 26682 24 18 0 58 April 2, 2026 at 04:31:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 14 2526 108 14504 537 1579 6880 9 35825 22 20 0 58 1 16 0 0 523 18 15320 841 1495 6631 11 37981 24 19 0 58 2 5 0 0 434 8 13245 387 1210 5806 19 35464 27 20 0 53 3 12 0 7 696 320 12387 349 1070 6291 7 32993 26 20 0 53 4 8 0 1416 798 430 12354 538 1024 6142 13 34581 29 19 0 52 5 10 0 0 407 6 10117 271 825 5966 18 30730 32 22 0 46 6 9 0 0 386 12 10792 238 873 6350 8 30790 26 20 0 54 7 8 0 3 626 112 10649 350 831 6393 20 30766 29 18 0 52 April 2, 2026 at 04:31:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 12 0 0 2529 107 14174 429 1402 6351 22 35797 24 21 0 55 1 11 0 14 440 9 14083 434 1292 6807 23 34725 24 18 0 58 2 13 0 0 467 13 13555 651 1156 6131 23 36667 28 20 0 52 3 5 0 7 739 315 12443 390 1006 6360 16 34742 28 20 0 52 4 4 0 1413 701 389 11730 359 909 6235 27 34971 28 21 0 51 5 9 0 0 450 8 11598 443 858 6359 26 33447 31 20 0 50 6 7 0 0 387 11 11435 236 830 6314 28 30940 24 20 0 57 7 10 0 3 576 105 10520 213 766 6070 13 29335 27 19 0 54 April 2, 2026 at 04:31:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 0 2535 112 14208 464 1534 6453 14 34949 23 18 0 59 1 6 0 14 431 14 13146 398 1339 6077 17 33836 25 19 0 57 2 7 0 7 520 17 13702 563 1287 6089 14 34918 28 17 0 55 3 13 0 0 757 328 11559 316 1045 5674 14 31336 28 18 0 54 4 8 0 1375 743 430 11274 268 937 6033 12 30756 27 18 0 55 5 8 0 0 391 15 10501 239 856 6055 16 28352 23 18 0 59 6 5 0 0 410 13 11176 236 850 6449 23 28621 25 17 0 58 7 5 0 3 674 112 11337 520 840 5953 16 30761 28 16 0 56 April 2, 2026 at 04:31:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2126 101 760 1 128 2981 11 11 0 4 0 96 1 2 0 14 288 5 675 1 101 2705 6 283 0 4 0 96 2 0 0 7 250 3 642 2 119 2582 0 259 0 4 0 96 3 0 0 0 299 186 714 1 111 2794 2 305 0 4 0 96 4 0 0 18 452 290 719 1 126 2829 16 308 0 4 0 96 5 0 0 0 259 48 1214 2 141 2984 10 1497 0 2 0 97 6 0 0 0 196 2 1052 1 146 2827 7 14 0 2 0 98 7 0 0 2 483 103 725 1 116 2928 7 1 0 4 0 96 April 2, 2026 at 04:31:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 101 18 0 1 1 0 3 0 0 0 100 1 0 0 14 17 6 16 0 1 0 0 276 0 0 0 100 2 0 0 7 21 7 20 0 2 0 0 272 0 0 0 100 3 0 0 0 13 2 6 0 0 0 0 301 0 0 0 100 4 0 0 3 216 104 6 0 1 0 0 301 0 0 0 100 5 0 0 0 118 55 140 1 0 0 0 1479 0 0 0 99 6 0 0 0 6 0 2 0 0 0 0 4 0 0 0 100 7 0 0 3 310 102 104 0 1 0 0 3 0 0 0 100 April 2, 2026 at 04:31:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 102 14 0 0 0 0 2 0 0 0 100 1 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 2 0 0 7 28 9 24 1 2 0 0 268 0 0 0 100 3 0 0 0 14 1 10 0 3 0 0 300 0 0 0 100 4 0 0 3 215 104 6 0 0 0 0 301 0 0 0 100 5 0 0 0 112 53 136 1 0 0 0 1478 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 309 102 102 0 0 0 0 0 0 0 0 100 April 2, 2026 at 04:31:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 6 2120 103 35 0 7 2 4 38 0 0 0 99 1 18 0 33 27 1 38 0 7 21 3 383 0 0 0 100 2 1060 0 17 66 10 195 1 10 146 2 1564 0 1 0 98 3 1913 0 12 55 3 285 3 10 142 0 2568 1 1 0 99 4 1278 0 13 262 104 43 0 10 106 5 701 0 0 0 99 5 1063 0 15 57 10 81 2 8 86 3 1809 0 1 0 99 6 948 0 22 123 44 133 0 11 44 3 265 0 2 0 97 7 275 0 42 346 103 148 1 16 4 2 411 0 0 0 99 April 2, 2026 at 04:31:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 0 2155 112 161 2 23 4450 1 37 0 2 0 98 1 21 0 17 248 43 352 0 17 213 8 1050 0 2 0 98 2 8885 0 21 174 5 296 0 45 874 9 2109 1 6 0 93 3 12831 0 329 95 4 147 8 46 2315 3 21322 2 22 0 76 4 9809 0 72 388 108 249 1 42 550 6 3822 1 3 0 96 5 4310 0 55 425 33 239 0 43 2581 7 3210 1 3 0 97 6 4 0 0 32 1 42 0 11 4141 1 64 0 2 0 98 7 506 0 58 265 103 94 3 18 71 3 1691 0 5 0 95 April 2, 2026 at 04:31:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2013 0 104 2282 100 474 3 69 84 49 2370 1 2 0 97 1 1703 0 416 376 15 368 7 57 90 45 5539 1 2 0 97 2 1178 0 15 389 14 416 1 67 94 40 1465 0 1 0 99 3 1512 0 127 378 34 423 0 61 134 37 1628 0 2 0 98 4 5303 0 275 571 105 387 2 56 283 54 7191 2 5 0 94 5 5814 0 751 344 20 417 5 65 358 53 3045 1 3 0 96 6 5524 0 21 276 2 392 0 74 330 53 4640 1 2 0 97 7 3567 0 16 524 102 322 0 51 233 43 1435 0 1 0 99 April 2, 2026 at 04:31:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 108 0 0 0 0 2 0 0 0 100 1 0 0 14 17 3 14 0 0 0 0 267 0 0 0 100 2 0 0 7 14 3 10 1 0 0 0 258 0 0 0 100 3 0 0 0 112 51 108 0 0 0 0 300 0 0 0 100 4 0 0 3 210 103 4 0 1 0 0 300 0 0 0 100 5 0 0 0 13 3 38 1 1 1 0 1372 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 211 103 4 0 0 0 0 1 0 0 0 100 April 2, 2026 at 04:31:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2152 100 128 0 1 2 0 0 0 1 0 99 1 0 0 14 68 3 14 0 0 0 0 267 0 0 0 100 2 0 0 7 62 3 8 0 0 0 0 258 0 0 0 100 3 0 0 0 162 52 104 0 0 0 0 300 0 0 0 100 4 0 0 3 260 103 2 0 0 0 0 300 0 0 0 100 5 0 0 336 15 3 40 0 1 3 0 1346 0 1 0 99 6 0 0 0 59 1 2 0 0 0 0 1 0 0 0 100 7 0 0 3 262 102 4 0 0 1 0 0 0 0 0 100 April 2, 2026 at 04:31:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 108 0 0 1 0 2 0 0 0 100 1 0 0 14 16 2 18 0 1 0 0 266 0 0 0 100 2 0 0 7 11 3 8 0 0 0 0 258 0 0 0 100 3 0 0 0 109 51 104 0 1 0 0 300 0 0 0 100 4 0 0 3 209 103 2 0 0 0 0 300 0 0 0 100 5 0 0 0 12 3 36 1 0 1 0 1345 0 0 0 100 6 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 April 2, 2026 at 04:31:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2105 100 110 0 1 0 0 0 0 0 0 100 1 0 0 14 20 4 14 0 0 1 0 267 0 0 0 100 2 0 0 7 18 4 18 0 0 1 0 278 0 0 0 100 3 0 0 0 111 52 102 0 0 1 0 300 0 0 0 100 4 0 0 7 214 103 10 0 0 1 0 312 0 0 0 100 5 0 0 0 21 9 36 2 0 3 0 1346 0 0 0 100 6 0 0 0 12 2 4 0 1 1 0 1 0 0 0 100 7 0 0 7 223 104 18 0 0 1 0 10 0 0 0 100 April 2, 2026 at 04:31:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10968 0 4 2901 112 10255 1118 3100 29457 97 39671 12 46 0 42 1 9387 0 24 1118 12 11307 1330 3354 25164 79 43152 12 41 0 47 2 13657 0 12 1398 16 11774 1413 3501 10671 69 44768 13 38 0 50 3 7958 0 2 1430 406 10599 1391 3032 24764 117 40068 13 42 0 45 4 8485 0 717 1721 533 10437 1230 3113 14604 82 37553 12 37 0 51 5 9288 0 5 1038 11 10205 1287 3017 27985 82 39954 13 40 0 47 6 7635 0 140 1028 14 10853 1444 3149 27641 95 40900 12 54 0 34 7 6758 0 5 1168 109 8691 1165 2787 26171 76 33660 11 42 0 47 April 2, 2026 at 04:31:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 38 0 7 4362 132 18247 1899 5747 20436 179 69466 24 71 0 5 1 32 0 0 2386 38 20210 1975 6172 21311 172 73625 23 70 0 6 2 158 0 14 2314 47 19784 1906 6113 21595 184 74564 21 72 0 7 3 172 0 7 3086 822 20512 1990 6276 21552 200 74936 23 70 0 7 4 67 0 1400 3106 903 19075 2009 5896 20301 217 73514 24 69 0 7 5 853 0 6 2350 43 18983 1951 6029 21552 182 75122 21 71 0 8 6 2 0 6089 1438 35 18491 1911 5798 19747 199 69076 20 73 0 7 7 0 0 3 2484 136 17206 1924 5557 20731 195 67962 22 70 0 8 April 2, 2026 at 04:31:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1030 0 0 3390 127 19478 1716 5719 20087 148 72595 25 69 0 6 1 0 0 0 1438 30 20054 1765 5895 22065 150 74943 24 69 0 7 2 0 0 7 1383 34 19369 1689 5833 19994 114 74377 23 70 0 7 3 0 0 0 2199 811 20009 1816 5975 20238 189 75071 22 70 0 8 4 1028 0 1414 2173 932 19115 1848 5835 21595 159 73562 22 70 0 8 5 0 0 0 1387 33 19143 1657 5940 21010 185 73565 21 70 0 9 6 0 0 11 1481 29 19963 1919 5885 19494 157 76649 23 68 0 8 7 0 0 3 1503 128 17196 1574 5245 19633 131 67955 23 68 0 8 April 2, 2026 at 04:31:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 32 0 0 3503 128 16962 1808 5463 18444 122 66157 24 70 0 6 1 64 0 0 1383 31 18393 1684 5472 20906 127 69562 22 71 0 7 2 1569 0 0 1565 37 21434 2125 6075 22584 121 79115 23 69 0 8 3 194 0 0 2242 793 20657 1947 6235 19121 152 79335 22 71 0 7 4 128 0 1414 2269 890 19074 1933 5951 20354 139 73184 23 69 0 8 5 590 0 7 1652 37 19946 2133 6007 21269 93 75078 23 68 0 8 6 0 0 11 1514 33 18191 1853 5598 21198 105 71786 24 68 0 8 7 0 0 3 1625 136 19215 1795 5718 19822 192 75221 21 71 0 8 April 2, 2026 at 04:31:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 0 3187 126 14879 1375 4670 19006 85 56000 17 62 0 21 1 11 0 0 1308 34 16896 1607 4775 19738 78 60883 18 59 0 22 2 9 0 0 1304 28 15954 1673 4615 18785 113 58383 20 56 0 23 3 8 0 0 1892 728 15307 1472 4715 18640 117 59884 18 61 0 21 4 2 0 1163 1935 840 14593 1572 4390 18737 103 54104 19 59 0 22 5 2 0 0 1286 49 16884 1671 4873 18402 120 64061 19 58 0 23 6 2 0 47 1215 33 15780 1411 4650 16564 125 58546 18 60 0 22 7 20 0 99 1384 138 15253 1503 4631 19534 112 57892 18 57 0 25 April 2, 2026 at 04:31:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2147 111 393 0 64 1892 7 23 0 1 0 99 1 0 0 0 261 49 468 1 55 1675 12 4 0 1 0 99 2 0 0 0 39 1 594 1 69 1755 12 5 0 1 0 99 3 0 0 0 149 86 471 2 63 1933 30 297 0 1 0 99 4 0 0 4 374 194 504 2 60 1880 13 1450 0 1 0 99 5 0 0 0 159 3 409 1 50 1723 18 3 0 1 0 99 6 5 0 14 141 1 297 1 53 1409 8 311 0 1 0 99 7 0 0 9 309 103 452 0 57 1545 25 560 0 1 0 99 April 2, 2026 at 04:31:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2114 106 14 0 0 0 0 9 0 0 0 100 1 0 0 0 107 51 102 0 0 0 0 1 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 19 2 14 0 1 0 0 294 0 0 0 100 4 0 0 3 317 105 138 1 0 2 0 1448 0 0 0 100 5 0 0 0 12 2 8 0 0 0 0 0 0 0 0 100 6 0 0 14 10 1 6 0 1 1 0 266 0 0 0 100 7 0 0 10 218 105 18 0 1 0 0 560 0 0 0 100 April 2, 2026 at 04:31:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2118 107 30 0 1 2 0 11 0 0 0 100 1 0 0 0 110 51 106 0 0 0 0 2 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 3 0 0 0 19 2 14 0 1 0 0 294 0 0 0 100 4 0 0 3 316 105 138 1 0 0 0 1448 0 0 0 100 5 0 0 0 14 3 8 0 0 0 0 21 0 0 0 100 6 0 0 14 9 2 6 0 0 0 0 267 0 0 0 100 7 0 0 10 214 104 8 0 0 0 0 560 0 0 0 100 April 2, 2026 at 04:31:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 269 0 12 2205 108 4528 265 1232 228 12 32924 3 5 0 91 1 5391 0 0 815 47 4255 230 1047 193 10 31719 3 5 0 91 2 173 0 6 230 1 4533 242 1066 194 5 32778 3 5 0 92 3 117 0 0 841 2 3771 186 884 144 4 30911 3 4 0 93 4 146 0 185 609 105 4107 193 916 173 7 33572 3 4 0 93 5 236 0 0 812 5 3737 150 827 159 5 29942 3 4 0 93 6 2698 0 45 359 1 3845 192 841 179 11 31497 3 8 0 89 7 236 0 25 744 106 3718 163 770 181 9 30585 3 4 0 93 April 2, 2026 at 04:31:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 277 0 7 3002 109 34705 2205 10753 7849 16 238703 23 43 0 34 1 230 0 161 785 7 33466 2124 10262 7883 20 245103 23 42 0 35 2 194 0 0 817 12 31648 1870 9635 8216 25 241460 22 41 0 36 3 199 0 0 1291 371 34183 1969 9059 8120 20 247939 23 39 0 38 4 135 0 1418 1093 470 30080 1635 8617 7881 17 237862 21 41 0 38 5 123 0 0 878 25 31287 1771 8480 7932 17 243721 23 39 0 38 6 118 0 0 853 11 30010 1666 8216 7840 24 239742 22 39 0 40 7 106 0 10 904 107 28593 1549 7893 7327 17 232671 21 39 0 41 April 2, 2026 at 04:31:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 114 0 0 2782 113 36701 1404 12248 8616 19 242241 24 42 0 34 1 140 0 0 649 9 36200 1284 11776 9225 19 246276 23 41 0 36 2 88 0 0 618 6 35469 1216 11124 8707 21 244158 22 40 0 38 3 88 0 71 1018 395 33889 1034 10646 9228 34 241491 23 40 0 37 4 86 0 1416 991 492 33516 993 10210 8680 35 240578 22 40 0 37 5 79 0 0 673 14 33581 1040 10124 8914 25 242988 22 38 0 40 6 61 0 7 693 6 33463 1259 9958 8688 28 244962 24 38 0 38 7 60 0 14 820 111 34627 1371 9873 8450 28 248453 24 38 0 39 April 2, 2026 at 04:31:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 80 0 0 2738 114 34980 1551 11371 10227 26 237755 22 44 0 33 1 73 0 7 715 8 35530 1714 10871 10340 19 246910 23 42 0 35 2 64 0 0 713 14 33754 1519 10343 10131 29 240601 22 42 0 36 3 88 0 0 1082 453 32923 1257 9740 10301 18 233591 22 42 0 36 4 93 0 1416 1097 558 36129 1490 9376 9789 24 244359 23 40 0 37 5 69 0 7 626 6 32115 1164 9261 9760 25 232093 22 41 0 37 6 69 0 0 646 11 32879 1319 9147 9490 29 230391 22 41 0 36 7 55 0 13 759 108 31159 1115 8853 9513 26 228667 21 41 0 38 April 2, 2026 at 04:31:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 61 0 0 2860 112 37502 1677 11605 9316 24 245272 24 42 0 34 1 56 0 0 683 8 33822 1460 10716 9112 10 238618 22 42 0 36 2 54 0 0 654 7 33817 1406 10386 9184 28 245293 23 41 0 36 3 43 0 0 1240 502 34499 1677 9989 9777 28 246689 24 39 0 37 4 88 0 1485 1174 604 31877 1352 9484 9015 27 241801 22 40 0 38 5 73 0 7 671 22 31018 1183 9148 8798 26 239077 21 39 0 39 6 74 0 0 697 11 32625 1234 9215 8782 24 243728 23 38 0 39 7 73 0 14 843 116 30051 1104 8944 8543 28 235703 22 38 0 40 April 2, 2026 at 04:31:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 24 0 0 2397 104 21640 469 6956 8603 9 132407 13 28 0 59 1 27 0 0 380 7 20280 417 6413 8638 25 128594 13 29 0 58 2 28 0 0 387 30 20213 390 6253 8192 20 129344 13 28 0 60 3 22 0 0 811 429 19285 391 6031 8344 19 129824 13 28 0 60 4 48 0 843 837 528 19897 472 5784 8117 23 131842 13 26 0 61 5 24 0 7 513 10 22042 417 5712 8260 23 137109 13 24 0 62 6 19 0 0 523 4 19601 398 5673 8151 16 128690 12 26 0 61 7 18 0 3 667 107 19266 403 5497 8088 14 127890 12 26 0 62 April 2, 2026 at 04:31:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2118 104 527 1 58 1314 0 304 0 1 0 99 1 0 0 0 149 2 401 1 42 1016 0 30 0 1 0 99 2 0 0 0 230 13 451 0 52 1166 0 625 0 1 0 99 3 0 0 0 231 168 510 3 55 1216 0 1002 0 1 0 99 4 0 0 33 337 225 718 1 58 1065 0 271 0 1 0 99 5 0 0 7 168 11 524 1 61 1137 1 269 0 1 0 99 6 0 0 0 180 1 357 0 43 948 0 10 0 1 0 99 7 0 0 1 336 101 406 1 70 911 1 164 0 1 0 99 April 2, 2026 at 04:31:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 25 10 20 0 0 0 0 609 0 0 0 100 3 0 0 0 113 50 108 0 1 0 0 0 0 0 0 100 4 0 0 17 216 104 16 0 1 0 0 267 0 0 0 100 5 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 6 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 7 0 0 3 212 103 34 1 0 1 0 1148 0 0 0 100 April 2, 2026 at 04:31:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 116 0 0 0 0 296 0 0 0 100 1 0 0 0 12 3 6 0 0 0 0 3 0 0 0 100 2 0 0 0 25 10 20 0 0 0 0 609 0 0 0 100 3 0 0 0 111 50 106 0 1 0 0 0 0 0 0 100 4 0 0 17 211 103 4 0 0 0 0 266 0 0 0 100 5 0 0 7 12 2 8 1 1 0 0 259 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 3 211 103 34 0 0 0 0 1147 0 0 0 100 April 2, 2026 at 04:31:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11057 0 77 2200 101 444 2 77 643 15 4330 1 5 0 94 1 5634 0 98 378 2 136 1 34 1096 3 1688 1 2 0 97 2 1315 0 12 83 9 124 0 16 110 8 1129 1 1 0 99 3 7 0 1 149 50 163 0 17 20 8 62 0 0 0 100 4 1 0 30 232 103 22 0 4 645 0 279 0 1 0 99 5 45 0 23 200 20 321 4 29 357 8 1491 1 2 0 97 6 10210 0 3 194 1 287 3 49 1005 11 2148 2 6 0 93 7 12875 0 377 285 103 568 7 50 1616 7 28197 2 16 0 82 April 2, 2026 at 04:31:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 56 2119 104 248 0 14 92 6 372 0 1 0 99 1 3 0 0 79 3 102 0 14 58 1 19 0 0 0 100 2 22 0 0 69 8 96 0 9 63 0 718 0 0 0 100 3 5 0 0 194 74 208 0 12 47 4 28 0 0 0 100 4 2 0 17 291 127 141 0 13 45 3 294 0 0 0 100 5 143 0 7 79 10 111 0 10 29 2 321 0 1 0 99 6 357 0 1 63 1 92 1 10 57 1 118 0 0 0 100 7 16 0 3 268 104 135 1 12 37 1 829 0 0 0 100 April 2, 2026 at 04:31:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 42 2164 104 35 1 2 3 0 307 0 1 0 99 1 0 0 350 120 3 106 0 1 3 0 0 0 0 0 100 2 0 0 0 113 25 50 0 1 1 0 619 0 0 0 100 3 1 0 0 175 52 114 0 0 1 0 13 0 0 0 100 4 0 0 21 270 103 4 0 0 1 0 266 0 0 0 100 5 0 0 7 82 12 14 0 1 2 0 274 0 0 0 100 6 0 0 0 77 3 14 0 0 1 0 6 0 0 0 100 7 0 0 7 275 103 44 0 1 1 0 763 0 0 0 100 April 2, 2026 at 04:31:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 10 1 0 0 0 294 0 0 0 100 1 0 0 0 109 1 104 0 0 0 0 2 0 0 0 100 2 0 0 0 56 25 52 0 1 0 0 620 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 7 0 0 3 212 103 34 1 0 2 0 755 0 0 0 100 April 2, 2026 at 04:31:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 32 0 1 0 0 294 0 0 0 100 1 0 0 0 105 0 100 0 0 0 0 0 0 0 0 100 2 0 0 0 55 25 50 0 0 0 0 620 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 213 103 36 0 1 2 0 753 0 0 0 100 April 2, 2026 at 04:31:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2102 101 14 0 0 0 0 294 0 0 0 100 1 0 0 0 110 1 110 0 1 1 0 2 0 0 0 100 2 0 0 0 55 25 50 0 0 0 0 620 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 212 103 34 1 0 0 0 753 0 0 0 100 April 2, 2026 at 04:31:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 19 0 0 1 0 294 0 0 0 100 1 0 0 0 108 0 106 0 0 0 0 0 0 0 0 100 2 0 0 0 58 26 54 0 0 0 0 621 0 0 0 100 3 0 0 0 112 50 106 0 0 0 0 2 0 0 0 100 4 0 0 17 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 16 5 10 0 0 0 0 262 0 0 0 100 6 0 0 0 11 1 10 0 0 0 0 6 0 0 0 100 7 0 0 3 212 103 34 1 0 0 0 756 0 0 0 100 April 2, 2026 at 04:31:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 12 0 0 0 0 294 0 0 0 100 1 0 0 0 109 1 104 0 0 2 0 2 0 0 0 100 2 0 0 0 56 25 52 0 1 1 0 621 0 0 0 100 3 0 0 0 116 50 116 0 1 0 0 12 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 20 8 16 1 0 0 0 263 0 0 0 100 6 0 0 0 18 3 14 0 0 0 0 25 0 0 0 100 7 0 0 3 215 103 36 1 0 1 0 753 0 0 0 100 April 2, 2026 at 04:31:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 10 1 0 0 0 294 0 0 0 100 1 0 0 0 105 0 100 0 0 0 0 0 0 0 0 100 2 0 0 0 55 25 50 0 0 0 0 619 0 0 0 100 3 0 0 0 113 50 108 0 0 0 0 0 0 0 0 100 4 0 0 17 213 104 12 0 1 0 0 267 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 211 103 34 0 0 0 0 753 0 0 0 100 April 2, 2026 at 04:31:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 12 0 0 0 0 294 0 0 0 100 1 0 0 0 109 2 104 0 0 0 0 3 0 0 0 100 2 0 0 0 55 25 50 0 0 0 0 620 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 1 0 17 208 103 2 0 0 0 0 289 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 7 0 0 3 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:31:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 14 0 0 0 0 295 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 1 0 0 0 100 2 0 0 0 55 25 50 0 0 0 0 620 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 1 0 17 209 103 4 0 0 0 0 266 0 0 0 100 5 0 0 7 12 3 10 0 1 0 0 279 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 3 211 103 34 0 0 0 0 753 0 0 0 100 April 2, 2026 at 04:31:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 12 0 0 1 0 294 0 0 0 100 1 0 0 0 110 1 108 0 0 0 0 2 0 0 0 100 2 0 0 0 56 25 52 0 0 0 0 619 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 15 3 12 1 0 0 0 259 0 0 0 100 6 0 0 0 7 0 4 0 1 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:31:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 24 1 1 0 0 295 0 0 0 100 1 0 0 0 107 1 100 0 0 1 0 0 0 0 0 100 2 0 0 0 19 7 10 0 0 1 0 600 0 0 0 100 3 0 0 0 155 70 152 0 1 1 0 30 0 0 0 100 4 0 0 17 209 103 2 0 0 1 0 266 0 0 0 100 5 0 0 7 29 13 18 0 0 1 0 267 0 0 0 100 6 0 0 0 12 1 10 0 0 1 0 20 0 0 0 100 7 0 0 3 215 103 36 1 0 2 0 754 0 0 0 100 April 2, 2026 at 04:31:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 12 0 0 0 0 294 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 151 70 146 0 0 0 0 20 0 0 0 100 4 0 0 17 208 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 3 212 103 36 0 1 1 0 754 0 0 0 100 April 2, 2026 at 04:31:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 32 0 1 0 0 294 0 0 0 100 1 0 0 0 105 0 100 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 150 70 144 0 0 0 0 20 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 3 214 103 36 1 0 3 0 754 0 0 0 100 April 2, 2026 at 04:31:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 10 0 0 0 0 294 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 151 70 146 0 0 0 0 20 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 11 3 8 1 0 0 0 259 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 211 103 34 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:31:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 14 1 0 0 0 294 0 0 0 100 1 0 0 0 108 0 106 0 1 0 0 0 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 600 0 0 0 100 3 0 0 0 151 70 144 0 0 0 0 20 0 0 0 100 4 0 0 17 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 3 212 103 34 1 0 1 0 754 0 0 0 100 April 2, 2026 at 04:31:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 16 0 0 0 0 294 0 0 0 100 1 0 0 0 109 1 104 0 0 0 0 2 0 0 0 100 2 0 0 0 16 5 12 0 1 0 0 600 0 0 0 100 3 0 0 0 156 70 154 0 1 0 0 30 0 0 0 100 4 0 0 17 207 103 4 0 1 0 0 268 0 0 0 100 5 0 0 7 26 11 20 0 1 0 0 276 0 0 0 100 6 0 0 0 12 1 12 0 0 0 0 12 0 0 0 100 7 0 0 4 214 103 36 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:31:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 10 0 0 0 0 294 0 0 0 100 1 0 0 0 105 0 100 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 119 54 114 0 1 0 0 4 0 0 0 100 4 0 0 16 240 119 36 0 1 0 0 283 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 1 0 754 0 0 0 100 April 2, 2026 at 04:31:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 12 0 0 1 0 294 0 0 0 100 1 0 0 0 109 2 104 0 0 0 0 3 0 0 0 100 2 0 0 0 19 5 14 0 0 1 0 600 0 0 0 100 3 0 0 0 115 52 110 0 0 0 0 2 0 0 0 100 4 0 0 16 247 123 42 0 0 0 0 286 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 4 211 103 34 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:31:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 14 1 0 1 0 295 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 1 0 0 0 100 2 0 0 0 19 5 16 0 0 1 0 599 0 0 0 100 3 0 0 0 113 51 108 0 1 0 0 1 0 0 0 100 4 0 0 16 247 123 42 0 0 0 0 286 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 753 0 0 0 100 April 2, 2026 at 04:31:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 12 0 0 0 0 294 0 0 0 100 1 0 0 0 109 1 106 0 0 0 0 2 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 601 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 0 0 16 247 123 42 0 0 0 0 286 0 0 0 100 5 0 0 7 10 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 8 1 6 0 1 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:31:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 22 0 1 1 0 295 0 0 0 100 1 0 0 0 107 1 100 0 0 1 0 0 0 0 0 100 2 0 0 0 21 6 14 0 0 2 0 599 0 0 0 100 3 0 0 0 119 53 114 0 0 1 0 16 0 0 0 100 4 0 0 16 251 123 50 0 0 1 0 297 0 0 0 100 5 0 0 7 16 8 6 0 0 2 0 258 0 0 0 100 6 0 0 0 12 1 10 0 0 1 0 13 0 0 0 100 7 0 0 4 214 103 36 0 0 1 0 754 0 0 0 100 April 2, 2026 at 04:31:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 12 0 0 0 0 294 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 2 0 0 0 100 2 0 0 0 20 5 16 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 16 247 123 42 0 0 0 0 286 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:31:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 10 1 0 0 0 294 0 0 0 100 1 0 0 0 105 0 100 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 16 223 111 18 0 0 0 0 274 0 0 0 100 5 0 0 7 32 13 30 0 1 0 0 270 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 7 0 0 4 211 103 34 1 0 0 0 753 0 0 0 100 April 2, 2026 at 04:31:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 16 0 0 1 0 294 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 2 0 0 0 100 2 0 0 0 20 5 16 0 0 1 0 599 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 49 22 48 0 1 0 0 278 0 0 0 100 6 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:31:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 12 0 0 0 0 294 0 0 0 100 1 0 0 0 107 0 104 0 0 0 0 0 0 0 0 100 2 0 0 0 23 6 22 0 0 0 0 601 0 0 0 100 3 0 0 0 111 50 106 0 1 0 0 0 0 0 0 100 4 0 0 16 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 49 22 46 0 0 0 0 278 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 16 0 0 0 0 294 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 116 50 116 0 0 0 0 22 0 0 0 100 4 0 0 16 211 103 10 0 0 0 0 278 0 0 0 100 5 0 0 7 61 31 46 1 0 0 0 278 0 0 0 100 6 0 0 0 16 2 14 0 0 0 0 10 0 0 0 100 7 0 0 4 215 103 38 0 0 1 0 754 0 0 0 100 April 2, 2026 at 04:32:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 102 20 1 2 0 0 294 0 0 0 100 1 0 0 0 106 0 102 0 1 0 0 0 0 0 0 100 2 0 0 0 23 6 20 0 1 1 0 599 0 0 0 100 3 0 0 0 112 50 108 0 1 0 0 0 0 0 0 100 4 0 0 16 211 104 6 0 0 0 0 267 0 0 0 100 5 0 0 7 51 23 48 0 0 0 0 278 0 0 0 100 6 0 0 0 10 2 6 0 0 0 0 1 0 0 0 100 7 0 0 4 213 103 36 1 1 0 0 754 0 0 0 100 April 2, 2026 at 04:32:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 14 0 0 1 0 294 0 0 0 100 1 0 0 0 109 2 104 0 0 0 0 3 0 0 0 100 2 0 0 0 20 5 16 0 0 0 0 600 0 0 0 100 3 0 0 0 113 51 106 0 0 0 0 24 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 50 22 48 0 0 0 0 278 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 4 211 103 34 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 12 0 0 0 0 295 0 0 0 100 1 0 0 0 107 1 102 0 0 0 0 1 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 52 23 48 1 0 0 0 299 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 753 0 0 0 100 April 2, 2026 at 04:32:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 14 0 0 0 0 294 0 0 0 100 1 0 0 0 109 1 106 0 0 0 0 2 0 0 0 100 2 0 0 0 23 6 20 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 0 0 16 211 104 8 0 0 0 0 275 0 0 0 100 5 0 0 7 51 22 52 1 1 0 0 296 0 0 0 100 6 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 7 0 0 4 213 103 34 2 0 0 0 756 0 0 0 100 April 2, 2026 at 04:32:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 24 1 1 1 0 295 0 0 0 100 1 0 0 0 108 1 100 0 0 1 0 0 0 0 0 100 2 0 0 0 22 6 14 0 0 1 0 600 0 0 0 100 3 0 0 0 119 51 116 0 0 1 0 23 0 0 0 100 4 0 0 21 212 103 10 0 0 1 0 278 0 0 0 100 5 0 0 7 60 29 46 0 0 2 0 278 0 0 0 100 6 0 0 0 20 3 16 0 0 1 0 10 0 0 0 100 7 0 0 7 215 103 36 0 0 2 0 753 0 0 0 100 April 2, 2026 at 04:32:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 54 0 2 0 0 294 0 0 0 100 1 0 0 0 67 1 60 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 50 22 46 0 0 0 0 278 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 110 0 1 0 0 294 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 22 5 16 0 1 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 25 10 20 0 0 0 0 265 0 0 0 100 6 0 0 0 30 12 26 0 1 0 0 13 0 0 0 100 7 0 0 4 211 103 34 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 114 0 1 1 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 19 5 14 0 0 3 0 601 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 10 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 753 0 0 0 100 April 2, 2026 at 04:32:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 112 1 0 0 0 294 0 0 0 100 1 0 0 0 7 0 4 0 0 0 0 0 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 106 0 1 0 0 0 0 0 0 100 4 0 0 15 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 50 22 46 0 0 0 0 21 0 0 0 100 7 0 0 5 211 103 34 0 0 0 0 755 0 0 0 100 April 2, 2026 at 04:32:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 122 0 0 1 0 294 0 0 0 100 1 0 0 0 12 1 7 0 0 0 0 2 0 0 0 100 2 0 0 0 19 5 14 0 0 2 0 600 0 0 0 100 3 0 0 0 114 50 114 0 1 0 0 12 0 0 0 100 4 0 0 15 211 103 10 0 0 0 0 278 0 0 0 100 5 0 0 7 20 13 6 0 0 1 0 258 0 0 0 100 6 0 0 0 57 22 56 0 0 0 0 40 0 0 0 100 7 0 0 5 217 103 40 1 0 1 0 753 0 0 0 100 April 2, 2026 at 04:32:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 112 0 0 1 0 294 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 18 5 12 0 0 1 0 601 0 0 0 100 3 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 4 0 0 16 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 10 2 10 0 2 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 4 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:32:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2102 101 110 0 0 0 0 293 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 3 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 106 0 1 0 0 0 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 11 4 6 1 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 4 211 103 34 0 0 0 0 753 0 0 0 100 April 2, 2026 at 04:32:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 116 1 0 0 0 295 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 13 2 10 0 0 1 0 258 0 0 0 100 6 0 0 0 50 22 46 0 0 0 0 21 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 9 1 6 0 0 0 0 2 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 601 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 11 2 8 0 0 0 0 258 0 0 0 100 6 0 0 0 46 20 42 0 1 0 0 20 0 0 0 100 7 0 0 5 213 103 36 1 1 1 0 755 0 0 0 100 April 2, 2026 at 04:32:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 102 120 0 1 0 0 295 0 0 0 100 1 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 2 0 0 0 17 6 10 0 0 1 0 600 0 0 0 100 3 0 0 0 115 51 112 0 0 1 0 12 0 0 0 100 4 0 0 15 211 103 10 0 0 1 0 278 0 0 0 100 5 0 0 7 19 10 6 0 0 2 0 258 0 0 0 100 6 0 0 0 59 23 56 0 0 1 0 39 0 0 0 100 7 0 0 5 215 103 38 0 0 1 0 754 0 0 0 100 April 2, 2026 at 04:32:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 122 0 1 2 0 295 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 214 103 36 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 116 1 0 1 0 294 0 0 0 100 1 0 0 0 7 0 4 0 1 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 50 22 46 0 0 0 0 21 0 0 0 100 7 0 0 5 211 103 34 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 753 0 0 0 100 April 2, 2026 at 04:32:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 9 0 6 0 0 0 0 0 0 0 0 100 2 0 0 0 21 6 20 0 1 0 0 601 0 0 0 100 3 0 0 0 111 50 106 0 1 0 0 0 0 0 0 100 4 0 0 15 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:32:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 119 0 0 2 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 18 5 12 0 0 0 0 599 0 0 0 100 3 0 0 0 120 50 124 0 1 1 0 16 0 0 0 100 4 1 0 15 210 103 10 0 0 0 0 277 0 0 0 100 5 0 0 7 18 9 6 1 0 0 0 258 0 0 0 100 6 0 0 0 55 22 52 0 0 0 0 36 0 0 0 100 7 0 0 5 212 102 36 0 0 0 0 753 0 0 0 100 April 2, 2026 at 04:32:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 103 114 1 0 0 0 298 0 0 0 100 1 0 0 0 8 1 164 0 1 0 0 331 0 0 0 100 2 0 0 0 17 6 12 0 0 0 0 602 0 0 0 100 3 0 0 0 115 52 108 0 0 0 0 1 0 0 0 100 4 3 0 16 210 104 8 0 2 0 0 274 0 0 0 100 5 0 0 7 10 2 8 0 1 0 0 261 0 0 0 100 6 0 0 0 48 21 44 0 0 0 0 21 0 0 0 100 7 0 0 4 213 103 38 1 1 0 0 756 0 0 0 100 April 2, 2026 at 04:32:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 3 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 113 50 108 0 0 0 0 0 0 0 0 100 4 0 0 15 208 103 4 0 1 0 0 266 0 0 0 100 5 0 0 7 10 2 10 0 1 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 211 103 34 0 0 0 0 755 0 0 0 100 April 2, 2026 at 04:32:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 102 114 0 0 0 0 295 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 18 3 18 0 0 0 0 279 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 114 0 0 0 0 294 0 0 0 100 1 0 0 0 9 1 6 0 0 0 0 2 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 46 20 42 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 757 0 0 0 100 April 2, 2026 at 04:32:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2109 102 124 1 1 0 0 295 0 0 0 100 1 0 0 0 8 1 0 0 0 1 0 0 0 0 0 100 2 0 0 0 18 6 10 0 0 1 0 601 0 0 0 100 3 0 0 0 120 53 114 0 0 1 0 16 0 0 0 100 4 0 0 21 212 103 12 0 0 2 0 277 0 0 0 100 5 0 0 7 21 10 8 0 0 1 0 258 0 0 0 100 6 0 0 0 60 22 62 0 1 1 0 33 0 0 0 100 7 0 0 7 215 103 36 0 0 1 0 754 0 0 0 100 April 2, 2026 at 04:32:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 47 20 42 0 0 1 0 20 0 0 0 100 7 0 0 5 214 103 38 1 1 1 0 755 0 0 0 100 April 2, 2026 at 04:32:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 110 0 0 0 0 294 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 16 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 4 211 103 34 0 0 0 0 755 0 0 0 100 April 2, 2026 at 04:32:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 122 0 1 2 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 48 21 44 0 0 0 0 20 0 0 0 100 7 0 0 5 214 103 36 1 0 1 0 754 0 0 0 100 April 2, 2026 at 04:32:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 112 1 0 0 0 294 0 0 0 100 1 0 0 0 8 0 6 0 1 0 0 0 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 599 0 0 0 100 3 0 0 0 111 50 106 0 1 0 0 0 0 0 0 100 4 0 0 15 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 47 21 42 0 0 0 0 21 0 0 0 100 7 0 0 5 211 103 34 0 0 1 0 756 0 0 0 100 April 2, 2026 at 04:32:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 116 0 1 0 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 114 50 112 0 0 0 0 12 0 0 0 100 4 0 0 15 211 103 10 0 0 0 0 278 0 0 0 100 5 0 0 7 17 8 6 0 0 0 0 258 0 0 0 100 6 0 0 0 58 22 58 0 0 0 0 41 0 0 0 100 7 0 0 5 215 103 36 1 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 114 0 0 0 0 294 0 0 0 100 1 0 0 0 9 0 4 0 0 1 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 109 50 100 0 0 0 0 0 0 0 0 100 4 0 0 15 209 104 4 0 0 0 0 267 0 0 0 100 5 0 0 7 9 2 8 0 1 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 756 0 0 0 100 April 2, 2026 at 04:32:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 116 0 0 0 0 294 0 0 0 100 1 0 0 0 11 2 6 0 0 0 0 3 0 0 0 100 2 0 0 0 16 5 12 0 1 0 0 599 0 0 0 100 3 0 0 0 108 50 104 0 1 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 1 0 0 0 258 0 0 0 100 6 0 0 0 48 21 44 0 0 0 0 20 0 0 0 100 7 0 0 5 211 103 34 0 0 0 0 754 0 0 0 100 April 2, 2026 at 04:32:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 114 1 0 0 0 295 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 4 0 0 15 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 9 2 6 0 0 0 0 258 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 5 212 103 34 1 0 0 0 755 0 0 0 100 April 2, 2026 at 04:32:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 112 0 0 0 0 294 0 0 0 100 1 0 0 0 9 1 6 0 0 0 0 2 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 601 0 0 0 100 3 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 4 0 0 15 212 104 10 0 1 1 0 275 0 0 0 100 5 0 0 7 11 2 10 0 0 0 0 276 0 0 0 100 6 0 0 0 47 21 42 0 0 0 0 21 0 0 0 100 7 0 0 5 211 103 34 0 0 0 0 756 0 0 0 100 April 2, 2026 at 04:32:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 102 124 0 1 0 0 295 0 0 0 100 1 0 0 0 7 1 0 0 0 1 0 0 0 0 0 100 2 0 0 0 17 6 10 0 0 1 0 599 0 0 0 100 3 0 0 0 112 51 108 0 0 1 0 12 0 0 0 100 4 0 0 17 215 103 14 0 0 1 0 278 0 0 0 100 5 0 0 7 18 10 38 0 2 2 0 904 0 0 0 100 6 0 0 0 59 23 56 0 0 1 0 38 0 0 0 100 7 0 0 3 214 103 5 2 0 1 0 108 0 0 0 100 April 2, 2026 at 04:32:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 101 114 0 0 0 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 3 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 13 3 38 2 0 0 0 1013 0 0 0 100 6 0 0 0 48 21 44 0 0 0 0 20 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 April 2, 2026 at 04:32:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 112 1 0 0 0 294 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 4 0 0 17 209 103 4 0 0 1 0 266 0 0 0 100 5 0 0 7 15 3 46 1 1 4 0 1013 0 0 0 100 6 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 April 2, 2026 at 04:32:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 116 0 0 2 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 4 0 0 17 207 103 2 0 0 0 0 266 0 0 0 100 5 0 0 7 16 3 42 1 0 3 0 1013 0 0 0 100 6 0 0 0 47 21 42 0 0 0 0 21 0 0 0 100 7 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 April 2, 2026 at 04:32:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2110 101 461 0 1 16 0 294 0 0 0 100 1 0 0 1 10 0 8 0 0 0 0 1 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 601 0 0 0 100 3 1940 0 2 148 50 172 2 0 229 0 358 0 1 0 99 4 0 0 20 216 104 14 0 0 0 0 281 0 0 0 100 5 0 0 7 955 930 57 1 2 575 0 1014 0 1 0 99 6 0 0 0 40 17 36 0 0 0 0 23 0 0 0 100 7 0 0 3 354 102 290 0 1 198 0 8 0 0 0 100 April 2, 2026 at 04:32:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 101 82 0 2 0 0 294 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 599 0 0 0 100 3 0 0 0 121 52 118 0 0 0 0 27 0 0 0 100 4 0 0 17 212 103 12 0 0 0 0 278 0 0 0 100 5 0 0 7 68 23 74 1 1 1 0 1012 0 0 0 100 6 0 0 0 11 2 4 0 1 0 0 0 0 0 0 100 7 1 0 3 230 105 28 0 0 0 0 45 0 0 0 100 April 2, 2026 at 04:32:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2107 101 123 1 0 2 0 294 0 0 0 100 1 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 600 0 0 0 100 3 0 0 0 109 50 106 0 0 0 0 2 0 0 0 100 4 0 0 17 211 104 8 0 0 0 0 273 0 0 0 100 5 0 0 7 52 40 43 1 0 3 0 1012 0 0 0 100 6 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 7 1 0 3 232 104 38 0 1 1 0 49 0 0 0 100