April 1, 2026 at 06:53:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1125 0 86 2378 141 9104 96 392 2237 6 11404 2 10 0 88 1 1321 0 144 552 14 11240 24 685 2234 9 22688 3 6 0 91 2 1416 0 286 378 18 5487 16 385 2130 13 9731 2 4 0 94 3 1372 0 237 658 329 4705 19 330 2080 13 11671 6 7 0 87 4 1065 0 74 713 327 7036 16 430 2238 12 17992 2 4 0 94 5 1191 0 100 7200 6838 4826 35 439 3650 10 9230 1 6 0 92 6 1258 0 64 358 12 6012 24 470 2033 15 11093 13 4 0 84 7 1692 0 123 434 22 5805 31 260 2205 13 4710 3 4 0 93 April 1, 2026 at 06:53:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2426 0 223 2193 113 683 1 128 159 81 2601 0 9 0 90 1 1613 0 45 287 33 506 0 88 384 49 1764 0 1 0 99 2 4558 0 32 482 8 453 1 84 290 72 3772 3 2 0 94 3 3328 0 31 415 17 380 1 73 318 62 3718 3 2 0 95 4 8444 0 76 326 89 354 7 50 700 26 4364 13 6 0 81 5 4986 0 718 404 69 179 8 9 411 30 3306 13 25 0 62 6 10922 0 32 372 4 452 4 83 1002 56 7984 13 5 0 83 7 4639 0 40 182 2 463 1 94 247 54 3751 5 2 0 93 April 1, 2026 at 06:53:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 26 0 0 2154 104 736 5 134 2876 1 1046 0 10 0 90 1 0 0 21 215 13 1938 1 240 1645 2 825 0 2 0 98 2 0 0 5 280 15 1443 6 233 1825 1 1 0 3 0 97 3 0 0 0 477 438 686 5 137 2987 2 300 0 9 0 91 4 0 0 3 677 537 799 4 120 3030 0 0 0 10 0 90 5 0 0 3 238 106 734 5 121 3060 2 0 0 10 0 90 6 0 0 0 246 19 606 6 116 2693 2 302 0 10 0 90 7 0 0 0 212 9 636 7 119 2958 0 0 0 10 0 90 April 1, 2026 at 06:53:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 2110 104 150 0 0 0 0 1054 0 1 0 99 1 0 0 21 14 3 14 0 3 0 0 823 0 0 0 100 2 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 300 0 0 0 100 4 0 0 3 213 103 8 0 0 0 0 19 0 0 0 100 5 0 0 3 210 102 4 0 1 0 0 0 0 0 0 100 6 0 0 0 11 3 6 0 0 0 0 294 0 0 0 100 7 0 0 0 107 51 102 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:54:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2108 101 127 1 2 0 0 248 0 0 0 100 1 0 0 21 114 54 114 0 1 0 0 833 0 0 0 100 2 0 0 1 17 2 16 0 1 1 0 16 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 5 0 0 3 216 108 4 0 1 0 0 0 0 0 0 100 6 0 0 0 11 3 6 0 0 0 0 294 0 0 0 100 7 0 0 0 19 2 12 0 0 0 0 1 0 0 0 100 April 1, 2026 at 06:54:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 0 2109 102 149 0 0 1 0 816 0 0 0 100 1 0 0 21 110 53 108 0 0 0 0 824 0 0 0 100 2 0 0 0 17 2 12 0 0 0 0 1 0 0 0 100 3 0 0 2 9 2 4 0 0 0 0 304 0 0 0 100 4 0 0 3 209 102 2 0 0 0 0 0 0 0 0 100 5 0 0 3 215 103 10 0 0 0 0 5 0 0 0 100 6 0 0 0 11 3 6 0 0 0 0 294 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:54:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 53762 0 3 3434 109 15916 3497 3595 29893 384 105404 19 39 0 41 1 11394 0 22 1611 33 13482 2942 3165 36748 335 91809 17 33 0 50 2 14666 0 7 1919 57 18852 4315 4149 24953 356 110801 17 34 0 49 3 14043 0 3 1749 216 16821 3718 3831 28055 366 102840 18 32 0 50 4 11909 0 3 2071 306 14142 3289 3351 34137 389 92398 17 34 0 49 5 15870 0 740 1796 108 14239 3147 3281 36509 394 94621 17 36 0 47 6 16847 0 1 1882 12 17200 3994 3733 26029 378 109807 18 33 0 49 7 13532 0 1 1399 8 15551 3488 3472 34438 389 95998 17 35 0 49 April 1, 2026 at 06:54:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2084 0 51 4067 114 30021 3268 4605 27447 178 152551 36 62 0 1 1 1232 0 79 2169 17 32558 3837 5123 27358 129 179036 35 64 0 1 2 3130 0 2828 2145 87 36738 4700 5431 24746 180 184260 36 63 0 2 3 1977 0 190 2553 582 33923 3240 5189 23541 225 172599 36 63 0 1 4 1609 0 36 2889 676 31667 3454 4869 29651 222 161292 37 62 0 1 5 2427 0 1482 2260 121 30846 3842 4644 27010 192 159968 40 59 0 1 6 1243 0 16 1976 15 28219 3056 4430 29775 191 153190 36 62 0 1 7 2172 0 55 2149 15 30779 3573 4876 22853 173 171005 35 63 0 2 April 1, 2026 at 06:54:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 3567 136 33622 3088 5314 22462 147 162491 38 61 0 1 1 7 0 0 1612 30 34117 3244 5433 22524 76 166260 40 58 0 1 2 33 0 21 2036 96 42566 4152 6329 18078 137 190133 38 60 0 2 3 0 0 0 2083 690 36888 3041 5858 21920 135 173444 35 63 0 2 4 33 0 3 2506 775 35830 3485 5639 23379 142 167402 37 62 0 2 5 33 0 1416 1647 122 40106 3922 5813 22360 92 187655 35 63 0 2 6 0 0 0 1539 25 36104 3020 5369 22753 103 175236 39 59 0 2 7 0 0 0 1562 18 33088 3208 5145 25100 95 163856 37 61 0 2 April 1, 2026 at 06:54:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 25 0 0 3851 123 36610 3948 5241 24344 185 162759 36 63 0 1 1 46 0 0 1613 24 34761 3867 5341 22476 133 167888 38 61 0 1 2 103 0 21 2234 106 40109 4792 5996 20265 129 179903 35 64 0 1 3 64 0 0 2484 747 36328 3820 5585 16600 146 174305 35 64 0 1 4 17 0 3 2696 841 34602 3814 5410 18441 140 166578 38 61 0 1 5 16 0 1417 1957 137 36651 3993 5587 17507 101 175600 36 63 0 1 6 9 0 0 1689 19 34483 3667 5123 22465 113 162471 40 59 0 1 7 4 0 0 1709 24 35957 3531 5200 23327 164 170217 37 63 0 1 April 1, 2026 at 06:54:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 0 5352 137 42048 7221 6757 18433 28 182636 36 64 0 1 1 1 0 13 3449 37 43012 7797 7375 19352 52 185880 37 62 0 1 2 6 0 0 3810 163 47265 8287 7354 17818 56 189620 34 65 0 1 3 2 0 1961 3432 622 40274 7099 6561 18877 39 178264 35 64 0 1 4 3 0 6 3944 715 37845 7391 6319 20269 40 174305 37 62 0 1 5 3 0 1423 3294 127 38883 7390 6271 20839 53 170869 38 62 0 1 6 0 0 2 3358 29 42569 7709 6807 19209 28 185624 36 63 0 1 7 1 0 0 3161 29 40632 6833 6550 18070 36 177225 35 64 0 1 April 1, 2026 at 06:54:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 5145 137 40494 7860 6918 18581 65 176168 33 66 0 1 1 0 0 0 3015 31 38447 7298 6097 21706 41 164877 35 65 0 1 2 33 0 0 3622 126 43435 8542 6620 20345 31 178206 36 64 0 1 3 0 0 0 3992 741 42647 8102 6799 18254 65 182132 35 65 0 1 4 34 0 10 3870 863 41280 7418 6675 24984 76 168517 35 64 0 1 5 16 0 1445 2943 128 39790 7547 6260 21023 52 173243 35 64 0 1 6 33 0 0 3015 26 38972 7616 6272 20987 50 166951 35 64 0 1 7 33 0 0 3207 28 40912 8034 6481 22551 40 174762 36 63 0 1 April 1, 2026 at 06:54:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 4176 128 29285 5078 5085 17244 63 122815 25 49 0 26 1 5 0 0 1969 32 27907 4631 4853 17893 54 116111 26 48 0 27 2 6 0 0 2590 108 31786 6218 5331 14774 39 124080 27 49 0 24 3 4 0 0 2667 592 26369 4847 4819 17900 57 111226 24 49 0 27 4 1 0 7 2880 710 29162 5138 5082 14784 74 120877 26 48 0 27 5 0 0 1078 2208 129 30884 5094 5161 16233 35 126226 24 50 0 25 6 3 0 0 2308 24 31595 5579 5240 17517 44 125191 27 45 0 28 7 4 0 0 2333 25 30509 5525 5317 16940 59 128014 29 44 0 26 April 1, 2026 at 06:54:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2125 107 217 0 18 329 1 10 0 0 0 100 1 0 0 0 103 8 257 0 20 288 35 300 0 0 0 100 2 0 0 0 142 30 248 0 17 299 18 829 0 0 0 100 3 0 0 0 126 46 156 0 13 293 10 300 0 0 0 100 4 0 0 3 258 147 191 0 17 315 14 1 0 0 0 100 5 3 0 24 302 105 201 0 21 302 23 833 0 0 0 100 6 0 0 5 138 17 233 5 21 190 19 520 0 1 0 99 7 0 0 0 74 0 148 0 18 212 18 0 0 0 0 100 April 1, 2026 at 06:54:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2122 110 134 0 0 0 0 21 0 0 0 99 1 0 0 0 22 2 24 0 1 1 0 325 0 0 0 100 2 0 0 0 112 51 140 1 0 0 0 1360 0 0 0 100 3 0 0 0 10 2 6 0 0 1 0 300 0 0 0 100 4 0 0 3 212 103 5 0 1 0 0 0 0 0 0 100 5 0 0 24 219 110 8 0 0 0 0 820 0 0 0 100 6 0 0 0 16 1 14 0 0 0 0 0 0 3 0 97 7 0 0 0 12 1 4 0 0 1 0 0 0 0 0 100 April 1, 2026 at 06:54:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2122 108 118 0 0 0 0 13 0 0 0 100 1 0 0 0 17 2 10 0 1 0 0 300 0 0 0 100 2 0 0 0 113 53 138 1 1 0 0 1350 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 4 0 0 3 215 103 6 0 1 0 0 0 0 0 0 100 5 0 0 24 212 104 8 0 0 0 0 818 0 0 0 100 6 0 0 0 8 1 4 0 1 0 0 0 0 0 0 100 7 0 0 0 10 1 6 0 0 0 0 3 0 0 0 100 April 1, 2026 at 06:54:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1185 0 15 2158 108 1456 14 64 213 11 4571 4 2 0 93 1 170 0 8 97 3 1426 10 77 74 10 3355 2 7 0 91 2 86 0 14 179 4 1172 6 43 85 9 5513 3 2 0 95 3 82 0 0 684 48 1474 4 42 57 4 3403 1 1 0 98 4 41080 0 3 387 105 1319 10 40 50 2 3394 4 6 0 90 5 1498 0 184 350 104 1006 12 31 340 9 5166 6 3 0 91 6 40 0 0 286 4 1264 4 41 44 6 2944 2 1 0 97 7 35 0 0 257 2 896 16 19 117 8 4580 7 2 0 91 April 1, 2026 at 06:54:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 0 2539 107 12983 319 1288 4709 25 32833 28 18 0 54 1 28 0 0 489 9 13126 365 1193 5349 21 33228 25 17 0 58 2 12 0 7 419 8 11848 275 998 4641 25 35147 33 17 0 50 3 20 0 0 762 290 11889 366 897 5019 23 31782 26 16 0 58 4 30 0 3 893 385 12031 371 841 4926 10 30768 24 15 0 61 5 15 0 1414 389 109 11147 208 806 5010 24 31913 28 17 0 55 6 48 0 29 379 8 10421 223 712 4487 19 31748 32 17 0 51 7 47 0 74 381 9 10920 432 722 4757 16 30514 28 15 0 56 April 1, 2026 at 06:54:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 14 2559 111 13567 459 1519 5992 23 32954 24 18 0 57 1 8 0 0 461 11 13811 464 1356 6483 15 32760 21 17 0 62 2 17 0 0 449 13 11730 341 1078 5814 21 33426 32 20 0 49 3 8 0 7 877 422 12079 363 1062 5688 12 31482 28 17 0 54 4 9 0 3 1017 527 10814 284 838 5638 19 31388 33 19 0 48 5 9 0 1418 346 109 10326 199 841 5639 21 29833 29 20 0 51 6 2 0 7 420 10 10725 275 850 5891 34 29881 27 19 0 54 7 8 0 0 435 11 11118 348 817 5524 12 29639 27 17 0 56 April 1, 2026 at 06:54:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 17 0 14 2559 113 14870 682 1557 5839 7 37389 28 19 0 53 1 12 0 0 411 8 13612 383 1427 6256 8 33102 24 19 0 56 2 13 0 7 417 10 12636 336 1192 6137 8 32868 27 20 0 53 3 6 0 3 818 377 11843 337 1045 5386 12 33239 30 18 0 52 4 9 0 3 1058 484 11594 439 996 5273 15 31820 28 18 0 54 5 3 0 1416 397 114 10465 242 883 5678 13 28917 26 20 0 54 6 8 0 7 379 7 10567 231 847 5635 15 28850 27 18 0 55 7 11 0 0 446 12 10705 371 855 5948 21 29294 28 18 0 54 April 1, 2026 at 06:54:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 21 2579 108 12997 527 1387 6297 10 33860 28 19 0 53 1 17 0 0 454 11 13308 559 1282 6498 18 30944 23 18 0 59 2 6 0 0 397 8 11984 333 1135 6587 20 30865 25 20 0 56 3 6 0 0 767 332 11026 481 972 5924 21 31879 32 19 0 49 4 6 0 3 921 431 10590 294 872 5907 20 29030 27 19 0 54 5 11 0 1420 411 112 10565 252 796 5539 20 29348 29 19 0 52 6 12 0 0 418 9 10188 265 770 6182 18 29290 31 19 0 50 7 9 0 0 432 24 11113 362 787 6227 18 28460 24 16 0 60 April 1, 2026 at 06:54:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 21 2592 112 13820 846 1398 5919 8 33723 25 17 0 58 1 13 0 0 484 14 13310 594 1298 6572 7 32723 28 18 0 53 2 4 0 0 430 12 11773 331 1080 5868 11 30219 28 20 0 52 3 10 0 0 734 305 11397 316 997 5849 3 28131 27 18 0 56 4 8 0 3 911 418 10720 248 890 6269 6 27348 27 18 0 55 5 7 0 1416 425 111 10124 249 801 5601 7 28020 29 20 0 51 6 14 0 0 429 12 10285 286 813 6070 10 27491 28 18 0 54 7 11 0 0 388 6 10204 239 750 6334 5 28435 28 18 0 54 April 1, 2026 at 06:54:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7 0 21 2558 112 13759 386 1443 6275 21 35087 22 18 0 60 1 10 0 51 437 6 13364 358 1288 6063 5 33016 24 17 0 60 2 16 0 130 498 14 13577 489 1187 6418 22 32078 22 15 0 63 3 7 0 0 754 328 11671 286 959 6195 18 31800 27 18 0 55 4 7 0 3 931 428 10811 286 866 5680 19 30010 30 17 0 53 5 16 0 1416 522 110 12198 982 865 5347 16 34484 34 16 0 49 6 7 0 0 417 15 10211 215 811 5432 25 29475 31 18 0 51 7 5 0 0 446 9 10365 248 773 6090 18 30612 32 18 0 51 April 1, 2026 at 06:54:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 14 2529 111 13021 438 1424 6166 8 33201 25 20 0 56 1 21 0 7 442 13 13201 436 1312 6332 7 34185 25 19 0 56 2 5 0 3 409 11 12600 346 1207 6406 16 31487 24 19 0 57 3 6 0 0 757 326 11455 327 1035 5753 23 30740 26 19 0 55 4 9 0 3 961 425 11004 385 973 6079 10 30666 30 18 0 52 5 8 0 1420 463 112 11241 536 955 5321 19 30862 28 18 0 54 6 16 0 0 427 8 10633 483 826 5731 19 30596 32 17 0 51 7 13 0 0 429 9 9826 359 833 5721 13 28141 30 18 0 52 April 1, 2026 at 06:54:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 14 2570 111 14402 583 1409 6588 13 34066 22 18 0 59 1 10 0 7 389 9 13025 335 1239 6362 15 32181 21 18 0 60 2 8 0 0 443 14 11856 389 1073 6298 17 31184 27 19 0 54 3 10 0 0 776 309 11492 582 961 6006 24 33218 33 18 0 49 4 3 0 3 936 422 11181 262 885 6153 16 29551 28 20 0 52 5 5 0 1417 410 118 10253 227 797 5865 18 28511 28 20 0 52 6 7 0 0 400 11 10189 203 758 5671 15 27614 28 19 0 53 7 3 0 0 387 10 9616 218 763 5532 19 27406 30 19 0 51 April 1, 2026 at 06:54:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 14 2325 107 6160 218 641 3970 6 16510 14 11 0 75 1 6 0 0 297 10 6030 147 582 4214 7 16693 13 11 0 76 2 6 0 31 253 4 5805 147 493 3936 3 15569 14 11 0 76 3 6 0 0 588 241 5891 248 487 3871 8 17095 18 10 0 72 4 9 0 3 650 318 6374 332 484 4061 9 16306 13 9 0 79 5 4 0 716 400 107 5340 101 417 4139 7 14242 13 11 0 76 6 6 0 0 280 5 5838 92 447 3949 4 14228 11 10 0 80 7 4 0 0 289 4 5477 119 421 4136 3 12594 11 10 0 79 April 1, 2026 at 06:54:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2109 104 12 0 1 0 0 863 0 0 0 100 1 0 0 0 24 6 44 1 0 0 0 1352 0 0 0 100 2 0 0 0 11 1 6 0 1 0 0 4 0 0 0 100 3 0 0 0 112 51 114 0 1 0 0 300 0 0 0 100 4 0 0 10 224 109 18 0 2 0 0 269 0 0 0 100 5 0 0 3 308 101 102 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 12 0 1 0 0 12 0 0 0 100 7 0 0 0 13 1 8 0 1 0 0 1 0 0 0 100 April 1, 2026 at 06:54:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 103 8 1 0 0 0 860 0 0 0 100 1 0 0 0 18 5 40 1 0 0 0 1350 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 108 51 106 0 1 0 0 300 0 0 0 100 4 0 0 10 219 104 12 0 1 0 0 261 0 0 0 100 5 0 0 3 308 101 102 0 0 0 0 0 0 0 0 100 6 0 0 0 20 7 14 0 0 0 0 9 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:54:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2111 106 18 0 0 0 0 860 0 0 0 100 1 0 0 0 17 4 40 1 2 0 0 1348 0 0 0 100 2 0 0 0 7 0 4 0 2 0 0 0 0 0 0 100 3 0 0 0 113 51 110 0 3 0 0 300 0 0 0 100 4 8 0 10 219 103 14 0 2 0 0 302 0 0 0 100 5 0 0 3 313 102 108 0 1 0 0 1 0 0 0 100 6 0 0 0 20 7 16 0 1 0 0 6 0 0 0 100 7 0 0 0 8 1 4 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:54:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1087 0 49 2171 107 386 3 39 335 16 1920 1 2 0 97 1 9560 0 35 169 6 316 0 47 5842 4 3845 2 7 0 92 2 12407 0 194 114 2 186 11 61 5802 8 20792 2 23 0 75 3 10023 0 64 264 34 355 1 53 577 13 5473 1 3 0 95 4 5672 0 82 534 129 415 4 54 424 17 4933 1 5 0 94 5 1032 0 28 377 129 209 8 42 199 9 395 0 4 0 95 6 1909 0 29 88 5 360 3 19 208 7 2343 0 1 0 99 7 1289 0 31 65 1 84 0 13 4818 4 403 0 2 0 98 April 1, 2026 at 06:54:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2283 0 47 2272 105 1270 1 192 2190 56 5417 2 4 0 94 1 1217 0 291 518 5 845 1 143 1948 38 4413 1 4 0 95 2 893 0 10 442 1 680 2 132 1804 47 2352 0 3 0 96 3 753 0 19 562 124 752 1 139 2084 24 1191 0 3 0 97 4 2959 0 310 860 232 782 1 108 2313 28 5174 1 6 0 93 5 12634 0 237 703 142 973 0 153 2181 44 3317 1 4 0 94 6 1977 0 61 404 4 948 1 174 1865 57 1348 0 4 0 96 7 3638 0 391 548 19 925 0 137 2076 59 4048 1 4 0 95 April 1, 2026 at 06:54:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 98 2157 104 108 1 4 7 0 859 0 1 0 99 1 0 0 0 90 2 46 0 2 0 0 1076 0 0 0 100 2 0 0 0 171 52 106 0 1 0 0 1 0 0 0 100 3 0 0 343 33 3 16 0 0 6 0 300 0 0 0 99 4 0 0 17 281 107 14 0 0 0 0 263 0 0 0 100 5 0 0 3 278 105 8 0 1 0 0 0 0 0 0 100 6 0 0 0 76 1 10 0 1 0 0 0 0 0 0 100 7 0 0 0 75 3 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:54:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 35 2159 103 122 0 3 2 0 861 0 1 0 99 1 0 0 0 71 3 38 1 1 1 0 1050 0 0 0 99 2 0 0 0 163 53 104 0 0 1 0 21 0 0 0 100 3 0 0 336 16 2 8 0 0 4 0 300 0 0 0 100 4 0 0 14 264 103 4 0 0 1 0 258 0 0 0 100 5 0 0 7 264 103 6 0 0 1 0 0 0 0 0 100 6 0 0 0 63 2 4 0 0 3 0 0 0 0 0 100 7 0 0 0 63 2 4 0 1 1 0 0 0 0 0 100 April 1, 2026 at 06:54:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 104 120 0 0 0 0 868 0 0 0 99 1 0 0 0 12 2 34 1 0 0 0 1052 0 0 0 100 2 0 0 0 109 51 104 0 1 0 0 0 0 0 0 100 3 0 0 0 10 1 6 0 1 0 0 300 0 0 0 100 4 0 0 11 213 104 8 0 0 0 0 278 0 0 0 100 5 0 0 2 214 103 8 0 0 0 0 1 0 0 0 100 6 0 0 0 7 1 4 0 1 0 0 0 0 0 0 100 7 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:54:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 103 126 1 0 0 0 872 0 0 0 100 1 0 0 0 20 2 52 1 1 0 0 1063 0 0 0 100 2 0 0 0 13 3 10 0 0 0 0 13 0 0 0 100 3 0 0 0 108 51 104 0 0 0 0 300 0 0 0 100 4 0 0 10 209 103 2 0 0 0 0 258 0 0 0 100 5 0 0 3 216 108 4 0 0 1 0 0 0 0 0 100 6 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 7 0 0 0 12 2 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:54:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 62 0 14 2126 103 361 3 43 19854 11 1195 0 7 0 93 1 0 0 9 43 2 181 17 9 21677 0 1053 0 14 0 86 2 1309 0 14 116 1 318 1 51 17265 12 349 0 6 0 94 3 1081 0 2 237 85 516 4 87 7937 10 416 0 7 0 93 4 502 0 12 450 208 335 4 32 18106 8 1212 0 7 0 93 5 1191 0 14 303 102 298 2 39 19272 9 748 0 9 0 90 6 1715 0 11 230 5 540 2 74 7952 13 850 0 4 0 96 7 93 0 6 124 1 388 1 73 9919 11 519 0 4 0 96 April 1, 2026 at 06:54:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 7830 0 5380 14520 120 20099 2983 6557 17625 139 75078 22 70 0 8 1 526 0 42908 6583 27 15811 2199 5098 17424 31 58235 17 78 0 5 2 11215 0 28419 9120 28 18708 2588 5793 17458 176 65984 19 73 0 8 3 12890 0 10 14056 808 22104 3382 6501 17515 104 75720 24 69 0 7 4 9692 0 9 14354 915 21620 3092 6739 17561 187 78199 23 68 0 9 5 9193 0 1190 13508 131 21242 3130 6837 18497 159 75710 22 69 0 10 6 8764 0 2467 12929 36 19126 2959 6131 19445 130 70240 24 67 0 10 7 8184 0 0 13421 26 20769 3092 6453 16716 131 77263 24 67 0 9 April 1, 2026 at 06:54:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 290 0 14 3590 137 18785 1965 5551 20098 110 72400 24 70 0 6 1 129 0 103 1518 28 19867 1868 5912 20733 113 75679 22 71 0 7 2 73 0 0 1592 39 20489 1922 5917 22519 90 76592 23 70 0 7 3 122 0 2 2219 870 18365 1669 5500 21048 110 69088 22 70 0 7 4 224 0 7 2564 988 18951 1990 5775 18863 88 71969 23 70 0 7 5 32 0 1416 1518 139 19144 1903 5820 21892 107 74992 22 70 0 8 6 64 0 0 1523 35 20476 1938 6125 20970 83 79510 22 71 0 7 7 2152 0 0 1557 31 17171 1902 5506 20186 73 69815 23 70 0 7 April 1, 2026 at 06:54:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 64 0 14 3548 127 18804 1821 5742 19785 155 73341 23 71 0 6 1 73 0 0 1511 40 19085 1790 5800 18931 142 73416 23 71 0 7 2 0 0 7 1641 51 20936 1989 6233 22101 114 77032 22 70 0 8 3 0 0 75 2316 809 19862 1973 6072 20633 104 75273 23 69 0 8 4 32 0 3 2496 922 19561 1925 6089 21418 131 75688 22 71 0 7 5 1 0 1417 1556 136 19339 2043 5779 20387 135 72661 24 68 0 8 6 88 0 0 1502 28 18585 1877 5801 20127 121 73306 22 70 0 8 7 2 0 0 1633 24 19597 2124 5852 21110 122 75191 24 68 0 8 April 1, 2026 at 06:54:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 3611 132 19575 2242 5766 20634 76 72364 24 70 0 6 1 0 0 0 1476 33 18959 1856 6065 22716 138 73858 22 72 0 6 2 0 0 0 1462 34 18689 1805 5856 20029 144 71143 22 72 0 6 3 0 0 0 2411 927 20792 2009 6503 21370 107 77917 22 70 0 8 4 0 0 17 2585 1036 20221 2030 6187 20165 80 77011 21 71 0 8 5 0 0 1418 1602 141 20242 2124 6134 19611 96 74471 24 69 0 7 6 0 0 7 1584 43 19784 2007 6020 22101 93 77438 23 70 0 8 7 0 0 0 1644 38 19573 2015 5812 20580 36 73551 25 67 0 8 April 1, 2026 at 06:54:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2597 109 6468 598 1826 9521 48 22351 8 25 0 67 1 2 0 0 502 11 6630 614 1897 9242 51 24551 7 25 0 67 2 4 0 0 597 51 7006 634 1939 9812 68 25261 7 26 0 67 3 10 0 0 830 359 6193 582 1852 7980 29 22550 8 25 0 67 4 15 0 19 1106 466 6773 733 1832 9215 51 24372 8 24 0 68 5 11 0 518 620 116 6560 537 1991 9340 40 24038 7 25 0 68 6 11 0 7 568 13 6507 647 1914 8462 27 25103 9 24 0 67 7 2 0 0 544 14 7568 617 1961 9631 63 25923 7 25 0 68 April 1, 2026 at 06:54:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2106 100 14 0 2 0 0 0 0 0 0 100 1 0 0 0 16 4 38 1 0 1 0 1438 0 0 0 100 2 0 0 0 112 52 108 0 1 0 0 300 0 0 0 100 3 0 0 0 22 7 14 0 0 0 0 9 0 0 0 100 4 0 0 17 315 106 108 0 0 0 0 269 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 6 0 0 7 13 3 8 0 0 0 0 559 0 0 0 100 7 0 0 0 9 0 4 0 1 0 0 2 0 0 0 100 April 1, 2026 at 06:54:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 10 0 2 0 0 0 0 0 0 100 1 0 0 0 19 5 38 2 0 2 0 1438 0 0 0 100 2 0 0 0 116 53 109 0 2 1 0 300 0 0 0 100 3 0 0 0 21 7 14 0 0 1 0 10 0 0 0 100 4 0 0 17 308 103 102 0 0 1 0 266 0 0 0 100 5 0 0 3 213 103 6 0 1 1 0 2 0 0 0 100 6 0 0 7 15 5 10 0 1 1 0 559 0 0 0 100 7 0 0 0 8 1 2 0 1 1 0 0 0 0 0 100 April 1, 2026 at 06:54:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 0 2104 100 26 0 1 1 0 0 0 0 0 100 1 0 0 0 17 5 40 0 0 1 0 1439 0 0 0 100 2 0 0 0 46 14 40 0 0 0 0 300 0 0 0 100 3 0 0 0 95 44 92 0 2 0 0 9 0 0 0 100 4 0 0 17 308 103 102 0 0 0 0 266 0 0 0 100 5 0 0 3 210 103 4 0 0 0 0 1 0 0 0 100 6 0 0 7 12 4 8 0 0 0 0 560 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 2 0 0 0 100 April 1, 2026 at 06:54:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1645 0 29 2675 105 20993 1799 5887 4538 34 148156 15 26 0 60 1 480 0 1 1198 7 18845 1283 5431 4527 36 142166 13 25 0 62 2 408 0 0 1563 7 18071 1236 4986 4781 32 143720 13 24 0 63 3 278 0 5 1354 233 17744 1094 4700 4502 20 140014 14 24 0 62 4 210 0 3 1128 304 18422 1062 4597 4679 30 142174 13 24 0 63 5 5435 0 843 897 116 18492 1128 4334 4319 27 141306 13 24 0 63 6 1634 0 21 1260 10 16379 954 4167 4195 25 135902 13 24 0 63 7 227 0 8 920 2 16647 952 4104 4345 27 137250 12 26 0 62 April 1, 2026 at 06:54:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 147 0 21 2868 108 35381 1728 11808 9396 28 243250 24 42 0 34 1 110 0 0 729 9 34307 1506 10923 9198 24 243467 23 41 0 35 2 122 0 0 793 13 34949 1554 10699 8707 27 252746 24 39 0 37 3 117 0 2 1228 461 35093 1378 10079 9183 23 247428 23 39 0 38 4 103 0 177 1342 555 33191 1450 9678 8168 30 240575 22 39 0 39 5 115 0 1417 705 112 31556 1275 9433 9007 23 239056 23 40 0 37 6 88 0 0 700 10 32843 1354 9383 8957 22 242249 23 38 0 40 7 127 0 10 714 8 31712 1219 9110 8618 25 237408 21 38 0 41 April 1, 2026 at 06:54:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 86 0 85 2797 111 39140 1559 12020 9534 13 245949 25 43 0 32 1 65 0 0 703 4 34290 1284 11159 9481 23 237375 23 43 0 34 2 103 0 14 869 17 37021 1625 10798 9623 16 244633 23 41 0 35 3 82 0 7 1423 654 35166 1427 10253 9762 18 244905 22 41 0 37 4 66 0 3 1477 757 31805 1028 9738 9238 17 233388 22 42 0 36 5 46 0 1418 705 111 34172 1152 9858 9403 17 239102 22 41 0 38 6 44 0 0 627 18 31526 1060 9665 8884 23 235033 22 40 0 38 7 50 0 7 669 5 32469 1074 9486 9365 22 232599 22 40 0 38 April 1, 2026 at 06:54:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 94 0 12 2943 107 36941 1887 11933 9744 21 239709 24 42 0 34 1 45 0 0 792 8 35061 1696 11164 9929 16 237353 23 43 0 35 2 72 0 8 843 14 37571 1703 10832 9959 20 247878 24 40 0 36 3 76 0 0 1687 880 36735 1646 10403 9845 21 244355 22 39 0 38 4 54 0 3 1779 987 32709 1415 9819 9834 20 234485 22 41 0 38 5 55 0 1416 757 108 31914 1316 9523 9881 30 234097 22 41 0 37 6 52 0 6 698 8 32068 1302 9463 9072 26 236022 22 39 0 38 7 59 0 10 822 13 32910 1420 9275 9688 31 236222 22 39 0 39 April 1, 2026 at 06:54:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 96 0 21 2740 111 35915 1260 11916 9345 20 228490 23 44 0 33 1 67 0 0 694 9 36351 1332 11501 10310 23 233421 24 43 0 34 2 61 0 0 797 14 35561 1444 11137 9901 16 237544 23 42 0 35 3 40 0 0 1367 725 32970 1098 10554 9425 20 229070 22 42 0 35 4 55 0 3 1574 822 32338 1045 10114 9704 21 228520 22 42 0 37 5 62 0 1418 666 113 34906 1164 9927 9496 16 235254 22 41 0 37 6 65 0 0 739 9 35472 1314 9812 9306 16 235361 23 40 0 37 7 27 0 7 657 9 32379 1251 9406 9343 21 226901 21 40 0 39 April 1, 2026 at 06:54:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 21 2290 103 6135 304 1892 5186 4 33850 3 10 0 86 1 7 0 0 221 25 6692 254 1784 5034 3 34122 3 9 0 88 2 6 0 0 506 6 5772 240 1554 5061 3 34553 3 8 0 89 3 16 0 0 601 408 5628 250 1521 4994 1 33481 3 9 0 88 4 2 0 3 810 518 5390 206 1470 5053 3 32864 3 9 0 88 5 6 0 227 599 110 5281 225 1368 4747 4 33077 3 9 0 88 6 2 0 0 461 8 5321 206 1421 4341 4 32743 3 10 0 87 7 8 0 0 407 3 5059 202 1320 4818 2 30939 3 9 0 88 April 1, 2026 at 06:54:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 23 2105 102 114 0 2 0 0 525 0 0 0 100 1 0 0 0 10 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 14 4 8 0 0 0 0 593 0 0 0 100 3 0 0 0 12 0 4 0 0 0 0 0 0 0 0 100 4 0 0 3 317 154 106 0 1 0 0 0 0 0 0 100 5 0 0 3 218 107 12 0 0 0 0 9 0 0 0 100 6 0 0 0 14 4 40 0 0 0 0 1150 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:54:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2105 102 116 0 0 0 0 525 0 0 0 100 1 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 2 0 0 0 18 5 12 0 1 0 0 596 0 0 0 100 3 0 0 0 8 0 0 0 0 0 0 0 0 0 0 100 4 0 0 3 319 156 118 0 1 1 0 4 0 0 0 100 5 0 0 3 220 108 14 0 0 0 0 10 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 1151 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:54:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2108 102 116 0 1 0 0 526 0 0 0 100 1 0 0 0 9 1 0 0 0 1 0 0 0 0 0 100 2 0 0 0 23 7 14 1 0 1 0 615 0 0 0 100 3 0 0 0 10 1 2 0 0 1 0 0 0 0 0 100 4 0 0 7 313 153 104 0 0 1 0 0 0 0 0 100 5 0 0 7 223 108 18 0 1 1 0 7 0 0 0 100 6 0 0 0 16 4 38 1 0 1 0 1150 0 0 0 100 7 0 0 0 10 2 2 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:54:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11166 0 89 2190 102 455 3 51 1001 8 4994 1 5 0 94 1 5668 0 102 428 4 231 1 53 319 4 2461 1 2 0 97 2 1178 0 16 65 7 81 1 15 628 7 1000 1 1 0 98 3 524 0 22 67 1 111 1 24 52 9 364 0 0 0 99 4 11 0 16 344 153 164 0 19 19 6 99 0 0 0 100 5 31 0 39 395 123 263 2 15 218 4 778 1 2 0 98 6 9883 0 12 190 3 297 2 44 1622 9 3146 2 6 0 92 7 12724 0 333 92 1 469 8 58 850 16 26735 2 16 0 82 April 1, 2026 at 06:54:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 17 2119 101 172 0 7 3 3 299 0 0 0 100 1 14 0 63 29 2 36 0 3 3 4 300 0 1 0 99 2 4 0 0 48 7 50 0 3 4 1 649 0 0 0 100 3 27 0 0 56 14 62 0 4 13 4 134 0 0 0 100 4 0 0 3 325 153 114 0 1 1 1 6 0 0 0 100 5 136 0 4 252 117 47 0 4 12 1 79 0 0 0 100 6 361 0 0 31 3 65 1 4 7 3 929 0 0 0 99 7 16 0 0 34 1 30 0 1 1 5 315 0 0 0 100 April 1, 2026 at 06:54:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2158 101 116 1 0 0 0 266 0 1 0 99 1 0 0 56 62 1 8 0 0 2 0 258 0 1 0 99 2 0 0 343 25 5 12 0 0 2 0 596 0 0 0 100 3 0 0 0 101 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 368 154 104 0 0 0 0 0 0 0 0 100 5 0 0 3 268 101 8 0 0 0 0 0 0 0 0 100 6 0 0 0 69 3 38 1 0 0 0 762 0 0 0 100 7 0 0 0 63 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:54:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 15 2104 101 118 0 0 0 0 266 0 0 0 100 1 0 0 7 10 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 14 4 8 1 0 0 0 594 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:54:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 596 0 0 0 100 3 0 0 0 47 20 42 0 1 0 0 20 0 0 0 100 4 0 0 3 313 154 106 0 0 0 0 0 0 0 0 100 5 0 0 3 208 101 2 0 0 0 0 0 0 0 0 100 6 0 0 0 17 3 44 1 1 1 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:54:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 257 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 594 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 309 152 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 17 4 42 1 1 0 0 754 0 0 0 100 7 0 0 0 8 1 4 0 1 1 0 300 0 0 0 100 April 1, 2026 at 06:54:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 130 1 0 0 0 281 0 0 0 99 1 0 0 7 11 2 8 0 0 0 0 258 0 0 0 100 2 0 0 0 28 8 32 0 0 0 0 620 0 0 0 100 3 0 0 0 46 20 42 0 0 0 0 21 0 0 0 100 4 0 0 3 313 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 220 112 2 0 0 0 0 0 0 0 0 100 6 0 0 0 15 3 44 0 0 0 0 753 0 0 0 100 7 0 0 0 18 2 12 0 0 0 0 311 0 0 0 100 April 1, 2026 at 06:54:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 136 0 1 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 1 0 0 258 0 0 0 100 2 0 0 0 16 4 8 1 0 0 0 595 0 0 0 100 3 0 0 0 46 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 312 153 106 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 754 0 0 0 100 7 0 0 0 9 1 4 0 1 2 0 300 0 0 0 100 April 1, 2026 at 06:54:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 14 2106 101 116 0 1 1 0 288 0 0 0 100 1 0 0 7 9 1 4 0 1 0 0 258 0 0 0 100 2 0 0 0 16 5 12 0 1 0 0 596 0 0 0 100 3 0 0 0 46 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 316 156 108 0 0 0 0 3 0 0 0 100 5 0 0 3 207 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 2 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:54:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 14 2102 101 116 0 0 0 0 266 0 0 0 100 1 0 0 7 9 2 2 0 0 1 0 258 0 0 0 100 2 0 0 0 15 5 8 0 0 1 0 593 0 0 0 100 3 0 0 0 47 21 40 0 0 1 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 1 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 1 0 0 0 0 0 100 6 0 0 0 14 4 38 0 0 1 0 753 0 0 0 100 7 0 0 0 9 2 2 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:54:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 102 120 1 0 0 0 275 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 21 6 16 0 0 0 0 598 0 0 0 100 3 0 0 0 50 20 50 0 1 0 0 20 0 0 0 100 4 0 0 3 314 154 108 0 0 0 0 18 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 752 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 101 122 0 0 1 0 276 0 0 0 100 1 0 0 7 11 2 8 0 0 0 0 258 0 0 0 100 2 0 0 0 20 6 16 1 0 0 0 606 0 0 0 100 3 0 0 0 47 20 42 0 0 0 0 20 0 0 0 100 4 0 0 3 314 153 110 0 1 0 0 0 0 0 0 100 5 0 0 3 218 108 8 0 1 0 0 11 0 0 0 100 6 0 0 0 14 3 42 0 0 0 0 754 0 0 0 100 7 0 0 0 12 1 8 0 0 0 0 304 0 0 0 100 April 1, 2026 at 06:55:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 116 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 17 5 10 0 0 0 0 596 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 312 153 106 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 752 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 594 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 312 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 210 101 10 0 1 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 755 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 114 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 596 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 212 103 4 0 0 0 0 1 0 0 0 100 6 0 0 0 16 3 46 0 1 1 0 752 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 112 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 14 4 8 1 0 0 0 594 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 312 154 104 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 138 0 1 0 0 277 0 0 0 99 1 0 0 7 12 2 6 0 0 0 0 258 0 0 0 100 2 1 0 0 20 5 22 0 0 0 0 611 0 0 0 100 3 0 0 0 46 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 221 109 10 0 0 1 0 15 0 0 0 100 6 0 0 0 17 3 44 1 1 2 0 754 0 0 0 100 7 0 0 0 11 1 6 0 1 0 0 300 0 0 0 100 April 1, 2026 at 06:55:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 118 0 0 1 0 266 0 0 0 100 1 0 0 7 9 1 4 0 1 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 593 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 14 4 40 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 114 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 21 8 16 0 0 0 0 600 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 318 157 110 0 0 0 0 3 0 0 0 100 5 0 0 3 208 102 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 1 0 752 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2103 101 114 0 1 0 0 266 0 0 0 100 1 0 0 7 12 2 4 0 0 2 0 258 0 0 0 100 2 0 0 0 22 6 16 1 1 1 0 614 0 0 0 100 3 0 0 0 48 21 40 0 0 1 0 20 0 0 0 100 4 0 0 7 311 153 102 0 0 1 0 0 0 0 0 100 5 0 0 7 207 101 0 0 0 1 0 0 0 0 0 100 6 0 0 0 16 4 38 1 0 1 0 754 0 0 0 100 7 0 0 0 10 2 2 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 118 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 19 5 14 0 0 0 0 596 0 0 0 100 3 0 0 0 46 20 42 0 1 0 0 20 0 0 0 100 4 0 0 3 313 154 106 0 0 0 0 0 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 101 126 0 0 0 0 279 0 0 0 100 1 0 0 7 11 2 6 0 0 0 0 258 0 0 0 100 2 0 0 0 23 6 26 0 0 0 0 614 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 308 152 102 0 0 0 0 0 0 0 0 100 5 0 0 3 217 108 6 0 0 0 0 9 0 0 0 100 6 0 0 0 15 3 42 1 0 0 0 753 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 17 5 10 0 0 0 0 597 0 0 0 100 3 0 0 0 49 20 44 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 1 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2100 101 114 0 0 0 0 265 0 0 0 99 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 16 5 10 1 0 0 0 595 0 0 0 100 3 0 0 0 47 20 42 0 0 0 0 20 0 0 0 100 4 0 0 3 313 154 106 0 1 1 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 595 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 0 0 2 0 266 0 0 0 100 1 0 0 7 8 1 4 0 1 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 595 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 315 153 108 0 0 1 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 14 4 40 0 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 101 124 1 0 1 0 277 0 0 0 100 1 0 0 7 11 2 8 0 0 0 0 258 0 0 0 100 2 0 0 0 24 7 26 0 0 0 0 616 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 314 154 106 0 0 0 0 0 0 0 0 100 5 0 0 3 220 110 6 0 1 0 0 8 0 0 0 100 6 0 0 0 16 3 44 1 1 0 0 756 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 4 8 1 0 0 0 593 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 118 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 596 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 319 157 114 0 0 0 0 27 0 0 0 100 5 0 0 3 210 101 4 0 0 2 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 114 0 1 0 0 266 0 0 0 100 1 0 0 7 9 2 2 0 0 1 0 258 0 0 0 100 2 0 0 0 15 5 8 0 0 1 0 595 0 0 0 100 3 0 0 0 47 21 40 0 0 1 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 1 0 0 0 0 0 100 5 0 0 3 208 101 2 0 0 1 0 0 0 0 0 100 6 0 0 0 16 4 40 1 1 2 0 753 0 0 0 100 7 0 0 0 9 2 2 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 17 5 12 0 0 0 0 596 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 126 0 0 0 0 277 0 0 0 99 1 0 0 7 11 2 6 0 0 0 0 258 0 0 0 100 2 0 0 0 25 7 26 1 0 0 0 611 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 312 154 104 0 0 0 0 0 0 0 0 100 5 0 0 3 212 107 0 0 0 1 0 0 0 0 0 100 6 0 0 0 19 3 48 1 0 1 0 764 0 0 0 100 7 0 0 0 11 1 6 0 1 0 0 300 0 0 0 100 April 1, 2026 at 06:55:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 596 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 3 38 1 0 0 0 753 0 0 0 100 7 0 0 0 13 1 10 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 594 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 313 154 106 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 1 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 134 1 1 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 15 5 10 0 0 0 0 596 0 0 0 100 3 0 0 0 45 20 40 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 753 0 0 0 100 7 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 103 122 0 0 2 0 266 0 0 0 100 1 0 0 7 11 2 6 0 1 1 0 258 0 0 0 100 2 0 0 0 17 5 12 1 1 0 0 594 0 0 0 100 3 0 0 0 48 21 44 0 1 0 0 20 0 0 0 100 4 0 0 3 309 152 105 0 2 1 0 0 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 0 0 0 0 100 6 0 0 0 16 5 42 0 0 0 0 753 0 0 0 100 7 0 0 0 8 1 4 0 1 0 0 300 0 0 0 100 April 1, 2026 at 06:55:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 101 132 0 0 0 0 278 0 0 0 100 1 0 0 7 11 2 6 0 0 0 0 258 0 0 0 100 2 0 0 0 19 6 16 0 0 0 0 610 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 313 154 106 0 0 0 0 0 0 0 0 100 5 0 0 3 214 109 0 0 0 1 0 0 0 0 0 100 6 0 0 0 20 3 54 1 0 0 0 767 0 0 0 100 7 0 0 0 11 1 6 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 3 8 0 0 0 0 593 0 0 0 100 3 0 0 0 52 21 52 0 1 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 754 0 0 0 100 7 0 0 0 9 1 5 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 116 1 0 0 0 266 0 0 0 99 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 596 0 0 0 100 3 0 0 0 53 21 52 0 0 0 0 20 0 0 0 100 4 0 0 3 317 156 110 0 0 0 0 3 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2105 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 10 2 2 0 0 1 0 258 0 0 0 100 2 0 0 0 17 5 8 1 0 1 0 616 0 0 0 100 3 0 0 0 50 22 42 0 0 1 0 20 0 0 0 100 4 0 0 7 313 154 104 0 0 1 0 0 0 0 0 100 5 0 0 7 207 101 0 0 0 1 0 0 0 0 0 100 6 0 0 0 18 5 40 1 0 1 0 754 0 0 0 100 7 0 0 0 10 2 2 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 102 122 0 0 0 0 275 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 4 10 0 0 0 0 595 0 0 0 100 3 0 0 0 49 21 44 0 0 1 0 20 0 0 0 100 4 0 0 3 316 153 114 0 1 0 0 18 0 0 0 100 5 0 0 3 210 104 2 0 0 0 0 1 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 130 0 0 0 0 278 0 0 0 100 1 0 0 7 11 2 6 0 0 0 0 257 0 0 0 100 2 0 0 0 16 3 18 0 0 0 0 607 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 317 154 110 0 0 0 0 0 0 0 0 100 5 0 0 3 210 105 0 0 0 0 0 0 0 0 0 100 6 0 0 0 20 5 50 0 0 1 0 766 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 112 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 596 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 4 308 152 102 0 0 0 0 0 0 0 0 100 5 0 0 2 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 3 38 1 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 14 4 8 1 0 0 0 595 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 312 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 207 101 2 0 1 1 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 752 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 118 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 596 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 106 0 0 0 0 0 0 0 0 100 5 0 0 3 210 101 6 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 11 3 6 0 0 0 0 594 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2107 101 126 1 0 0 0 278 0 0 0 100 1 0 0 7 11 2 8 0 0 0 0 258 0 0 0 100 2 0 0 0 22 6 24 0 0 0 0 614 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 214 107 2 0 0 0 0 0 0 0 0 100 6 0 0 0 21 4 212 1 1 0 0 1092 0 0 0 100 7 0 0 0 11 1 6 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 102 116 0 0 0 0 268 0 0 0 100 1 0 0 7 9 1 4 0 0 0 0 259 0 0 0 100 2 0 0 0 14 3 6 1 0 0 0 595 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 315 155 108 0 0 0 0 1 0 0 0 100 5 3 0 3 211 103 8 0 2 0 0 11 0 0 0 100 6 0 0 0 18 4 44 1 1 1 0 758 0 0 0 100 7 0 0 0 8 1 4 0 1 0 0 300 0 0 0 100 April 1, 2026 at 06:55:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 13 4 8 0 0 0 0 596 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 316 156 108 0 0 0 0 3 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 755 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 134 0 1 0 0 266 0 0 0 100 1 0 0 7 9 2 2 0 0 1 0 258 0 0 0 100 2 0 0 0 13 4 6 0 0 1 0 594 0 0 0 100 3 0 0 0 49 22 42 0 0 1 0 20 0 0 0 100 4 0 0 3 311 153 106 0 0 1 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 1 0 0 0 0 0 100 6 0 0 0 14 4 38 0 0 1 0 753 0 0 0 100 7 0 0 0 11 2 4 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 116 1 0 0 0 266 0 0 0 100 1 0 0 7 9 1 6 0 1 0 0 258 0 0 0 100 2 0 0 0 15 4 10 0 0 0 0 597 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 101 126 0 0 0 0 278 0 0 0 100 1 0 0 7 11 2 6 0 0 0 0 258 0 0 0 100 2 0 0 0 23 6 24 1 0 0 0 612 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 309 152 104 0 0 0 0 0 0 0 0 100 5 0 0 3 210 105 2 0 1 0 0 0 0 0 0 100 6 0 0 0 19 3 46 3 0 0 0 763 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 112 0 1 0 0 266 0 0 0 100 1 0 0 7 12 1 8 0 1 1 0 258 0 0 0 100 2 0 0 0 16 4 10 0 1 0 0 596 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 312 154 104 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 112 0 1 0 0 266 0 0 0 100 1 0 0 7 10 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 16 3 16 0 1 0 0 595 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 313 153 104 0 1 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 114 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 15 4 10 0 0 0 0 595 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 311 153 104 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 110 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 18 4 12 1 0 1 0 595 0 0 0 100 3 0 0 0 51 21 54 0 2 0 0 20 0 0 0 100 4 0 0 4 312 154 104 0 0 0 0 0 0 0 0 100 5 0 0 2 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 14 4 40 0 0 0 0 755 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2108 101 122 0 0 0 0 278 0 0 0 100 1 0 0 7 11 2 8 0 0 0 0 258 0 0 0 100 2 0 0 0 21 6 18 0 0 0 0 609 0 0 0 100 3 0 0 0 54 21 52 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 211 106 0 0 0 0 0 0 0 0 0 100 6 0 0 0 20 3 54 1 0 0 0 767 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 114 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 3 8 0 0 0 0 595 0 0 0 100 3 0 0 0 46 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 313 154 106 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 757 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 110 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 4 10 0 0 0 0 595 0 0 0 100 3 0 0 0 49 21 44 0 0 0 0 20 0 0 0 100 4 0 0 3 319 155 118 0 1 0 0 3 0 0 0 100 5 0 0 3 206 101 2 0 1 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2101 101 114 0 1 0 0 265 0 0 0 99 1 0 0 7 10 2 2 0 0 1 0 258 0 0 0 100 2 0 0 0 19 5 10 1 0 1 0 614 0 0 0 100 3 0 0 0 50 21 40 1 0 1 0 19 0 0 0 100 4 0 0 7 313 153 104 0 0 1 0 0 0 0 0 100 5 0 0 7 210 101 8 0 1 2 0 0 0 0 0 100 6 0 0 0 18 5 40 1 0 1 0 755 0 0 0 100 7 0 0 0 10 2 2 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 112 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 17 4 12 0 0 0 0 597 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 208 102 2 0 0 0 0 1 0 0 0 100 6 0 0 0 13 3 38 1 0 0 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 124 0 0 0 0 278 0 0 0 100 1 0 0 7 11 2 6 0 0 0 0 258 0 0 0 100 2 0 0 0 18 3 20 0 0 0 0 608 0 0 0 100 3 0 0 0 48 21 44 0 1 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 217 108 4 0 0 1 0 0 0 0 0 100 6 0 0 0 20 5 50 0 0 0 0 767 0 0 0 100 7 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 114 1 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 15 4 12 0 1 0 0 595 0 0 0 100 3 0 0 0 52 21 48 0 0 0 0 20 0 0 0 100 4 0 0 4 309 152 102 0 0 0 0 0 0 0 0 100 5 0 0 2 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 15 3 38 1 0 1 0 753 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2106 101 112 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 14 3 8 1 0 0 0 594 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 310 153 102 0 0 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 12 3 38 0 0 0 0 755 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 110 0 0 0 0 266 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 17 5 12 0 0 0 0 597 0 0 0 100 3 0 0 0 49 21 44 0 0 0 0 20 0 0 0 100 4 0 0 3 313 153 110 0 1 0 0 0 0 0 0 100 5 0 0 3 206 101 0 0 0 0 0 0 0 0 0 100 6 0 0 0 13 3 38 1 0 1 0 754 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2102 101 114 0 0 2 0 266 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 13 3 8 0 0 0 0 594 0 0 0 100 3 0 0 0 47 21 42 0 0 0 0 20 0 0 0 100 4 0 0 3 312 152 110 0 0 2 0 0 0 0 0 100 5 0 0 3 206 101 2 0 1 0 0 0 0 0 0 100 6 0 0 0 15 4 40 1 0 0 0 755 0 0 0 100 7 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2109 101 421 1 0 9 0 289 0 0 0 100 1 0 0 7 13 2 8 0 1 0 0 258 0 0 0 100 2 1935 0 1 68 6 94 2 0 235 0 862 0 1 0 99 3 0 0 0 28 11 22 0 0 0 0 16 0 0 0 100 4 0 0 7 311 153 102 0 0 0 0 0 0 0 0 100 5 0 0 7 1034 926 2 0 0 628 0 0 0 0 0 100 6 7 0 4 26 3 58 0 0 0 0 879 0 0 0 100 7 0 0 0 135 1 252 0 0 221 0 300 0 0 0 100 April 1, 2026 at 06:55:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2104 101 116 0 0 0 0 268 0 0 0 100 1 0 0 7 8 1 2 0 0 0 0 258 0 0 0 100 2 0 0 0 21 5 14 1 0 0 0 605 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 3 310 152 104 0 0 0 0 0 0 0 0 100 5 0 0 3 225 115 4 0 1 0 0 0 0 0 0 100 6 0 0 0 22 4 50 1 0 0 0 777 0 0 0 100 7 0 0 0 9 1 6 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2105 101 126 0 0 1 0 283 0 0 0 100 1 0 0 7 8 1 4 0 0 0 0 258 0 0 0 100 2 0 0 0 17 4 14 0 0 0 0 599 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 3 316 156 108 0 0 0 0 3 0 0 0 100 5 0 0 3 252 140 4 0 0 3 0 0 0 0 0 100 6 1 0 0 29 6 60 1 1 0 0 801 0 0 0 100 7 0 0 0 13 1 12 0 0 0 0 300 0 0 0 100