April 1, 2026 at 06:55:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1038 0 103 2348 138 7697 84 391 2144 7 7146 2 7 0 91 1 1285 0 269 280 14 8104 27 365 1922 7 15345 15 10 0 75 2 1452 0 60 291 16 6640 19 379 1799 7 11463 3 4 0 92 3 1421 0 42 711 311 8627 19 526 1917 8 15966 7 5 0 88 4 857 0 205 543 315 9653 16 467 1922 7 20435 7 6 0 88 5 625 0 166 8421 8209 4366 33 312 3670 5 9751 2 7 0 90 6 906 0 124 290 13 6636 15 369 1860 5 13435 6 5 0 89 7 1213 0 117 260 21 6277 24 310 2293 8 4499 4 6 0 91 April 1, 2026 at 06:55:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5170 0 37 2263 163 402 12 67 413 23 3753 13 9 0 78 1 6603 0 56 205 0 747 1 118 1064 70 2668 2 21 0 77 2 3638 0 65 195 23 739 3 120 599 102 1387 1 14 0 85 3 810 0 5 254 70 493 2 74 593 42 2557 4 1 0 95 4 3887 0 11 190 74 949 0 97 1643 81 1232 1 2 0 97 5 2585 0 21 481 28 1017 0 125 1018 61 1542 1 2 0 97 6 7603 0 26 306 11 746 2 137 648 69 2434 1 2 0 97 7 11304 0 72 462 78 935 9 109 1310 71 2646 9 7 0 83 April 1, 2026 at 06:55:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2307 202 110 0 0 0 0 567 0 0 0 100 1 0 0 0 14 0 8 0 1 1 0 0 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 27 0 0 11 3 4 0 0 0 0 556 0 0 0 100 4 0 0 0 7 1 1 0 1 0 0 27 0 0 0 100 5 0 0 0 18 4 15 0 2 0 0 300 0 0 0 100 6 0 0 0 10 1 6 0 1 0 0 0 0 0 0 100 7 0 0 8 310 153 104 0 0 0 0 259 0 0 0 100 April 1, 2026 at 06:55:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 17 2322 202 249 8 72 777 10 566 0 14 0 86 1 0 0 0 83 0 200 7 57 441 6 0 0 14 0 86 2 0 0 0 495 40 996 0 90 631 10 1 0 1 0 99 3 0 0 0 346 161 401 0 85 674 5 763 0 1 0 99 4 0 0 0 245 157 204 9 60 506 5 294 0 14 0 86 5 0 0 0 104 4 228 8 60 505 8 300 0 14 0 86 6 0 0 0 88 1 205 7 49 454 5 0 0 14 0 86 7 0 0 11 303 112 221 7 55 428 7 262 0 14 0 86 April 1, 2026 at 06:55:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 18 2306 202 339 0 87 1261 41 565 0 1 0 99 1 0 0 0 114 0 288 0 72 625 26 12 0 1 0 99 2 1 0 0 527 32 1003 0 82 748 37 22 0 1 0 99 3 0 0 0 379 168 455 1 75 908 25 1042 0 1 0 99 4 0 0 0 336 188 349 0 66 797 35 295 0 1 0 99 5 0 0 0 135 1 318 0 70 668 34 300 0 1 0 99 6 0 0 0 125 3 305 0 60 556 32 1 0 1 0 99 7 0 0 9 323 103 299 1 63 711 33 247 0 1 0 99 April 1, 2026 at 06:55:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 20 2307 202 290 0 73 1152 10 567 0 1 0 99 1 0 0 7 106 3 290 0 69 496 11 1293 0 1 0 99 2 0 0 0 500 1 955 0 81 614 14 0 0 1 0 99 3 0 0 0 312 169 338 1 70 589 3 8 0 1 0 99 4 0 0 0 368 217 380 0 76 707 12 294 0 1 0 99 5 0 0 0 109 2 255 0 66 419 10 300 0 0 0 99 6 0 0 0 105 2 254 0 63 407 9 0 0 0 0 100 7 0 0 0 304 102 261 0 66 439 10 2 0 1 0 99 April 1, 2026 at 06:55:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 524 0 72 2322 207 620 4 98 496 47 1432 0 1 0 98 1 1985 0 7 228 31 529 7 64 369 32 2108 2 1 0 97 2 700 0 8 363 11 785 6 74 367 31 757 1 2 0 98 3 241 0 4 277 77 502 2 69 233 20 929 0 1 0 99 4 1294 0 11 220 89 418 2 67 341 27 1049 1 2 0 97 5 294 0 5 174 15 432 2 60 316 27 1027 0 1 0 98 6 8080 0 6 150 7 482 7 57 510 29 2004 2 4 0 94 7 847 0 18 373 104 548 1 70 207 44 764 0 1 0 99 April 1, 2026 at 06:55:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2308 202 8 0 0 0 0 567 0 0 0 100 1 0 0 7 114 14 138 1 1 0 0 1432 0 0 0 100 2 0 0 0 109 40 102 0 1 0 0 0 0 0 0 100 3 0 0 0 10 1 4 0 1 0 0 0 0 0 0 100 4 0 0 0 12 2 8 0 1 0 0 294 0 0 0 100 5 17 0 0 22 7 16 0 0 0 0 308 0 0 0 100 6 0 0 0 21 2 14 0 1 0 0 0 0 0 0 100 7 0 0 8 214 103 8 0 2 0 0 2 0 0 0 100 April 1, 2026 at 06:55:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 20 2308 203 147 0 10 89 0 565 0 2 0 97 1 6 0 7 163 3 242 0 4 79 0 1382 0 0 0 100 2 0 0 0 77 8 124 0 6 53 0 0 0 0 0 100 3 0 0 0 221 90 314 0 12 56 0 0 0 0 0 100 4 0 0 0 120 45 142 0 9 80 0 294 0 0 0 100 5 0 0 0 85 7 147 0 8 54 0 308 0 0 0 100 6 0 0 0 79 1 139 0 14 61 0 0 0 0 0 100 7 0 0 0 280 102 146 0 10 68 0 0 0 0 0 100 April 1, 2026 at 06:55:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 20 2307 202 8 0 0 0 0 567 0 0 0 100 1 0 0 7 112 3 136 1 0 1 0 1380 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 294 0 0 0 100 5 0 0 0 20 7 18 0 1 0 0 308 0 0 0 100 6 0 0 0 17 1 10 0 0 0 0 0 0 0 0 100 7 0 0 0 211 103 4 0 0 0 0 2 0 0 0 100 April 1, 2026 at 06:55:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 22 0 30 2312 202 42 1 7 5 7 620 0 1 0 99 1 11 0 21 62 3 103 1 9 2 7 1417 0 0 0 99 2 5 0 7 30 2 35 0 6 6 2 40 0 0 0 100 3 10 0 0 126 21 126 0 6 12 3 36 0 0 0 100 4 8 0 4 88 34 88 0 7 7 3 324 0 0 0 100 5 12 0 2 44 10 38 0 3 3 3 353 0 0 0 100 6 306 0 1 31 1 41 2 7 10 6 115 0 0 0 100 7 15 0 1 218 103 11 0 0 1 1 12 0 0 0 100 April 1, 2026 at 06:55:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2306 202 10 0 0 0 0 566 0 0 0 100 1 0 0 7 14 3 36 1 0 1 0 1326 0 0 0 100 2 0 0 0 22 4 18 0 0 0 0 18 0 0 0 100 3 0 0 7 108 43 104 0 2 0 0 0 0 0 0 100 4 0 0 0 115 10 117 0 4 0 0 306 0 0 0 100 5 0 0 0 17 7 8 0 0 0 0 300 0 1 0 99 6 0 0 0 22 1 20 0 1 2 0 12 0 0 0 100 7 0 0 1 223 103 22 0 2 0 0 2 0 0 0 100 April 1, 2026 at 06:55:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 20 2306 202 68 0 0 0 0 566 0 0 0 100 1 0 0 7 12 3 36 1 0 0 0 1323 0 0 0 100 2 0 0 0 10 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 111 48 104 0 3 0 0 0 0 0 0 100 4 0 0 7 49 4 42 0 2 0 0 294 0 0 0 100 5 0 0 0 20 3 14 0 3 0 0 300 0 0 0 100 6 0 0 0 12 2 6 0 1 0 0 0 0 0 0 100 7 0 0 0 216 101 8 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:55:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2308 202 132 0 1 0 0 566 0 0 0 100 1 0 0 7 11 3 36 0 0 0 0 1322 0 0 0 100 2 0 0 0 10 2 4 0 0 0 0 1 0 0 0 100 3 0 0 0 113 53 108 0 0 0 0 0 0 0 0 100 4 0 0 7 13 3 8 0 1 2 0 295 0 0 0 100 5 0 0 0 13 2 10 0 0 0 0 300 0 0 0 100 6 0 0 0 15 2 10 0 0 0 0 0 0 0 0 100 7 0 0 1 221 102 14 0 0 1 0 2 0 0 0 100 April 1, 2026 at 06:55:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2305 202 110 0 0 0 0 566 0 0 0 100 1 0 0 7 12 3 38 1 1 1 0 1322 0 0 0 100 2 0 0 0 11 2 6 0 1 0 0 1 0 0 0 100 3 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 6 0 1 0 0 295 0 0 0 100 5 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 6 0 0 0 13 3 6 0 0 0 0 1 0 0 0 100 7 0 0 1 215 101 8 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:55:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2752 0 70 2312 203 531 6 24 31 5 1653 2 1 0 97 1 140 0 22 258 5 526 4 16 17 6 3067 1 1 0 98 2 96 0 0 285 3 534 5 19 18 4 950 1 0 0 99 3 336 0 0 330 22 608 2 12 15 0 1326 1 0 0 99 4 34 0 0 272 12 516 2 11 21 2 1424 1 0 0 99 5 379 0 0 218 26 355 5 12 37 6 1750 1 1 0 98 6 2556 0 1 285 3 565 6 14 62 3 1621 1 1 0 98 7 691 0 0 368 102 311 4 10 61 5 1462 1 1 0 98 April 1, 2026 at 06:55:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2306 201 114 0 0 1 0 300 0 0 0 100 1 0 0 21 15 5 38 1 0 1 0 1650 0 0 0 100 2 0 0 0 24 5 20 0 1 1 0 11 0 0 0 100 3 0 0 0 15 4 6 0 1 1 0 1 0 0 0 100 4 0 0 1 20 4 20 0 1 1 0 318 0 0 0 100 5 35 0 0 137 68 120 0 0 1 0 309 0 0 0 100 6 0 0 0 17 3 12 0 0 1 0 12 0 0 0 100 7 0 0 7 223 103 18 0 1 0 0 2 0 0 0 100 April 1, 2026 at 06:55:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 106 0 0 0 0 300 0 0 0 100 1 0 0 21 11 4 40 1 1 0 0 1651 0 0 0 100 2 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 10 2 4 0 0 0 0 294 0 0 0 100 5 0 0 0 125 58 120 1 1 1 0 309 0 0 0 100 6 0 0 0 12 2 6 0 1 0 0 0 0 0 0 100 7 0 0 1 217 102 10 0 0 0 0 2 0 0 0 100 April 1, 2026 at 06:55:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2311 201 214 0 13 74 0 300 0 1 0 99 1 0 0 21 55 4 129 1 5 61 0 1646 0 0 0 100 2 0 0 0 50 1 88 0 5 63 0 0 0 0 0 100 3 0 0 0 94 31 148 0 5 56 0 0 0 0 0 100 4 0 0 0 82 31 90 0 5 60 0 294 0 0 0 100 5 0 0 0 166 57 209 0 8 71 0 308 0 0 0 100 6 0 0 0 68 2 122 0 5 52 0 0 0 0 0 100 7 0 0 0 251 101 80 0 7 38 0 0 0 0 0 100 April 1, 2026 at 06:55:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 9 0 12 2310 201 151 1 8 3 0 346 0 1 0 99 1 16 0 36 31 5 69 1 9 4 4 1689 0 0 0 99 2 0 0 0 22 2 18 0 2 0 1 41 0 0 0 100 3 16 0 0 29 3 34 0 7 5 6 42 0 0 0 100 4 26 0 4 25 2 34 0 5 9 6 328 0 0 0 100 5 12 0 13 139 60 144 1 9 10 5 363 0 0 0 100 6 286 0 3 25 2 21 1 3 7 2 107 0 0 0 100 7 18 0 2 231 103 25 0 2 6 1 17 0 0 0 100 April 1, 2026 at 06:55:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 108 0 0 0 0 300 0 0 0 100 1 0 0 21 14 4 41 2 1 0 0 1592 0 0 0 100 2 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 10 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 12 3 4 0 0 0 0 295 0 0 0 100 5 0 0 0 116 52 112 0 1 0 0 300 0 0 0 100 6 0 0 7 15 2 8 0 2 0 0 0 0 0 0 100 7 0 0 1 216 101 8 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:55:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2308 201 110 0 0 0 0 300 0 0 0 100 1 0 0 28 14 4 41 1 0 0 0 1590 0 0 0 100 2 1 0 0 15 1 14 0 0 0 0 13 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 20 5 18 1 1 0 0 312 0 0 0 100 5 0 0 0 120 59 108 1 0 0 0 300 0 0 0 100 6 0 0 0 18 2 14 0 0 0 0 12 0 0 0 100 7 0 0 0 222 102 16 0 1 0 0 2 0 0 0 100 April 1, 2026 at 06:55:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 203 112 0 0 0 0 299 0 0 0 99 1 0 0 28 15 4 48 1 4 0 0 1586 0 0 0 100 2 0 0 0 10 1 6 0 2 0 0 0 0 0 0 100 3 0 0 0 9 1 4 0 1 0 0 0 0 0 0 100 4 0 0 0 12 2 4 0 1 0 0 294 0 0 0 100 5 0 0 0 113 52 108 0 1 0 0 300 0 0 0 100 6 0 0 0 14 2 6 0 0 1 0 0 0 0 0 100 7 0 0 1 218 101 14 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:55:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 128 0 1 3 0 300 0 0 0 100 1 0 0 21 10 4 38 0 0 0 0 1602 0 0 0 100 2 0 0 0 11 3 6 0 0 0 0 2 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 12 3 8 0 0 1 0 294 0 0 0 100 5 0 0 0 111 52 108 0 0 1 0 300 0 0 0 100 6 0 0 0 14 2 10 0 0 0 0 0 0 0 0 100 7 0 0 1 220 102 14 0 0 3 0 2 0 0 0 100 April 1, 2026 at 06:55:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 384 0 762 2469 208 9437 308 888 287 3 32780 18 6 0 76 1 522 0 21 832 7 8377 218 663 251 12 30429 23 5 0 72 2 270 0 0 703 5 7040 236 634 277 6 28525 21 4 0 74 3 394 0 0 514 3 7754 225 636 285 9 30107 19 4 0 77 4 409 0 0 602 10 7543 251 617 316 3 31903 20 4 0 76 5 156 0 0 993 31 7521 198 585 264 4 29860 19 4 0 76 6 4741 0 9 349 6 8404 221 605 297 4 31352 18 5 0 77 7 884 0 2 1286 106 8583 188 545 232 9 27989 20 4 0 75 April 1, 2026 at 06:55:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 89 0 1434 2506 208 14032 278 1176 441 0 52182 39 8 0 54 1 28 0 21 423 11 13433 334 1191 467 0 53649 38 7 0 55 2 12 0 0 440 8 15598 313 1211 535 0 57125 38 8 0 54 3 33 0 0 418 11 15544 299 1196 451 0 51394 33 7 0 60 4 40 0 0 404 18 14466 284 1058 453 0 52814 34 7 0 59 5 12 0 0 368 9 13883 250 981 444 0 48980 34 7 0 59 6 19 0 0 393 9 14237 261 983 504 0 53449 33 7 0 60 7 22 0 7 579 109 13029 244 879 430 0 49493 32 7 0 62 April 1, 2026 at 06:55:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 31 0 1417 2484 206 15452 292 1330 463 0 54542 37 8 0 55 1 24 0 7 396 15 15133 251 1264 460 0 51940 33 7 0 60 2 27 0 0 379 15 14894 257 1170 411 0 53287 39 7 0 53 3 17 0 14 370 12 14832 242 1137 480 0 55845 37 7 0 56 4 15 0 0 358 7 14609 226 1054 393 0 50469 33 7 0 60 5 42 0 0 373 19 13237 213 956 469 0 53866 34 7 0 59 6 21 0 0 364 8 13047 233 925 488 0 54932 33 7 0 60 7 32 0 3 559 117 13590 168 948 439 0 51768 36 6 0 58 April 1, 2026 at 06:55:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 81 0 1375 2480 211 14427 267 1180 503 1 52229 38 8 0 55 1 90 0 0 370 5 15033 275 1206 506 3 53742 30 7 0 62 2 17 0 0 389 14 13580 250 1115 424 0 49117 35 7 0 58 3 80 0 0 376 14 13345 234 1088 456 2 52825 34 7 0 59 4 97 0 14 350 7 14043 199 1023 418 1 49864 33 7 0 60 5 59 0 10 348 10 13934 199 996 410 0 50975 32 7 0 61 6 124 0 0 344 11 12533 225 883 450 0 50402 32 6 0 61 7 19 0 9 566 110 12873 205 863 420 1 49493 36 6 0 58 April 1, 2026 at 06:55:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2322 201 171 1 11 75 0 321 0 0 0 100 1 9 0 8 80 13 107 0 10 30 0 39 0 0 0 100 2 0 0 0 65 4 100 0 8 39 0 9 0 0 0 100 3 0 0 0 40 25 155 0 10 51 0 1433 0 0 0 100 4 0 0 14 78 26 90 1 6 47 0 266 0 0 0 100 5 0 0 0 33 3 73 0 8 46 0 13 0 0 0 100 6 0 0 0 29 2 101 0 11 63 0 13 0 0 0 100 7 0 0 8 332 146 163 0 6 38 0 560 0 0 0 100 April 1, 2026 at 06:55:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 110 0 0 0 0 305 0 0 0 100 1 0 0 0 24 7 16 0 0 1 0 14 0 0 0 100 2 0 0 0 12 2 10 0 1 1 0 7 0 0 0 100 3 0 0 0 16 2 40 2 1 0 0 1431 0 0 0 100 4 0 0 14 7 2 2 0 0 0 0 266 0 0 0 100 5 0 0 0 17 1 16 0 2 0 0 4 0 0 0 100 6 0 0 0 12 2 6 0 0 0 0 3 0 0 0 100 7 0 0 8 316 155 108 1 0 0 0 560 0 0 0 100 April 1, 2026 at 06:55:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2305 201 106 0 0 1 0 300 0 0 0 100 1 0 0 0 15 5 10 0 0 0 0 5 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 10 2 34 1 0 0 0 1428 0 0 0 100 4 0 0 14 9 3 4 0 0 0 0 267 0 0 0 100 5 0 0 0 16 1 14 0 1 0 0 0 0 0 0 100 6 0 0 0 11 2 4 0 0 0 0 0 0 0 0 100 7 0 0 7 314 155 108 0 0 0 0 560 0 0 0 100 April 1, 2026 at 06:55:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14 0 36 2309 202 125 1 3 2 0 320 0 1 0 99 1 33 0 7 39 6 39 1 5 5 4 50 0 0 0 99 2 4 0 2 32 3 39 1 5 1 0 75 0 0 0 100 3 15 0 3 27 3 56 0 5 0 2 1490 0 0 0 100 4 3 0 16 17 2 17 0 7 3 2 297 0 0 0 100 5 4 0 4 47 12 40 0 3 6 4 42 0 0 0 100 6 284 0 4 26 2 15 0 5 17 1 101 0 0 0 100 7 11 0 8 339 155 145 0 4 5 3 605 0 0 0 100 April 1, 2026 at 06:55:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 202 115 0 2 0 0 302 0 0 0 100 1 0 0 7 8 1 4 0 1 0 0 0 0 0 0 100 2 0 0 0 11 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 13 3 36 1 0 0 0 1374 0 0 0 100 4 0 0 14 11 3 6 1 0 0 0 266 0 0 0 100 5 0 0 0 23 2 21 0 1 0 0 0 0 0 0 100 6 0 0 0 14 2 4 0 0 0 0 0 0 0 0 100 7 0 0 8 317 156 110 0 0 0 0 559 0 0 0 100 April 1, 2026 at 06:55:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2312 203 196 0 6 67 0 305 0 0 0 99 1 0 0 0 46 0 76 0 10 59 0 0 0 0 0 100 2 0 0 0 52 4 84 0 5 35 0 5 0 0 0 100 3 0 0 0 85 25 144 0 7 50 0 1370 0 0 0 100 4 0 0 14 71 26 83 0 6 58 0 266 0 0 0 100 5 0 0 0 63 1 105 0 5 49 0 3 0 0 0 100 6 0 0 0 48 2 76 0 3 50 0 0 0 0 0 100 7 0 0 7 346 155 172 1 8 31 0 560 0 0 0 100 April 1, 2026 at 06:55:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2307 202 112 0 0 0 0 302 0 0 0 100 1 0 0 0 8 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 10 2 4 0 0 0 0 1 0 0 0 100 3 0 0 0 12 2 34 2 0 1 0 1369 0 0 0 100 4 0 0 14 7 2 2 0 0 0 0 266 0 0 0 100 5 0 0 0 24 2 18 0 0 0 0 1 0 0 0 100 6 0 0 0 17 2 16 0 2 0 0 1 0 0 0 100 7 0 0 8 315 155 108 0 0 0 0 559 0 0 0 100 April 1, 2026 at 06:55:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 118 0 1 0 0 302 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 3 0 0 0 10 2 34 1 0 1 0 1369 0 0 0 100 4 0 0 14 6 2 2 0 0 0 0 266 0 0 0 100 5 0 0 0 16 1 12 0 0 0 0 0 0 0 0 100 6 0 0 0 13 2 8 0 0 1 0 0 0 0 0 100 7 0 0 8 315 155 110 0 1 0 0 559 0 0 0 100 April 1, 2026 at 06:55:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 132 0 7 2311 202 187 3 10 12 5 518 0 0 0 99 1 161 0 0 38 2 59 1 9 6 4 146 0 0 0 100 2 215 0 0 45 4 78 4 11 13 3 248 0 0 0 100 3 62 0 0 61 4 125 2 5 15 0 1539 0 0 0 99 4 2502 0 22 39 4 61 2 8 10 5 615 1 0 0 98 5 221 0 1 58 10 89 3 7 32 8 334 0 0 0 99 6 2405 0 1 71 4 134 4 13 45 7 941 0 1 0 99 7 800 0 14 382 156 240 1 7 27 6 918 0 0 0 99 April 1, 2026 at 06:55:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1190 0 1424 2508 209 6221 241 982 176 2 36826 30 6 0 63 1 735 0 0 626 9 6183 221 859 133 1 32850 26 5 0 69 2 972 0 0 665 11 5852 174 765 166 5 34964 26 5 0 69 3 802 0 0 524 12 5981 157 682 145 2 31904 23 5 0 73 4 657 0 14 607 23 4905 145 543 172 0 34510 22 4 0 74 5 746 0 0 399 6 4563 109 482 147 0 35688 23 4 0 72 6 674 0 0 490 8 4744 111 442 140 2 32096 20 4 0 76 7 725 0 2 679 107 4296 123 423 140 1 33420 21 4 0 76 April 1, 2026 at 06:55:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 45 0 1418 2539 214 6904 240 1138 191 0 40390 29 6 0 65 1 93 0 7 402 2 6940 198 1052 200 0 40108 28 5 0 66 2 135 0 0 390 13 6433 177 862 210 0 40466 26 5 0 69 3 79 0 0 399 36 6279 176 803 209 0 37201 24 5 0 71 4 5 0 92 357 39 5807 156 735 188 0 37831 23 5 0 72 5 4 0 7 332 6 5536 137 584 195 0 37781 23 4 0 72 6 28 0 14 328 9 5272 100 540 172 0 36146 23 4 0 73 7 3 0 7 541 113 5199 130 517 179 0 36096 21 4 0 74 April 1, 2026 at 06:55:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 24 0 717 2383 208 4709 66 816 84 0 23623 16 4 0 81 1 27 0 0 209 7 4634 64 720 97 0 25120 15 3 0 82 2 87 0 0 186 12 4379 64 615 100 1 24475 13 3 0 84 3 36 0 0 199 20 4095 30 532 99 0 27110 13 3 0 84 4 13 0 0 164 12 3906 41 467 75 0 25111 13 3 0 84 5 98 0 0 154 3 3619 48 399 72 0 24549 13 3 0 84 6 5 0 21 152 3 3564 51 363 61 0 21537 12 2 0 86 7 15 0 4 371 109 3366 40 338 51 0 21935 10 2 0 87 April 1, 2026 at 06:55:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 94 0 2 0 0 300 0 0 0 100 1 0 0 0 17 1 11 0 3 0 0 0 0 0 0 100 2 0 0 0 121 56 115 1 2 0 0 5 0 0 0 100 3 0 0 0 19 0 10 0 0 0 0 0 0 0 0 100 4 0 0 0 15 4 38 1 0 1 0 1429 0 0 0 100 5 0 0 0 12 1 9 0 2 1 0 0 0 0 0 100 6 0 0 21 14 4 10 1 1 0 0 525 0 0 0 100 7 0 0 1 213 102 2 1 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 122 0 0 0 0 318 0 0 0 100 1 0 0 0 17 2 12 0 0 1 0 3 0 0 0 100 2 0 0 0 132 61 132 0 1 0 0 31 0 0 0 100 3 0 0 0 7 0 4 0 0 0 0 2 0 0 0 100 4 0 0 0 17 4 38 2 0 0 0 1435 0 0 0 100 5 0 0 0 21 8 12 0 2 0 0 3 0 0 0 100 6 0 0 21 22 4 26 0 0 1 0 543 0 0 0 100 7 0 0 1 212 102 6 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:55:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 106 0 0 0 0 300 0 0 0 100 1 0 0 0 15 1 10 0 0 0 0 0 0 0 0 100 2 0 0 0 123 58 116 0 0 0 0 9 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 1429 0 0 0 100 5 0 0 0 9 1 6 0 0 0 0 3 0 0 0 100 6 0 0 21 12 4 10 0 0 0 0 526 0 0 0 100 7 0 0 1 214 104 8 0 0 0 0 304 0 0 0 100 April 1, 2026 at 06:55:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 33 0 26 2318 204 252 1 17 78 5 349 0 1 0 99 1 5 0 0 78 1 101 0 12 41 1 18 0 0 0 100 2 8 0 5 169 57 214 1 10 60 5 49 0 0 0 100 3 0 0 0 100 26 107 0 11 44 2 31 0 0 0 100 4 26 0 11 74 26 123 1 13 33 7 1459 0 0 0 100 5 3 0 10 79 5 135 2 13 60 4 38 0 0 0 100 6 291 0 25 57 4 70 1 17 33 4 686 0 0 0 100 7 12 0 17 276 102 118 1 11 51 2 338 0 1 0 99 April 1, 2026 at 06:55:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 117 0 1 3 0 300 0 0 0 100 1 0 0 0 15 2 8 0 1 1 0 1 0 0 0 100 2 0 0 0 118 55 112 0 0 0 0 23 0 0 0 100 3 0 0 7 8 0 2 0 1 0 0 0 0 0 0 100 4 0 0 0 13 3 36 0 1 0 0 1374 0 0 0 100 5 0 0 0 12 2 6 0 0 0 0 1 0 0 0 100 6 0 0 21 16 5 14 1 2 0 0 524 0 0 0 100 7 0 0 1 211 102 2 1 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2309 202 117 0 0 0 0 302 0 0 0 100 1 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 110 52 104 0 0 0 0 0 0 0 0 100 3 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 4 0 0 0 14 3 36 2 1 0 0 1368 0 0 0 100 5 0 0 0 12 1 8 0 0 0 0 0 0 0 0 100 6 0 0 21 13 4 8 0 0 0 0 526 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 14 2304 201 130 0 1 0 0 312 0 0 0 99 1 0 0 0 15 3 6 0 0 2 0 1 0 0 0 100 2 0 0 0 125 56 120 0 1 1 0 14 0 0 0 100 3 0 0 0 11 2 2 0 0 1 0 1 0 0 0 100 4 0 0 0 19 5 38 1 0 1 0 1370 0 0 0 100 5 0 0 0 20 9 6 0 0 2 0 0 0 0 0 100 6 0 0 21 20 5 20 0 0 1 0 538 0 0 0 100 7 0 0 7 216 103 8 0 0 1 0 301 0 0 0 100 April 1, 2026 at 06:55:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 120 0 0 0 0 302 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 113 52 106 0 0 0 0 0 0 0 0 100 3 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 4 0 0 0 12 3 36 1 0 0 0 1370 0 0 0 100 5 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 6 0 0 21 12 4 8 0 0 0 0 524 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:55:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 265 0 103 2337 201 963 46 162 31 6 5250 2 1 0 97 1 303 0 0 169 1 778 31 138 37 4 4420 2 1 0 97 2 276 0 0 382 30 852 25 119 16 4 3852 2 1 0 97 3 279 0 0 300 0 565 25 88 31 7 4106 2 1 0 98 4 130 0 0 163 25 744 25 103 9 2 5874 2 1 0 97 5 231 0 0 307 5 648 24 82 39 1 3698 2 1 0 98 6 5197 0 30 331 6 658 27 80 56 12 5255 3 1 0 95 7 919 0 2 552 102 719 27 90 31 11 4270 2 1 0 98 April 1, 2026 at 06:55:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2307 202 118 0 2 0 0 318 0 0 0 100 1 34 0 0 22 5 14 0 0 0 0 13 0 0 0 100 2 0 0 0 19 4 8 0 1 0 0 13 0 0 0 100 3 0 0 0 13 1 8 0 1 0 0 5 0 0 0 100 4 0 0 0 123 53 148 2 1 1 0 1435 0 0 0 100 5 0 0 0 13 2 4 0 0 0 0 0 0 0 0 100 6 0 0 21 15 4 12 0 1 0 0 540 0 0 0 100 7 0 0 1 221 105 12 0 1 0 0 308 0 0 0 100 April 1, 2026 at 06:56:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 112 0 0 0 0 300 0 0 0 100 1 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 2 0 0 0 11 3 6 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 33 12 54 1 0 1 0 1427 0 0 0 100 5 0 0 0 96 44 94 0 2 0 0 1 0 0 0 100 6 0 0 21 12 4 10 0 1 0 0 528 0 0 0 100 7 0 0 1 212 103 6 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2302 202 128 0 0 0 0 313 0 0 0 99 1 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 2 0 0 0 17 5 14 0 0 0 0 13 0 0 0 100 3 0 0 0 5 0 2 0 1 0 0 0 0 0 0 100 4 0 0 0 11 3 34 0 0 0 0 1426 0 0 0 100 5 0 0 0 122 61 112 0 0 1 0 4 0 0 0 100 6 0 0 21 18 4 22 0 1 0 0 542 0 0 0 100 7 0 0 1 212 102 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 17 2313 201 147 2 9 3 2 350 0 1 0 99 1 9 0 6 31 7 26 0 3 1 3 44 0 0 0 100 2 27 0 2 31 3 36 0 6 2 7 33 0 0 0 100 3 11 0 7 26 0 22 1 5 1 2 29 0 0 0 100 4 4 0 14 22 3 50 1 6 1 5 1453 0 0 0 100 5 5 0 0 132 54 131 2 3 5 3 54 0 0 0 100 6 284 0 21 22 4 24 1 6 7 1 637 0 0 0 100 7 10 0 2 225 103 21 1 3 2 3 329 0 0 0 100 April 1, 2026 at 06:56:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2311 203 214 1 6 73 0 302 0 1 0 99 1 0 0 0 47 0 81 0 7 39 0 0 0 0 0 100 2 0 0 0 51 4 85 0 7 50 0 1 0 0 0 100 3 0 0 0 74 25 87 0 5 41 0 0 0 0 0 100 4 0 0 0 67 27 107 2 8 38 0 1373 0 0 0 100 5 0 0 7 151 54 179 0 5 40 0 0 0 0 0 100 6 0 0 21 63 4 98 0 7 50 0 525 0 0 0 100 7 0 0 1 268 103 113 0 9 33 0 300 0 0 0 100 April 1, 2026 at 06:56:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2307 201 115 0 0 0 0 300 0 0 0 100 1 0 0 0 9 1 2 0 0 0 0 1 0 0 0 100 2 0 0 0 14 4 8 0 0 0 0 1 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 12 3 34 1 0 0 0 1369 0 0 0 100 5 0 0 0 113 52 108 0 0 0 0 1 0 0 0 100 6 0 0 21 14 4 12 0 1 0 0 525 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2307 202 142 0 1 0 0 302 0 0 0 100 1 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 2 0 0 0 12 3 6 0 0 0 0 0 0 0 0 100 3 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 12 3 34 1 0 1 0 1369 0 0 0 100 5 0 0 0 111 51 108 0 0 0 0 18 0 0 0 100 6 0 0 21 13 4 10 0 1 0 0 526 0 0 0 100 7 0 0 1 216 103 10 0 0 2 0 309 0 0 0 100 April 1, 2026 at 06:56:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2306 201 128 0 0 3 0 310 0 0 0 100 1 0 0 0 11 2 4 0 1 4 0 1 0 0 0 100 2 0 0 0 25 8 20 0 1 1 0 15 0 0 0 100 3 0 0 0 10 2 2 0 0 1 0 1 0 0 0 100 4 0 0 0 19 5 42 0 1 0 0 1371 0 0 0 100 5 0 0 0 122 60 106 0 0 2 0 0 0 0 0 100 6 0 0 21 20 5 20 1 0 1 0 539 0 0 0 100 7 0 0 7 219 104 10 1 0 1 0 301 0 0 0 100 April 1, 2026 at 06:56:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 326 0 496 2362 208 3403 33 160 66 27 7465 8 2 0 90 1 272 0 0 224 1 3225 34 131 56 8 7701 10 2 0 88 2 226 0 0 301 5 2911 13 84 70 12 7445 6 2 0 92 3 50 0 0 350 0 3078 13 38 83 3 8661 13 2 0 86 4 294 0 0 464 4 2784 16 34 41 1 8402 5 2 0 93 5 335 0 0 421 40 2909 13 31 66 3 6918 7 2 0 91 6 2898 0 30 137 7 2984 18 35 132 38 7719 6 6 0 88 7 1066 0 1 613 104 3341 19 51 86 29 7391 5 2 0 93 April 1, 2026 at 06:56:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 237 0 1153 2495 210 7773 130 456 186 10 17514 24 5 0 71 1 2974 0 26 300 13 8063 103 361 150 14 17270 26 4 0 70 2 400 0 36 284 15 7765 66 247 132 13 16947 20 4 0 76 3 255 0 7 311 42 7364 66 197 160 13 15867 14 3 0 83 4 165 0 6 298 40 6274 61 162 159 13 17881 14 3 0 83 5 99 0 6 283 36 6341 44 123 239 14 18195 17 4 0 79 6 2740 0 50 265 15 6540 63 149 229 24 16300 14 4 0 82 7 1274 0 13 509 134 6624 46 119 219 15 16965 14 3 0 82 April 1, 2026 at 06:56:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 36 0 19 2314 205 78 0 2 0 0 16 0 0 0 100 1 0 0 0 57 5 44 1 2 0 0 300 0 0 0 100 2 0 0 0 76 31 72 0 4 1 0 8 0 0 0 100 3 0 0 0 23 1 18 0 3 1 0 8 0 0 0 100 4 10 0 0 19 3 40 0 1 0 0 1439 0 0 0 100 5 0 0 0 12 1 6 0 0 0 0 8 0 0 0 100 6 37 0 21 22 6 18 0 2 0 0 539 0 0 0 100 7 0 0 8 260 120 50 0 3 0 0 305 0 0 0 100 April 1, 2026 at 06:56:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2313 205 114 0 1 0 0 8 0 0 0 100 1 0 0 0 10 1 4 0 1 0 0 300 0 0 0 100 2 0 0 0 116 52 108 0 1 0 0 0 0 0 0 100 3 0 0 0 15 2 9 0 3 0 0 1 0 0 0 100 4 4 0 0 15 4 36 1 0 0 0 1430 0 0 0 100 5 0 0 0 14 3 12 0 1 0 0 4 0 0 0 100 6 0 0 21 14 4 10 1 0 0 0 577 0 0 0 100 7 0 0 1 214 102 6 0 1 0 0 300 0 0 0 100 April 1, 2026 at 06:56:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2312 204 110 0 0 0 0 4 0 0 0 100 1 0 0 7 14 3 10 0 1 0 0 306 0 0 0 100 2 0 0 0 118 51 117 0 2 0 0 13 0 0 0 100 3 0 0 0 25 4 20 0 1 0 0 17 0 0 0 100 4 0 0 0 16 3 42 1 2 0 0 1426 0 0 0 100 5 0 0 0 19 8 6 0 0 0 0 0 0 0 0 100 6 1 0 21 17 4 18 0 0 0 0 549 0 0 0 100 7 0 0 1 215 102 8 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 253 0 47 2314 200 322 4 25 23 15 841 0 1 0 99 1 191 0 0 97 7 143 3 12 7 5 673 0 0 0 100 2 125 0 7 209 51 246 5 21 11 8 337 0 1 0 99 3 78 0 0 77 2 145 6 17 11 4 260 0 0 0 100 4 187 0 16 61 4 119 4 13 14 3 1664 0 0 0 99 5 235 0 5 99 29 113 2 12 49 5 378 0 0 0 99 6 5497 0 40 75 4 151 2 19 66 15 1487 2 1 0 97 7 1516 0 5 291 103 169 4 18 52 19 987 0 0 0 99 April 1, 2026 at 06:56:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 38 0 19 2320 207 271 0 11 80 0 22 0 0 0 99 1 0 0 7 77 3 139 1 12 66 0 305 0 0 0 100 2 0 0 0 155 52 189 0 9 56 0 2 0 0 0 100 3 0 0 0 88 32 109 0 7 65 0 5 0 0 0 100 4 0 0 0 98 36 143 0 4 42 0 1432 0 0 0 100 5 0 0 0 51 1 90 0 7 60 0 8 0 0 0 100 6 0 0 21 76 5 127 0 5 95 0 536 0 0 0 100 7 0 0 1 264 103 101 0 6 60 0 308 0 0 0 100 April 1, 2026 at 06:56:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2313 205 122 0 0 0 0 8 0 0 0 100 1 0 0 0 12 2 6 0 0 0 0 301 0 0 0 100 2 0 0 0 121 56 116 0 2 0 0 25 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 25 4 50 2 1 1 0 1427 0 0 0 100 5 0 0 0 12 2 6 0 0 0 0 1 0 0 0 100 6 0 0 21 14 4 8 1 0 0 0 528 0 0 0 100 7 0 0 1 212 102 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2314 206 122 0 0 0 0 11 0 0 0 100 1 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 110 51 104 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 7 21 4 48 1 0 0 0 1423 0 0 0 99 5 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 6 0 0 21 13 4 10 0 0 0 0 527 0 0 0 100 7 0 0 1 212 102 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1675 0 42 2349 206 482 4 66 77 57 978 2 2 0 97 1 934 0 8 177 6 415 1 68 55 54 1487 1 1 0 98 2 5955 0 13 295 50 440 3 51 34 35 698 2 3 0 95 3 94 0 13 152 7 253 2 45 29 29 676 0 0 0 100 4 73 0 8 137 7 247 2 39 23 25 1838 0 0 0 99 5 143 0 13 134 26 186 2 31 49 27 594 0 1 0 99 6 4581 0 140 127 5 249 3 37 124 47 1730 2 1 0 97 7 4195 0 23 369 103 328 2 47 105 56 1604 1 2 0 98 April 1, 2026 at 06:56:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 576 0 33 2319 203 190 4 17 14 14 236 0 1 0 99 1 74 0 0 67 2 109 1 12 16 10 505 0 0 0 100 2 19321 0 8 32 2 113 11 14 29 11 718 4 16 0 80 3 9 0 7 139 33 164 3 12 5 3 519 0 0 0 100 4 84 0 0 80 24 119 2 11 3 4 1449 0 0 0 100 5 78 0 0 69 25 70 0 11 14 2 111 0 0 0 100 6 229 0 21 47 6 71 1 10 11 2 641 0 0 0 100 7 4330 0 10 255 103 69 1 5 17 7 763 1 1 0 98 April 1, 2026 at 06:56:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1058 0 141 2340 200 221 1 14 42 10 231 1 1 0 98 1 39 0 233 124 3 156 1 11 46 8 412 0 0 0 99 2 11 0 0 102 2 81 0 6 36 3 62 0 0 0 100 3 2214 0 0 131 24 113 2 8 37 5 430 0 1 0 99 4 146 0 0 191 44 214 1 14 41 18 1511 0 1 0 99 5 8 0 0 183 33 184 0 10 40 1 67 0 0 0 100 6 60 0 21 126 8 131 1 11 54 4 622 0 0 0 100 7 6 0 1 318 102 118 0 12 45 2 406 0 0 0 100 April 1, 2026 at 06:56:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 0 0 0 0 2 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 14 3 10 0 0 0 0 4 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 14 4 36 2 0 1 0 1424 0 0 0 100 5 0 0 0 24 9 20 0 0 0 0 0 0 0 0 100 6 0 0 21 105 50 104 0 1 0 0 535 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 303 0 0 0 100 April 1, 2026 at 06:56:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 9 1 6 0 1 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 17 5 38 2 0 2 0 1421 0 0 0 100 5 0 0 0 10 1 6 0 0 0 0 0 0 0 0 100 6 0 0 21 126 59 126 0 1 0 0 533 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 114 0 0 0 0 2 0 0 0 100 1 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 15 3 14 0 0 0 0 17 0 0 0 100 4 0 0 0 19 4 50 0 0 0 0 1436 0 0 0 100 5 0 0 0 17 6 12 0 1 0 0 9 0 0 0 100 6 0 0 21 126 60 124 0 1 1 0 533 0 0 0 100 7 0 0 1 215 102 14 1 1 0 0 300 0 0 0 100 April 1, 2026 at 06:56:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 2 0 0 0 11 1 8 0 0 0 0 4 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 4 1 0 0 26 9 50 1 0 0 0 1432 0 0 0 100 5 0 0 0 9 1 6 0 0 1 0 3 0 0 0 100 6 0 0 21 117 56 116 1 1 0 0 532 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 303 0 0 0 100 April 1, 2026 at 06:56:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 116 0 0 1 0 2 0 0 0 100 1 22 0 0 11 3 6 0 0 2 0 329 0 0 0 100 2 0 0 0 12 2 8 0 0 0 0 1 0 0 0 100 3 21 0 0 10 2 8 0 0 1 0 5 0 0 0 100 4 0 0 0 24 9 48 1 0 0 0 1428 0 0 0 100 5 0 0 0 11 2 8 0 0 1 0 0 0 0 0 100 6 0 0 21 112 54 110 0 0 0 0 526 0 0 0 100 7 0 0 1 218 102 16 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 132 0 1 0 0 0 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 301 0 0 0 100 2 0 0 0 14 3 8 0 0 0 0 2 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 24 9 46 2 0 0 0 1424 0 0 0 100 5 0 0 0 10 2 8 0 1 0 0 1 0 0 0 100 6 0 0 21 112 54 108 0 0 0 0 527 0 0 0 100 7 0 0 1 211 102 4 0 0 3 0 300 0 0 0 100 April 1, 2026 at 06:56:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 114 0 0 0 0 2 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 26 10 48 0 0 0 0 1421 0 0 0 100 5 0 0 0 11 2 8 0 0 0 0 0 0 0 0 100 6 0 0 21 112 54 110 0 0 0 0 526 0 0 0 100 7 0 0 1 210 102 2 1 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2304 201 122 0 0 3 0 1 0 0 0 100 1 0 0 0 14 3 6 1 1 2 0 301 0 0 0 100 2 0 0 0 13 2 6 0 1 1 0 0 0 0 0 100 3 0 0 0 16 2 14 0 0 1 0 13 0 0 0 100 4 0 0 0 35 13 62 1 1 0 0 1443 0 0 0 100 5 0 0 0 21 7 14 0 0 1 0 12 0 0 0 100 6 0 0 21 114 55 108 1 0 1 0 525 0 0 0 100 7 0 0 7 215 103 6 0 0 1 0 301 0 0 0 100 April 1, 2026 at 06:56:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 222 0 31 2310 202 322 3 20 5 0 448 0 1 0 99 1 37 0 0 67 4 102 0 8 4 0 710 0 0 0 100 2 141 0 0 80 3 139 0 6 12 3 297 0 0 0 99 3 1 0 0 47 1 65 0 4 1 0 288 0 0 0 100 4 232 0 0 86 6 181 0 8 5 1 1878 0 0 0 99 5 226 0 0 95 36 104 0 8 2 0 402 0 1 0 99 6 405 0 21 126 17 210 0 13 8 1 1039 0 1 0 99 7 125 0 3 395 141 297 0 13 5 3 757 0 0 0 100 April 1, 2026 at 06:56:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 201 219 0 6 92 0 0 0 0 0 100 1 0 0 0 53 1 90 0 5 30 0 300 0 0 0 100 2 0 0 0 74 8 122 0 6 48 0 12 0 0 0 100 3 0 0 0 78 30 97 0 3 49 0 0 0 0 0 100 4 0 0 0 104 33 158 2 9 70 0 1431 0 0 0 100 5 0 0 0 59 2 107 0 7 57 0 0 0 0 0 100 6 2 0 21 61 4 112 0 6 78 0 542 0 0 0 100 7 0 0 1 367 152 215 0 5 54 0 303 0 0 0 100 April 1, 2026 at 06:56:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 112 0 0 0 0 2 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 23 8 18 0 0 0 0 7 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 15 4 40 1 1 0 0 1431 0 0 0 100 5 0 0 0 12 1 12 0 1 0 0 0 0 0 0 100 6 0 0 21 12 4 8 0 0 0 0 527 0 0 0 100 7 0 0 1 310 152 102 1 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 2 0 0 0 19 6 14 0 0 0 0 9 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 16 5 38 1 0 1 0 1432 0 0 0 100 5 0 0 0 10 1 8 0 1 0 0 0 0 0 0 100 6 0 0 21 13 4 10 1 1 0 0 525 0 0 0 100 7 0 0 2 311 153 104 0 0 0 0 301 0 0 0 100 April 1, 2026 at 06:56:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 284 0 12 2391 203 779 5 155 507 109 2912 0 1 0 98 1 1386 0 161 302 1 559 3 89 168 98 4567 1 1 0 98 2 176 0 25 286 9 594 4 115 119 100 4207 1 1 0 99 3 102 0 33 294 5 536 1 117 728 70 2811 0 1 0 98 4 74 0 27 328 5 585 2 113 151 66 3720 0 1 0 99 5 54 0 20 302 38 526 0 102 56 69 2045 0 0 0 99 6 34 0 41 301 40 445 0 67 590 51 2480 0 1 0 99 7 9709 0 235 473 117 545 4 83 144 96 4245 2 2 0 95 April 1, 2026 at 06:56:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 28 0 12 2318 202 135 0 5 7 1 20 0 1 0 99 1 13 0 0 37 2 38 0 5 12 9 317 0 0 0 100 2 6 0 0 30 2 13 0 2 9 2 10 0 0 0 100 3 2 0 0 26 2 15 0 3 3 3 7 0 0 0 100 4 3 0 84 27 7 54 2 4 8 0 1128 0 1 0 99 5 9 0 0 37 3 29 0 1 6 1 24 0 0 0 100 6 1 0 28 132 54 120 0 2 4 1 532 0 0 0 100 7 1 0 1 233 102 24 0 4 4 2 326 0 0 0 100 April 1, 2026 at 06:56:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2412 201 118 0 0 2 0 2 0 1 0 99 1 0 0 679 16 1 4 0 0 2 0 300 0 0 0 100 2 0 0 0 113 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 113 1 4 0 0 0 0 0 0 0 0 100 4 0 0 49 117 5 42 1 0 2 0 1061 0 1 0 99 5 0 0 0 117 2 10 0 1 0 0 0 0 0 0 100 6 0 0 21 219 54 112 0 1 0 0 526 0 0 0 100 7 0 0 9 321 102 14 1 1 0 0 300 0 0 0 100 April 1, 2026 at 06:56:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 200 114 0 1 0 0 0 0 0 0 100 1 0 0 0 12 2 4 1 0 0 0 301 0 0 0 100 2 0 0 0 11 2 6 0 1 0 0 22 0 0 0 100 3 0 0 0 11 2 4 0 0 0 0 1 0 0 0 100 4 0 0 14 16 5 40 0 0 0 0 1058 0 0 0 100 5 0 0 0 13 2 6 0 0 0 0 1 0 0 0 100 6 0 0 21 114 54 108 1 0 0 0 525 0 0 0 100 7 0 0 1 213 102 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 114 0 0 0 0 2 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 15 5 38 1 0 0 0 1058 0 0 0 100 5 0 0 0 13 1 10 0 0 0 0 18 0 0 0 100 6 0 0 21 113 54 112 0 1 0 0 525 0 0 0 100 7 0 0 1 213 103 8 0 0 0 0 309 0 0 0 100 April 1, 2026 at 06:56:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10319 0 159 2504 220 645 9 115 720 105 11748 3 4 0 93 1 6595 0 24 401 5 531 2 98 881 100 8504 2 2 0 96 2 7733 0 381 400 6 534 7 92 1383 116 8129 2 3 0 95 3 6298 0 429 464 5 576 10 102 313 107 15701 2 4 0 94 4 1797 0 10 385 15 691 9 105 366 109 2438 0 1 0 98 5 4528 0 475 448 18 466 2 84 815 68 1953 1 2 0 97 6 4013 0 373 402 23 472 3 69 423 77 1818 1 1 0 98 7 1805 0 125 582 102 390 7 66 156 64 7188 1 2 0 97 April 1, 2026 at 06:56:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2362 251 114 0 1 0 0 2 0 0 0 100 1 0 0 7 15 1 4 0 1 0 0 300 0 0 0 100 2 0 0 42 8 0 2 0 0 4 0 0 0 0 0 100 3 0 0 0 15 1 4 0 0 4 0 0 0 0 0 100 4 0 0 0 125 5 141 1 1 0 0 1451 0 0 0 100 5 0 0 0 15 1 4 0 0 0 0 0 0 0 0 100 6 0 0 21 22 5 14 0 0 0 0 525 0 0 0 100 7 0 0 1 217 102 2 1 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2360 210 580 0 91 1691 1 0 0 2 0 98 1 0 0 0 220 37 643 1 75 1704 0 300 0 2 0 98 2 0 0 0 197 0 597 1 88 1492 2 1121 0 2 0 98 3 0 0 224 221 116 597 0 95 1468 0 0 0 2 0 98 4 0 0 0 261 125 591 2 101 1687 0 309 0 2 0 98 5 0 0 0 198 2 498 0 77 1425 0 0 0 2 0 98 6 0 0 21 138 4 486 1 84 1485 0 524 0 2 0 98 7 0 0 3 361 102 610 0 78 1555 0 300 0 2 0 98 April 1, 2026 at 06:56:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 243 2303 201 75 0 2 0 0 2 0 1 0 99 1 0 0 0 75 16 34 0 3 0 0 300 0 0 0 100 2 0 0 0 53 4 42 1 2 0 0 1138 0 0 0 100 3 0 0 0 147 34 106 0 4 1 0 1 0 0 0 100 4 0 0 0 45 3 4 0 0 0 0 294 0 0 0 100 5 0 0 0 46 3 6 0 0 0 0 0 0 0 0 100 6 0 0 21 46 4 10 0 0 0 0 525 0 0 0 100 7 0 0 1 247 102 8 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2303 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 9 1 2 0 0 0 0 300 0 0 0 100 2 0 0 0 10 1 32 1 0 0 0 1136 0 0 0 100 3 0 0 0 109 51 102 0 0 0 0 0 0 0 0 100 4 0 0 0 15 4 6 1 0 0 0 295 0 0 0 100 5 0 0 0 14 3 8 0 0 0 0 1 0 0 0 100 6 0 0 21 14 4 10 0 1 0 0 526 0 0 0 100 7 0 0 1 211 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11185 0 86 2340 201 1312 30 113 212 45 6253 4 4 0 93 1 1384 0 21 179 6 904 30 98 147 57 4323 2 1 0 97 2 450 0 1 161 1 348 5 46 168 26 5733 2 2 0 96 3 2300 0 6 333 26 846 16 73 159 49 3660 3 2 0 95 4 3127 0 12 475 24 1219 27 87 78 31 3495 2 1 0 97 5 891 0 3 533 22 1084 19 77 108 19 2934 1 1 0 98 6 595 0 26 164 7 279 6 38 117 22 3928 3 1 0 96 7 381 0 16 634 102 888 17 59 132 22 2734 1 1 0 98 April 1, 2026 at 06:56:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37 0 5 2318 207 117 0 1 0 0 11 0 0 0 100 1 3 0 0 21 2 176 1 4 0 0 630 0 0 0 100 2 0 0 7 13 2 36 0 2 0 0 1133 0 0 0 100 3 0 0 0 10 1 6 0 1 0 0 0 0 0 0 100 4 0 0 0 121 54 114 0 1 0 0 294 0 0 0 100 5 0 0 0 17 4 10 0 1 0 0 0 0 0 0 100 6 14 0 21 15 4 14 1 2 0 0 619 0 0 0 100 7 0 0 1 211 102 4 0 1 0 0 303 0 0 0 100 April 1, 2026 at 06:56:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 115 2341 209 533 1 76 1723 1 18 0 2 0 98 1 0 0 0 227 11 484 1 83 1611 1 300 0 2 0 98 2 0 0 0 213 5 653 4 82 1725 1 1133 0 2 0 98 3 0 0 7 255 116 528 0 83 1861 4 2 0 2 0 98 4 0 0 0 344 141 566 0 88 1949 1 294 0 2 0 98 5 0 0 0 229 15 593 1 81 1968 1 0 0 2 0 98 6 0 0 21 120 6 511 0 86 1743 1 529 0 2 0 98 7 0 0 4 308 102 621 1 87 1755 2 302 0 1 0 99 April 1, 2026 at 06:56:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2313 205 68 0 0 0 0 8 0 0 0 100 1 0 0 0 16 4 10 0 1 0 0 301 0 0 0 100 2 0 0 0 13 3 36 1 0 0 0 1129 0 0 0 100 3 0 0 0 12 1 6 0 1 0 0 0 0 0 0 100 4 0 0 0 120 31 114 3 2 0 0 294 0 0 0 100 5 0 0 0 18 1 14 0 2 0 0 1 0 0 0 100 6 0 0 21 61 27 56 0 1 0 0 525 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 11 0 61 2329 215 651 10 33 6 0 1301 1 1 0 98 1 49 0 0 323 15 572 2 26 6 1 1634 1 0 0 99 2 67 0 0 28 3 50 1 1 40 0 3751 2 1 0 97 3 81 0 0 113 2 716 3 19 3 0 1148 1 0 0 99 4 112 0 0 251 38 409 6 19 21 0 1964 2 1 0 98 5 32 0 0 54 1 71 1 5 26 0 1682 1 1 0 98 6 36 0 21 208 5 389 2 12 5 0 1461 1 0 0 99 7 39 0 1 407 103 427 4 20 6 0 1355 1 0 0 99 April 1, 2026 at 06:56:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2303 200 106 0 1 1 0 0 0 0 0 100 1 0 0 0 119 54 110 1 1 1 0 300 0 0 0 100 2 0 0 0 11 2 32 1 0 1 0 1130 0 0 0 100 3 0 0 0 18 4 10 0 0 1 0 14 0 0 0 100 4 0 0 0 32 10 26 0 0 1 0 315 0 0 0 100 5 0 0 0 30 9 18 0 1 1 0 1 0 0 0 100 6 0 0 21 20 5 22 1 0 1 0 541 0 0 0 100 7 0 0 7 215 102 4 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:56:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 809 0 5 2324 201 149 1 6 10 11 6543 1 1 0 98 1 744 0 116 131 52 161 0 8 7 12 482 0 0 0 99 2 109 0 0 57 2 106 1 12 9 17 1301 0 0 0 100 3 87 0 0 48 3 55 0 6 5 8 163 0 0 0 100 4 1912 0 0 63 9 66 2 8 3 7 642 0 1 0 99 5 15 0 0 37 0 32 0 4 4 5 67 0 0 0 100 6 8 0 21 40 4 43 0 6 2 2 604 0 0 0 100 7 5 0 1 235 102 30 0 5 6 2 376 0 0 0 100 April 1, 2026 at 06:56:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2317 202 473 1 66 1120 0 0 0 2 0 98 1 0 0 0 178 12 360 1 51 1105 1 300 0 1 0 99 2 0 0 0 212 41 470 2 50 1239 1 1217 0 1 0 99 3 0 0 0 162 77 302 1 52 1144 1 1 0 1 0 99 4 0 0 0 171 84 380 1 54 1242 0 303 0 1 0 99 5 0 0 0 110 0 323 1 54 1229 1 0 0 1 0 99 6 0 0 21 158 5 320 0 50 1113 0 527 0 1 0 99 7 0 0 4 387 102 518 1 65 1186 0 300 0 1 0 99 April 1, 2026 at 06:56:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 637 0 5 2346 202 11513 47 190 90 0 23261 8 6 0 87 1 142 0 0 593 4 9219 31 133 60 0 24445 7 5 0 88 2 70 0 0 215 40 9308 27 100 73 0 19920 6 5 0 90 3 604 0 0 1092 1 9242 15 89 81 0 20260 7 4 0 89 4 41 0 0 475 17 5826 15 55 39 0 14088 4 3 0 93 5 109 0 0 511 2 5137 15 51 79 0 16805 7 3 0 90 6 132 0 21 443 6 5713 10 54 41 0 14402 5 3 0 92 7 76 0 1 989 110 6330 14 37 59 0 16251 5 4 0 91 April 1, 2026 at 06:56:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 85 0 3 2354 211 19405 61 303 245 0 50120 16 11 0 73 1 102 0 0 92 16 18601 43 235 217 0 46295 16 10 0 75 2 67 0 0 71 9 18717 34 169 140 0 40603 12 9 0 80 3 73 0 0 69 14 20191 23 132 163 0 36875 11 8 0 81 4 67 0 0 72 19 16380 28 111 114 0 34079 11 7 0 81 5 97 0 0 46 11 12065 24 86 80 0 29170 8 6 0 86 6 41 0 21 52 14 16984 16 82 92 0 30426 12 7 0 81 7 65 0 4 258 112 16095 21 80 210 0 40256 12 7 0 81 April 1, 2026 at 06:56:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 113 53 108 0 1 0 0 302 0 0 0 100 2 0 0 0 12 2 32 2 0 0 0 1221 0 0 0 100 3 2 0 0 19 2 16 0 1 0 0 14 0 0 0 100 4 0 0 0 16 2 14 0 2 1 0 12 0 0 0 100 5 0 0 0 21 8 16 0 1 1 0 295 0 0 0 100 6 0 0 21 28 9 28 0 0 0 0 546 0 0 0 100 7 0 0 1 225 108 18 0 1 0 0 309 0 0 0 100 April 1, 2026 at 06:56:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2302 200 110 0 0 0 0 0 0 0 0 100 1 0 0 0 112 52 106 1 0 0 0 300 0 0 0 100 2 0 0 0 8 1 32 1 0 0 0 1218 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 6 0 0 21 15 4 12 0 0 0 0 525 0 0 0 100 7 0 0 1 221 108 14 0 0 0 0 309 0 0 0 100 April 1, 2026 at 06:56:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2322 200 443 1 53 778 0 0 0 1 0 99 1 0 0 0 152 11 302 0 45 888 3 302 0 1 0 99 2 0 0 0 208 44 361 0 41 711 0 1220 0 1 0 99 3 0 0 0 186 65 244 0 33 734 1 0 0 1 0 99 4 0 0 0 199 69 325 0 40 772 1 0 0 1 0 99 5 0 0 0 119 2 255 0 45 879 0 294 0 1 0 99 6 1 0 74 105 4 212 1 31 630 1 526 0 1 0 99 7 0 0 2 406 108 365 0 37 641 0 306 0 1 0 99 April 1, 2026 at 06:56:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 126 0 1 1 0 19 0 0 0 100 1 0 0 0 20 4 18 0 0 0 0 312 0 0 0 100 2 0 0 0 113 53 140 1 1 2 0 1244 0 0 0 100 3 0 0 0 6 0 2 0 0 3 0 3 0 0 0 100 4 0 0 0 12 3 8 0 0 0 0 2 0 0 0 100 5 0 0 0 13 3 8 1 0 1 0 297 0 0 0 100 6 0 0 21 15 4 12 1 1 0 0 527 0 0 0 100 7 0 0 1 222 107 16 1 1 0 0 311 0 0 0 100 April 1, 2026 at 06:56:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 61 2349 203 751 56 132 77 0 3193 2 1 0 97 1 53 0 0 297 18 636 30 112 61 7 3801 2 1 0 97 2 46 0 0 399 34 862 60 125 33 0 4584 1 1 0 98 3 28 0 14 267 8 516 32 77 76 0 3190 2 1 0 97 4 8 0 7 211 3 487 30 85 51 0 2890 2 1 0 98 5 33 0 11 174 3 585 41 97 71 0 3134 1 1 0 97 6 6 0 21 161 4 324 16 44 85 4 3725 2 1 0 97 7 2 0 1 431 103 501 35 86 47 0 3246 2 1 0 97 April 1, 2026 at 06:56:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2318 207 36 0 2 0 0 10 0 0 0 100 1 0 0 0 126 35 118 1 6 1 0 300 0 0 0 100 2 0 0 0 14 3 32 1 0 1 0 1136 0 0 0 100 3 0 0 0 54 6 48 0 4 1 0 17 0 0 0 100 4 0 0 0 91 22 84 0 3 1 0 12 0 0 0 100 5 0 0 7 26 11 16 0 2 1 0 295 0 0 0 100 6 3 0 21 21 5 20 0 0 1 0 539 0 0 0 100 7 0 0 7 214 102 4 0 0 1 0 300 0 0 0 100 April 1, 2026 at 06:56:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2321 209 34 0 0 0 0 9 0 0 0 100 1 0 0 0 130 16 108 0 2 0 0 300 0 0 0 100 2 0 0 0 28 1 40 1 1 0 0 1135 0 0 0 100 3 0 0 0 24 0 2 0 1 0 0 0 0 0 0 100 4 0 0 0 128 40 106 0 1 0 0 0 0 0 0 100 5 0 0 0 37 10 10 0 0 0 0 296 0 0 0 100 6 0 0 21 31 3 12 1 1 0 0 532 0 0 0 100 7 0 0 1 229 102 6 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:56:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2330 205 918 1 128 1835 0 9 0 2 0 98 1 0 0 0 148 4 582 0 87 1941 0 300 0 1 0 99 2 0 0 0 121 3 528 0 88 1783 1 1134 0 2 0 98 3 0 0 7 317 125 620 0 74 1801 1 0 0 2 0 98 4 0 0 0 265 135 593 1 98 1775 0 0 0 2 0 98 5 0 0 0 183 16 558 2 87 1823 0 294 0 2 0 98 6 0 0 21 171 3 517 2 70 1653 2 526 0 2 0 98 7 0 0 3 309 102 603 1 85 1743 3 300 0 2 0 98 April 1, 2026 at 06:56:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 75 2330 212 781 6 15 2 0 1721 2 1 0 97 1 0 0 0 260 2 529 6 20 14 0 2186 1 0 0 99 2 1 0 0 298 1 689 5 14 10 0 2573 1 1 0 99 3 13 0 1 362 3 701 6 17 26 0 2107 1 1 0 98 4 5 0 0 64 5 53 2 4 56 0 2587 2 1 0 98 5 0 0 0 85 28 76 3 6 39 0 2624 1 1 0 98 6 6 0 21 149 28 242 2 7 7 0 1174 0 0 0 99 7 8 0 1 413 102 446 3 9 28 0 1827 1 0 0 99 April 1, 2026 at 06:57:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2319 207 20 0 1 0 0 9 0 0 0 100 1 0 0 0 13 1 4 1 0 0 0 300 0 0 0 100 2 0 0 0 12 2 32 1 0 0 0 1134 0 0 0 100 3 0 0 0 9 1 2 0 0 1 0 0 0 0 0 100 4 0 0 0 119 17 117 0 4 1 0 1 0 0 0 100 5 0 0 0 47 19 44 0 2 0 0 294 0 0 0 100 6 0 0 21 77 25 72 0 3 0 0 525 0 0 0 100 7 0 0 0 209 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:57:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 4 2333 206 54 0 8 7 3 101 0 0 0 99 1 4 0 0 33 1 21 0 5 4 1 342 0 0 0 100 2 0 0 0 32 4 43 1 0 2 0 1156 0 0 0 100 3 3417 0 114 42 1 72 3 1 4 12 6890 2 1 0 97 4 159 0 0 164 45 204 0 18 8 16 169 0 0 0 100 5 51 0 3 166 20 168 0 13 9 11 433 0 0 0 100 6 10 0 21 61 7 74 0 10 7 6 659 0 0 0 100 7 9 0 2 241 103 38 0 5 6 6 397 0 0 0 100 April 1, 2026 at 06:57:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2317 207 24 0 0 0 0 10 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 2 0 0 0 8 1 32 1 0 0 0 1219 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 21 6 12 0 1 0 0 0 0 0 0 100 5 0 0 0 120 48 118 1 5 0 0 294 0 0 0 100 6 0 0 21 114 8 111 1 5 0 0 526 0 0 0 100 7 0 0 1 210 102 2 1 0 0 0 300 0 0 0 100 April 1, 2026 at 06:57:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 112 0 3 2361 211 6732 37 199 1293 1 16639 6 6 0 88 1 276 0 0 1144 20 9078 34 180 1369 0 25573 7 5 0 88 2 69 0 0 663 3 6877 19 150 1225 0 16378 5 5 0 91 3 27 0 0 1010 86 6713 14 119 1249 2 13232 5 4 0 91 4 414 0 0 786 91 5219 7 91 1271 0 11479 4 4 0 92 5 97 0 0 1072 20 6028 18 92 1299 0 14707 4 4 0 91 6 12 0 21 689 9 5641 6 74 1340 0 8588 3 3 0 93 7 119 0 3 694 103 3723 13 78 1299 0 10414 5 3 0 92 April 1, 2026 at 06:57:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 108 0 3 2377 210 18751 92 406 208 0 48570 17 11 0 72 1 13 0 0 120 14 23978 77 326 201 0 51658 15 11 0 74 2 27 0 0 86 12 20574 58 245 212 0 42977 14 9 0 76 3 21 0 0 73 10 20427 43 174 209 0 44633 15 9 0 75 4 4 0 0 82 23 17875 33 130 74 0 32700 10 7 0 83 5 40 0 0 66 13 12840 23 112 120 0 36726 12 8 0 81 6 9 0 7 66 12 18763 22 91 138 0 38753 12 8 0 80 7 90 0 18 270 113 18154 22 81 226 0 44674 13 8 0 78 April 1, 2026 at 06:57:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 202 6 0 2 0 0 1 0 0 0 100 1 0 0 0 116 1 110 0 2 0 0 300 0 0 0 100 2 0 0 3 9 1 4 0 1 0 0 1 0 0 0 100 3 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 4 0 0 0 113 54 106 0 0 0 0 0 0 0 0 100 5 0 0 0 27 10 52 1 0 1 0 1246 0 0 0 99 6 0 0 7 14 4 8 0 0 0 0 260 0 0 0 100 7 0 0 15 225 106 18 0 3 1 0 870 0 0 0 100 April 1, 2026 at 06:57:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2304 200 8 0 2 0 0 0 0 0 0 100 1 0 0 0 117 3 108 1 0 1 0 300 0 0 0 100 2 0 0 0 10 1 2 0 1 1 0 0 0 0 0 100 3 0 0 0 15 1 14 0 0 1 0 18 0 0 0 100 4 0 0 0 123 55 124 0 1 1 0 12 0 0 0 100 5 0 0 0 37 15 52 1 0 1 0 1231 0 0 0 99 6 1 0 7 22 6 18 0 0 1 0 277 0 0 0 100 7 0 0 21 223 104 18 1 0 1 0 859 0 0 0 100 April 1, 2026 at 06:57:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 2 0 0 0 0 0 0 0 0 100 1 0 0 0 111 2 106 0 0 0 0 300 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 0 112 54 106 0 0 0 0 0 0 0 0 100 5 0 0 0 23 8 48 1 0 0 0 1231 0 0 0 99 6 0 0 7 14 3 8 0 0 0 0 260 0 0 0 100 7 0 0 15 219 104 14 0 0 0 0 860 0 0 0 100 April 1, 2026 at 06:57:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 60 2380 225 1024 50 191 1051 0 3428 2 2 0 96 1 1 0 0 455 3 1106 41 167 848 0 3307 3 1 0 96 2 7 0 14 499 3 1144 62 193 924 0 3250 1 2 0 97 3 49 0 0 435 66 799 37 122 943 0 3285 2 2 0 96 4 44 0 7 393 80 659 31 110 847 1 3373 2 2 0 96 5 5 0 1 341 20 737 29 116 964 0 4079 2 2 0 96 6 0 0 17 357 3 805 49 144 879 1 3661 2 2 0 96 7 2 0 16 631 105 893 35 128 871 0 3810 2 2 0 97 April 1, 2026 at 06:57:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 112 0 0 0 0 1 0 0 0 100 1 0 0 0 12 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 10 1 2 0 1 0 0 0 0 0 0 100 3 0 0 0 10 2 2 0 0 0 0 0 0 0 0 100 4 0 0 0 17 5 8 0 1 0 0 0 0 0 0 100 5 0 0 7 67 28 90 1 2 0 0 1144 0 0 0 99 6 0 0 7 84 35 80 0 2 0 0 260 0 0 0 100 7 3 0 15 220 105 10 0 0 0 0 861 0 0 0 100 April 1, 2026 at 06:57:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2307 202 116 0 0 0 0 5 0 0 0 100 1 0 0 0 26 2 4 0 0 0 0 300 0 0 0 100 2 0 0 0 23 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 21 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 30 5 8 0 0 0 0 1 0 0 0 100 5 0 0 0 39 7 48 1 1 0 0 1144 0 0 0 100 6 0 0 7 129 53 110 0 2 0 0 260 0 0 0 100 7 0 0 15 227 104 6 1 0 0 0 860 0 0 0 100 April 1, 2026 at 06:57:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 14 3 6 1 0 0 0 301 0 0 0 100 2 0 0 7 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 16 3 14 0 0 0 0 18 0 0 0 100 4 0 0 0 17 4 14 0 0 0 0 12 0 0 0 100 5 0 0 0 29 13 50 0 0 0 0 1146 0 0 0 100 6 0 0 7 121 53 122 0 1 0 0 273 0 0 0 100 7 0 0 15 219 105 16 0 1 0 0 871 0 0 0 100 April 1, 2026 at 06:57:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 75 2312 203 970 3 16 1 0 1065 1 1 0 98 1 1 0 0 117 5 543 2 10 16 0 1869 1 0 0 99 2 3 0 0 254 6 519 2 8 25 0 2345 1 0 0 99 3 0 0 0 29 0 20 2 2 28 0 2433 1 1 0 98 4 2 0 0 182 5 413 3 6 7 0 1194 2 0 0 98 5 5 0 0 243 9 507 2 8 9 0 2429 1 0 0 99 6 1 0 7 105 41 94 2 3 24 1 2775 2 1 0 98 7 2 0 15 418 105 464 2 6 17 0 2403 1 0 0 99 April 1, 2026 at 06:57:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2326 206 665 0 112 2186 0 0 0 2 0 98 1 0 0 0 247 37 584 0 91 1952 1 301 0 2 0 98 2 0 0 0 256 12 798 0 117 2247 0 1 0 1 0 99 3 0 0 0 220 112 492 0 84 1922 1 9 0 2 0 98 4 0 0 0 206 108 477 0 84 2004 1 0 0 2 0 98 5 0 0 0 208 2 562 1 83 1976 0 1135 0 2 0 98 6 0 0 7 106 3 469 0 72 2030 0 260 0 2 0 98 7 0 0 17 365 104 478 1 79 1794 1 860 0 2 0 98 April 1, 2026 at 06:57:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 5 2320 200 150 0 10 5 4 54 0 0 0 99 1 6 0 0 48 7 40 0 4 4 5 367 0 0 0 100 2 3411 0 113 126 39 151 3 5 10 15 6907 2 1 0 97 3 155 0 0 88 18 114 0 12 9 15 176 0 0 0 100 4 44 0 3 43 3 61 0 7 2 12 128 0 0 0 100 5 23 0 0 41 2 87 1 7 10 10 1258 0 0 0 100 6 11 0 7 42 3 40 0 5 2 4 369 0 0 0 100 7 5 0 15 248 105 45 2 5 5 3 933 0 0 0 100 April 1, 2026 at 06:57:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 114 0 0 0 0 1 0 0 0 100 1 0 0 0 11 2 6 1 1 0 0 300 0 0 0 100 2 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 3 0 0 0 123 57 116 0 1 0 0 9 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 10 2 36 0 0 1 0 1221 0 0 0 100 6 0 0 7 14 4 10 0 0 0 0 261 0 0 0 100 7 0 0 15 216 106 10 0 0 0 0 860 0 0 0 100 April 1, 2026 at 06:57:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 42 0 5 2316 202 6056 16 82 102 0 14778 4 4 0 92 1 71 0 0 553 4 6016 20 63 74 0 15500 4 3 0 93 2 450 0 0 634 2 2436 9 44 25 0 7267 3 2 0 96 3 50 0 0 340 50 5190 6 50 24 0 15606 4 3 0 93 4 2 0 0 239 6 5856 6 29 20 0 7998 3 2 0 95 5 128 0 0 666 13 3459 13 19 79 0 11547 5 2 0 93 6 43 0 7 114 6 2606 6 26 29 0 7625 3 2 0 96 7 31 0 15 656 105 2642 7 20 16 0 8522 2 2 0 96 April 1, 2026 at 06:57:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 34 0 3 2412 212 26147 127 515 408 0 64330 21 13 0 66 1 24 0 0 137 15 23297 111 449 252 0 49556 17 11 0 71 2 25 0 0 100 9 26622 76 304 322 0 53318 17 11 0 73 3 54 0 0 74 5 21549 59 238 241 0 45266 14 10 0 76 4 78 0 0 78 13 20804 40 169 148 0 40677 13 9 0 79 5 65 0 0 76 16 14417 26 123 200 0 35571 12 7 0 81 6 58 0 7 61 13 16396 29 117 184 0 42642 14 9 0 78 7 40 0 17 299 128 14619 35 129 166 0 37909 12 8 0 80 April 1, 2026 at 06:57:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2330 203 447 0 56 1016 0 300 0 2 0 98 1 0 0 0 142 17 395 0 57 872 0 0 0 1 0 99 2 0 0 0 204 33 386 0 52 1051 0 300 0 1 0 99 3 0 0 23 203 79 425 5 52 874 0 0 0 2 0 98 4 0 0 0 211 80 292 0 53 1069 0 0 0 1 0 99 5 0 0 0 137 0 327 0 54 908 0 0 0 1 0 99 6 0 0 7 137 7 289 1 42 855 0 1482 0 1 0 99 7 0 0 16 323 109 327 1 41 975 0 569 0 1 0 99 April 1, 2026 at 06:57:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 0 0 0 0 300 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 300 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 10 1 4 0 0 0 0 2 0 0 0 100 6 0 0 7 16 4 42 0 1 0 0 1481 0 0 0 100 7 0 0 15 221 109 16 0 0 0 0 568 0 0 0 100 April 1, 2026 at 06:57:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 75 2359 205 921 60 169 58 0 3689 2 1 0 97 1 4 0 0 309 1 672 50 122 48 1 3274 3 1 0 96 2 0 0 0 298 42 562 15 70 93 2 3586 2 1 0 98 3 52 0 0 162 1 343 20 55 100 0 3396 2 1 0 97 4 0 0 0 318 10 700 48 113 57 0 3212 1 1 0 98 5 1 0 9 200 0 478 32 85 83 0 2971 2 1 0 97 6 49 0 14 143 4 325 10 46 113 4 4751 2 1 0 97 7 1 0 15 573 110 789 45 104 29 2 3520 1 1 0 98 April 1, 2026 at 06:57:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2357 252 123 0 1 1 0 303 0 0 0 100 1 0 0 0 17 4 10 0 0 0 0 8 0 0 0 100 2 0 0 0 11 1 4 0 0 1 0 303 0 0 0 100 3 0 0 0 32 11 28 0 0 0 0 30 0 0 0 100 4 1 0 0 122 4 122 0 0 0 0 19 0 0 0 100 5 0 0 0 24 10 14 0 1 0 0 2 0 0 0 100 6 0 0 7 28 5 58 1 0 0 0 1413 0 0 0 100 7 3 0 22 218 105 16 0 1 0 0 561 0 0 0 100 April 1, 2026 at 06:57:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2356 252 119 1 0 0 0 300 0 1 0 99 1 0 0 0 38 8 16 0 0 0 0 10 0 0 0 100 2 0 0 0 24 1 2 1 0 0 0 300 0 0 0 100 3 0 0 0 23 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 126 3 104 0 0 0 0 0 0 0 0 100 5 0 0 0 22 0 2 0 0 0 0 0 0 0 0 100 6 0 0 7 37 6 46 1 0 0 0 1399 0 0 0 100 7 0 0 15 228 103 6 2 0 0 0 560 0 0 0 100 April 1, 2026 at 06:57:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 10 2331 213 726 0 112 1941 0 300 0 2 0 98 1 0 0 0 167 7 479 0 75 1651 0 9 0 2 0 98 2 0 0 0 163 2 476 0 73 1834 2 301 0 2 0 98 3 0 0 0 198 114 515 0 74 2012 0 0 0 2 0 98 4 0 0 0 225 121 554 0 78 1796 0 0 0 2 0 98 5 0 0 0 115 6 520 0 83 1795 1 2 0 2 0 98 6 0 0 7 178 35 566 0 74 1619 1 1394 0 2 0 98 7 0 0 17 398 103 757 0 92 1485 0 561 0 1 0 99 April 1, 2026 at 06:57:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 75 2307 202 630 2 3 31 0 2184 1 1 0 98 1 0 0 0 256 8 538 1 2 17 0 1623 2 0 0 97 2 0 0 0 46 8 38 2 3 59 0 3481 2 1 0 97 3 0 0 0 268 0 585 2 4 24 0 1645 1 0 0 99 4 0 0 0 229 3 520 0 1 38 0 1595 1 0 0 99 5 1 0 0 40 1 38 7 5 50 0 2953 2 1 0 97 6 9 0 7 282 49 510 3 2 17 0 2612 1 0 0 99 7 0 0 15 616 105 839 2 4 0 0 1407 1 0 0 99 April 1, 2026 at 06:57:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2320 209 128 0 1 0 0 310 0 0 0 100 1 0 0 0 11 2 2 0 0 0 0 0 0 0 0 100 2 0 0 0 109 51 102 0 0 0 0 300 0 0 0 100 3 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 4 0 0 0 12 4 4 0 0 0 0 0 0 0 0 100 5 0 0 0 12 3 6 0 0 0 0 3 0 0 0 100 6 0 0 7 17 4 40 1 0 0 0 1393 0 0 0 100 7 0 0 15 210 103 6 0 1 0 0 561 0 0 0 100 April 1, 2026 at 06:57:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 87 0 8 2335 208 221 0 16 14 15 449 0 1 0 99 1 10 0 0 43 2 45 0 7 3 3 72 0 0 0 100 2 782 0 0 128 45 122 1 6 4 6 6805 1 1 0 98 3 12 0 0 59 8 50 0 4 5 1 108 0 0 0 100 4 4 0 0 40 4 28 0 4 6 2 54 0 0 0 100 5 22 0 0 58 12 43 0 2 2 3 70 0 0 0 100 6 2644 0 121 55 7 110 3 5 8 15 1852 1 1 0 98 7 111 0 21 257 103 73 1 8 6 14 725 0 0 0 100 April 1, 2026 at 06:57:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2320 208 130 1 0 0 0 309 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 3 0 0 0 107 51 102 0 0 0 0 0 0 0 0 100 4 0 0 0 12 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 15 1 14 0 0 0 0 2 0 0 0 100 6 0 0 7 19 4 42 1 0 1 0 1480 0 0 0 100 7 0 0 15 213 104 8 1 0 0 0 560 0 0 0 100 April 1, 2026 at 06:57:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 110 0 3 2349 212 3924 14 119 1247 0 6642 3 4 0 94 1 437 0 0 889 33 2764 16 101 1270 0 6147 2 2 0 95 2 92 0 0 654 3 2755 10 79 1182 0 5383 1 2 0 96 3 3 0 0 1089 84 3140 9 85 1296 0 11296 2 2 0 95 4 70 0 0 1023 74 2524 7 65 1308 1 6311 2 3 0 95 5 9 0 0 253 1 1984 6 68 1249 0 4197 2 2 0 96 6 5 0 7 229 4 1611 8 67 984 1 6959 4 2 0 94 7 14 0 18 992 104 1875 3 70 1135 0 4277 1 2 0 97 April 1, 2026 at 06:57:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37 0 2 2432 211 30869 138 536 394 0 69503 23 15 0 63 1 14 0 0 159 14 27724 111 445 299 0 58804 20 12 0 68 2 65 0 0 125 8 28633 91 355 187 0 51080 18 12 0 71 3 23 0 0 90 13 22042 76 264 228 0 53331 18 11 0 71 4 40 0 0 84 20 14980 44 176 168 0 41892 13 8 0 79 5 84 0 0 65 8 19711 30 125 201 0 46364 15 9 0 76 6 5 0 0 81 19 18842 31 129 163 0 43914 13 8 0 79 7 60 0 26 267 114 17221 34 110 160 0 41837 12 8 0 80 April 1, 2026 at 06:57:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2305 202 104 0 4 0 0 0 0 0 0 100 1 0 0 0 20 4 15 0 2 0 0 0 0 0 0 100 2 0 0 0 21 7 16 0 3 0 0 300 0 0 0 100 3 0 0 0 90 41 86 1 2 0 0 300 0 0 0 100 4 0 0 0 15 5 6 0 0 0 0 1 0 0 0 100 5 0 0 0 28 8 24 0 0 0 0 11 0 0 0 100 6 0 0 0 13 1 6 0 0 0 0 0 0 0 0 100 7 0 0 21 215 106 40 2 0 1 0 2038 0 0 0 99 April 1, 2026 at 06:57:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 89 2347 201 937 52 181 1389 1 3159 2 3 0 95 1 5 0 0 335 1 931 45 171 1526 2 3033 1 3 0 96 2 49 0 0 214 1 736 51 135 1543 2 3509 2 2 0 96 3 0 0 0 468 95 1005 72 194 1240 3 3463 3 3 0 95 4 1 0 10 353 49 743 42 137 1397 0 3104 1 3 0 96 5 44 0 0 233 14 517 27 93 1321 2 3284 2 3 0 95 6 9 0 14 252 3 883 47 167 1459 2 3093 1 3 0 96 7 1 0 29 514 107 773 45 115 1467 3 5379 2 3 0 95 April 1, 2026 at 06:57:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2312 203 452 0 46 777 2 0 0 1 0 99 1 0 0 0 113 46 482 0 52 823 1 0 0 0 0 100 2 0 0 0 27 9 395 0 44 922 1 309 0 0 0 99 3 0 0 0 83 70 307 0 45 705 2 300 0 0 0 99 4 0 0 0 81 72 333 0 36 823 0 0 0 0 0 100 5 0 0 0 17 3 315 0 34 825 0 0 0 1 0 99 6 0 0 0 27 5 326 0 51 768 1 0 0 1 0 99 7 3 0 22 232 109 379 1 43 716 1 1959 0 1 0 99 April 1, 2026 at 06:57:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2304 201 120 1 0 0 0 3 0 0 0 100 1 0 0 0 127 50 106 0 2 0 0 3 0 0 0 100 2 0 0 0 46 11 22 0 0 0 0 318 0 0 0 100 3 0 0 0 24 1 6 0 2 0 0 301 0 0 0 100 4 0 0 0 30 5 8 0 0 0 0 4 0 0 0 100 5 0 0 0 28 2 8 0 1 1 0 2 0 0 0 100 6 3 0 0 35 1 18 0 1 0 0 3 0 0 0 100 7 0 0 22 235 108 44 0 0 0 0 1956 0 0 0 100 April 1, 2026 at 06:57:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2307 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 110 51 104 0 0 0 0 1 0 0 0 100 2 0 0 0 27 10 20 1 0 0 0 333 0 0 0 100 3 0 0 0 9 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 8 1 4 0 1 0 0 1 0 0 0 100 6 0 0 7 14 1 8 0 0 0 0 0 0 0 0 100 7 0 0 21 221 108 44 3 0 1 0 1952 0 0 0 100 April 1, 2026 at 06:57:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 61 2305 202 152 3 0 53 0 3155 2 1 0 97 1 0 0 0 240 49 686 0 8 37 0 2454 1 0 0 99 2 1 0 0 353 8 725 6 10 19 0 1912 3 0 0 97 3 1 0 0 366 2 775 5 8 14 0 1589 1 0 0 99 4 1 0 0 217 6 438 3 6 11 0 950 1 0 0 99 5 0 0 0 133 1 232 0 2 12 0 760 0 0 0 100 6 16 0 0 40 1 45 3 3 39 0 3015 2 1 0 97 7 0 0 22 543 110 728 5 9 19 0 3952 1 1 0 98 April 1, 2026 at 06:57:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2319 205 402 0 68 1291 0 5 0 1 0 99 1 0 0 0 194 46 343 0 57 1081 0 0 0 2 0 98 2 0 0 0 114 4 280 0 66 1176 0 300 0 1 0 99 3 0 0 0 165 57 252 1 50 1088 0 310 0 1 0 98 4 0 0 0 165 51 267 0 56 1119 0 12 0 1 0 99 5 0 0 0 111 10 228 0 55 1117 0 1 0 1 0 99 6 0 0 0 116 2 255 0 45 1019 2 26 0 1 0 99 7 0 0 21 384 108 428 0 66 927 1 1959 0 1 0 98 April 1, 2026 at 06:57:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 726 0 118 2332 210 398 1 38 489 7 169 0 1 0 99 1 2019 0 0 195 44 345 2 35 489 13 437 0 1 0 99 2 37 0 2 49 4 287 0 37 498 7 392 0 0 0 100 3 9 0 0 92 46 246 0 34 440 9 90 0 0 0 100 4 788 0 0 124 48 225 1 26 455 9 6522 1 1 0 98 5 13 0 0 93 1 231 0 26 416 5 115 0 0 0 100 6 24 0 0 121 1 247 0 25 440 5 57 0 0 0 100 7 48 0 21 273 111 376 1 20 433 4 2306 0 1 0 99 April 1, 2026 at 06:57:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2316 208 126 0 0 0 0 10 0 0 0 100 1 0 0 0 14 0 14 0 0 0 0 0 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 300 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 4 0 1 0 0 0 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 12 1 6 0 0 0 0 0 0 0 0 100 7 0 0 22 222 109 46 2 0 0 0 2340 0 0 0 99 April 1, 2026 at 06:57:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 65 0 5 2321 208 410 4 12 1 0 1028 0 1 0 99 1 24 0 0 371 1 955 1 7 1 0 7186 1 0 0 98 2 85 0 0 142 52 167 0 3 0 0 485 0 0 0 100 3 2 0 0 181 0 440 0 3 4 0 1357 0 0 0 99 4 473 0 0 107 2 209 3 7 13 0 1530 1 0 0 99 5 81 0 0 26 1 39 3 8 41 0 1806 2 0 0 97 6 3 0 0 250 1 482 0 2 10 0 1126 0 0 0 99 7 0 0 22 470 110 542 1 5 7 0 3721 0 1 0 99 April 1, 2026 at 06:57:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 63 0 4 2408 214 24382 138 504 315 0 64295 22 14 0 64 1 81 0 0 453 9 25351 108 403 250 0 57791 20 12 0 68 2 138 0 14 744 18 29271 83 298 314 0 60696 18 13 0 69 3 31 0 0 170 10 22412 64 227 229 0 51323 17 11 0 72 4 25 0 0 323 14 22881 42 160 256 0 48039 16 10 0 74 5 47 0 0 738 20 24811 42 132 167 0 47696 14 10 0 75 6 26 0 0 633 8 19660 35 110 172 0 43427 15 9 0 76 7 116 0 9 311 114 13514 22 106 193 0 39818 11 7 0 82 April 1, 2026 at 06:57:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 47 2369 210 2622 81 237 1103 0 7512 3 3 0 94 1 14 0 14 346 36 2591 99 235 945 1 6771 3 3 0 94 2 7 0 14 327 5 1878 61 153 953 2 6927 3 2 0 95 3 1 0 45 479 48 2820 85 231 1088 5 7693 3 2 0 95 4 0 0 7 318 50 3383 95 217 1011 1 6338 3 2 0 95 5 52 0 10 348 12 2251 49 140 959 1 6134 2 2 0 96 6 40 0 0 309 4 1675 60 148 1006 2 6202 3 3 0 94 7 0 0 8 455 120 1181 43 108 955 0 6953 2 2 0 95 April 1, 2026 at 06:57:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2361 251 181 0 10 23 0 15 0 0 0 100 1 0 0 0 96 1 158 0 7 24 0 6 0 0 0 100 2 3 0 14 26 4 80 1 4 28 0 866 0 0 0 100 3 0 0 0 72 23 72 0 5 18 0 0 0 0 0 100 4 0 0 0 50 31 83 0 4 34 0 11 0 0 0 100 5 0 0 7 10 1 58 0 10 27 0 1 0 0 0 100 6 0 0 0 15 1 25 1 4 9 0 12 1 0 0 99 7 0 0 8 253 107 104 1 4 17 0 1713 0 0 0 100 April 1, 2026 at 06:57:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 118 2359 253 119 0 2 0 0 7 0 0 0 100 1 0 0 0 124 0 102 0 0 0 0 0 0 0 0 100 2 0 0 14 33 5 12 2 0 0 0 867 0 0 0 100 3 0 0 0 22 0 2 0 0 0 0 2 0 0 0 100 4 0 0 0 36 8 14 0 0 0 0 9 0 0 0 100 5 0 0 0 27 1 4 0 1 0 0 2 0 0 0 100 6 0 0 0 25 0 2 0 0 0 0 0 0 0 0 100 7 0 0 7 239 107 48 0 3 0 0 1689 0 0 0 100 April 1, 2026 at 06:57:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2363 255 120 0 2 0 0 7 0 0 0 100 1 0 0 7 117 4 114 0 1 0 0 5 0 0 0 100 2 0 0 14 16 5 12 0 0 0 0 867 0 0 0 100 3 0 0 0 14 0 12 0 0 0 0 3 0 0 0 100 4 0 0 0 25 9 18 0 0 0 0 18 0 0 0 100 5 0 0 0 9 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 11 0 8 0 1 0 0 4 0 0 0 100 7 0 0 8 223 106 42 1 1 0 0 1690 0 0 0 100 April 1, 2026 at 06:57:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2359 253 129 0 4 0 0 43 0 0 0 100 1 0 0 0 110 1 104 0 1 0 0 0 0 0 0 100 2 0 0 14 16 4 15 0 3 0 0 867 0 0 0 100 3 0 0 0 15 0 17 0 1 0 0 83 0 0 0 100 4 0 0 0 29 9 29 0 0 2 0 51 0 0 0 100 5 0 0 0 9 1 6 0 0 0 0 18 0 0 0 100 6 0 0 0 13 0 13 0 0 3 0 29 0 0 0 100 7 0 0 8 228 106 61 2 0 0 0 1675 0 0 0 99 April 1, 2026 at 06:57:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 77 2332 215 961 3 79 1487 0 2606 1 2 0 97 1 0 0 0 365 12 725 1 67 1240 0 1573 1 2 0 97 2 0 0 14 481 42 960 1 59 1156 0 2568 1 2 0 97 3 0 0 0 311 47 610 2 59 1258 0 1575 1 2 0 97 4 0 0 0 305 50 623 0 64 1261 0 1136 0 2 0 98 5 0 0 0 463 8 949 3 52 1039 1 885 2 2 0 96 6 1 0 0 128 2 259 2 50 1190 0 3063 2 2 0 96 7 0 0 14 429 105 568 3 78 1178 0 4179 2 2 0 96 April 1, 2026 at 06:57:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2312 202 383 1 36 805 1 294 0 1 0 99 1 0 0 0 14 0 297 1 39 688 1 0 0 0 0 100 2 0 0 14 218 62 459 1 41 653 0 874 0 1 0 99 3 0 0 0 102 75 321 1 46 746 0 0 0 0 0 100 4 0 0 0 131 79 293 2 36 784 0 0 0 0 0 100 5 0 0 0 87 1 281 1 30 719 0 2 0 0 0 100 6 0 0 0 92 0 273 1 33 776 0 0 0 1 0 99 7 0 0 8 218 105 542 2 36 633 0 1395 0 1 0 99 April 1, 2026 at 06:57:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 55 0 3 2326 202 171 0 10 5 9 400 0 1 0 99 1 5 0 0 39 2 21 0 3 2 2 61 0 0 0 100 2 2634 0 127 60 12 81 5 4 9 12 1333 1 1 0 99 3 89 0 0 158 51 176 0 12 18 7 166 0 0 0 100 4 28 0 4 37 2 33 0 5 12 2 96 0 0 0 100 5 16 0 0 41 0 48 0 8 6 7 97 0 0 0 100 6 53 0 0 43 1 46 0 6 3 7 84 0 0 0 100 7 778 0 10 243 105 72 1 7 2 2 7975 1 1 0 98 April 1, 2026 at 06:57:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2307 202 116 0 0 0 0 294 0 0 0 100 1 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 2 0 0 14 23 9 18 0 0 0 0 874 0 0 0 100 3 0 0 0 110 51 102 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 4 0 1 0 0 2 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 7 215 105 38 1 0 1 0 1477 0 0 0 100 April 1, 2026 at 06:57:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 464 0 14 2405 208 28285 140 470 290 0 64825 21 14 0 65 1 146 0 0 666 5 25765 104 375 253 0 54242 18 12 0 70 2 38 0 0 669 20 25059 64 257 165 0 46241 14 10 0 76 3 247 0 0 204 16 23077 56 195 268 0 52428 19 11 0 70 4 44 0 0 604 9 14138 28 129 246 0 46868 14 9 0 77 5 101 0 14 243 15 21296 38 124 184 0 41828 15 10 0 76 6 46 0 0 360 17 18462 37 131 241 0 42059 13 8 0 78 7 54 0 7 650 108 16594 34 107 205 0 50364 14 9 0 78 April 1, 2026 at 06:57:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 13 2323 205 1931 13 85 958 0 2810 1 2 0 97 1 1 0 0 213 43 1516 9 77 938 0 2863 1 1 0 98 2 6 0 0 135 9 1718 6 59 919 0 3172 1 2 0 98 3 0 0 0 166 54 1079 3 62 870 0 1774 1 1 0 98 4 9 0 0 154 50 1900 2 65 916 0 3761 1 2 0 97 5 0 0 14 122 10 785 1 57 914 0 2284 1 1 0 98 6 2 0 0 135 6 1533 8 58 871 0 2916 1 2 0 98 7 6 0 0 362 113 1076 2 62 830 0 3766 1 2 0 97 April 1, 2026 at 06:57:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2306 202 187 0 6 41 0 260 0 0 0 100 1 0 0 0 138 53 156 0 4 26 0 295 0 0 0 100 2 0 0 0 25 6 58 0 1 26 0 308 0 0 0 100 3 0 0 0 53 23 60 0 4 28 0 300 0 0 0 100 4 0 0 0 36 20 79 0 4 43 0 0 0 0 0 100 5 0 0 14 20 1 64 0 4 41 0 265 0 0 0 100 6 0 0 0 31 0 50 0 5 17 0 0 0 0 0 100 7 0 0 0 225 103 92 1 2 28 0 1220 0 0 0 100 April 1, 2026 at 06:57:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2308 202 116 0 2 0 0 263 0 0 0 100 1 0 0 0 113 53 110 0 2 0 0 329 0 0 0 100 2 0 0 0 26 10 22 0 0 0 0 314 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 4 0 1 0 0 0 0 0 0 100 5 0 0 14 8 2 4 0 0 0 0 268 0 0 0 100 6 0 0 0 10 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 221 103 43 2 2 1 0 1210 0 0 0 100 April 1, 2026 at 06:57:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2306 202 128 0 1 0 0 260 0 0 0 100 1 0 0 0 113 54 138 0 0 0 0 1515 0 0 0 100 2 0 0 0 24 9 18 1 0 0 0 331 0 0 0 100 3 0 0 0 12 3 6 1 0 0 0 300 0 0 0 100 4 0 0 0 8 2 4 0 1 0 0 0 0 0 0 100 5 0 0 14 8 2 4 1 0 0 0 267 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 213 102 4 0 0 1 0 0 0 0 0 100 April 1, 2026 at 06:57:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2310 203 116 0 0 0 0 261 0 0 0 100 1 0 0 0 113 53 136 2 0 0 0 1514 0 0 0 100 2 0 0 0 21 8 16 0 0 0 0 307 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 7 2 4 0 0 0 0 268 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:57:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2306 202 126 0 0 0 0 260 0 0 0 100 1 0 0 0 124 56 152 1 1 1 0 1519 0 0 0 100 2 0 0 0 24 9 18 0 0 2 0 309 0 0 0 100 3 0 0 0 13 4 6 0 0 1 0 300 0 0 0 100 4 0 0 0 15 3 12 0 0 1 0 12 0 0 0 100 5 0 0 14 19 9 8 0 0 1 0 267 0 0 0 100 6 0 0 0 15 1 16 0 0 1 0 23 0 0 0 100 7 3 0 1 217 103 12 0 0 3 0 5 0 0 0 100 April 1, 2026 at 06:57:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2304 202 116 0 0 0 0 260 0 0 0 100 1 0 0 0 118 53 140 1 0 0 0 1513 0 0 0 100 2 0 0 0 19 7 14 0 0 0 0 309 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 5 0 0 14 7 2 4 0 0 0 0 268 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:57:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2308 202 116 0 0 0 0 260 0 0 0 100 1 0 0 0 111 53 136 0 0 0 0 1511 0 0 0 100 2 0 0 0 22 8 18 1 1 0 0 311 0 0 0 100 3 0 0 0 15 4 10 1 0 0 0 300 0 0 0 100 4 0 0 0 9 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 6 1 2 1 0 0 0 265 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 0 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:57:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2306 202 118 0 1 1 0 260 0 0 0 100 1 0 0 0 70 30 90 2 0 0 0 1511 0 0 0 100 2 0 0 0 69 31 66 0 2 0 0 308 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 7 2 4 0 0 0 0 268 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2306 202 114 0 0 0 0 260 0 0 0 100 1 0 0 0 17 5 40 1 0 0 0 1513 0 0 0 100 2 0 0 0 121 57 116 0 1 1 0 309 0 0 0 100 3 0 0 0 12 3 8 0 1 0 0 300 0 0 0 100 4 0 0 0 9 2 4 0 1 0 0 0 0 0 0 100 5 0 0 14 7 2 4 0 0 0 0 267 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 494 0 30 2413 209 24205 127 601 989 0 63243 21 15 0 64 1 65 0 0 252 14 24500 114 476 881 0 56925 19 13 0 68 2 32 0 0 894 21 23357 67 361 1019 0 53271 17 12 0 71 3 233 0 0 348 58 25014 63 333 954 0 55154 17 12 0 71 4 16 0 0 377 63 20374 60 263 962 1 46868 15 10 0 75 5 98 0 14 597 26 16959 47 195 739 1 40007 13 8 0 79 6 54 0 0 216 10 16323 37 183 846 1 36873 11 8 0 80 7 98 0 3 751 108 20755 42 176 874 1 41003 14 10 0 76 April 1, 2026 at 06:58:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 10 2329 216 3749 10 69 61 0 9911 3 2 0 94 1 4 0 0 100 36 4462 9 47 65 0 10748 4 2 0 94 2 0 0 0 23 7 3975 5 44 18 0 6391 2 1 0 97 3 0 0 0 39 21 5037 6 26 57 0 9697 3 2 0 95 4 4 0 0 24 14 1852 2 22 26 0 5790 1 1 0 97 5 1 0 14 15 5 2561 3 21 41 0 8301 2 2 0 96 6 5 0 0 17 3 2463 3 26 61 0 6332 2 2 0 96 7 5 0 4 244 108 3854 7 28 42 0 7260 2 2 0 96 April 1, 2026 at 06:58:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2321 210 132 0 0 0 0 267 0 0 0 100 1 0 0 0 112 53 136 1 0 0 0 1517 0 0 0 100 2 0 0 0 8 1 2 0 0 0 0 1 0 0 0 100 3 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 4 0 0 0 10 2 4 0 1 0 0 0 0 0 0 100 5 0 0 14 16 4 16 1 1 0 0 568 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2321 209 130 0 0 0 0 269 0 0 0 100 1 0 0 0 115 54 138 2 0 0 0 1516 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 11 4 8 0 0 0 0 567 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2319 209 128 0 0 0 0 269 0 0 0 100 1 0 0 0 69 32 92 0 0 0 0 1516 0 0 0 100 2 0 0 0 52 23 48 0 1 0 0 1 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 16 4 14 0 0 0 0 586 0 0 0 100 6 0 0 0 12 0 12 0 2 0 0 0 0 0 0 100 7 0 0 1 213 103 8 0 0 0 0 9 0 0 0 100 April 1, 2026 at 06:58:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2330 212 320 0 26 343 0 278 0 1 0 99 1 0 0 0 96 6 200 2 17 253 0 1531 0 1 0 99 2 0 0 0 201 51 299 0 23 394 0 25 0 0 0 100 3 0 0 0 112 41 184 0 20 353 0 302 0 0 0 99 4 0 0 0 119 43 168 0 18 239 0 0 0 0 0 100 5 0 0 14 114 15 196 1 24 338 0 582 0 0 0 99 6 0 0 0 92 1 170 0 16 247 0 0 0 0 0 100 7 0 0 7 292 102 168 0 14 248 0 3 0 0 0 100 April 1, 2026 at 06:58:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2319 209 130 0 0 0 0 266 0 0 0 100 1 0 0 0 14 3 36 1 0 1 0 1515 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 12 4 10 1 1 0 0 567 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2319 209 148 0 1 0 0 270 0 0 0 100 1 0 0 0 12 3 38 1 1 0 0 1515 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 9 3 6 0 0 0 0 567 0 0 0 100 6 0 0 0 10 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2317 209 130 0 0 0 0 269 0 0 0 100 1 0 0 0 16 4 40 2 1 1 0 1514 0 0 0 100 2 0 0 0 106 50 102 0 1 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 11 4 8 0 0 0 0 567 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2319 209 130 0 0 0 0 269 0 0 0 100 1 0 0 0 14 4 38 1 0 0 0 1518 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 1 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 12 4 8 1 0 0 0 568 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3241 0 493 2967 219 1967 749 136 170 15 8660 22 4 0 74 1 2309 0 0 780 7 1627 661 111 144 7 8015 23 3 0 74 2 2925 0 0 980 16 2357 965 126 183 11 10010 22 4 0 73 3 9158 0 101 786 22 1883 743 152 247 9 8148 21 5 0 74 4 4573 0 0 917 28 2280 960 121 284 15 6228 22 3 0 74 5 3790 0 227 783 15 1670 739 96 153 10 6475 23 3 0 74 6 2568 0 0 778 5 1598 726 65 136 5 6337 24 3 0 74 7 1626 0 4 876 104 1342 616 79 110 7 5245 24 2 0 74 April 1, 2026 at 06:58:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2307 203 118 0 0 1 0 260 0 0 0 100 1 0 0 0 25 8 46 1 0 1 0 1539 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 4 0 1 0 0 300 0 0 0 100 4 0 0 0 108 52 102 0 0 0 0 0 0 0 0 100 5 2 0 14 16 3 16 0 0 0 0 580 0 0 0 100 6 0 0 0 10 1 2 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2305 203 116 0 0 0 0 260 0 0 0 100 1 0 0 0 23 8 46 2 0 0 0 1537 0 0 0 100 2 0 0 0 11 3 6 0 0 0 0 2 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 108 52 102 0 0 0 0 0 0 0 0 100 5 0 0 14 11 4 8 0 0 0 0 567 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2309 203 116 0 0 0 0 260 0 0 0 100 1 0 0 0 24 9 48 1 0 0 0 1539 0 0 0 100 2 0 0 0 11 3 6 0 0 0 0 22 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 108 52 102 0 0 0 0 0 0 0 0 100 5 0 0 14 13 4 10 1 0 0 0 568 0 0 0 100 6 0 0 0 10 0 8 0 1 1 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 96 2335 205 1082 28 90 30 0 2364 1 1 0 98 1 7 0 0 97 6 217 7 19 92 0 5688 5 1 0 94 2 2 0 9 40 1 48 4 7 123 4 4273 5 2 0 94 3 65 0 0 33 1 28 5 7 109 3 4577 5 1 0 94 4 0 0 0 417 57 781 16 55 42 0 2182 1 0 0 98 5 2 0 14 316 4 644 17 46 35 0 2431 1 0 0 99 6 0 0 0 324 1 674 25 54 28 0 1882 3 0 0 97 7 0 0 8 503 102 648 21 55 32 0 2134 1 0 0 99 April 1, 2026 at 06:58:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2332 209 554 0 76 1420 0 277 0 2 0 98 1 0 0 0 131 3 313 1 54 1362 0 1457 0 1 0 99 2 0 0 0 103 4 231 0 54 1302 0 19 0 2 0 98 3 0 0 0 140 46 229 0 42 1336 3 300 0 2 0 98 4 0 0 0 245 98 327 0 48 1428 2 15 0 2 0 98 5 1 0 14 113 14 237 0 56 1489 1 583 0 2 0 98 6 0 0 2 95 1 228 0 48 1380 4 1 0 2 0 98 7 0 0 7 310 102 244 0 49 1334 1 0 0 2 0 98 April 1, 2026 at 06:58:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 124 2333 216 401 0 23 322 1 271 0 1 0 99 1 0 0 0 96 22 245 1 22 340 1 1433 0 1 0 99 2 0 0 0 97 22 195 0 19 377 1 0 0 0 0 100 3 0 0 0 97 39 160 0 22 343 0 300 0 0 0 100 4 0 0 0 131 45 159 0 22 359 0 0 0 0 0 100 5 0 0 14 92 4 149 0 11 360 1 569 0 0 0 100 6 0 0 0 32 0 139 1 15 381 0 0 0 0 0 100 7 0 0 1 298 102 166 0 14 320 1 0 0 0 0 100 April 1, 2026 at 06:58:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2323 210 136 0 0 0 0 267 0 0 0 99 1 0 0 0 16 2 42 2 1 1 0 1434 0 0 0 100 2 0 0 0 108 51 102 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 9 2 2 0 0 0 0 0 0 0 0 100 5 0 0 14 11 3 6 1 0 0 0 565 0 0 0 100 6 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 82 2326 213 1031 8 23 4 0 1769 3 1 0 97 1 0 0 0 274 3 605 5 17 17 0 3126 1 1 0 98 2 6 0 0 307 22 652 6 15 19 0 1840 1 0 0 99 3 9 0 0 26 1 19 2 5 48 0 2629 1 1 0 98 4 18 0 0 256 5 525 6 11 31 0 1627 1 0 0 99 5 6 0 0 113 32 127 4 6 62 1 2631 1 1 0 98 6 0 0 0 234 1 479 3 14 19 0 1591 1 0 0 99 7 0 0 1 290 102 193 2 9 4 0 718 0 0 0 99 April 1, 2026 at 06:58:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2321 210 130 0 0 0 0 536 0 1 0 99 1 0 0 0 14 3 40 0 1 0 0 1435 0 0 0 100 2 0 0 0 14 3 6 0 0 0 0 3 0 0 0 100 3 0 0 0 13 1 12 1 1 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 110 52 104 1 0 0 0 300 0 0 0 100 6 0 0 0 10 1 6 0 1 0 0 1 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2328 211 447 0 68 1048 1 536 0 2 0 98 1 0 0 0 171 5 396 1 49 1016 0 1446 0 1 0 99 2 0 0 0 105 3 237 0 41 1013 0 26 0 1 0 99 3 0 0 0 149 48 215 0 44 965 0 300 0 1 0 99 4 0 0 0 153 50 254 0 50 1196 0 1 0 1 0 99 5 0 0 0 220 61 355 0 44 1046 1 315 0 1 0 99 6 0 0 0 102 0 240 0 37 1094 0 0 0 1 0 99 7 0 0 1 305 102 245 0 49 1035 1 0 0 1 0 99 April 1, 2026 at 06:58:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2322 210 258 1 4 112 0 532 0 1 0 99 1 0 0 0 13 2 157 1 5 127 0 1433 0 0 0 99 2 0 0 0 51 2 89 0 4 142 0 1 0 0 0 100 3 0 0 0 45 26 93 0 5 155 0 300 0 0 0 100 4 0 0 0 65 25 81 0 4 147 0 0 0 0 0 100 5 0 0 0 143 52 174 0 1 123 0 299 0 0 0 100 6 0 0 0 43 0 72 0 3 92 0 0 0 0 0 100 7 0 0 1 240 102 97 0 6 128 0 0 0 0 0 100 April 1, 2026 at 06:58:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2313 207 128 0 0 0 0 533 0 0 0 100 1 0 0 0 13 2 38 2 0 0 0 1440 0 0 0 100 2 0 0 0 17 5 16 0 1 0 0 13 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 10 2 4 0 1 0 0 0 0 0 0 100 5 0 0 0 118 53 118 0 1 0 0 378 0 0 0 100 6 0 0 0 23 6 18 0 0 0 0 14 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2309 204 120 0 0 0 0 527 0 0 0 100 1 0 0 0 12 3 36 1 0 0 0 1435 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 3 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 118 53 118 0 1 0 0 301 0 0 0 100 6 0 0 0 20 6 14 0 0 0 0 9 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2307 205 122 0 0 0 0 526 0 0 0 99 1 0 0 0 11 3 36 0 0 0 0 1435 0 0 0 100 2 0 0 0 11 3 6 0 0 0 0 2 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 4 0 1 0 0 0 0 0 0 100 5 0 0 0 112 53 106 1 0 0 0 302 0 0 0 100 6 0 0 0 20 6 14 0 0 0 0 9 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2309 204 126 1 0 1 0 526 0 0 0 100 1 0 0 0 25 6 52 2 0 2 0 1445 0 0 0 99 2 0 0 0 13 2 12 0 0 1 0 21 0 0 0 100 3 0 0 0 9 2 2 0 0 1 0 300 0 0 0 100 4 0 0 0 11 3 4 0 0 1 0 0 0 0 0 100 5 0 0 0 127 60 118 1 0 1 0 313 0 0 0 100 6 0 0 0 21 6 18 0 2 0 0 6 0 0 0 100 7 0 0 1 216 102 14 0 1 1 0 0 0 0 0 100 April 1, 2026 at 06:58:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2317 210 136 0 0 0 0 536 0 0 0 99 1 0 0 0 15 2 38 2 0 1 0 1439 0 0 0 100 2 0 0 0 15 4 10 0 0 0 0 12 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 113 53 112 0 1 0 0 377 0 0 0 100 6 0 0 0 16 3 10 0 0 0 0 7 0 0 0 100 7 0 0 1 216 102 12 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2323 211 132 0 0 0 0 537 0 0 0 100 1 0 0 0 10 2 34 1 0 0 0 1435 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 4 1 1 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 110 52 104 0 0 0 0 300 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 720 0 141 2318 210 181 0 9 4 6 641 0 1 0 99 1 100 0 0 61 4 103 1 5 4 11 1659 0 0 0 99 2 66 0 0 59 7 68 0 8 3 7 142 0 0 0 100 3 2665 0 0 57 3 66 3 3 10 14 7124 1 1 0 97 4 27 0 0 45 2 49 0 7 7 8 92 0 0 0 100 5 13 0 0 95 28 105 1 12 8 10 406 0 0 0 100 6 15 0 3 92 26 94 0 9 5 6 115 0 0 0 100 7 43 0 1 238 102 30 0 5 10 4 71 0 0 0 100 April 1, 2026 at 06:58:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2321 210 134 1 0 0 0 533 0 0 0 100 1 0 0 0 14 3 42 0 1 2 0 1507 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 110 51 106 0 0 0 0 1 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 263 0 26 2406 216 16382 112 421 513 0 41981 12 9 0 79 1 95 0 0 1005 13 14873 85 337 631 0 35739 12 8 0 79 2 44 0 0 681 11 15086 72 273 547 0 29722 11 7 0 82 3 60 0 0 837 51 11653 55 224 515 0 30866 10 7 0 83 4 141 0 0 393 50 9435 30 170 510 0 21869 6 5 0 89 5 240 0 0 932 23 9595 32 162 454 0 22406 6 5 0 89 6 15 0 0 270 28 8955 22 120 584 0 22181 7 5 0 88 7 38 0 1 768 106 11579 56 150 582 0 24331 10 6 0 85 April 1, 2026 at 06:58:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 19 0 23 2346 214 11059 38 228 130 0 28088 10 6 0 83 1 3 0 0 107 33 14899 24 138 213 0 34169 10 6 0 84 2 17 0 0 54 7 12634 29 137 137 0 23846 8 5 0 86 3 34 0 0 33 7 10031 27 121 78 0 19163 7 4 0 89 4 4 0 0 35 9 7795 13 57 51 0 17993 5 3 0 92 5 23 0 0 26 9 6284 11 53 76 0 17851 6 4 0 91 6 25 0 0 48 5 8417 11 60 57 0 16656 6 4 0 90 7 14 0 5 270 118 9586 10 55 130 0 25385 8 5 0 88 April 1, 2026 at 06:58:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2305 204 120 0 0 0 0 525 0 0 0 100 1 0 0 0 126 60 150 1 0 1 0 1525 0 0 0 100 2 0 0 0 9 1 4 0 1 0 0 1 0 0 0 100 3 0 0 0 12 2 6 1 0 0 0 300 0 0 0 100 4 0 0 0 10 1 8 0 1 0 0 0 0 0 0 100 5 0 0 0 14 3 6 0 0 0 0 302 0 0 0 100 6 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2324 219 118 1 1 0 0 527 0 0 0 100 1 0 0 0 125 45 149 0 3 0 0 1523 0 0 0 100 2 0 0 0 11 2 6 0 1 0 0 22 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 12 3 6 1 0 0 0 301 0 0 0 100 6 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 27 2343 239 123 0 2 0 0 527 0 0 0 100 1 0 0 0 121 23 144 1 3 1 0 1519 0 0 0 100 2 0 0 0 17 4 12 0 2 0 0 5 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 0 8 1 2 0 0 1 0 0 0 0 0 100 5 0 0 0 14 3 12 0 1 0 0 320 0 0 0 100 6 0 0 0 9 0 4 0 1 0 0 0 0 0 0 100 7 0 0 0 213 103 8 0 0 0 0 9 0 0 0 100 April 1, 2026 at 06:58:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 28 2313 204 408 1 39 577 0 526 0 1 0 99 1 0 0 0 204 52 351 3 26 528 0 1525 0 1 0 99 2 0 0 0 104 9 209 1 30 603 0 10 0 1 0 99 3 0 0 0 164 58 224 0 32 511 0 320 0 1 0 99 4 0 0 0 125 54 223 1 28 581 0 0 0 1 0 99 5 0 0 0 164 10 307 1 29 422 0 313 0 0 0 99 6 0 0 0 140 3 306 0 37 543 0 0 0 1 0 99 7 0 0 7 301 102 202 1 26 531 0 0 0 1 0 99 April 1, 2026 at 06:58:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2308 204 132 0 1 2 0 526 0 0 0 100 1 0 0 0 16 3 52 1 1 2 0 1516 0 0 0 100 2 0 0 0 19 7 22 0 1 3 0 9 0 0 0 100 3 0 0 0 121 59 114 0 0 0 0 300 0 0 0 100 4 0 0 0 13 8 8 0 0 3 0 0 0 0 0 100 5 0 0 0 18 3 20 0 0 0 0 302 0 0 0 100 6 0 0 0 8 0 20 0 0 2 0 0 0 0 0 100 7 0 0 1 214 102 12 0 1 3 0 0 0 0 0 100 April 1, 2026 at 06:58:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2307 204 138 1 1 0 0 526 0 0 0 100 1 0 0 0 13 3 38 0 0 0 0 1540 0 0 0 99 2 0 0 0 25 9 20 1 0 0 0 13 0 0 0 100 3 0 0 0 110 52 104 1 0 0 0 300 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 211 102 4 0 1 1 0 0 0 0 0 100 April 1, 2026 at 06:58:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2307 204 120 0 0 0 0 526 0 0 0 100 1 0 0 0 11 2 36 1 1 1 0 1517 0 0 0 100 2 0 0 0 19 7 14 0 0 0 0 6 0 0 0 100 3 0 0 0 109 52 104 0 0 0 0 300 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 12 3 6 1 0 0 0 302 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 209 102 4 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:58:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2305 204 118 0 0 0 0 525 0 0 0 99 1 0 0 0 12 3 36 1 0 1 0 1516 0 0 0 100 2 0 0 0 21 8 16 0 0 0 0 10 0 0 0 100 3 0 0 0 109 52 104 0 0 0 0 300 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 10 1 6 0 1 0 0 1 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 26 2313 205 126 0 0 0 0 528 0 0 0 100 1 0 0 0 24 5 54 2 0 0 0 1532 0 0 0 100 2 0 0 0 21 7 18 0 1 1 0 7 0 0 0 100 3 0 0 0 115 52 116 0 0 0 0 313 0 0 0 100 4 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 5 0 0 0 25 10 20 0 0 0 0 316 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 217 103 14 0 0 0 0 1 0 0 0 100 April 1, 2026 at 06:58:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 47 0 26 2359 209 16158 76 275 170 0 47733 14 9 0 77 1 18 0 0 358 9 11728 52 214 85 0 26590 9 6 0 84 2 37 0 0 1222 15 13729 46 157 135 0 26847 9 6 0 85 3 1 0 0 471 31 14180 28 116 159 0 30606 11 6 0 83 4 21 0 0 896 10 12700 27 81 128 0 29825 9 6 0 85 5 7 0 0 515 10 10135 14 77 116 0 28598 9 6 0 85 6 2 0 0 376 11 11783 18 69 70 0 22551 7 5 0 88 7 16 0 12 818 109 7799 21 66 109 0 19956 7 4 0 89 April 1, 2026 at 06:58:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 21 0 17 2356 211 15540 50 279 251 0 38444 13 8 0 80 1 26 0 7 81 22 14581 28 208 138 0 30047 11 6 0 83 2 14 0 0 70 8 14704 37 185 139 0 29970 10 6 0 84 3 16 0 0 58 8 10816 21 110 90 0 26992 9 6 0 86 4 12 0 0 37 5 13185 21 93 152 0 30199 10 6 0 84 5 15 0 0 29 4 13442 8 65 114 0 25809 8 6 0 86 6 10 0 0 52 10 9975 17 67 110 0 26738 8 5 0 88 7 9 0 4 259 120 7925 10 56 68 0 18906 6 4 0 91 April 1, 2026 at 06:58:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2301 201 114 0 0 0 0 266 0 0 0 100 1 0 0 7 115 55 140 1 0 0 0 1776 0 0 0 100 2 0 0 0 9 1 4 0 1 0 0 1 0 0 0 100 3 0 0 0 17 4 16 0 1 0 0 300 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 11 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 13 1 8 1 1 0 0 300 0 0 0 100 7 0 0 1 223 109 16 0 0 0 0 10 0 0 0 100 April 1, 2026 at 06:58:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2307 202 116 0 0 0 0 267 0 0 0 100 1 0 0 7 114 54 140 1 1 1 0 1775 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 15 4 10 0 1 1 0 300 0 0 0 100 4 0 0 0 9 1 6 0 1 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 6 0 0 0 12 1 4 0 0 0 0 300 0 0 0 100 7 0 0 1 221 108 14 0 0 0 0 9 0 0 0 100 April 1, 2026 at 06:58:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 21 2310 201 398 1 43 1031 0 266 0 2 0 98 1 0 0 7 196 56 359 2 34 1018 0 1791 0 1 0 98 2 0 0 0 106 1 209 0 38 901 0 0 0 1 0 99 3 0 0 0 157 56 278 0 50 828 0 318 0 1 0 99 4 0 0 0 135 50 221 0 52 834 0 0 0 1 0 99 5 0 0 0 130 10 260 0 45 939 0 13 0 1 0 99 6 0 0 0 112 2 230 0 35 843 0 300 0 1 0 99 7 0 0 7 355 108 305 0 53 795 0 6 0 1 0 99 April 1, 2026 at 06:58:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2309 202 248 0 14 119 0 269 0 1 0 99 1 0 0 7 27 7 160 1 9 113 0 1784 0 0 0 99 2 0 0 0 104 46 187 0 6 143 0 1 0 0 0 100 3 0 0 0 71 47 138 1 6 110 0 322 0 0 0 100 4 0 0 0 43 35 96 0 12 106 0 3 0 0 0 100 5 0 0 0 48 2 112 0 9 65 0 2 0 0 0 100 6 0 0 0 41 1 106 0 7 123 0 304 0 0 0 100 7 0 0 1 261 105 127 0 5 57 0 18 0 0 0 100 April 1, 2026 at 06:58:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2303 201 114 0 0 0 0 266 0 0 0 100 1 0 0 7 15 5 40 1 0 0 0 1773 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 28 11 22 1 0 0 0 310 0 0 0 100 4 0 0 0 7 1 2 0 1 0 0 0 0 0 0 100 5 0 0 0 8 1 2 0 1 1 0 0 0 0 0 100 6 0 0 0 11 1 10 0 1 0 0 300 0 0 0 100 7 0 0 1 210 102 4 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:58:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2303 201 112 0 0 0 0 266 0 0 0 100 1 0 0 7 13 4 38 0 0 0 0 1775 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 25 10 20 0 0 0 0 309 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 4 0 1 0 0 2 0 0 0 100 6 0 0 0 11 1 4 1 0 0 0 300 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2301 201 112 1 0 0 0 266 0 0 0 100 1 1 0 7 17 6 42 1 0 0 0 1779 0 0 0 100 2 0 0 0 106 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 25 10 20 0 0 0 0 309 0 0 0 100 4 0 0 0 8 1 2 0 1 0 0 0 0 0 0 100 5 0 0 0 6 0 4 0 2 0 0 0 0 0 0 100 6 0 0 0 12 2 6 0 0 0 0 301 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2309 202 118 0 0 0 0 267 0 0 0 100 1 0 0 7 21 6 52 2 1 0 0 1790 0 0 0 100 2 0 0 0 108 51 104 0 0 0 0 0 0 0 0 100 3 0 0 0 34 10 34 1 0 0 0 319 0 0 0 100 4 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 5 0 0 0 25 9 18 0 0 0 0 16 0 0 0 100 6 0 0 0 11 1 6 0 1 0 0 300 0 0 0 100 7 0 0 1 219 104 16 0 1 0 0 1 0 0 0 100 April 1, 2026 at 06:58:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 23 0 397 3007 204 1966 851 114 39 0 5199 23 3 0 74 1 546 0 7 760 7 1782 773 124 37 0 6265 23 3 0 74 2 325 0 0 930 32 2034 883 106 67 0 4980 23 3 0 75 3 350 0 63 888 20 2007 881 133 47 0 5148 23 3 0 75 4 0 0 0 768 3 1635 742 89 46 0 4254 23 2 0 75 5 783 0 0 512 2 1120 509 74 19 1 3088 24 2 0 75 6 17 0 0 966 6 2208 1018 127 45 0 5498 23 3 0 75 7 3 0 1 1079 108 2092 915 127 50 0 5366 23 2 0 75 April 1, 2026 at 06:58:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 34 2310 205 135 0 2 0 0 302 0 0 0 100 1 0 0 7 17 4 46 0 1 0 0 1798 0 0 0 99 2 0 0 0 16 3 10 0 0 0 0 10 0 0 0 100 3 1 0 0 115 53 108 1 1 0 0 309 0 0 0 100 4 7 0 0 9 1 2 0 1 0 0 9 0 0 0 100 5 0 0 0 13 1 12 0 1 0 0 10 0 0 0 100 6 2 0 0 18 2 12 0 3 1 0 308 0 0 0 100 7 0 0 0 214 102 6 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:58:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 18 2314 208 130 1 0 0 0 275 0 0 0 99 1 0 0 7 19 6 46 1 1 0 0 1796 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 22 0 0 0 100 3 0 0 0 113 54 108 0 0 0 0 301 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 13 2 8 1 1 0 0 300 0 0 0 100 7 0 0 2 211 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2318 208 126 0 0 0 0 272 0 0 0 100 1 0 0 7 14 4 38 1 0 0 0 1791 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 113 54 110 0 1 0 0 301 0 0 0 100 4 0 0 0 6 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 2 0 0 0 100 6 0 0 0 12 2 6 0 0 0 0 300 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 37 0 75 2333 212 1214 3 138 1298 2 3057 2 2 0 96 1 1 0 14 414 10 887 9 114 1138 0 2611 1 2 0 97 2 0 0 14 120 2 239 1 44 1176 3 3071 2 2 0 96 3 25 0 0 265 90 375 7 51 1349 1 2997 3 2 0 95 4 0 0 0 460 51 973 8 111 1194 0 2244 1 2 0 97 5 0 0 0 310 10 940 2 105 1181 0 2969 1 2 0 98 6 4 0 9 138 3 274 3 47 1220 1 3322 2 3 0 95 7 0 0 1 392 111 1049 4 119 1219 0 2266 1 2 0 97 April 1, 2026 at 06:58:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 19 2356 245 475 0 35 484 0 269 0 1 0 99 1 0 0 7 150 4 356 0 31 603 0 555 0 0 0 100 2 0 0 7 74 7 258 0 30 529 1 0 0 0 0 100 3 0 0 0 90 68 266 0 21 576 0 308 0 0 0 100 4 0 0 0 112 62 259 0 26 517 1 0 0 0 0 100 5 0 0 0 37 7 286 2 28 558 0 1159 0 1 0 99 6 0 0 0 61 2 270 0 20 695 0 306 0 0 0 100 7 0 0 1 224 102 251 0 27 552 1 3 0 0 0 100 April 1, 2026 at 06:58:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 131 2358 254 116 1 0 0 0 271 0 1 0 99 1 0 0 7 136 4 116 0 0 0 0 555 0 0 0 100 2 0 0 0 25 0 4 0 0 0 0 0 0 0 0 100 3 0 0 0 41 8 18 1 1 0 0 308 0 0 0 100 4 0 0 0 22 1 0 0 0 0 0 0 0 0 0 100 5 0 0 0 24 1 32 1 0 0 0 1147 0 0 0 100 6 0 0 0 28 2 8 0 0 0 0 300 0 0 0 100 7 0 0 1 225 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:58:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2357 253 110 0 0 0 0 267 0 0 0 100 1 0 0 7 119 3 114 0 0 0 0 554 0 0 0 100 2 0 0 7 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 25 8 18 0 0 0 0 308 0 0 0 100 4 0 0 0 9 1 8 0 2 0 0 0 0 0 0 100 5 0 0 0 11 2 34 1 0 0 0 1148 0 0 0 100 6 0 0 0 14 2 6 1 0 0 0 300 0 0 0 100 7 0 0 1 213 103 4 1 0 0 0 1 0 0 0 100 April 1, 2026 at 06:59:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 75 2357 246 589 7 12 13 0 1314 1 1 0 98 1 0 0 7 147 5 142 3 4 52 0 3670 2 1 0 97 2 0 0 0 257 14 480 2 6 24 0 1622 1 0 0 99 3 0 0 0 299 10 628 0 6 11 0 1707 1 0 0 99 4 3 0 0 30 2 24 3 1 45 1 3004 2 1 0 98 5 0 0 0 260 3 569 3 7 16 0 1889 2 0 0 97 6 0 0 0 290 6 625 1 2 17 0 1698 1 0 0 99 7 1 0 1 415 103 420 0 6 5 0 662 1 0 0 99 April 1, 2026 at 06:59:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 20 2328 208 294 1 55 1241 0 276 0 2 0 98 1 0 0 7 206 24 379 3 55 961 1 572 0 1 0 99 2 0 0 0 191 30 303 1 59 887 0 0 0 1 0 99 3 0 0 0 144 53 285 3 50 1039 0 317 0 1 0 99 4 0 0 0 151 49 225 2 41 1041 0 0 0 1 0 99 5 0 0 0 165 8 382 1 52 931 1 1159 0 1 0 99 6 0 0 0 135 3 295 3 58 1018 0 301 0 1 0 99 7 0 0 0 315 103 223 2 37 918 0 1 0 1 0 99 April 1, 2026 at 06:59:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 758 0 19 2339 211 301 2 21 213 9 6773 1 1 0 98 1 5 0 7 101 32 245 0 16 216 4 643 0 0 0 100 2 304 0 0 49 2 154 0 12 189 6 115 0 0 0 100 3 2057 0 0 116 44 248 2 23 254 19 743 0 1 0 99 4 443 0 113 95 40 180 0 16 116 8 142 0 0 0 100 5 44 0 2 79 17 298 1 18 183 10 1276 0 0 0 99 6 24 0 0 65 2 193 0 21 200 4 404 0 0 0 99 7 6 0 1 266 102 146 0 14 190 0 56 0 0 0 100 April 1, 2026 at 06:59:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2304 202 110 0 0 0 0 266 0 0 0 100 1 0 0 7 13 4 8 1 0 0 0 553 0 0 0 100 2 0 0 0 10 2 4 0 0 0 0 2 0 0 0 100 3 0 0 0 14 4 8 1 0 0 0 300 0 0 0 100 4 0 0 0 17 6 10 0 0 0 0 8 0 0 0 100 5 1 0 0 114 53 138 1 0 0 0 1236 0 0 0 100 6 0 0 0 22 1 22 0 3 0 0 300 0 0 0 100 7 0 0 1 211 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:59:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 86 0 19 2324 203 4125 37 105 56 0 12618 4 4 0 92 1 329 0 7 951 6 4721 21 75 74 0 14301 5 3 0 92 2 60 0 0 696 8 2281 5 46 5 0 5211 2 1 0 97 3 2 0 0 705 6 5473 9 39 18 0 12460 3 2 0 95 4 3 0 0 883 9 5387 7 19 219 0 14674 6 2 0 92 5 0 0 0 505 45 5856 4 18 45 0 8645 3 2 0 95 6 22 0 0 507 3 4192 8 31 54 0 16600 5 3 0 93 7 13 0 1 424 105 3425 5 22 19 0 5762 2 2 0 97 April 1, 2026 at 06:59:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 95 0 2 2391 213 21271 99 421 348 0 55722 18 12 0 70 1 37 0 14 125 8 22508 97 350 209 0 43280 15 10 0 75 2 47 0 7 75 16 19055 62 244 224 0 44858 14 9 0 76 3 22 0 0 71 15 17447 54 193 139 0 34166 11 8 0 82 4 34 0 0 70 9 15454 36 131 197 0 32354 10 7 0 84 5 53 0 0 58 14 13117 29 123 179 0 37081 12 7 0 81 6 82 0 0 67 13 16792 29 117 149 0 34798 11 8 0 81 7 40 0 5 301 118 18123 32 99 323 0 42208 13 8 0 79 April 1, 2026 at 06:59:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2308 200 357 0 50 958 0 0 0 1 0 99 1 0 0 14 206 53 330 1 34 942 0 279 0 1 0 99 2 0 0 7 109 5 228 0 45 878 0 554 0 1 0 99 3 0 0 0 145 53 243 0 40 694 2 318 0 1 0 99 4 0 0 0 131 57 202 0 36 834 3 8 0 1 0 99 5 0 0 0 127 9 282 1 44 838 0 1241 0 1 0 99 6 0 0 0 151 3 321 0 53 774 0 300 0 1 0 99 7 0 0 7 305 102 220 0 45 812 0 0 0 1 0 99 April 1, 2026 at 06:59:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2352 246 205 0 9 89 0 0 0 0 0 100 1 0 0 14 124 7 195 0 12 75 0 266 0 0 0 100 2 0 0 7 53 4 88 0 7 50 0 555 0 0 0 100 3 0 0 0 52 34 118 0 5 68 0 300 0 0 0 100 4 0 0 0 53 41 90 0 5 68 0 10 0 0 0 100 5 0 0 0 18 3 130 1 7 60 0 1230 0 0 0 100 6 0 0 0 75 1 134 1 4 57 0 300 0 0 0 100 7 0 0 1 248 102 90 0 7 59 0 0 0 0 0 100 April 1, 2026 at 06:59:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 250 102 0 1 0 0 0 0 0 0 100 1 0 0 14 108 2 104 0 0 0 0 266 0 0 0 100 2 0 0 7 13 3 8 0 0 0 0 553 0 0 0 100 3 0 0 0 11 2 4 0 0 0 0 300 0 0 0 100 4 0 0 0 23 9 16 1 0 0 0 7 0 0 0 100 5 0 0 0 14 4 38 1 2 0 0 1229 0 0 0 100 6 0 0 0 22 1 20 0 2 0 0 300 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:59:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 250 104 0 0 0 0 0 0 0 0 100 1 0 0 14 107 2 104 0 0 0 0 266 0 0 0 100 2 0 0 7 12 3 8 0 1 0 0 553 0 0 0 100 3 0 0 0 10 2 4 1 0 0 0 300 0 0 0 100 4 0 0 0 20 8 14 0 0 0 0 9 0 0 0 100 5 0 0 0 11 3 36 0 0 0 0 1231 0 0 0 100 6 0 0 0 20 1 16 0 0 0 0 300 0 0 0 100 7 0 0 1 212 102 6 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:59:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 5 2355 251 104 0 0 0 0 5 0 0 0 100 1 0 0 14 110 3 106 1 0 0 0 267 0 0 0 100 2 0 0 7 13 3 8 1 0 0 0 555 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 19 0 0 24 10 18 0 0 0 0 15 0 0 0 100 5 0 0 0 10 2 34 1 0 1 0 1226 0 0 0 100 6 0 0 0 20 2 16 0 1 0 0 301 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:59:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2356 250 112 0 0 2 0 0 0 0 0 100 1 0 0 14 115 4 116 0 0 0 0 290 0 0 0 100 2 0 0 7 12 3 8 0 0 0 0 554 0 0 0 100 3 0 0 0 15 2 16 0 0 0 0 320 0 0 0 100 4 0 0 0 21 8 16 0 0 0 0 9 0 0 0 100 5 0 0 0 29 13 50 1 0 1 0 1237 0 0 0 100 6 0 0 0 24 3 20 1 1 0 0 302 0 0 0 100 7 0 0 1 221 103 16 0 0 1 0 1 0 0 0 100 April 1, 2026 at 06:59:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2353 250 104 0 0 0 0 0 0 0 0 100 1 0 0 14 107 2 106 0 1 0 0 266 0 0 0 100 2 0 0 7 13 3 10 0 0 0 0 555 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 0 24 10 18 0 0 0 0 8 0 0 0 100 5 0 0 0 11 2 34 1 0 0 0 1224 0 0 0 100 6 0 0 0 23 1 18 0 0 0 0 300 0 0 0 100 7 0 0 0 209 102 4 0 1 0 0 0 0 0 0 100 April 1, 2026 at 06:59:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 250 104 0 0 0 0 0 0 0 0 100 1 0 0 14 108 2 104 1 0 0 0 266 0 0 0 100 2 0 0 7 17 5 14 0 0 0 0 560 0 0 0 100 3 0 0 0 10 2 4 1 0 0 0 300 0 0 0 100 4 0 0 0 26 11 20 0 0 0 0 15 0 0 0 100 5 0 0 0 12 3 36 1 0 0 0 1226 0 0 0 100 6 0 0 0 19 1 16 0 1 0 0 300 0 0 0 100 7 0 0 1 210 102 2 0 0 0 0 0 0 0 0 100 April 1, 2026 at 06:59:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2355 250 104 0 0 0 0 3 0 0 0 100 1 0 0 14 115 6 112 0 0 0 0 270 0 0 0 100 2 0 0 7 19 6 14 1 0 0 0 577 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 0 27 10 20 0 0 0 0 13 0 0 0 100 5 0 0 0 12 3 36 1 0 1 0 1225 0 0 0 100 6 0 0 0 20 1 16 0 0 0 0 300 0 0 0 100 7 0 0 1 210 102 4 0 1 1 0 0 0 0 0 100 April 1, 2026 at 06:59:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 31 0 5 2361 242 4968 23 69 89 0 13179 4 3 0 92 1 3 0 14 512 4 5547 12 53 21 0 11829 3 3 0 94 2 0 0 7 933 8 5182 9 31 44 0 15237 4 2 0 94 3 64 0 0 97 3 4934 9 39 77 1 14061 5 3 0 92 4 2 0 0 845 9 4247 9 27 54 0 12115 4 2 0 94 5 0 0 0 418 3 7035 8 26 60 0 11423 4 3 0 94 6 8 0 0 422 3 3071 6 27 15 0 8188 3 2 0 95 7 0 0 1 595 106 1315 5 17 58 0 6823 4 1 0 96 April 1, 2026 at 06:59:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 28 0 7 2378 213 26529 94 451 1313 1 63537 20 14 0 66 1 25 0 14 110 14 22547 72 346 1225 1 49412 17 12 0 71 2 13 0 7 96 20 23667 43 284 1283 1 45421 15 11 0 74 3 12 0 0 120 62 23020 42 229 1140 1 42777 13 10 0 77 4 32 0 0 133 61 19122 37 177 1233 0 46759 14 10 0 75 5 33 0 0 83 27 18339 33 158 1211 0 47675 13 10 0 77 6 10 0 0 67 9 16786 30 160 1224 0 33973 11 8 0 81 7 30 0 7 280 118 13736 25 145 1093 0 36509 13 8 0 79 April 1, 2026 at 06:59:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 201 212 0 8 64 0 0 0 0 0 100 1 0 0 14 15 3 106 1 4 60 0 265 0 0 0 100 2 0 0 7 110 52 212 0 8 58 0 260 0 0 0 100 3 0 0 0 52 35 92 0 3 43 0 605 0 0 0 100 4 0 0 0 39 28 87 0 6 62 0 0 0 0 0 100 5 0 0 0 12 3 122 1 6 80 0 1223 0 0 0 100 6 0 0 0 13 0 90 0 6 61 0 0 0 0 0 100 7 0 0 1 212 103 74 1 6 47 0 300 0 0 0 100 April 1, 2026 at 06:59:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2305 201 116 0 0 0 0 1 0 0 0 100 1 0 0 14 11 2 6 0 0 0 0 266 0 0 0 100 2 0 0 7 112 52 110 0 1 1 0 260 0 0 0 100 3 0 0 0 24 9 18 1 0 0 0 602 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 12 3 36 1 0 1 0 1222 0 0 0 100 6 0 0 0 12 1 6 0 1 0 0 0 0 0 0 100 7 0 0 0 211 103 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 108 0 0 0 0 0 0 0 0 100 1 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 2 0 0 7 110 53 106 0 0 0 0 260 0 0 0 100 3 0 0 0 23 9 18 0 0 0 0 604 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 12 3 36 1 0 0 0 1222 0 0 0 100 6 0 0 0 10 0 6 0 0 0 0 0 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 110 0 0 0 0 0 0 0 0 100 1 0 0 14 9 2 6 0 0 0 0 269 0 0 0 100 2 0 0 7 112 52 110 0 1 0 0 266 0 0 0 100 3 0 0 0 30 11 26 0 1 0 0 610 0 0 0 100 4 0 0 0 13 4 8 0 0 0 0 5 0 0 0 100 5 2 0 0 14 4 40 0 0 0 0 1228 0 0 0 100 6 0 0 0 14 1 12 0 1 0 0 3 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 128 0 1 0 0 10 0 0 0 100 1 1 0 14 9 3 6 1 0 0 0 267 0 0 0 100 2 0 0 7 108 52 104 0 0 0 0 260 0 0 0 100 3 0 0 0 33 10 34 0 0 0 0 623 0 0 0 100 4 0 0 0 11 2 6 0 1 0 0 0 0 0 0 100 5 0 0 0 23 8 48 1 0 0 0 1234 0 0 0 100 6 0 0 0 14 2 10 0 0 0 0 2 0 0 0 100 7 0 0 1 218 103 14 1 1 0 0 300 0 0 0 100 April 1, 2026 at 06:59:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 110 0 0 0 0 1 0 0 0 100 1 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 2 0 0 7 108 52 104 0 0 0 0 260 0 0 0 100 3 0 0 0 24 9 18 1 0 0 0 603 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 10 2 34 1 0 1 0 1222 0 0 0 100 6 0 0 0 10 0 6 0 0 0 0 0 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 110 0 0 0 0 3 0 0 0 100 1 0 0 14 9 3 6 0 0 0 0 290 0 0 0 100 2 0 0 7 111 53 106 0 0 0 0 261 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 603 0 0 0 100 4 0 0 0 15 4 10 0 1 0 0 4 0 0 0 100 5 0 0 0 13 3 38 1 1 1 0 1223 0 0 0 100 6 0 0 0 11 0 8 0 1 0 0 0 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2303 200 108 0 0 0 0 0 0 0 0 100 1 0 0 14 9 3 6 0 0 0 0 267 0 0 0 100 2 0 0 7 112 54 108 0 0 0 0 262 0 0 0 100 3 0 0 0 23 9 18 0 0 1 0 603 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 12 3 36 1 0 0 0 1221 0 0 0 100 6 0 0 0 12 0 8 0 0 0 0 0 0 0 0 100 7 0 0 0 214 103 10 0 1 2 0 300 0 0 0 100 April 1, 2026 at 06:59:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 291 0 318 2805 202 1655 631 166 48 0 5730 20 3 0 77 1 11 0 14 433 2 1004 439 118 31 0 3601 21 1 0 78 2 70 0 7 767 43 1940 733 142 31 1 5943 20 2 0 78 3 25 0 0 766 11 1746 775 106 36 0 5339 20 2 0 78 4 294 0 0 658 5 1625 693 159 31 2 5178 20 2 0 78 5 14 0 0 691 5 1640 720 139 44 0 5065 20 2 0 78 6 791 0 0 626 2 1526 620 135 51 0 4855 20 2 0 78 7 51 0 1 893 104 1660 726 160 38 0 6521 20 2 0 78 April 1, 2026 at 06:59:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 65 0 63 2386 207 319 85 15 8 0 400 3 1 0 96 1 9 0 14 81 4 161 67 14 6 0 707 3 0 0 97 2 0 0 7 195 48 329 98 17 6 0 930 3 0 0 96 3 0 0 0 144 6 257 107 12 12 0 1225 3 0 0 96 4 2 0 0 114 3 245 110 14 7 0 727 3 0 0 97 5 2 0 0 107 9 238 101 15 8 0 703 3 0 0 97 6 0 0 0 132 3 233 103 14 7 0 563 3 0 0 97 7 0 0 7 315 107 231 76 22 8 0 2213 3 1 0 96 April 1, 2026 at 06:59:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 200 112 0 0 0 0 0 0 0 0 100 1 1 0 14 11 2 12 0 1 0 0 266 0 0 0 100 2 0 0 7 122 59 118 0 0 0 0 270 0 0 0 100 3 0 0 0 11 2 4 2 0 0 0 595 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 6 0 0 0 10 0 6 0 1 0 0 0 0 0 0 100 7 0 0 1 212 103 36 1 0 2 0 1547 0 0 0 100 April 1, 2026 at 06:59:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 108 0 0 0 0 0 0 0 0 100 1 0 0 14 7 2 4 0 0 0 0 266 0 0 0 100 2 0 0 7 120 58 116 0 0 0 0 268 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 594 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 1 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 6 0 0 0 10 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 214 104 38 1 1 1 0 1545 0 0 0 100 April 1, 2026 at 06:59:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 108 0 0 0 0 0 0 0 0 100 1 0 0 14 10 2 6 1 0 0 0 266 0 0 0 100 2 0 0 7 128 61 126 0 1 0 0 268 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 594 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 9 2 6 0 1 0 0 2 0 0 0 100 6 0 0 0 10 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 213 104 36 0 0 0 0 1545 0 0 0 100 April 1, 2026 at 06:59:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 62 2324 207 857 19 64 40 0 2139 3 1 0 97 1 2 0 14 463 42 895 18 66 29 0 2107 1 1 0 98 2 0 0 7 238 9 496 13 35 58 0 2366 1 1 0 98 3 0 0 0 366 8 769 15 43 26 0 2384 1 0 0 98 4 25 0 9 120 3 228 8 18 86 1 2658 2 1 0 97 5 0 0 14 30 1 26 2 5 104 2 2852 2 1 0 97 6 4 0 0 39 1 42 2 7 144 0 3139 2 1 0 97 7 36 0 7 549 104 764 23 49 44 5 3887 1 1 0 98 April 1, 2026 at 06:59:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2325 203 513 4 69 1375 1 11 0 1 0 99 1 0 0 14 201 53 336 1 52 1209 1 267 0 1 0 99 2 0 0 7 92 3 214 2 40 1297 0 260 0 2 0 98 3 0 0 0 162 55 238 3 56 1154 1 627 0 2 0 98 4 0 0 0 147 47 223 3 48 1267 1 0 0 2 0 98 5 0 0 0 102 8 192 2 43 908 1 14 0 2 0 98 6 0 0 0 114 1 248 2 51 1305 1 1 0 2 0 98 7 0 0 1 325 104 286 2 49 1205 3 1447 0 2 0 98 April 1, 2026 at 06:59:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2330 207 400 0 25 455 0 0 0 1 0 99 1 0 0 14 145 45 310 0 27 660 0 266 0 1 0 99 2 0 0 7 64 5 228 1 27 556 0 260 0 0 0 100 3 0 0 0 114 52 220 0 25 473 0 603 0 0 0 100 4 0 0 0 89 50 237 0 26 553 2 6 0 0 0 100 5 0 0 112 99 2 198 0 17 533 0 0 0 0 0 100 6 0 0 0 140 4 223 0 18 535 0 0 0 0 0 100 7 0 0 1 238 105 264 1 18 575 0 1445 0 1 0 99 April 1, 2026 at 06:59:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 112 0 0 0 0 0 0 0 0 100 1 0 0 14 109 51 104 1 1 0 0 266 0 0 0 100 2 0 0 7 15 4 10 0 1 0 0 261 0 0 0 100 3 0 0 0 24 8 18 0 1 0 0 600 0 0 0 100 4 0 0 7 14 2 10 0 4 0 0 0 0 0 0 100 5 0 0 0 14 2 6 0 1 0 0 2 0 0 0 100 6 0 0 7 14 0 10 0 3 1 0 0 0 0 0 100 7 0 0 1 218 105 38 0 0 1 0 1446 0 0 0 100 April 1, 2026 at 06:59:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 4 0 74 2311 202 779 3 14 12 0 1394 1 1 0 98 1 0 0 14 213 7 579 3 4 25 0 1732 1 0 0 99 2 4 0 7 49 10 47 2 4 49 0 3230 2 1 0 97 3 1 0 0 356 45 661 4 12 28 0 2507 1 0 0 99 4 1 0 0 256 4 749 6 7 18 0 1922 2 0 0 97 5 0 0 0 265 7 495 1 6 6 0 683 0 0 0 99 6 0 0 0 208 1 414 2 2 15 0 1530 1 0 0 99 7 3 0 2 251 105 84 4 3 49 0 4655 2 1 0 97 April 1, 2026 at 06:59:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 4 0 1 0 0 1 0 0 0 100 1 0 0 14 7 1 2 0 0 0 0 266 0 0 0 100 2 0 0 7 23 9 18 1 0 0 0 269 0 0 0 100 3 0 0 0 118 16 112 1 5 0 0 595 0 0 0 100 4 0 0 0 99 33 90 0 4 0 0 0 0 0 0 100 5 0 0 0 23 7 20 0 1 0 0 20 0 0 0 100 6 0 0 0 14 1 10 0 1 3 0 1 0 0 0 100 7 0 0 1 227 106 58 2 1 0 0 1446 0 0 0 100 April 1, 2026 at 06:59:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2316 203 282 0 59 1044 0 10 0 1 0 98 1 0 0 14 95 2 243 0 33 928 1 551 0 1 0 99 2 0 0 7 117 10 237 1 35 1083 0 269 0 1 0 99 3 0 0 0 260 64 450 1 60 878 0 330 0 1 0 99 4 0 0 0 178 75 302 0 55 1139 0 0 0 1 0 99 5 0 0 0 149 20 268 1 63 1025 0 19 0 1 0 99 6 0 0 0 136 4 267 0 52 1042 0 0 0 1 0 99 7 0 0 7 324 105 275 1 47 1043 1 1437 0 2 0 98 April 1, 2026 at 06:59:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 200 137 0 10 151 0 0 0 0 0 100 1 0 0 14 7 2 144 1 9 168 0 565 0 0 0 100 2 0 0 7 32 10 131 0 11 177 0 270 0 0 0 100 3 0 0 0 158 72 264 0 16 117 0 294 0 0 0 100 4 0 0 0 150 58 245 0 16 175 0 0 0 0 0 100 5 0 0 0 62 2 122 0 10 166 0 2 0 0 0 100 6 0 0 0 67 0 126 0 9 158 1 0 0 0 0 100 7 0 0 1 250 105 167 0 9 158 0 1437 0 0 0 100 April 1, 2026 at 06:59:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 96 0 4 2445 206 23919 132 514 324 13 58948 21 13 0 66 1 78 0 0 1335 9 25967 97 401 323 10 55593 18 12 0 70 2 132 0 21 568 12 22070 92 326 249 6 56055 18 11 0 71 3 86 0 0 339 11 20719 60 222 164 2 44181 13 9 0 77 4 155 0 0 469 19 18425 45 166 245 2 45902 14 9 0 76 5 203 0 0 501 19 14217 37 120 137 0 33084 11 7 0 82 6 3721 0 114 686 17 16277 43 122 130 18 42369 12 9 0 79 7 157 0 3 443 111 17795 31 117 204 18 39515 12 8 0 80 April 1, 2026 at 06:59:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 3 2323 203 3497 12 76 37 0 7254 3 2 0 95 1 7 0 0 29 3 3385 11 52 91 0 9375 3 2 0 96 2 2 0 21 33 6 2765 12 43 44 0 6908 2 1 0 97 3 1 0 0 36 10 3300 10 34 30 0 6192 2 1 0 97 4 2 0 0 22 5 2540 9 19 16 0 5943 2 1 0 98 5 16 0 0 37 8 2485 4 27 24 0 4883 2 1 0 97 6 2 0 0 23 2 1813 4 16 22 0 5218 2 1 0 97 7 2 0 3 315 152 2202 4 19 7 0 5770 1 1 0 97 April 1, 2026 at 06:59:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 200 104 0 0 0 0 0 0 0 0 100 1 19 0 0 12 2 6 1 1 0 0 305 0 0 0 100 2 0 0 21 10 4 6 0 0 0 0 527 0 0 0 100 3 0 0 0 28 7 23 1 1 0 0 303 0 0 0 100 4 0 0 0 8 2 2 0 0 0 0 0 0 0 0 100 5 0 0 0 11 3 6 0 0 0 0 2 0 0 0 100 6 0 0 0 12 1 4 0 0 0 0 1 0 0 0 100 7 0 0 1 317 155 140 1 1 0 0 1520 0 0 0 100 April 1, 2026 at 06:59:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2313 202 400 0 72 939 1 11 0 1 0 99 1 0 0 0 122 4 261 0 52 838 0 305 0 1 0 99 2 0 0 21 106 3 244 1 43 786 0 525 0 1 0 99 3 0 0 0 164 59 345 0 54 949 2 323 0 1 0 99 4 0 0 0 157 51 259 0 54 876 1 0 0 1 0 99 5 0 0 0 121 13 239 0 40 842 0 18 0 1 0 99 6 0 0 0 106 0 250 0 46 834 2 0 0 1 0 99 7 0 0 1 471 155 478 1 57 769 0 1518 0 1 0 99 April 1, 2026 at 06:59:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2356 247 232 0 10 78 0 15 0 0 0 100 1 0 0 0 132 2 184 0 6 58 0 300 0 0 0 100 2 0 0 21 50 3 99 0 5 67 0 526 0 0 0 100 3 0 0 0 61 38 120 1 6 82 0 303 0 0 0 100 4 0 0 0 45 34 91 0 5 62 0 6 0 0 0 100 5 0 0 0 23 1 98 0 7 67 0 0 0 0 0 100 6 1 0 0 25 0 104 0 7 87 0 9 0 0 0 100 7 0 0 1 256 109 175 2 7 78 0 1519 0 0 0 100 April 1, 2026 at 06:59:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2357 252 108 0 1 0 0 4 0 0 0 100 1 0 0 0 92 1 84 0 0 0 0 300 0 0 0 100 2 0 0 21 12 5 10 0 0 0 0 528 0 0 0 100 3 0 0 0 45 7 41 0 1 0 0 304 0 0 0 100 4 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 5 0 0 0 10 2 6 0 0 0 0 2 0 0 0 100 6 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 217 105 40 1 0 0 0 1517 0 0 0 100 April 1, 2026 at 06:59:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 250 104 0 0 1 0 0 0 0 0 100 1 0 0 0 12 2 10 0 2 0 0 301 0 0 0 100 2 0 0 21 13 5 12 0 1 0 0 527 0 0 0 100 3 2 0 0 129 8 124 0 0 0 0 308 0 0 0 100 4 0 0 0 12 4 6 0 0 0 0 5 0 0 0 100 5 0 0 0 11 3 6 0 0 0 0 1 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 219 105 40 1 0 1 0 1514 0 0 0 100 April 1, 2026 at 06:59:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 250 102 0 0 0 0 0 0 0 0 100 1 0 0 0 10 1 4 1 1 0 0 299 0 0 0 100 2 0 0 21 10 3 8 1 1 0 0 527 0 0 0 100 3 0 0 0 131 8 124 1 0 0 0 304 0 0 0 100 4 0 0 0 13 3 10 0 1 0 0 0 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 6 0 0 0 10 1 6 0 0 0 0 1 0 0 0 100 7 0 0 1 216 105 38 1 0 0 0 1512 0 0 0 100 April 1, 2026 at 06:59:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2361 253 124 0 0 1 0 12 0 0 0 100 1 0 0 0 11 2 4 0 0 1 0 300 0 0 0 100 2 0 0 21 12 4 8 0 0 1 0 525 0 0 0 100 3 0 0 0 135 8 134 0 0 1 0 323 0 0 0 100 4 0 0 0 15 5 8 0 0 2 0 0 0 0 0 100 5 1 0 0 23 9 16 0 0 1 0 13 0 0 0 100 6 0 0 0 11 1 6 0 0 2 0 1 0 0 0 100 7 0 0 1 222 105 48 1 1 3 0 1510 0 0 0 100 April 1, 2026 at 06:59:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2353 250 104 0 0 0 0 0 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 2 0 0 21 8 3 6 0 0 0 0 526 0 0 0 100 3 0 0 0 130 7 122 1 0 0 0 303 0 0 0 100 4 0 0 0 12 3 6 0 1 0 0 0 0 0 0 100 5 0 0 0 13 2 12 0 1 0 0 2 0 0 0 100 6 0 0 0 9 0 4 0 0 0 0 0 0 0 0 100 7 0 0 1 216 105 38 1 0 0 0 1512 0 0 0 100 April 1, 2026 at 06:59:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 250 104 0 0 0 0 0 0 0 0 100 1 0 0 0 10 1 4 0 0 0 0 300 0 0 0 100 2 0 0 21 8 3 8 0 1 0 0 527 0 0 0 100 3 0 0 0 127 7 122 0 0 0 0 303 0 0 0 100 4 0 0 0 10 3 4 0 0 0 0 0 0 0 0 100 5 0 0 0 14 2 10 0 0 1 0 1 0 0 0 100 6 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 216 105 39 1 1 0 0 1512 0 0 0 100 April 1, 2026 at 06:59:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 33 0 3 2388 220 21426 97 406 190 0 56220 19 12 0 69 1 114 0 0 452 9 24929 71 304 195 0 48616 17 11 0 73 2 9 0 0 679 14 19117 51 213 223 0 48013 14 10 0 76 3 5 0 7 782 12 20033 53 175 158 0 48305 15 9 0 76 4 43 0 14 800 15 15917 28 123 150 0 32894 12 7 0 81 5 9 0 0 171 13 19759 35 112 240 0 47315 16 9 0 75 6 92 0 0 342 11 15900 21 97 132 0 37564 12 8 0 81 7 7 0 3 454 114 22117 18 92 265 0 50653 14 10 0 76 April 1, 2026 at 06:59:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 3 2321 205 7414 19 119 104 0 19804 6 4 0 90 1 5 0 0 84 33 4994 14 90 56 0 12125 4 2 0 93 2 4 0 0 24 4 4744 6 58 43 0 10369 4 2 0 94 3 0 0 7 23 6 4875 7 54 45 0 11259 3 2 0 95 4 4 0 14 21 4 3580 7 45 34 0 9295 3 2 0 95 5 3 0 5 35 12 3015 3 25 28 0 8092 2 1 0 96 6 5 0 0 31 5 3333 5 25 37 0 9791 3 2 0 95 7 1 0 4 252 120 6490 1 23 18 0 7987 3 2 0 95 April 1, 2026 at 06:59:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2320 204 349 0 52 990 0 10 0 2 0 98 1 0 0 0 258 49 469 0 53 887 0 2 0 1 0 99 2 0 0 0 111 2 246 0 44 984 0 300 0 1 0 99 3 0 0 7 158 51 241 1 50 1086 0 575 0 1 0 99 4 0 0 14 155 54 230 0 49 923 1 266 0 1 0 99 5 0 0 0 131 17 248 1 43 892 0 23 0 1 0 99 6 0 0 0 128 0 299 5 48 876 0 1209 0 1 0 99 7 0 0 1 309 102 225 1 33 943 0 300 0 1 0 99 April 1, 2026 at 06:59:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2307 201 86 0 2 33 0 0 0 0 0 100 1 0 0 0 30 1 118 0 10 29 0 0 0 0 0 100 2 0 0 0 68 1 84 0 7 24 0 300 0 0 0 100 3 0 0 7 51 27 56 0 4 31 0 553 0 0 0 100 4 0 0 14 39 27 52 0 4 29 0 266 0 0 0 100 5 0 0 0 146 26 165 0 5 29 0 9 0 0 0 100 6 0 0 0 120 33 180 1 5 30 0 1208 0 0 0 100 7 0 0 0 210 102 52 1 3 30 0 300 0 0 0 100 April 1, 2026 at 06:59:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2302 201 6 0 1 1 0 0 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 12 2 8 0 2 0 0 301 0 0 0 100 3 0 0 7 11 3 6 0 0 0 0 554 0 0 0 100 4 0 0 14 8 3 4 1 0 0 0 266 0 0 0 100 5 0 0 0 125 27 118 0 3 0 0 11 0 0 0 100 6 0 0 0 67 7 88 1 3 0 0 1210 0 0 0 100 7 0 0 1 268 128 66 0 1 0 0 300 0 0 0 100 April 1, 2026 at 06:59:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 106 0 1 2 0 3 0 0 0 100 1 0 0 0 9 2 4 0 0 0 0 1 0 0 0 100 2 0 0 0 25 8 26 0 0 0 0 337 0 0 0 100 3 1 0 7 13 4 10 0 0 1 0 558 0 0 0 100 4 0 0 14 8 3 6 0 1 0 0 266 0 0 0 100 5 0 0 0 118 55 114 0 1 1 0 24 0 0 0 100 6 0 0 0 23 1 50 1 1 0 0 1220 0 0 0 100 7 0 0 1 217 103 8 0 1 0 0 303 0 0 0 100 April 1, 2026 at 06:59:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2306 202 108 0 0 0 0 1 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 22 7 16 1 0 0 0 310 0 0 0 100 3 0 0 7 11 3 6 1 0 0 0 554 0 0 0 100 4 0 0 14 8 3 4 0 0 0 0 266 0 0 0 100 5 0 0 0 111 53 108 0 1 0 0 2 0 0 0 100 6 0 0 0 21 2 44 1 0 0 0 1209 0 0 0 100 7 0 0 0 209 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2311 203 128 0 1 0 0 10 0 0 0 100 1 0 0 0 12 2 4 0 0 1 0 0 0 0 0 100 2 0 0 0 27 9 20 0 0 1 0 309 0 0 0 100 3 0 0 7 21 4 20 0 1 1 0 577 0 0 0 100 4 0 0 14 11 4 4 0 0 1 0 266 0 0 0 100 5 0 0 0 133 63 122 0 0 1 0 13 0 0 0 100 6 0 0 0 25 2 46 1 0 4 0 1210 0 0 0 100 7 0 0 7 218 102 12 1 1 3 0 300 0 0 0 100 April 1, 2026 at 06:59:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 106 0 0 0 0 0 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 22 7 16 0 0 0 0 309 0 0 0 100 3 0 0 7 10 3 6 0 0 0 0 554 0 0 0 100 4 0 0 14 8 3 4 1 0 0 0 266 0 0 0 100 5 0 0 0 113 54 110 0 1 0 0 3 0 0 0 100 6 0 0 0 18 1 42 0 0 0 0 1209 0 0 0 100 7 0 0 1 213 102 6 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2302 201 104 0 0 0 0 0 0 0 0 100 1 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 2 0 0 0 21 7 16 0 0 0 0 309 0 0 0 100 3 0 0 7 10 3 6 0 0 0 0 554 0 0 0 100 4 0 0 14 9 3 4 0 0 0 0 266 0 0 0 100 5 0 0 0 109 52 106 0 1 0 0 0 0 0 0 100 6 0 0 0 19 1 42 1 0 1 0 1208 0 0 0 100 7 0 0 1 209 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 06:59:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 6 0 402 2882 203 1670 660 233 40 0 6863 24 3 0 74 1 888 0 0 785 7 1952 764 255 79 0 7778 23 3 0 74 2 60 0 0 806 13 1951 758 252 53 0 7343 24 2 0 74 3 12 0 7 772 18 1903 755 246 63 0 7668 24 2 0 74 4 261 0 14 698 12 1715 667 238 64 0 7056 24 2 0 74 5 1875 0 0 663 13 1714 648 268 75 1 7275 23 3 0 74 6 27 0 0 712 9 1936 711 296 50 0 8001 23 3 0 74 7 744 0 4 955 104 1830 747 243 55 0 6920 23 2 0 74 April 1, 2026 at 07:00:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 10 0 1 0 0 0 0 0 0 100 1 0 0 0 110 4 102 0 3 0 0 0 0 0 0 100 2 0 0 0 10 1 4 0 1 0 0 300 0 0 0 100 3 0 0 7 26 10 22 0 1 1 0 562 0 0 0 100 4 2 0 14 32 10 30 0 5 0 0 267 0 0 0 100 5 0 0 0 93 42 89 0 2 0 0 0 0 0 0 100 6 0 0 0 13 2 38 1 1 1 0 1231 0 0 0 100 7 0 0 1 211 102 2 1 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2312 204 31 0 2 0 0 10 0 0 0 100 1 0 0 0 109 2 106 0 1 0 0 1 0 0 0 100 2 0 0 0 12 2 8 0 0 0 0 300 0 0 0 100 3 0 0 7 29 10 32 0 0 0 0 583 0 0 0 100 4 1 0 14 10 4 6 1 0 0 0 268 0 0 0 100 5 0 0 0 137 63 120 0 1 1 0 14 0 0 0 100 6 0 0 0 14 1 38 1 1 3 0 1229 0 0 0 99 7 0 0 1 216 102 14 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2306 202 10 0 0 0 0 0 0 0 0 100 1 0 0 0 112 1 108 0 1 0 0 0 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 3 0 0 7 24 10 22 0 1 0 0 561 0 0 0 100 4 0 0 14 8 2 4 0 0 1 0 266 0 0 0 100 5 0 0 0 111 51 108 0 1 0 0 0 0 0 0 100 6 0 0 0 13 2 36 1 0 0 0 1231 0 0 0 99 7 0 0 0 209 102 2 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 14979 0 427 2587 207 2207 525 557 2894 26 10167 36 8 0 56 1 14481 0 9 413 8 2491 501 676 2805 24 8722 20 7 0 73 2 7824 0 20 287 28 1275 181 284 281 17 6357 30 3 0 67 3 14423 0 23 451 19 3048 616 755 1161 22 9160 20 8 0 72 4 7513 0 28 307 16 1734 283 426 365 29 6888 24 4 0 72 5 14696 0 2 445 14 2554 511 679 3063 15 6960 17 7 0 76 6 8659 0 2 264 2 844 187 226 2652 20 6762 41 6 0 54 7 16903 0 3 563 108 2509 547 711 3038 18 10250 31 8 0 61 April 1, 2026 at 07:00:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 31 0 143 2386 204 1311 103 282 1879 1 3418 5 2 0 93 1 2 0 0 196 4 1218 97 250 1789 5 4973 6 2 0 92 2 43 0 7 105 3 1301 112 307 1983 2 3666 5 2 0 93 3 38 0 7 325 158 1144 125 265 1775 1 3068 6 2 0 92 4 25 0 28 198 126 999 65 200 1844 8 4181 5 3 0 92 5 0 0 9 139 8 1362 96 284 2089 5 4370 4 4 0 93 6 7 0 0 157 8 975 81 182 1824 8 4595 7 2 0 90 7 43 0 4 316 110 1386 87 261 2096 2 4127 4 2 0 94 April 1, 2026 at 07:00:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 203 108 0 0 0 0 0 0 0 0 100 1 0 0 0 14 2 36 5 1 0 0 1431 0 0 0 99 2 0 0 0 12 1 6 0 1 0 0 1 0 0 0 100 3 0 0 7 10 2 4 0 0 0 0 263 0 0 0 100 4 0 0 14 11 2 6 1 2 0 0 266 0 0 0 100 5 0 0 7 22 2 20 0 0 1 0 312 0 0 0 100 6 0 0 0 10 1 4 0 1 0 0 0 0 0 0 100 7 0 0 1 329 159 124 0 0 0 0 320 0 0 0 100 April 1, 2026 at 07:00:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2326 203 128 1 1 1 0 14 0 0 0 100 1 0 0 0 35 3 42 0 0 2 0 1431 0 0 0 100 2 0 0 0 31 3 6 0 0 1 0 5 0 0 0 100 3 0 0 7 39 5 18 0 0 1 0 277 0 0 0 100 4 0 0 21 27 3 4 0 0 1 0 266 0 0 0 100 5 0 0 112 37 10 28 0 0 2 0 307 0 0 0 100 6 0 0 0 28 2 2 0 0 1 0 0 0 0 0 100 7 0 0 7 343 158 118 0 0 1 0 309 0 0 0 100 April 1, 2026 at 07:00:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2313 207 110 0 2 0 0 1 0 0 0 100 1 0 0 0 34 12 58 1 1 0 0 1431 0 0 0 100 2 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 12 2 4 0 0 0 0 259 0 0 0 100 4 0 0 21 8 2 4 0 0 0 0 266 0 0 0 100 5 0 0 0 18 2 14 0 2 0 0 294 0 0 0 100 6 0 0 0 12 1 4 0 1 0 0 0 0 0 0 100 7 0 0 1 306 147 96 0 2 0 0 309 0 0 0 100 April 1, 2026 at 07:00:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 5 2312 205 175 0 13 275 0 113 0 2 0 98 1 0 0 0 165 54 263 2 26 547 0 1498 0 1 0 99 2 0 0 0 35 4 52 0 11 201 0 27 0 1 0 99 3 0 0 7 55 14 105 0 30 477 0 377 0 0 0 99 4 26 0 14 49 18 64 0 10 487 0 304 0 1 0 99 5 0 0 0 40 3 69 2 14 454 0 1114 0 1 0 99 6 0 0 0 44 1 71 0 15 437 1 833 0 1 0 99 7 9 0 1 243 105 65 0 11 421 0 379 0 1 0 99 April 1, 2026 at 07:00:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2319 203 409 1 77 1558 0 0 0 1 0 99 1 0 0 0 124 6 660 2 85 1506 1 1431 0 1 0 98 2 0 0 0 218 36 468 1 73 1250 0 1 0 1 0 99 3 0 0 7 236 97 518 1 74 1812 0 260 0 1 0 99 4 0 0 14 178 92 411 4 71 1670 3 275 0 1 0 99 5 0 0 0 164 5 383 1 72 1684 0 294 0 1 0 99 6 0 0 0 124 0 389 1 76 1508 0 0 0 1 0 99 7 0 0 0 307 103 378 3 71 1571 0 302 0 1 0 99 April 1, 2026 at 07:00:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 203 6 0 0 0 0 0 0 0 0 100 1 0 0 0 10 2 34 1 0 0 0 1431 0 0 0 100 2 0 0 0 115 32 110 0 3 0 0 5 0 0 0 100 3 0 0 7 38 15 32 0 2 0 0 260 0 0 0 100 4 0 0 14 90 15 86 0 2 0 0 275 0 0 0 100 5 0 0 0 15 3 11 0 1 0 0 294 0 0 0 100 6 0 0 0 9 1 4 0 1 0 0 1 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2312 205 26 0 0 1 0 23 0 0 0 100 1 0 0 0 18 3 46 0 1 0 0 1431 0 0 0 100 2 0 0 0 108 50 102 0 1 0 0 0 0 0 0 100 3 0 0 8 16 3 18 0 0 0 0 270 0 0 0 100 4 0 0 14 118 8 114 0 0 0 0 290 0 0 0 100 5 0 0 0 33 9 24 0 0 0 0 306 0 0 0 100 6 0 0 0 8 0 2 0 1 0 0 0 0 0 0 100 7 0 0 1 216 103 10 0 1 0 0 302 0 0 0 100 April 1, 2026 at 07:00:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 5 2307 203 14 0 0 0 0 9 0 0 0 100 1 4 0 0 27 8 52 1 1 3 0 1447 0 0 0 100 2 0 0 0 114 52 114 0 1 2 0 2 0 0 0 100 3 0 0 7 11 2 8 0 0 0 0 264 0 0 0 100 4 0 0 14 115 5 112 1 0 0 0 277 0 0 0 100 5 0 0 0 19 2 14 0 0 0 0 294 0 0 0 100 6 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 7 0 0 1 214 103 10 0 0 0 0 333 0 0 0 100 April 1, 2026 at 07:00:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 203 6 0 0 0 0 0 0 0 0 100 1 0 0 0 17 5 40 1 0 0 0 1436 0 0 0 100 2 0 0 0 40 12 34 0 3 0 0 2 0 0 0 100 3 0 0 7 88 16 88 0 3 0 0 263 0 0 0 100 4 0 0 14 65 11 62 0 3 0 0 280 0 0 0 100 5 0 0 0 77 25 74 1 3 1 0 297 0 0 0 100 6 0 0 0 9 0 4 0 0 1 0 3 0 0 0 100 7 0 0 1 220 105 16 1 0 0 0 307 0 0 0 100 April 1, 2026 at 07:00:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 203 6 0 0 0 0 0 0 0 0 100 1 0 0 0 14 4 40 1 1 0 0 1420 0 0 0 100 2 0 0 0 15 3 10 0 2 0 0 26 0 0 0 100 3 0 0 7 111 3 108 0 1 0 0 261 0 0 0 100 4 21 0 14 23 10 18 0 0 0 0 285 0 0 0 100 5 0 0 0 123 54 118 0 0 0 0 300 0 0 0 100 6 0 0 0 9 1 2 0 0 0 0 5 0 0 0 100 7 0 0 1 214 104 8 0 1 0 0 301 0 0 0 100 April 1, 2026 at 07:00:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 203 10 0 1 0 0 0 0 0 0 100 1 0 0 0 10 2 36 0 1 0 0 1414 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 7 114 39 109 0 6 0 0 260 0 0 0 100 4 0 0 14 95 17 92 0 4 0 0 273 0 0 0 100 5 0 0 0 44 7 34 0 4 0 0 294 0 0 0 100 6 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 7 0 0 1 214 103 6 0 0 0 0 302 0 0 0 100 April 1, 2026 at 07:00:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2308 203 21 1 1 0 0 7 0 0 0 100 1 0 0 0 15 3 36 1 0 1 0 1413 0 0 0 100 2 0 0 0 16 4 9 0 1 1 0 2 0 0 0 100 3 0 0 7 124 37 122 0 5 1 0 271 0 0 0 100 4 0 0 14 93 13 82 1 4 1 0 275 0 0 0 100 5 0 0 0 65 26 56 0 2 1 0 317 0 0 0 100 6 0 0 0 12 1 6 0 1 1 0 9 0 0 0 100 7 0 0 7 214 102 6 0 0 1 0 300 0 0 0 100 April 1, 2026 at 07:00:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 203 10 0 0 0 0 1 0 0 0 100 1 0 0 0 10 2 36 1 1 1 0 1415 0 0 0 100 2 0 0 0 23 4 14 0 1 0 0 4 0 0 0 100 3 0 0 7 11 2 6 0 1 0 0 260 0 0 0 100 4 0 0 14 20 8 16 0 0 0 0 272 0 0 0 100 5 0 0 0 115 38 112 1 5 0 0 295 0 0 0 100 6 0 0 0 102 14 94 0 4 0 0 0 0 0 0 100 7 0 0 1 214 103 6 1 0 0 0 302 0 0 0 100 April 1, 2026 at 07:00:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 203 10 0 0 0 0 0 0 0 0 100 1 0 0 0 12 2 36 1 0 0 0 1415 0 0 0 100 2 0 0 0 17 2 12 0 0 0 0 5 0 0 0 100 3 0 0 7 13 4 12 0 1 0 0 260 0 0 0 100 4 0 0 14 22 9 20 0 0 0 0 282 0 0 0 100 5 0 0 0 118 37 113 0 3 1 0 297 0 0 0 100 6 0 0 0 110 15 106 0 4 3 0 3 0 0 0 100 7 0 0 1 213 102 10 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 203 40 0 1 0 0 0 0 0 0 100 1 0 0 0 10 2 32 0 0 0 0 1114 0 0 0 100 2 0 0 0 14 0 10 0 1 0 0 300 0 0 0 100 3 0 0 7 10 3 6 0 0 0 0 260 0 0 0 100 4 0 0 14 20 9 16 0 0 0 0 273 0 0 0 100 5 0 0 0 112 32 109 0 4 0 0 294 0 0 0 100 6 0 0 0 76 20 66 0 3 0 0 0 0 0 0 100 7 0 0 1 212 103 6 0 0 0 0 302 0 0 0 100 April 1, 2026 at 07:00:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 203 108 0 0 0 0 0 0 0 0 100 1 0 0 0 8 1 32 1 0 0 0 1115 0 0 0 100 2 0 0 0 19 3 14 0 0 0 0 305 0 0 0 100 3 0 0 7 12 4 8 0 0 0 0 261 0 0 0 100 4 0 0 14 18 8 14 1 0 0 0 275 0 0 0 100 5 0 0 0 111 52 106 0 0 0 0 294 0 0 0 100 6 0 0 0 11 1 4 0 0 0 0 1 0 0 0 100 7 0 0 1 211 102 8 0 2 1 0 300 0 0 0 100 April 1, 2026 at 07:00:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 203 112 0 0 0 0 0 0 0 0 100 1 0 0 0 14 2 38 1 1 0 0 1115 0 0 0 100 2 0 0 0 17 2 14 0 1 0 0 301 0 0 0 100 3 0 0 7 21 6 22 0 0 0 0 286 0 0 0 100 4 0 0 14 18 8 14 0 0 0 0 273 0 0 0 100 5 0 0 0 124 58 116 1 0 0 0 299 0 0 0 100 6 0 0 0 11 0 8 0 0 0 0 12 0 0 0 100 7 0 0 1 218 103 12 1 2 0 0 302 0 0 0 100 April 1, 2026 at 07:00:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 112 0 11 2382 216 22952 105 415 275 0 61496 19 12 0 69 1 10 0 0 444 7 20788 90 359 185 0 44520 16 10 0 74 2 45 0 0 1064 13 22644 73 245 214 0 45797 15 10 0 75 3 27 0 0 566 7 21567 58 193 217 0 45361 15 10 0 75 4 7 0 14 249 12 20118 36 136 227 0 45223 15 9 0 76 5 24 0 0 537 17 17259 21 105 175 0 43273 12 8 0 80 6 202 0 0 162 15 12692 30 93 74 1 26709 9 6 0 85 7 3 0 3 898 109 13480 23 77 141 0 37238 12 7 0 81 April 1, 2026 at 07:00:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 3 0 10 2374 239 8396 28 153 481 0 20707 6 4 0 89 1 8 0 0 64 5 7012 21 124 361 0 14830 5 4 0 91 2 12 0 0 52 6 5808 17 97 424 0 14641 5 4 0 91 3 2 0 0 130 21 6932 11 77 275 0 15804 5 4 0 92 4 6 0 14 52 15 4294 8 53 183 0 9877 3 3 0 94 5 0 0 0 46 12 3182 3 37 301 0 6581 2 2 0 96 6 5 0 0 75 13 4725 10 50 381 0 10671 4 3 0 93 7 14 0 4 261 107 5962 5 51 337 0 11615 4 3 0 93 April 1, 2026 at 07:00:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2335 230 367 0 40 787 0 259 0 1 0 99 1 0 0 0 125 14 373 2 42 829 0 1124 0 1 0 99 2 0 0 0 113 2 315 0 49 718 0 2 0 0 0 100 3 0 0 0 198 76 280 1 36 709 1 301 0 0 0 99 4 0 0 14 186 65 262 1 40 751 0 266 0 0 0 100 5 0 0 0 129 3 280 0 40 867 2 2 0 0 0 100 6 0 0 0 124 7 247 0 26 782 0 303 0 0 0 99 7 0 0 0 315 105 403 0 46 674 1 301 0 1 0 99 April 1, 2026 at 07:00:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2360 254 110 0 1 0 0 260 0 0 0 100 1 0 0 0 8 1 32 1 0 0 0 1123 0 0 0 100 2 0 0 0 10 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 10 2 4 0 0 0 0 300 0 0 0 100 4 0 0 14 14 2 12 0 2 0 0 266 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 6 0 0 0 19 6 12 0 0 0 0 302 0 0 0 100 7 0 0 1 314 104 108 0 0 0 0 302 0 0 0 100 April 1, 2026 at 07:00:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2343 241 121 0 1 1 0 261 0 0 0 100 1 0 0 0 39 15 62 1 2 1 0 1123 0 0 0 100 2 0 0 0 17 5 10 0 0 1 0 5 0 0 0 100 3 0 0 0 20 3 16 0 0 1 0 320 0 0 0 100 4 0 0 14 21 3 18 0 1 1 0 266 0 0 0 100 5 0 0 0 29 13 22 0 1 1 0 12 0 0 0 100 6 0 0 0 27 8 22 1 0 1 0 312 0 0 0 100 7 0 0 1 288 103 80 0 0 1 0 300 0 0 0 100 April 1, 2026 at 07:00:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2310 204 114 0 0 0 0 263 0 0 0 100 1 0 0 0 108 51 132 1 0 0 0 1123 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 14 14 2 10 0 1 1 0 266 0 0 0 100 5 0 0 0 13 1 12 0 1 2 0 0 0 0 0 100 6 0 0 0 29 10 22 1 0 0 0 307 0 0 0 100 7 0 0 1 217 104 8 1 1 0 0 302 0 0 0 100 April 1, 2026 at 07:00:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2310 204 116 0 0 0 0 260 0 0 0 100 1 0 0 0 108 51 132 1 0 0 0 1123 0 0 0 100 2 0 0 0 12 2 10 0 1 0 0 8 0 0 0 100 3 0 0 0 13 3 8 1 0 0 0 300 0 0 0 100 4 0 0 14 11 3 6 1 0 0 0 266 0 0 0 100 5 0 0 0 11 2 8 0 0 0 0 4 0 0 0 100 6 0 0 0 34 12 26 0 0 0 0 313 0 0 0 100 7 0 0 1 213 102 10 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2308 204 122 0 1 0 0 260 0 0 0 100 1 0 0 0 108 51 132 1 0 0 0 1122 0 0 0 100 2 0 0 0 9 1 4 0 0 0 0 1 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 14 9 3 4 0 0 0 0 266 0 0 0 100 5 0 0 0 9 1 4 0 1 1 0 0 0 0 0 100 6 0 0 0 22 7 16 0 1 0 0 303 0 0 0 100 7 0 0 1 213 103 8 0 1 1 0 302 0 0 0 100 April 1, 2026 at 07:00:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2308 204 120 0 0 0 0 260 0 0 0 100 1 0 0 0 111 51 136 1 1 0 0 1123 0 0 0 100 2 0 0 0 11 2 6 0 0 0 0 5 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 4 0 0 14 8 3 4 0 0 0 0 266 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 6 0 0 0 23 8 16 0 0 0 0 304 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:00:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2306 204 118 0 0 0 0 260 0 0 0 100 1 0 0 0 13 4 36 0 0 0 0 1124 0 0 0 100 2 0 0 0 104 48 100 0 1 0 0 0 0 0 0 100 3 0 0 0 16 3 16 0 0 0 0 321 0 0 0 100 4 0 0 14 8 3 6 0 1 0 0 266 0 0 0 100 5 0 0 0 26 11 18 0 0 0 0 10 0 0 0 100 6 1 0 0 26 7 22 1 0 0 0 312 0 0 0 100 7 0 0 1 216 103 10 1 0 0 0 302 0 0 0 100 April 1, 2026 at 07:00:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1108 0 668 2369 211 1173 42 155 21 1 5123 24 2 0 74 1 10 0 0 420 12 1286 43 181 19 1 7111 21 2 0 77 2 14 0 0 444 27 1066 28 148 10 0 5012 18 2 0 80 3 9 0 0 394 13 963 61 146 15 0 5211 23 2 0 76 4 4 0 14 543 12 974 42 129 18 0 6412 19 1 0 80 5 4 0 0 497 13 1070 29 126 8 0 6240 14 1 0 84 6 3 0 0 567 8 1212 36 123 15 0 7359 14 1 0 85 7 1 0 4 620 105 1218 30 124 17 0 7108 13 1 0 85 April 1, 2026 at 07:00:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 388 2356 214 834 23 108 6 0 3581 16 1 0 82 1 2 0 0 161 8 953 17 125 12 0 5711 10 1 0 89 2 2 0 0 319 28 744 17 87 7 0 3264 13 1 0 86 3 2 0 0 344 8 516 10 87 8 0 3372 12 1 0 88 4 0 0 14 289 9 542 19 77 7 0 3091 14 1 0 85 5 3 0 0 332 7 629 10 75 6 0 3859 10 1 0 89 6 0 0 0 366 5 650 11 68 3 0 3831 9 1 0 90 7 1 0 4 491 110 652 15 60 7 0 3787 11 1 0 88 April 1, 2026 at 07:00:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2315 207 122 1 0 0 0 577 0 0 0 99 1 3 0 0 20 5 48 1 3 0 0 1143 0 0 0 100 2 0 0 0 108 51 104 0 1 0 0 22 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 9 0 0 0 100 4 2 0 14 14 5 10 0 0 0 0 268 0 0 0 100 5 6 0 0 20 6 14 1 0 0 0 313 0 0 0 100 6 0 0 0 22 3 16 0 1 0 0 299 0 0 0 100 7 0 0 1 213 103 8 0 0 0 0 4 0 0 0 100 April 1, 2026 at 07:00:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2326 210 130 0 0 0 0 572 0 0 0 100 1 0 0 0 16 2 38 1 1 0 0 1129 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 11 4 8 0 0 0 0 266 0 0 0 100 5 0 0 0 15 4 12 0 0 0 0 321 0 0 0 100 6 0 0 0 15 1 6 0 0 0 0 294 0 0 0 100 7 0 0 1 221 104 18 0 0 1 0 11 0 0 0 100 April 1, 2026 at 07:00:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 13 0 14 2333 209 185 1 11 9 4 662 0 1 0 99 1 2 0 0 33 3 46 0 4 13 1 1141 0 0 0 100 2 1479 0 114 52 11 69 1 3 5 10 6597 1 1 0 98 3 150 0 0 136 41 159 0 12 8 14 198 0 0 0 100 4 17 0 14 45 5 38 1 6 5 5 380 0 0 0 100 5 32 0 3 52 13 45 0 5 10 5 428 0 0 0 100 6 1925 0 0 49 2 43 3 6 12 5 689 0 1 0 99 7 8 0 7 253 105 48 0 7 14 5 68 0 0 0 100 April 1, 2026 at 07:00:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 82 2351 212 841 32 78 27 0 2374 2 1 0 97 1 0 0 0 364 2 808 22 48 7 1 2840 1 1 0 98 2 64 0 7 30 0 33 3 4 125 1 3106 2 1 0 97 3 0 0 0 103 31 119 5 8 92 5 2805 2 1 0 98 4 0 0 14 199 4 679 20 51 24 0 2032 1 0 0 98 5 3 0 0 43 2 45 3 5 157 3 3173 2 1 0 97 6 0 0 0 343 20 634 14 40 42 3 2224 1 0 0 98 7 0 0 9 531 103 657 22 50 21 0 1616 1 2 0 97 April 1, 2026 at 07:00:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2325 210 203 0 15 378 0 569 0 1 0 99 1 0 0 0 39 2 87 1 12 208 0 1122 0 1 0 99 2 0 0 0 29 0 52 0 10 309 0 0 0 1 0 99 3 0 0 0 36 12 41 0 9 226 0 0 0 1 0 99 4 3 0 21 48 18 54 0 9 296 0 281 0 1 0 99 5 0 0 0 30 2 44 0 10 286 0 300 0 1 0 99 6 0 0 0 124 51 134 0 7 335 0 294 0 1 0 99 7 0 0 0 248 102 92 0 14 290 0 0 0 0 0 100 April 1, 2026 at 07:00:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 122 2336 215 560 0 75 1515 0 568 0 2 0 98 1 0 0 0 239 34 486 0 58 1441 1 1118 0 1 0 99 2 0 0 0 174 0 403 0 67 1381 0 0 0 1 0 99 3 0 0 0 216 82 371 0 54 1612 0 0 0 1 0 99 4 0 0 14 153 87 410 0 58 1601 0 271 0 1 0 99 5 0 0 0 155 2 433 0 66 1610 1 300 0 1 0 99 6 0 0 0 172 13 442 0 68 1383 1 294 0 1 0 99 7 0 0 4 369 103 574 0 65 1326 0 2 0 1 0 99 April 1, 2026 at 07:00:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 19 2322 210 134 0 0 0 0 570 0 0 0 99 1 0 0 0 113 52 134 1 0 0 0 1120 0 0 0 100 2 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 11 4 6 1 0 0 0 266 0 0 0 100 5 0 0 0 10 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 12 2 6 0 1 0 0 295 0 0 0 100 7 0 0 1 213 103 6 0 0 0 0 1 0 0 0 100 April 1, 2026 at 07:00:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2326 211 167 2 4 8 0 1514 0 1 0 99 1 0 0 0 115 52 146 1 3 0 0 1157 0 0 0 100 2 0 0 0 18 1 22 0 1 0 0 97 0 0 0 100 3 0 0 0 21 1 24 1 1 2 0 42 0 0 0 100 4 0 0 14 18 6 16 0 2 0 0 284 0 0 0 100 5 0 0 0 26 9 20 0 3 5 0 1121 0 0 0 100 6 0 0 0 21 2 26 1 2 0 0 321 0 0 0 100 7 0 0 0 234 106 37 0 2 6 0 69 0 0 0 100 April 1, 2026 at 07:00:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2313 204 118 0 0 0 0 563 0 0 0 100 1 0 0 0 112 52 134 1 0 1 0 1119 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 3 0 0 0 17 6 12 0 0 0 0 9 0 0 0 100 4 0 0 14 13 5 10 0 0 0 0 267 0 0 0 100 5 0 0 0 15 3 170 1 0 0 0 631 0 0 0 100 6 0 0 0 13 2 10 0 1 2 0 294 0 0 0 100 7 0 0 1 211 102 8 0 1 0 0 2 0 0 0 100 April 1, 2026 at 07:00:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2312 204 120 0 0 0 0 566 0 0 0 100 1 0 0 0 113 53 138 1 0 0 0 1119 0 0 0 100 2 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 3 0 0 0 19 7 14 0 0 0 0 10 0 0 0 100 4 0 0 14 16 6 14 0 0 0 0 269 0 0 0 100 5 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 6 0 0 0 10 1 6 0 0 0 0 294 0 0 0 100 7 0 0 1 216 103 14 0 0 0 0 4 0 0 0 100 April 1, 2026 at 07:00:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2306 203 118 0 0 0 0 560 0 0 0 99 1 0 0 0 19 7 42 0 0 0 0 1120 0 0 0 100 2 0 0 0 98 46 94 0 1 0 0 0 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 12 0 0 0 100 4 0 0 14 14 6 10 1 0 0 0 269 0 0 0 100 5 0 0 0 11 3 6 0 0 0 0 301 0 0 0 100 6 0 0 0 11 1 6 0 0 1 0 294 0 0 0 100 7 0 0 0 222 106 20 0 1 0 0 4 0 0 0 100 April 1, 2026 at 07:00:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2310 203 118 1 0 0 0 561 0 0 0 100 1 0 0 0 11 2 36 1 1 1 0 1118 0 0 0 100 2 0 0 0 107 50 106 0 1 0 0 33 0 0 0 100 3 0 0 0 24 7 22 0 0 0 0 16 0 0 0 100 4 0 0 14 17 6 16 0 1 0 0 281 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 14 2 10 1 0 0 0 315 0 0 0 100 7 0 0 1 215 103 10 0 1 2 0 3 0 0 0 100 April 1, 2026 at 07:00:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 14 2310 203 141 1 2 1 0 568 0 0 0 100 1 0 0 0 13 3 34 1 0 1 0 1120 0 0 0 100 2 0 0 0 108 51 100 0 0 1 0 0 0 0 0 100 3 0 0 0 10 1 6 0 0 1 0 7 0 0 0 100 4 0 0 14 16 6 8 0 0 1 0 267 0 0 0 100 5 0 0 0 24 11 10 1 0 1 0 304 0 0 0 100 6 0 0 0 30 9 24 0 0 1 0 318 0 0 0 100 7 0 0 7 227 105 25 0 1 1 0 32 0 0 0 100 April 1, 2026 at 07:00:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 11 2308 203 118 0 0 0 0 560 0 0 0 100 1 0 0 0 9 2 34 0 0 0 0 1119 0 0 0 100 2 0 0 0 112 50 110 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 5 0 0 0 100 4 0 0 14 14 6 10 0 0 0 0 271 0 0 0 100 5 19 0 0 11 3 6 0 0 0 0 305 0 0 0 100 6 0 0 0 9 1 4 0 0 0 0 294 0 0 0 100 7 0 0 2 224 109 18 0 0 0 0 11 0 0 0 100 April 1, 2026 at 07:00:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2310 204 118 0 0 0 0 560 0 0 0 100 1 0 0 0 15 3 40 1 0 0 0 1114 0 0 0 100 2 0 0 0 107 50 102 0 0 0 0 0 0 0 0 100 3 0 0 0 9 0 8 0 1 0 0 0 0 0 0 100 4 0 0 14 11 4 8 1 0 0 0 265 0 0 0 100 5 0 0 0 10 2 6 0 0 0 0 300 0 0 0 100 6 0 0 0 10 1 4 0 0 1 0 294 0 0 0 100 7 0 0 1 225 108 24 0 1 1 0 9 0 0 0 100 April 1, 2026 at 07:00:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2310 203 118 1 0 0 0 561 0 0 0 100 1 0 0 0 10 2 34 1 0 0 0 1113 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 14 6 10 0 0 0 0 268 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 10 1 4 1 0 0 0 294 0 0 0 100 7 0 0 1 224 109 18 0 0 0 0 11 0 0 0 100 April 1, 2026 at 07:00:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2308 203 116 0 0 0 0 560 0 0 0 100 1 0 0 0 10 2 34 0 0 0 0 1116 0 0 0 100 2 0 0 0 105 50 102 0 1 0 0 0 0 0 0 100 3 0 0 0 7 0 2 0 1 1 0 0 0 0 0 100 4 0 0 14 13 5 12 0 1 0 0 267 0 0 0 100 5 0 0 0 10 2 4 1 0 0 0 300 0 0 0 100 6 0 0 0 11 2 4 0 0 0 0 295 0 0 0 100 7 0 0 0 222 108 16 0 0 0 0 9 0 0 0 100 April 1, 2026 at 07:00:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 12 2315 206 140 1 1 0 0 583 0 0 0 100 1 0 0 0 12 2 38 1 1 1 0 1123 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 16 6 12 0 1 0 0 268 0 0 0 100 5 0 0 0 18 8 10 0 1 1 0 303 0 0 0 100 6 0 0 0 13 1 12 0 0 0 0 305 0 0 0 100 7 0 0 1 237 112 32 0 0 0 0 21 0 0 0 100 April 1, 2026 at 07:00:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2308 203 116 0 0 0 0 560 0 0 0 100 1 0 0 0 10 2 34 1 0 0 0 1114 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 1 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 11 4 6 1 0 0 0 266 0 0 0 100 5 0 0 0 9 2 6 0 1 0 0 300 0 0 0 100 6 0 0 0 9 1 2 0 0 0 0 294 0 0 0 100 7 0 0 1 224 109 18 0 0 0 0 10 0 0 0 100 April 1, 2026 at 07:00:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 13 2311 204 120 2 0 0 0 562 0 0 0 100 1 0 0 0 16 4 40 1 0 0 0 1138 0 0 0 100 2 0 0 0 105 50 100 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 14 18 8 16 0 1 0 0 274 0 0 0 100 5 0 0 0 11 2 6 0 1 0 0 300 0 0 0 100 6 0 0 0 11 1 4 1 1 0 0 294 0 0 0 100 7 0 0 0 224 108 22 0 0 0 0 11 0 0 0 100 April 1, 2026 at 07:00:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2308 203 118 0 0 0 0 560 0 0 0 100 1 0 0 0 12 3 36 0 0 0 0 1116 0 0 0 100 2 0 0 0 108 51 102 0 0 0 0 21 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 4 0 0 14 12 5 8 0 0 0 0 267 0 0 0 100 5 0 0 0 12 3 6 1 0 0 0 301 0 0 0 100 6 0 0 0 11 1 6 0 2 0 0 294 0 0 0 100 7 0 0 1 225 109 20 0 1 1 0 10 0 0 0 100 April 1, 2026 at 07:00:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 263 0 12 2327 205 7949 35 133 59 0 23651 7 5 0 87 1 6 0 0 979 2 9112 28 91 39 0 18923 6 4 0 90 2 0 0 0 1174 33 10758 26 56 53 0 20333 6 4 0 89 3 102 0 0 867 1 4653 11 48 53 0 16208 5 3 0 92 4 36 0 14 201 6 6132 14 37 28 0 12989 5 3 0 92 5 36 0 0 480 4 8580 13 32 122 0 20897 6 4 0 90 6 53 0 0 398 3 8898 10 29 116 0 20320 7 4 0 89 7 315 0 1 606 124 5522 10 26 69 1 15372 5 4 0 91 April 1, 2026 at 07:00:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 104 0 3 2350 209 22165 74 347 353 0 58680 19 11 0 70 1 14 0 0 92 19 20113 56 274 166 0 39280 14 9 0 78 2 11 0 0 79 14 18164 46 229 166 0 40341 14 9 0 77 3 15 0 7 67 14 17068 26 169 118 0 33928 11 8 0 81 4 14 0 14 53 15 14113 20 98 111 0 28328 9 6 0 85 5 10 0 0 75 25 15413 13 83 157 0 34499 11 7 0 81 6 3 0 0 84 22 14117 25 85 189 0 33633 10 6 0 84 7 34 0 4 262 109 14865 16 74 175 0 38632 10 7 0 82 April 1, 2026 at 07:00:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 102 0 0 0 0 300 0 0 0 100 1 0 0 0 19 7 44 0 0 0 0 1132 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 4 0 0 14 17 7 10 0 0 0 0 269 0 0 0 100 5 0 0 0 13 2 6 0 0 0 0 300 0 0 0 100 6 0 0 0 119 50 118 0 4 0 0 0 0 0 0 100 7 0 0 1 214 104 8 0 0 0 0 296 0 0 0 100 April 1, 2026 at 07:00:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 201 188 0 26 349 0 300 0 1 0 99 1 0 0 0 49 8 111 2 11 330 0 1131 0 1 0 99 2 0 0 0 29 0 59 0 18 278 0 17 0 1 0 99 3 0 0 7 46 14 56 0 13 309 0 260 0 1 0 99 4 0 0 14 46 16 63 0 15 328 0 267 0 1 0 99 5 0 0 0 34 2 59 0 11 348 0 300 0 1 0 99 6 0 0 0 136 50 159 0 8 307 0 0 0 1 0 99 7 0 0 1 252 104 106 1 17 338 0 252 0 0 0 100 April 1, 2026 at 07:00:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2355 243 473 1 61 772 0 300 0 1 0 99 1 0 0 0 121 7 323 3 33 734 0 1132 0 1 0 99 2 0 0 0 116 1 238 2 34 676 0 294 0 0 0 100 3 0 0 7 170 66 251 2 44 642 0 260 0 0 0 100 4 0 0 14 158 69 261 2 40 576 0 271 0 0 0 100 5 0 0 0 125 2 270 1 43 691 0 299 0 0 0 99 6 0 0 0 205 8 367 0 40 721 0 0 0 0 0 100 7 0 0 2 320 103 388 2 46 561 0 2 0 0 0 100 April 1, 2026 at 07:01:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 251 106 1 0 0 0 300 0 0 0 100 1 0 0 0 25 9 50 1 0 1 0 1135 0 0 0 100 2 0 0 0 11 1 8 1 1 0 0 297 0 0 0 100 3 0 0 7 11 3 8 0 1 0 0 260 0 0 0 100 4 0 0 14 13 4 8 1 2 0 0 266 0 0 0 100 5 0 0 0 11 2 4 1 0 0 0 300 0 0 0 100 6 0 0 0 115 1 108 0 2 0 0 1 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2359 252 114 0 0 0 0 304 0 0 0 100 1 0 0 0 29 10 52 1 0 0 0 1141 0 0 0 100 2 0 0 0 11 1 10 0 0 0 0 305 0 0 0 100 3 0 0 7 19 6 18 0 0 0 0 277 0 0 0 100 4 0 0 14 27 5 28 1 1 0 0 282 0 0 0 100 5 0 0 0 19 11 6 0 0 1 0 300 0 0 0 100 6 0 0 0 109 1 104 0 0 0 0 0 0 0 0 100 7 0 0 1 217 103 14 0 0 0 0 5 0 0 0 100 April 1, 2026 at 07:01:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2355 251 108 0 0 0 0 301 0 0 0 100 1 0 0 0 20 7 44 1 0 0 0 1132 0 0 0 100 2 0 0 0 9 2 4 0 0 0 0 294 0 0 0 100 3 0 0 7 14 3 8 0 0 0 0 260 0 0 0 100 4 0 0 14 24 6 22 0 1 2 0 270 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 300 0 0 0 100 6 0 0 0 109 1 104 0 0 0 0 0 0 0 0 100 7 0 0 0 210 102 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2357 251 108 0 0 0 0 300 0 0 0 100 1 0 0 0 11 2 34 0 1 1 0 1123 0 0 0 100 2 0 0 0 18 6 16 0 2 0 0 303 0 0 0 100 3 0 0 7 13 4 8 0 0 0 0 261 0 0 0 100 4 0 0 14 25 6 22 0 0 0 0 271 0 0 0 100 5 0 0 0 12 2 10 0 1 1 0 300 0 0 0 100 6 0 0 0 110 1 104 0 0 0 0 0 0 0 0 100 7 0 0 1 215 103 12 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2356 252 110 1 0 0 0 301 0 0 0 100 1 0 0 0 10 2 34 1 0 0 0 1123 0 0 0 100 2 0 0 0 24 8 16 2 0 0 0 301 0 0 0 100 3 0 0 7 12 4 8 0 0 0 0 261 0 0 0 100 4 0 0 14 16 3 12 1 0 0 0 266 0 0 0 100 5 0 0 0 12 3 8 1 1 0 0 301 0 0 0 100 6 0 0 0 109 1 102 0 0 0 0 0 0 0 0 100 7 0 0 1 212 103 6 0 0 0 0 1 0 0 0 100 April 1, 2026 at 07:01:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 370 2367 235 691 26 84 7 0 2811 8 1 0 91 1 1056 0 0 179 2 616 35 80 16 1 4233 8 1 0 90 2 5 0 0 213 15 564 17 74 8 0 3136 8 1 0 91 3 262 0 7 255 3 361 18 56 18 0 2847 10 1 0 89 4 2 0 14 255 8 514 26 72 10 0 2701 10 1 0 89 5 3 0 0 257 4 417 9 59 3 0 2708 8 1 0 91 6 23 0 0 287 5 690 31 65 8 0 3288 7 1 0 92 7 19 0 0 389 105 492 27 46 14 0 2838 6 1 0 93 April 1, 2026 at 07:01:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 382 2368 204 1361 36 177 34 0 6122 26 2 0 71 1 0 0 0 428 9 1397 32 175 22 0 7979 22 2 0 75 2 0 0 0 316 14 1448 42 182 24 0 7118 24 2 0 74 3 5 0 7 537 7 1130 37 144 15 0 6983 19 2 0 79 4 2 0 14 626 17 1030 26 119 28 0 6394 20 1 0 79 5 0 0 0 545 31 1252 22 131 24 0 7628 17 2 0 82 6 5 0 0 465 8 1279 30 132 21 0 6784 20 2 0 78 7 0 0 2 582 110 1286 20 102 16 0 7536 18 2 0 80 April 1, 2026 at 07:01:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 33 2306 202 29 2 5 1 0 405 2 0 0 98 1 0 0 0 17 1 58 4 5 0 0 1269 0 0 0 100 2 0 0 0 126 31 147 2 10 1 0 397 1 0 0 99 3 0 0 7 100 11 108 0 7 2 0 352 1 0 0 99 4 0 0 14 66 20 81 1 7 1 0 407 0 0 0 100 5 6 0 0 16 2 13 1 2 0 0 320 2 0 0 98 6 0 0 0 36 4 29 1 4 2 0 70 1 0 0 99 7 0 0 1 229 104 23 1 4 0 0 92 1 0 0 99 April 1, 2026 at 07:01:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2313 203 32 0 2 2 0 302 0 0 0 100 1 0 0 0 11 1 34 1 1 0 0 1129 0 0 0 100 2 0 0 0 107 1 100 0 0 0 0 294 0 0 0 100 3 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 4 3 0 14 113 55 112 1 1 0 0 280 0 0 0 100 5 0 0 0 9 1 6 0 0 0 0 300 0 0 0 100 6 0 0 0 30 7 24 0 0 0 0 5 0 0 0 100 7 0 0 1 216 102 12 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 42 0 1 0 0 300 0 0 0 100 1 0 0 0 11 1 36 1 1 1 0 1129 0 0 0 100 2 0 0 0 12 3 6 0 0 0 0 296 0 0 0 100 3 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 4 0 0 14 63 7 56 0 2 0 0 266 0 0 0 100 5 0 0 0 58 25 50 0 1 0 0 300 0 0 0 100 6 0 0 0 77 31 72 0 1 0 0 8 0 0 0 100 7 0 0 1 230 103 26 0 3 0 0 2 0 0 0 100 April 1, 2026 at 07:01:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 104 1 0 0 0 300 0 0 0 100 1 0 0 0 9 1 34 0 0 1 0 1128 0 0 0 100 2 0 0 0 10 2 4 1 0 0 0 295 0 0 0 100 3 0 0 7 10 2 6 0 0 0 0 262 0 0 0 100 4 0 0 14 10 4 6 0 0 0 0 266 0 0 0 100 5 0 0 0 8 1 4 1 1 0 0 300 0 0 0 100 6 0 0 0 136 60 130 0 0 0 0 11 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 41 0 47 2361 209 977 15 86 55 7 2912 1 1 0 98 1 7 0 0 214 43 343 8 14 65 0 3683 3 1 0 96 2 3381 0 120 84 2 105 7 10 152 13 10313 4 4 0 93 3 152 0 21 108 2 163 4 20 108 7 3051 2 1 0 97 4 41 0 15 360 5 775 8 56 54 10 2500 1 0 0 98 5 61 0 0 382 12 775 9 57 57 8 2697 1 1 0 98 6 13 0 0 345 17 651 7 42 112 4 2669 1 1 0 98 7 17 0 37 574 104 807 13 59 42 5 2173 1 1 0 98 April 1, 2026 at 07:01:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2316 207 126 0 0 0 0 307 0 0 0 99 1 0 0 0 111 51 134 1 1 1 0 1126 0 0 0 100 2 0 0 0 10 1 2 0 0 0 0 294 0 0 0 100 3 0 0 7 13 2 8 0 1 0 0 260 0 0 0 100 4 0 0 14 19 5 18 0 1 0 0 266 0 0 0 100 5 0 0 0 9 1 2 0 0 0 0 300 0 0 0 100 6 0 0 0 14 3 8 0 1 0 0 1 0 0 0 100 7 0 0 8 213 102 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2316 204 167 0 17 324 0 302 0 1 0 99 1 0 0 0 169 57 243 0 26 346 0 1134 0 1 0 99 2 0 0 0 41 1 49 0 10 360 0 294 0 1 0 99 3 0 0 7 61 14 68 1 20 344 0 261 0 1 0 99 4 0 0 14 58 16 54 0 14 302 1 266 0 1 0 99 5 0 0 0 46 2 50 0 11 287 1 301 0 1 0 99 6 0 0 0 45 2 45 0 10 325 0 0 0 1 0 99 7 0 0 1 268 103 111 0 22 388 0 2 0 0 0 100 April 1, 2026 at 07:01:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 3 2328 201 519 3 97 1395 1 300 0 1 0 99 1 0 0 0 223 59 679 3 67 1425 0 1131 0 1 0 99 2 0 0 0 168 2 449 1 71 1411 0 315 0 1 0 99 3 0 0 14 210 98 468 0 69 1372 2 260 0 1 0 99 4 0 0 14 155 101 444 1 73 1705 0 266 0 1 0 99 5 0 0 0 189 2 409 1 51 1315 1 301 0 1 0 99 6 0 0 0 137 2 430 0 62 1552 1 0 0 1 0 99 7 0 0 3 345 103 523 1 55 1384 1 1 0 1 0 99 April 1, 2026 at 07:01:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 130 1 3 0 0 354 0 0 0 99 1 1 0 0 137 60 167 1 2 1 0 1194 0 0 0 99 2 0 0 0 16 2 13 3 2 4 0 1146 0 0 0 100 3 0 0 7 20 3 22 0 1 0 0 326 0 0 0 100 4 0 0 14 18 5 22 1 1 0 0 285 0 0 0 100 5 0 0 0 13 1 10 1 1 1 0 388 0 0 0 100 6 0 0 0 21 3 24 0 2 0 0 47 0 0 0 100 7 0 0 1 223 104 24 0 1 7 0 831 0 0 0 100 April 1, 2026 at 07:01:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 114 0 0 1 0 300 0 0 0 100 1 0 0 0 45 18 66 0 0 1 0 1133 0 0 0 100 2 0 0 0 92 43 86 0 1 1 0 294 0 0 0 100 3 0 0 7 17 3 14 0 0 1 0 280 0 0 0 100 4 1 0 14 16 5 14 0 0 1 0 278 0 0 0 100 5 0 0 0 27 12 18 0 0 1 0 310 0 0 0 100 6 0 0 0 12 3 6 0 0 0 0 0 0 0 0 100 7 0 0 1 217 102 8 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2305 201 112 0 0 1 0 300 0 0 0 100 1 0 0 0 24 8 48 1 0 0 0 1132 0 0 0 100 2 0 0 0 112 53 108 0 1 0 0 296 0 0 0 100 3 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 4 0 0 14 10 4 6 0 0 0 0 266 0 0 0 100 5 0 0 0 12 2 6 0 0 0 0 301 0 0 0 100 6 0 0 0 14 2 6 0 0 0 0 0 0 0 0 100 7 0 0 0 212 103 6 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 202 118 0 0 0 0 300 0 0 0 100 1 0 0 0 25 7 50 1 0 1 0 1129 0 0 0 100 2 0 0 0 109 51 106 0 2 0 0 294 0 0 0 100 3 0 0 7 9 2 6 0 1 0 0 260 0 0 0 100 4 0 0 14 10 4 6 0 0 0 0 266 0 0 0 100 5 0 0 0 8 1 4 0 0 0 0 300 0 0 0 100 6 0 0 0 12 2 6 0 0 0 0 0 0 0 0 100 7 0 0 1 213 102 10 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 116 1 0 0 0 342 0 0 0 100 1 0 0 0 30 10 56 0 0 0 0 1145 0 0 0 100 2 0 0 0 114 53 110 1 1 0 0 300 0 0 0 100 3 0 0 7 12 2 12 0 0 0 0 272 0 0 0 100 4 0 0 14 15 5 12 1 0 0 0 272 0 0 0 100 5 0 0 0 8 1 2 1 0 0 0 300 0 0 0 100 6 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 7 0 0 1 212 103 6 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2305 201 112 0 0 0 0 301 0 0 0 100 1 0 0 0 28 9 50 2 0 1 0 1138 0 0 0 100 2 0 0 0 112 53 108 0 0 0 0 300 0 0 0 100 3 0 0 7 11 2 8 0 1 0 0 263 0 0 0 100 4 0 0 14 12 4 12 0 2 0 0 267 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 6 0 0 0 13 3 6 0 0 0 0 1 0 0 0 100 7 0 0 0 211 102 6 0 0 0 0 3 0 0 0 100 April 1, 2026 at 07:01:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 116 0 0 0 0 300 0 0 0 100 1 0 0 0 24 8 48 1 0 0 0 1124 0 0 0 100 2 0 0 0 111 53 106 0 0 0 0 299 0 0 0 100 3 21 0 7 17 5 16 0 0 0 0 282 0 0 0 100 4 0 0 14 16 4 16 0 1 0 0 277 0 0 0 100 5 1 0 0 29 12 24 0 1 0 0 320 0 0 0 100 6 0 0 0 13 3 6 0 0 0 0 5 0 0 0 100 7 0 0 1 216 103 10 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 5 2305 201 114 0 0 0 0 302 0 0 0 100 1 0 0 0 23 7 48 1 1 0 0 1125 0 0 0 100 2 0 0 0 109 51 104 0 0 0 0 301 0 0 0 100 3 5 0 7 11 3 10 0 1 0 0 266 0 0 0 100 4 3 0 14 12 4 10 0 2 0 0 278 0 0 0 100 5 1 0 0 12 2 6 0 1 0 0 304 0 0 0 100 6 1 0 0 14 3 8 0 0 0 0 2 0 0 0 100 7 0 0 1 210 102 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 118 0 0 0 0 300 0 0 0 100 1 0 0 0 22 7 48 0 0 0 0 1122 0 0 0 100 2 0 0 0 115 54 108 1 0 0 0 300 0 0 0 100 3 0 0 7 10 3 6 0 0 0 0 261 0 0 0 100 4 0 0 14 10 4 6 1 0 0 0 266 0 0 0 100 5 0 0 0 11 1 6 1 1 1 0 300 0 0 0 100 6 0 0 0 13 2 10 0 1 0 0 0 0 0 0 100 7 0 0 1 215 103 14 0 1 1 0 2 0 0 0 100 April 1, 2026 at 07:01:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 112 1 1 0 0 300 0 0 0 100 1 0 0 0 24 8 48 1 0 1 0 1122 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 295 0 0 0 100 3 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 4 0 0 14 11 4 6 0 0 0 0 266 0 0 0 100 5 0 0 0 9 2 6 0 1 0 0 301 0 0 0 100 6 0 0 0 11 2 4 0 0 0 0 0 0 0 0 100 7 0 0 1 216 104 10 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 110 0 0 0 0 300 0 0 0 100 1 0 0 0 27 9 52 1 0 0 0 1130 0 0 0 100 2 0 0 0 113 53 112 0 1 0 0 301 0 0 0 100 3 0 0 7 9 2 6 0 0 0 0 263 0 0 0 100 4 0 0 14 12 4 10 0 0 0 0 272 0 0 0 100 5 0 0 0 10 2 4 0 0 0 0 301 0 0 0 100 6 0 0 0 13 3 6 0 0 0 0 1 0 0 0 100 7 0 0 1 213 103 8 0 0 1 0 5 0 0 0 100 April 1, 2026 at 07:01:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2306 201 120 0 1 0 0 300 0 0 0 100 1 0 0 0 29 8 52 1 1 1 0 1122 0 0 0 100 2 0 0 0 112 52 106 0 1 1 0 294 0 0 0 100 3 0 0 7 17 3 16 0 0 1 0 286 0 0 0 100 4 0 0 14 17 5 14 0 0 1 0 278 0 0 0 100 5 0 0 0 26 10 18 0 0 1 0 310 0 0 0 100 6 0 0 0 13 3 4 0 0 1 0 0 0 0 0 100 7 7 0 7 218 104 10 0 0 1 0 5 0 0 0 100 April 1, 2026 at 07:01:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 112 0 0 0 0 300 0 0 0 100 1 0 0 0 21 7 46 0 0 0 0 1123 0 0 0 100 2 0 0 0 116 54 110 1 1 0 0 297 0 0 0 100 3 0 0 7 14 2 12 0 1 0 0 260 0 0 0 100 4 0 0 14 10 4 6 1 0 0 0 266 0 0 0 100 5 0 0 0 10 1 2 1 0 0 0 300 0 0 0 100 6 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 7 0 0 1 214 103 6 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 1 0 0 0 300 0 0 0 100 1 0 0 0 23 7 46 2 0 0 0 1121 0 0 0 100 2 0 0 0 107 51 102 0 0 0 0 294 0 0 0 100 3 0 0 7 8 2 4 0 0 0 0 260 0 0 0 100 4 0 0 14 10 4 6 0 0 0 0 266 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 300 0 0 0 100 6 0 0 0 11 2 6 0 1 0 0 0 0 0 0 100 7 0 0 1 212 102 8 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 102 0 3 2353 208 20646 59 285 219 0 58565 18 12 0 70 1 66 0 0 976 16 20531 47 224 198 0 44439 14 10 0 76 2 98 0 0 231 24 20868 41 169 198 0 46032 15 10 0 75 3 117 0 0 295 13 25038 33 116 295 0 50986 15 10 0 75 4 311 0 14 1100 11 22508 26 86 226 0 51539 15 10 0 75 5 17 0 7 677 18 9614 28 79 206 0 26455 10 5 0 85 6 39 0 0 233 9 19315 21 77 178 0 37955 14 8 0 78 7 52 0 3 713 108 20114 19 65 283 0 49144 16 11 0 74 April 1, 2026 at 07:01:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 3 2331 218 5011 15 81 59 0 11937 4 3 0 93 1 11 0 0 103 35 7067 15 49 119 0 15770 5 3 0 92 2 1 0 0 35 7 7892 9 23 94 0 13632 4 3 0 93 3 5 0 0 21 4 5032 9 42 34 0 10608 3 2 0 95 4 24 0 14 21 8 4505 4 21 65 0 10429 4 2 0 94 5 9 0 7 44 11 3345 4 22 30 0 8028 3 2 0 95 6 16 0 0 25 4 4732 5 18 55 0 12947 4 3 0 94 7 1 0 4 244 112 2685 3 22 28 0 8850 2 1 0 97 April 1, 2026 at 07:01:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 110 0 1 0 0 300 0 0 0 100 1 0 0 0 108 51 132 1 0 0 0 1123 0 0 0 100 2 0 0 0 9 1 2 0 0 0 0 294 0 0 0 100 3 1 0 0 14 1 12 0 0 0 0 21 0 0 0 100 4 1 0 14 20 7 20 1 0 0 0 284 0 0 0 100 5 0 0 7 40 18 36 0 0 1 0 578 0 0 0 100 6 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 7 0 0 1 225 104 20 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2341 237 114 0 4 0 0 300 0 0 0 100 1 0 0 0 111 17 136 0 4 3 0 1123 0 0 0 100 2 0 0 0 17 1 14 1 3 1 0 294 0 0 0 100 3 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 4 0 0 14 11 4 8 0 1 0 0 266 0 0 0 100 5 0 0 7 29 10 20 2 0 0 0 570 0 0 0 100 6 0 0 0 13 3 8 0 0 0 0 1 0 0 0 100 7 0 0 2 221 103 14 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2360 252 153 0 11 303 0 300 0 1 0 99 1 0 0 0 142 1 211 1 21 331 0 1123 0 1 0 99 2 0 0 0 30 1 58 0 10 373 0 294 0 1 0 99 3 0 0 0 38 13 51 0 13 301 0 1 0 1 0 99 4 0 0 14 47 19 61 0 12 265 0 271 0 1 0 99 5 1 0 7 51 12 83 0 19 361 0 569 0 1 0 99 6 0 0 0 28 1 46 0 11 305 0 0 0 1 0 99 7 0 0 1 259 103 114 1 21 336 0 2 0 0 0 100 April 1, 2026 at 07:01:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2314 204 331 1 48 802 0 300 0 1 0 99 1 0 0 0 211 47 388 0 34 648 1 1124 0 1 0 99 2 0 0 0 111 4 230 0 42 705 0 315 0 0 0 100 3 0 0 0 158 56 259 0 35 691 1 0 0 0 0 100 4 0 0 14 105 59 261 0 34 675 1 266 0 0 0 100 5 0 0 7 125 12 278 0 25 694 1 572 0 0 0 99 6 0 0 0 105 1 221 0 24 711 0 3 0 0 0 100 7 0 0 1 317 103 306 0 34 549 1 1 0 0 0 100 April 1, 2026 at 07:01:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2302 201 106 0 0 0 0 300 0 0 0 100 1 0 0 0 32 13 54 1 0 0 0 1122 0 0 0 100 2 0 0 0 85 39 82 0 1 0 0 297 0 0 0 100 3 0 0 0 8 0 4 0 0 0 0 1 0 0 0 100 4 0 0 14 23 8 24 1 1 0 0 272 0 0 0 100 5 0 0 7 32 12 28 1 0 0 0 595 0 0 0 100 6 0 0 0 11 2 6 0 0 0 0 1 0 0 0 100 7 0 0 1 225 104 22 0 0 0 0 14 0 0 0 100 April 1, 2026 at 07:01:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2306 201 112 0 1 0 0 300 0 0 0 100 1 0 0 0 15 3 36 1 0 1 0 1124 0 0 0 100 2 0 0 0 110 52 102 0 0 1 0 294 0 0 0 100 3 0 0 0 13 1 10 0 0 1 0 20 0 0 0 100 4 0 0 14 21 6 18 0 0 1 0 278 0 0 0 100 5 0 0 7 44 19 38 0 1 2 0 578 0 0 0 100 6 0 0 0 11 2 2 0 0 1 0 0 0 0 0 100 7 0 0 7 222 102 16 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 108 0 0 0 0 300 0 0 0 100 1 0 0 0 8 1 32 0 0 0 0 1124 0 0 0 100 2 0 0 0 108 51 102 1 0 0 0 294 0 0 0 100 3 0 0 0 7 1 4 0 1 0 0 5 0 0 0 100 4 0 0 14 17 7 14 0 1 0 0 279 0 0 0 100 5 0 0 7 26 9 18 2 0 0 0 570 0 0 0 100 6 0 0 0 9 1 2 0 0 0 0 0 0 0 0 100 7 0 0 1 220 103 14 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 110 1 0 2 0 301 0 0 0 100 1 0 0 0 13 3 40 1 1 0 0 1147 0 0 0 100 2 0 0 0 108 51 104 0 0 0 0 294 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 16 7 12 0 0 0 0 269 0 0 0 100 5 0 0 7 29 10 28 0 0 4 0 567 0 0 0 100 6 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 7 0 0 1 221 102 18 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 444 0 760 2372 208 1421 57 183 27 0 6656 23 3 0 75 1 14 0 0 490 4 1141 36 160 26 0 7041 19 2 0 78 2 286 0 0 445 20 1330 38 182 27 0 6923 18 2 0 80 3 265 0 0 536 8 1125 38 147 36 0 7483 18 2 0 80 4 265 0 18 617 9 1132 29 128 18 1 7317 18 1 0 81 5 297 0 7 575 19 1155 34 143 24 0 7601 16 2 0 83 6 893 0 0 491 9 1003 38 121 32 1 5075 19 2 0 79 7 7 0 2 723 110 1051 34 114 10 1 5684 19 1 0 79 April 1, 2026 at 07:01:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 441 2352 208 801 22 104 11 0 3851 11 2 0 88 1 2 0 0 140 6 687 16 97 10 0 3482 14 1 0 85 2 65 0 0 304 7 493 14 81 4 0 3558 15 1 0 85 3 3 0 0 116 4 681 21 93 11 0 3438 12 1 0 88 4 1 0 14 338 6 765 18 83 8 0 5130 8 1 0 91 5 0 0 7 398 9 606 16 67 2 0 4496 11 1 0 88 6 0 0 0 298 9 598 15 65 3 0 3433 11 1 0 88 7 0 0 7 515 132 640 9 54 11 0 3305 9 1 0 90 April 1, 2026 at 07:01:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 63 0 19 2384 251 160 1 11 15 5 442 0 1 0 99 1 749 0 0 49 0 42 1 6 7 7 6506 1 1 0 98 2 7 0 0 42 1 29 0 6 5 1 351 0 0 0 100 3 30 0 0 47 3 37 0 2 3 1 86 0 0 0 100 4 2652 0 128 58 6 114 3 6 10 13 1971 1 1 0 98 5 106 0 7 79 11 104 1 10 13 16 733 0 0 0 100 6 18 0 2 43 2 45 0 6 6 8 88 0 0 0 100 7 12 0 1 360 114 164 0 12 6 3 104 0 0 0 100 April 1, 2026 at 07:01:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2362 256 118 0 0 0 0 309 0 0 0 99 1 0 0 0 17 0 10 0 0 0 0 0 0 0 0 100 2 0 0 0 10 1 4 1 1 0 0 294 0 0 0 100 3 0 0 0 9 0 8 0 1 0 0 0 0 0 0 100 4 0 0 14 11 4 36 1 0 0 0 1477 0 0 0 100 5 0 0 7 10 3 6 0 0 0 0 560 0 0 0 100 6 0 0 0 11 2 6 0 1 0 0 1 0 0 0 100 7 0 0 1 314 104 108 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2371 258 120 1 0 0 0 315 0 0 0 100 1 0 0 0 16 1 12 0 1 0 0 0 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 294 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 4 0 0 14 14 4 40 2 1 0 0 1480 0 0 0 100 5 0 0 7 11 3 8 0 0 0 0 560 0 0 0 100 6 0 0 0 10 1 4 0 0 0 0 0 0 0 0 100 7 0 0 1 320 105 120 0 1 1 0 3 0 0 0 100 April 1, 2026 at 07:01:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 33 0 46 2362 239 230 5 18 99 3 3368 3 1 0 96 1 10 0 0 120 3 799 10 68 45 0 2744 1 1 0 98 2 2 0 0 38 1 38 3 2 105 5 3486 2 1 0 97 3 31 0 23 314 13 647 11 49 63 1 2538 1 1 0 98 4 4 0 20 348 4 772 9 59 56 0 3862 1 1 0 98 5 6 0 21 56 10 71 2 9 133 2 3755 2 1 0 97 6 0 0 0 372 2 811 12 62 23 0 2138 1 0 0 99 7 0 0 2 575 106 760 12 54 43 0 2021 1 1 0 98 April 1, 2026 at 07:01:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 202 82 0 1 0 0 301 0 0 0 100 1 0 0 0 13 2 6 0 1 1 0 0 0 0 0 100 2 0 0 0 10 1 2 0 0 0 0 294 0 0 0 100 3 0 0 0 37 0 28 0 0 0 0 0 0 0 0 100 4 3 0 21 21 3 46 1 2 1 0 1404 0 0 0 100 5 0 0 7 121 54 121 1 2 0 0 559 0 0 0 100 6 0 0 0 22 7 12 0 0 0 0 7 0 0 0 100 7 0 0 1 221 106 12 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2305 201 112 0 0 1 0 300 0 0 0 100 1 0 0 0 31 3 6 0 0 1 0 1 0 0 0 100 2 0 0 0 27 2 4 1 1 1 0 294 0 0 0 100 3 0 0 0 37 6 18 1 0 1 0 20 0 0 0 100 4 0 0 14 36 4 48 0 1 1 0 1398 0 0 0 100 5 0 0 7 151 62 131 0 4 2 0 574 0 0 0 100 6 0 0 0 35 6 10 1 0 1 0 8 0 0 0 100 7 0 0 1 235 105 12 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 1 0 0 0 301 0 0 0 100 1 0 0 0 8 0 2 0 0 0 0 0 0 0 0 100 2 0 0 0 10 2 4 0 0 0 0 293 0 0 0 100 3 0 0 0 14 3 6 0 0 0 0 4 0 0 0 100 4 0 0 14 10 3 36 2 1 1 0 1384 0 0 0 100 5 0 0 14 122 53 118 0 0 0 0 561 0 0 0 100 6 0 0 0 24 6 20 0 1 0 0 9 0 0 0 100 7 0 0 1 219 106 12 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2311 202 158 1 17 396 0 46 0 1 0 99 1 0 0 0 45 1 78 3 19 328 0 1189 0 1 0 99 2 0 0 0 27 2 43 0 8 284 0 300 0 1 0 99 3 3 0 0 49 14 69 0 14 364 0 49 0 1 0 99 4 0 0 14 38 13 77 1 10 318 0 1394 0 1 0 99 5 0 0 7 158 53 213 0 22 341 0 626 0 0 0 99 6 0 0 0 54 6 100 1 21 398 0 908 0 1 0 99 7 0 0 1 246 105 80 1 17 329 0 52 0 1 0 99 April 1, 2026 at 07:01:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2334 215 519 1 98 1452 0 10 0 1 0 99 1 0 0 0 150 1 478 2 68 1472 0 300 0 1 0 99 2 0 0 0 149 1 363 1 63 1311 1 0 0 1 0 99 3 0 0 0 219 92 437 0 59 1356 0 7 0 1 0 99 4 0 0 14 201 118 496 1 70 1546 1 1386 0 1 0 99 5 0 0 7 83 7 526 1 72 1161 0 559 0 1 0 99 6 0 0 0 162 0 349 1 63 1237 1 255 0 1 0 99 7 0 0 1 283 106 414 0 61 1582 1 2 0 1 0 99 April 1, 2026 at 07:01:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 106 0 0 0 0 294 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 21 8 16 0 0 0 0 14 0 0 0 100 4 0 0 14 109 53 134 0 0 0 0 1385 0 0 0 100 5 0 0 7 20 4 16 0 0 0 0 562 0 0 0 100 6 0 0 0 9 1 4 0 1 0 0 1 0 0 0 100 7 0 0 1 222 105 20 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:01:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 0 1 0 0 295 0 0 0 100 1 0 0 0 10 1 4 1 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 23 6 24 0 0 0 0 32 0 0 0 100 4 0 0 14 114 53 142 2 0 0 0 1397 0 0 0 100 5 0 0 7 38 12 30 0 0 1 0 570 0 0 0 100 6 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 7 0 0 1 223 106 16 0 1 0 0 2 0 0 0 100 April 1, 2026 at 07:01:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 104 0 0 0 0 294 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 2 0 0 0 11 1 10 0 0 0 0 11 0 0 0 100 3 0 0 0 30 10 28 1 0 0 0 30 0 0 0 100 4 0 0 14 111 53 138 1 2 0 0 1397 0 0 0 100 5 0 0 7 19 3 16 0 0 0 0 584 0 0 0 100 6 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 218 105 14 0 0 0 0 10 0 0 0 100 April 1, 2026 at 07:01:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 108 0 0 2 0 294 0 0 0 100 1 0 0 0 11 1 8 0 1 0 0 303 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 22 8 18 0 0 0 0 13 0 0 0 100 4 0 0 14 111 53 138 1 0 0 0 1386 0 0 0 100 5 0 0 7 20 3 18 1 1 0 0 559 0 0 0 100 6 0 0 0 11 1 6 0 0 2 0 3 0 0 0 100 7 0 0 1 223 106 22 0 0 2 0 8 0 0 0 100 April 1, 2026 at 07:01:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 102 0 1 0 0 294 0 0 0 100 1 2 0 0 16 3 10 0 0 0 0 306 0 0 0 100 2 0 0 0 13 2 8 0 2 0 0 21 0 0 0 100 3 19 0 0 23 9 18 0 0 0 0 16 0 0 0 100 4 0 0 14 38 18 62 0 0 0 0 1385 0 0 0 100 5 0 0 7 93 40 90 0 1 0 0 563 0 0 0 100 6 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 7 0 0 1 218 106 14 0 1 0 0 1 0 0 0 100 April 1, 2026 at 07:01:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 108 0 0 0 0 295 0 0 0 100 1 0 0 0 10 1 4 1 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 19 7 14 0 0 0 0 10 0 0 0 100 4 0 0 14 9 3 34 2 0 1 0 1381 0 0 0 100 5 0 0 7 118 53 114 0 0 0 0 560 0 0 0 100 6 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 7 0 0 1 218 106 12 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2305 201 114 0 1 0 0 295 0 0 0 100 1 0 0 0 16 3 8 0 0 1 0 301 0 0 0 100 2 0 0 0 12 2 4 0 0 1 0 0 0 0 0 100 3 0 0 0 32 11 28 0 1 2 0 28 0 0 0 100 4 0 0 14 16 4 42 1 0 2 0 1391 0 0 0 100 5 0 0 7 141 64 137 0 1 1 0 583 0 0 0 100 6 0 0 0 9 1 0 0 0 1 0 0 0 0 0 100 7 0 0 7 220 105 12 0 0 1 0 0 0 0 0 100 April 1, 2026 at 07:01:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 104 0 0 0 0 294 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 18 5 12 0 0 0 0 6 0 0 0 100 4 0 0 14 10 3 36 1 1 0 0 1380 0 0 0 100 5 0 0 7 120 53 116 1 0 0 0 559 0 0 0 100 6 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 7 0 0 1 218 106 12 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:01:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 106 0 0 5 0 294 0 0 0 100 1 0 0 0 10 1 6 0 0 0 0 302 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 3 0 0 0 22 7 18 1 0 0 0 17 0 0 0 100 4 0 0 14 13 4 38 1 0 0 0 1385 0 0 0 100 5 0 0 7 121 54 118 0 0 0 0 562 0 0 0 100 6 0 0 0 11 1 8 0 1 2 0 3 0 0 0 100 7 0 0 1 222 106 20 0 0 2 0 5 0 0 0 100 April 1, 2026 at 07:01:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 202 106 0 0 0 0 295 0 0 0 100 1 0 0 0 10 1 4 1 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 11 3 36 2 1 0 0 1380 0 0 0 100 5 0 0 7 119 53 114 0 0 0 0 560 0 0 0 100 6 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 7 0 0 1 230 112 24 0 0 0 0 11 0 0 0 100 April 1, 2026 at 07:02:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 102 0 1 0 0 294 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 300 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 6 0 0 0 100 4 0 0 14 8 3 34 0 0 0 0 1380 0 0 0 100 5 0 0 7 118 53 114 0 0 0 0 560 0 0 0 100 6 0 0 0 11 1 6 0 2 0 0 1 0 0 0 100 7 0 0 1 228 110 24 0 2 0 0 8 0 0 0 100 April 1, 2026 at 07:02:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 202 112 0 0 0 0 295 0 0 0 100 1 0 0 0 9 1 4 0 0 0 0 299 0 0 0 100 2 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 0 6 0 0 0 0 11 0 0 0 100 4 1 0 14 14 3 42 2 0 0 0 1391 0 0 0 100 5 0 0 7 140 62 134 1 0 1 0 582 0 0 0 100 6 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 7 0 0 1 235 112 28 0 1 0 0 11 0 0 0 100 April 1, 2026 at 07:02:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 188 0 5 2329 203 9339 39 126 74 0 22692 7 5 0 87 1 16 0 0 801 5 9441 24 104 58 0 17534 5 4 0 91 2 25 0 0 238 2 9656 24 78 97 0 19820 6 4 0 90 3 165 0 0 456 3 9515 21 53 152 0 25783 8 5 0 86 4 13 0 14 512 8 7256 11 35 31 0 14029 5 3 0 92 5 60 0 7 1285 41 5662 14 30 89 0 17234 6 4 0 90 6 131 0 0 977 2 8959 8 35 53 0 20683 6 4 0 91 7 250 0 1 648 114 4927 17 35 54 0 15687 5 3 0 91 April 1, 2026 at 07:02:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 50 0 3 2387 211 21115 85 415 489 0 49663 17 10 0 73 1 31 0 0 136 17 20026 70 342 501 0 42946 15 9 0 76 2 27 0 0 94 16 19402 64 259 357 0 40367 13 9 0 78 3 39 0 0 108 18 18305 43 170 361 0 33104 11 8 0 81 4 43 0 14 98 20 14226 31 141 404 0 36250 11 9 0 80 5 73 0 0 99 16 15311 28 107 395 0 38703 12 8 0 79 6 25 0 7 81 14 13133 17 101 275 0 28817 8 6 0 85 7 25 0 4 291 116 12779 20 99 414 0 32840 10 7 0 83 April 1, 2026 at 07:02:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2326 210 486 0 48 880 0 0 0 1 0 99 1 0 0 0 215 38 370 0 36 722 0 594 0 1 0 99 2 0 0 0 109 8 327 0 38 810 0 10 0 1 0 99 3 0 0 0 191 75 343 0 35 799 0 3 0 0 0 100 4 0 0 14 203 76 341 1 48 784 0 1388 0 1 0 99 5 0 0 0 78 2 289 0 40 837 0 301 0 0 0 99 6 0 0 7 123 3 299 0 40 626 0 260 0 0 0 100 7 0 0 2 321 112 269 0 30 727 0 1 0 0 0 100 April 1, 2026 at 07:02:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 118 0 0 0 0 4 0 0 0 100 1 0 0 0 111 52 106 1 1 0 0 594 0 0 0 100 2 0 0 0 19 6 16 0 1 0 0 8 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 3 0 0 0 100 4 0 0 14 9 3 34 1 0 2 0 1390 0 0 0 100 5 0 0 0 9 1 6 0 0 0 0 318 0 0 0 100 6 0 0 7 12 3 8 0 0 0 0 260 0 0 0 100 7 0 0 1 217 105 12 0 0 0 0 9 0 0 0 100 April 1, 2026 at 07:02:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2302 200 116 0 0 1 0 0 0 0 0 100 1 0 0 0 116 54 108 1 1 1 0 596 0 0 0 100 2 0 0 0 27 9 20 0 1 1 0 10 0 0 0 100 3 0 0 0 19 3 18 0 1 3 0 20 0 0 0 100 4 0 0 14 16 4 44 1 1 1 0 1398 0 0 0 100 5 0 0 0 21 10 4 1 0 1 0 300 0 0 0 100 6 0 0 7 20 6 18 0 0 0 0 276 0 0 0 100 7 0 0 1 216 104 10 0 1 1 0 0 0 0 0 100 April 1, 2026 at 07:02:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 114 0 0 0 0 5 0 0 0 100 1 0 0 0 109 52 104 0 0 0 0 593 0 0 0 100 2 0 0 0 25 9 20 0 0 0 0 13 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 5 0 0 0 100 4 0 0 14 11 3 36 2 1 2 0 1401 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 300 0 0 0 100 6 0 0 7 14 3 6 0 0 0 0 260 0 0 0 100 7 0 0 1 213 104 8 0 1 0 0 0 0 0 0 100 April 1, 2026 at 07:02:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 200 118 0 0 1 0 0 0 0 0 100 1 0 0 0 110 52 106 0 0 0 0 595 0 0 0 100 2 0 0 0 22 7 20 0 0 0 0 15 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 6 0 0 0 100 4 0 0 14 15 3 44 0 0 0 0 1389 0 0 0 100 5 0 0 0 15 3 10 1 0 0 0 304 0 0 0 100 6 0 0 7 14 3 10 0 1 2 0 263 0 0 0 100 7 0 0 1 217 104 14 0 0 0 0 3 0 0 0 100 April 1, 2026 at 07:02:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 202 114 0 0 0 0 3 0 0 0 100 1 0 0 0 110 52 106 1 1 0 0 595 0 0 0 100 2 0 0 0 20 7 16 0 0 0 0 9 0 0 0 100 3 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 4 0 0 14 11 3 36 1 1 0 0 1388 0 0 0 100 5 0 0 0 10 2 6 0 1 0 0 300 0 0 0 100 6 0 0 7 13 3 8 0 1 0 0 260 0 0 0 100 7 0 0 1 213 104 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2302 200 112 0 0 0 0 0 0 0 0 100 1 0 0 0 109 52 104 0 0 0 0 593 0 0 0 100 2 0 0 0 22 8 18 0 0 0 0 10 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 3 0 0 0 100 4 0 0 14 9 3 34 1 0 0 0 1389 0 0 0 100 5 0 0 0 8 1 4 1 1 0 0 300 0 0 0 100 6 0 0 7 14 4 8 0 0 0 0 261 0 0 0 100 7 0 0 0 213 104 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 202 118 0 0 0 0 3 0 0 0 100 1 0 0 0 109 52 104 0 0 0 0 595 0 0 0 100 2 0 0 0 18 6 14 0 0 0 0 8 0 0 0 100 3 0 0 0 13 2 10 1 0 0 0 16 0 0 0 100 4 0 0 14 13 3 42 2 0 0 0 1421 0 0 0 100 5 0 0 0 15 7 6 0 1 1 0 300 0 0 0 100 6 0 0 7 20 3 18 1 1 0 0 272 0 0 0 100 7 0 0 1 217 104 12 0 2 0 0 0 0 0 0 100 April 1, 2026 at 07:02:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1174 0 510 2334 201 696 28 100 20 0 3383 9 2 0 90 1 103 0 0 414 42 570 19 81 20 0 3507 8 1 0 91 2 295 0 0 231 16 848 51 98 33 0 4129 6 1 0 93 3 14 0 0 152 4 540 20 76 17 0 3226 8 1 0 91 4 318 0 14 173 4 547 28 75 18 1 3867 10 1 0 88 5 3 0 0 282 12 492 16 70 18 0 3187 8 1 0 91 6 7 0 7 217 4 545 31 73 13 1 3309 11 1 0 88 7 0 0 1 404 106 519 10 58 14 0 3236 9 1 0 91 April 1, 2026 at 07:02:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 8 0 1054 2392 209 1465 49 183 58 0 6691 27 3 0 70 1 0 0 0 433 8 1071 42 157 40 0 6220 29 2 0 69 2 0 0 0 322 27 1936 141 224 88 0 8581 13 2 0 85 3 6 0 0 584 11 1107 37 155 37 0 6067 22 2 0 76 4 3 0 14 583 13 1266 32 142 26 0 9130 18 2 0 80 5 0 0 0 449 7 1265 38 150 28 0 7013 21 2 0 78 6 0 0 7 606 18 1152 34 132 42 0 6986 20 2 0 78 7 0 0 2 645 105 1340 29 130 33 0 7755 16 2 0 82 April 1, 2026 at 07:02:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1 0 19 2307 201 123 1 7 0 0 38 0 0 0 100 1 0 0 0 24 5 22 2 1 0 0 684 2 0 0 98 2 7 0 0 27 2 38 1 7 2 0 119 0 0 0 100 3 0 0 0 37 2 56 1 4 0 0 137 0 0 0 100 4 0 0 14 37 8 71 4 3 0 0 1441 2 0 0 98 5 0 0 0 23 2 25 0 3 0 0 147 0 0 0 100 6 1 0 7 134 57 134 0 3 1 0 381 1 0 0 98 7 0 0 1 228 107 46 2 5 1 0 392 1 0 0 99 April 1, 2026 at 07:02:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 202 106 0 0 0 0 3 0 0 0 100 1 0 0 0 10 2 4 1 0 0 0 593 0 0 0 100 2 0 0 0 15 0 10 0 0 0 0 0 0 0 0 100 3 0 0 0 11 1 4 0 1 0 0 0 0 0 0 100 4 2 0 14 13 3 44 0 3 0 0 1396 0 0 0 100 5 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 6 0 0 7 126 59 120 0 1 0 0 270 0 0 0 100 7 0 0 1 217 106 10 0 0 0 0 300 0 0 0 100 April 1, 2026 at 07:02:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2303 200 108 0 1 0 0 0 0 0 0 100 1 0 0 0 17 4 8 1 1 1 0 595 0 0 0 100 2 0 0 0 19 1 10 0 0 1 0 0 0 0 0 100 3 0 0 0 16 2 14 0 0 1 0 13 0 0 0 100 4 0 0 14 24 7 50 1 0 2 0 1412 0 0 0 100 5 0 0 0 15 7 2 0 0 2 0 0 0 0 0 100 6 0 0 7 133 61 130 0 0 1 0 286 0 0 0 100 7 0 0 7 222 106 14 1 0 1 0 300 0 0 0 100 April 1, 2026 at 07:02:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 108 0 0 0 0 5 0 0 0 100 1 0 0 0 9 2 6 0 1 0 0 593 0 0 0 100 2 0 0 0 12 0 6 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 14 13 3 38 1 0 1 0 1395 0 0 0 100 5 0 0 0 7 0 2 0 1 0 0 0 0 0 0 100 6 0 0 7 129 60 122 0 0 0 0 273 0 0 0 100 7 0 0 1 219 106 12 0 1 0 0 300 0 0 0 100 April 1, 2026 at 07:02:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 62 0 75 2352 204 956 30 93 432 5 2654 3 1 0 96 1 8 0 0 363 11 744 13 64 248 5 2881 1 1 0 97 2 74 0 6 178 35 209 7 31 448 3 3753 4 2 0 94 3 5 0 14 428 14 916 21 74 319 6 1943 1 1 0 98 4 23 0 14 94 17 132 7 16 412 5 5042 4 2 0 94 5 3381 0 148 93 2 179 8 22 387 18 10424 6 3 0 91 6 109 0 7 441 12 892 13 64 324 16 2263 1 1 0 97 7 38 0 4 593 106 773 11 73 326 6 1859 1 1 0 98 April 1, 2026 at 07:02:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2323 204 697 1 94 1432 1 303 0 1 0 99 1 0 0 0 111 9 442 1 70 1456 0 593 0 1 0 99 2 0 0 0 119 7 450 1 75 1638 1 0 0 1 0 99 3 0 0 0 242 100 402 1 78 1377 0 1 0 1 0 99 4 0 0 14 222 96 454 1 66 1462 3 1389 0 1 0 99 5 0 0 0 193 31 446 1 74 1360 1 0 0 1 0 99 6 0 0 14 135 7 401 1 57 1501 1 265 0 1 0 99 7 0 0 1 350 105 387 1 61 1281 1 0 0 1 0 99 April 1, 2026 at 07:02:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 117 2304 201 139 1 1 0 0 300 0 1 0 99 1 0 0 0 27 2 4 1 0 0 0 595 0 0 0 100 2 0 0 0 24 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 23 1 4 0 1 0 0 0 0 0 0 100 4 0 0 14 33 6 42 1 0 1 0 1387 0 0 0 100 5 0 0 0 35 7 14 0 1 0 0 0 0 0 0 100 6 0 0 7 130 52 108 0 1 0 0 270 0 0 0 100 7 0 0 1 234 105 12 0 1 0 0 0 0 0 0 100 April 1, 2026 at 07:02:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 12 2308 202 122 0 0 0 0 303 0 0 0 100 1 0 0 0 14 2 8 1 1 0 0 594 0 0 0 100 2 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 14 3 14 0 1 0 0 16 0 0 0 100 4 0 0 14 16 3 44 1 0 0 0 1397 0 0 0 100 5 0 0 0 13 5 2 0 0 0 0 0 0 0 0 100 6 0 0 7 129 57 128 0 1 0 0 278 0 0 0 100 7 0 0 1 219 105 10 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2313 207 140 0 4 2 0 344 0 0 0 99 1 0 0 0 17 2 20 0 1 0 0 678 0 0 0 100 2 0 0 0 12 0 14 3 3 5 0 825 0 0 0 99 3 0 0 0 24 3 27 0 2 10 0 906 0 0 0 100 4 0 0 14 24 5 52 3 2 0 0 1449 0 0 0 99 5 0 0 0 8 0 8 0 1 1 0 21 0 0 0 100 6 0 0 7 129 56 131 0 1 4 0 329 0 0 0 100 7 0 0 1 216 105 10 0 0 1 0 13 0 0 0 100 April 1, 2026 at 07:02:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2321 208 126 0 0 0 0 312 0 0 0 100 1 0 0 0 14 3 10 0 1 2 0 617 0 0 0 100 2 0 0 0 12 1 6 0 0 1 0 0 0 0 0 100 3 0 0 0 10 1 6 0 1 1 0 0 0 0 0 100 4 0 0 14 18 6 44 1 1 2 0 1389 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 7 115 53 112 0 1 0 0 261 0 0 0 100 7 0 0 1 218 105 14 0 0 2 0 0 0 0 0 100 April 1, 2026 at 07:02:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2316 206 119 1 0 0 0 305 0 0 0 100 1 0 0 0 13 3 6 1 0 0 0 596 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 14 18 6 46 0 1 1 0 1390 0 0 0 100 5 0 0 0 10 1 8 0 1 0 0 1 0 0 0 100 6 0 0 7 112 52 106 0 0 0 0 260 0 0 0 100 7 0 0 1 217 106 10 0 0 0 0 1 0 0 0 100 April 1, 2026 at 07:02:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 6 2316 207 124 0 0 0 0 307 0 0 0 100 1 0 0 0 10 2 4 1 0 0 0 594 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 2 0 0 0 0 0 0 0 0 100 4 0 0 14 11 3 34 1 0 0 0 1385 0 0 0 100 5 0 0 0 5 0 2 0 1 0 0 0 0 0 0 100 6 0 0 7 112 52 106 0 0 0 0 260 0 0 0 100 7 0 0 0 215 105 10 0 1 0 0 0 0 0 0 100 April 1, 2026 at 07:02:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2321 209 144 0 2 0 0 319 0 0 0 100 1 0 0 0 19 4 12 1 1 1 0 620 0 0 0 100 2 0 0 0 11 1 4 0 0 1 0 1 0 0 0 100 3 0 0 0 16 2 14 0 0 1 0 13 0 0 0 100 4 0 0 14 21 6 48 2 1 1 0 1416 0 0 0 100 5 0 0 0 21 6 12 0 1 1 0 11 0 0 0 100 6 0 0 7 122 55 118 0 0 1 0 277 0 0 0 100 7 0 0 7 224 105 18 0 1 1 0 0 0 0 0 100 April 1, 2026 at 07:02:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2321 210 127 0 1 0 0 314 0 0 0 100 1 0 0 0 11 2 8 0 2 0 0 594 0 0 0 100 2 0 0 0 8 0 6 0 1 0 0 3 0 0 0 100 3 0 0 0 8 1 4 0 1 0 0 3 0 0 0 100 4 0 0 14 10 3 36 1 0 0 0 1386 0 0 0 100 5 0 0 0 7 0 2 1 1 0 0 3 0 0 0 100 6 0 0 7 112 52 108 0 0 0 0 260 0 0 0 100 7 0 0 1 217 104 8 0 1 0 0 0 0 0 0 100 April 1, 2026 at 07:02:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2318 206 120 0 0 0 0 305 0 0 0 100 1 0 0 0 13 3 8 1 0 0 0 593 0 0 0 100 2 0 0 0 9 1 6 0 0 0 0 0 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 4 19 0 14 18 7 42 1 0 1 0 1388 0 0 0 100 5 0 0 0 5 0 2 0 1 0 0 0 0 0 0 100 6 2 0 7 115 53 110 0 0 0 0 265 0 0 0 100 7 0 0 1 216 104 12 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2316 208 130 1 0 0 0 308 0 0 0 100 1 0 0 0 12 3 6 1 0 0 0 595 0 0 0 100 2 0 0 0 11 0 8 0 0 1 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 14 8 3 34 0 0 1 0 1380 0 0 0 100 5 0 0 0 6 0 0 0 0 0 0 0 0 0 0 100 6 0 0 7 112 52 108 0 1 0 0 260 0 0 0 100 7 0 0 1 213 104 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2316 207 122 0 0 0 0 307 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 594 0 0 0 100 2 0 0 0 8 0 4 0 1 0 0 0 0 0 0 100 3 0 0 0 9 1 6 0 1 0 0 0 0 0 0 100 4 0 0 0 15 5 36 1 0 0 0 1119 0 0 0 100 5 0 0 14 5 0 2 1 1 0 0 266 0 0 0 100 6 0 0 7 114 53 110 0 1 0 0 261 0 0 0 100 7 0 0 1 213 104 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2316 207 128 0 0 0 0 307 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 593 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 15 4 14 0 0 0 0 17 0 0 0 100 4 0 0 0 13 2 40 1 0 0 0 1124 0 0 0 100 5 0 0 14 14 9 4 0 0 1 0 266 0 0 0 100 6 0 0 7 118 52 120 0 0 0 0 274 0 0 0 100 7 0 0 1 216 104 8 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2310 205 128 0 1 0 0 309 0 0 0 100 1 0 0 0 14 4 8 1 1 0 0 594 0 0 0 100 2 0 0 0 9 1 6 0 1 1 0 1 0 0 0 100 3 0 0 0 16 2 10 0 0 2 0 3 0 0 0 100 4 0 0 0 29 11 56 0 1 0 0 1136 0 0 0 100 5 0 0 14 9 2 8 0 1 1 0 269 0 0 0 100 6 0 0 7 116 54 112 0 1 1 0 261 0 0 0 100 7 0 0 1 213 104 6 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 203 116 0 0 0 0 302 0 0 0 100 1 0 0 0 12 3 6 1 0 0 0 595 0 0 0 100 2 0 0 0 12 1 6 0 0 0 0 0 0 0 0 100 3 0 0 0 9 1 4 0 1 1 0 0 0 0 0 100 4 0 0 0 20 7 44 1 1 1 0 1125 0 0 0 100 5 0 0 14 5 1 2 0 0 0 0 266 0 0 0 100 6 0 0 7 112 52 108 0 0 0 0 260 0 0 0 100 7 0 0 1 213 103 8 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 114 0 0 0 0 300 0 0 0 100 1 0 0 0 13 4 8 0 0 0 0 595 0 0 0 100 2 0 0 0 8 1 4 0 0 0 0 21 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 25 10 48 1 0 0 0 1126 0 0 0 100 5 0 0 14 7 2 4 1 0 0 0 267 0 0 0 100 6 0 0 7 112 52 108 0 0 0 0 260 0 0 0 100 7 0 0 1 213 104 6 0 0 0 0 1 0 0 0 100 April 1, 2026 at 07:02:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 203 116 0 1 0 0 302 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 593 0 0 0 100 2 0 0 0 6 0 2 0 0 0 0 0 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 19 6 42 1 0 1 0 1118 0 0 0 100 5 0 0 14 8 1 8 0 1 0 0 284 0 0 0 100 6 0 0 7 114 53 108 0 0 0 0 261 0 0 0 100 7 0 0 1 215 104 10 0 0 0 0 9 0 0 0 100 April 1, 2026 at 07:02:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 348 0 7 2381 210 21062 105 413 263 0 49410 17 11 0 72 1 64 0 0 404 7 21060 97 351 270 0 49430 18 10 0 72 2 60 0 0 858 7 21658 58 251 159 0 46099 15 10 0 75 3 219 0 3 354 7 16612 50 201 167 1 41113 14 9 0 77 4 139 0 0 486 17 21217 34 150 225 1 53150 14 10 0 76 5 20 0 0 200 17 16372 28 100 159 0 37303 11 7 0 82 6 65 0 21 540 21 18152 27 116 173 0 41465 14 9 0 77 7 43 0 7 670 119 17588 33 105 162 0 38204 12 8 0 80 April 1, 2026 at 07:02:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 5 0 3 2369 250 5697 14 73 28 0 12347 3 3 0 94 1 6 0 0 84 7 4060 10 58 43 0 10178 3 2 0 95 2 15 0 0 27 5 4507 10 41 39 0 11843 4 2 0 94 3 5 0 0 34 8 6160 8 28 51 0 13593 4 3 0 93 4 1 0 0 36 9 6349 6 32 74 0 13240 4 3 0 93 5 7 0 0 25 4 3894 4 18 59 0 12692 4 3 0 93 6 3 0 21 30 6 7421 6 21 48 0 12099 4 3 0 93 7 2 0 4 233 108 4991 5 14 85 0 13165 4 2 0 94 April 1, 2026 at 07:02:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2357 251 203 0 20 282 0 0 0 1 0 99 1 0 0 0 136 3 162 0 11 235 0 600 0 1 0 99 2 0 0 0 36 2 64 2 16 238 0 294 0 1 0 99 3 0 0 0 50 17 64 0 14 340 0 5 0 1 0 99 4 0 0 0 44 13 89 2 19 321 0 1124 0 1 0 99 5 0 0 0 41 2 73 1 19 284 0 5 0 0 0 100 6 0 0 21 34 3 61 2 12 225 0 526 0 1 0 99 7 0 0 1 241 103 82 1 21 301 0 0 0 0 0 100 April 1, 2026 at 07:02:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2317 205 422 0 47 725 1 3 0 1 0 99 1 0 0 0 247 52 409 0 31 792 1 601 0 1 0 99 2 0 0 0 95 1 315 0 45 821 0 294 0 0 0 100 3 0 0 0 127 73 292 0 33 864 1 9 0 0 0 99 4 0 0 0 112 68 337 0 45 779 2 1123 0 1 0 99 5 0 0 0 97 0 299 0 37 623 1 0 0 0 0 100 6 0 0 21 82 3 278 0 33 653 2 525 0 0 0 99 7 0 0 1 289 103 283 0 27 627 1 0 0 0 0 100 April 1, 2026 at 07:02:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2303 201 8 0 1 0 0 0 0 0 0 100 1 0 0 0 113 6 108 0 3 0 0 600 0 0 0 100 2 0 0 0 108 48 108 0 4 0 0 294 0 0 0 100 3 0 0 0 17 6 12 0 0 0 0 5 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 1124 0 0 0 100 5 0 0 0 11 3 6 0 0 0 0 3 0 0 0 100 6 0 0 21 14 4 10 0 0 0 0 527 0 0 0 100 7 0 0 2 212 103 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 203 14 0 1 0 0 7 0 0 0 100 1 0 0 0 97 2 88 1 0 0 0 600 0 0 0 100 2 0 0 0 115 41 111 0 3 0 0 294 0 0 0 100 3 0 0 0 47 19 42 0 2 0 0 9 0 0 0 100 4 0 0 0 19 4 44 1 0 0 0 1139 0 0 0 100 5 0 0 0 22 8 19 0 2 1 0 16 0 0 0 100 6 0 0 21 16 3 18 0 0 0 0 539 0 0 0 100 7 0 0 1 215 103 10 0 1 0 0 1 0 0 0 100 April 1, 2026 at 07:02:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2345 241 86 0 1 0 0 2 0 0 0 100 1 0 0 0 19 2 14 1 1 0 0 603 0 0 0 100 2 0 0 0 113 3 106 0 4 0 0 294 0 0 0 100 3 0 0 0 39 14 30 0 2 1 0 16 0 0 0 100 4 0 0 0 25 7 52 1 1 3 0 1133 0 0 0 100 5 0 0 0 12 3 170 0 1 0 0 337 0 0 0 100 6 0 0 21 21 5 22 1 1 0 0 542 0 0 0 100 7 0 0 1 213 103 10 0 1 1 0 5 0 0 0 100 April 1, 2026 at 07:02:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2359 253 110 0 0 0 0 8 0 0 0 100 1 0 0 0 20 3 16 0 0 0 0 600 0 0 0 100 2 0 0 0 112 2 108 1 0 0 0 294 0 0 0 100 3 0 0 0 8 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 19 7 44 0 0 0 0 1132 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 21 13 3 12 0 0 1 0 527 0 0 0 100 7 0 0 1 215 103 12 0 0 0 0 2 0 0 0 100 April 1, 2026 at 07:02:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2353 251 112 0 1 0 0 0 0 0 0 100 1 0 0 0 19 3 14 0 0 0 0 600 0 0 0 100 2 0 0 0 111 2 106 0 0 0 0 294 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 19 7 42 1 0 0 0 1131 0 0 0 100 5 0 0 0 11 3 6 0 0 0 0 6 0 0 0 100 6 0 0 21 14 3 12 0 1 1 0 526 0 0 0 100 7 0 0 1 214 104 8 0 1 1 0 1 0 0 0 100 April 1, 2026 at 07:02:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2355 252 108 0 0 1 0 2 0 0 0 100 1 0 0 0 20 2 20 1 2 0 0 601 0 0 0 100 2 0 0 0 110 2 106 0 0 0 0 294 0 0 0 100 3 0 0 0 9 1 4 0 0 0 0 0 0 0 0 100 4 0 0 0 19 7 42 1 0 1 0 1128 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 21 12 3 8 0 0 0 0 526 0 0 0 100 7 0 0 1 211 103 4 0 0 0 0 0 0 0 0 100 April 1, 2026 at 07:02:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 281 0 611 2390 216 1393 43 181 42 1 6173 26 3 0 72 1 260 0 0 295 8 1192 43 175 42 0 6585 22 2 0 75 2 25 0 0 481 9 1252 31 165 43 0 6711 19 2 0 79 3 31 0 0 630 10 1102 37 149 45 0 6889 17 2 0 82 4 3 0 0 579 9 964 32 130 41 0 7881 17 2 0 82 5 784 0 0 465 17 1051 35 128 53 1 4971 18 2 0 80 6 4 0 14 274 21 1864 101 125 72 0 9213 12 2 0 86 7 2 0 14 697 115 1084 24 101 39 0 6949 18 2 0 81 April 1, 2026 at 07:02:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 227 2351 209 900 20 112 25 0 3865 12 2 0 86 1 0 0 0 178 5 589 24 81 23 0 4068 15 1 0 84 2 3 0 14 384 17 804 15 97 30 0 4903 11 1 0 88 3 0 0 0 357 4 584 18 67 12 0 3338 9 1 0 90 4 0 0 0 192 8 480 18 65 17 0 3937 16 1 0 83 5 0 0 0 417 28 662 15 63 17 0 3924 10 1 0 89 6 0 0 0 91 7 1034 45 64 51 0 4367 7 1 0 92 7 0 0 11 375 111 684 13 56 20 0 4062 12 1 0 87 April 1, 2026 at 07:02:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 2 0 5 2305 201 110 0 0 1 0 8 0 0 0 100 1 0 0 0 30 9 30 0 2 0 0 609 0 0 0 100 2 2 0 14 23 3 22 1 1 0 0 578 0 0 0 100 3 6 0 0 13 1 15 0 2 0 0 12 0 0 0 100 4 0 0 0 11 2 36 1 1 0 0 1133 0 0 0 100 5 0 0 0 114 53 112 0 0 0 0 9 0 0 0 100 6 0 0 0 11 0 8 0 2 1 0 8 0 0 0 100 7 0 0 8 216 104 14 0 0 0 0 261 0 0 0 100 April 1, 2026 at 07:02:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 106 0 0 0 0 2 0 0 0 100 1 0 0 0 24 9 18 0 0 0 0 610 0 0 0 100 2 0 0 14 16 2 16 0 1 0 0 559 0 0 0 100 3 0 0 0 7 1 2 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 1130 0 0 0 100 5 0 0 0 109 52 104 0 0 0 0 1 0 0 0 100 6 0 0 0 9 0 2 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:02:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 10 0 5 2320 202 148 0 9 9 3 114 0 0 0 99 1 7 0 0 50 11 43 0 3 7 4 662 0 0 0 100 2 308 0 14 47 2 45 1 6 3 6 668 0 0 0 100 3 115 0 0 46 1 56 0 10 11 8 141 0 0 0 100 4 60 0 0 47 2 82 1 9 6 7 1354 0 0 0 100 5 1175 0 113 59 14 79 1 6 4 8 6588 1 1 0 98 6 1958 0 3 131 41 142 2 8 3 13 377 0 1 0 99 7 10 0 8 241 104 33 0 4 9 3 316 0 0 0 100 April 1, 2026 at 07:02:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 1859 0 26 2348 218 245 5 24 168 15 488 1 1 0 98 1 80 0 2 122 19 195 5 30 35 13 904 0 0 0 100 2 15 0 28 61 4 110 3 16 2384 10 771 0 1 0 99 3 72 0 7 76 3 139 1 27 62 15 261 0 0 0 100 4 68 0 26 71 2 166 4 31 144 16 1481 0 3 0 97 5 69 0 10 127 53 99 3 14 1266 7 240 0 0 0 99 6 4 0 45 142 33 158 5 12 2062 1 40 0 1 0 99 7 5 0 32 251 106 68 1 13 2128 1 327 0 1 0 99 April 1, 2026 at 07:02:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 24 0 19 2345 232 104 1 7 9 4 39 0 1 0 99 1 7 0 0 112 42 96 0 5 3 1 628 0 0 0 100 2 1 0 14 30 3 17 1 2 2 0 567 0 0 0 100 3 8 0 0 30 4 27 1 3 2 4 18 0 0 0 100 4 2 0 0 27 3 43 1 4 0 1 834 0 0 0 100 5 3 0 0 24 1 12 0 2 2 1 9 0 0 0 100 6 22 0 56 120 3 118 0 3 6 2 14 0 0 0 100 7 8 0 8 233 104 29 0 3 3 3 315 0 0 0 100 April 1, 2026 at 07:02:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 460 2315 202 124 0 2 1 0 2 0 1 0 99 1 0 0 7 131 25 56 0 2 0 0 620 0 0 0 100 2 0 0 14 91 3 14 0 1 0 0 560 0 0 0 100 3 0 0 0 85 2 6 0 1 0 0 0 0 0 0 100 4 0 0 0 84 3 34 1 0 0 0 754 0 0 0 100 5 0 0 0 79 0 0 0 0 0 0 0 0 0 0 100 6 0 0 49 180 50 110 0 2 2 0 0 0 0 0 100 7 0 0 8 288 104 12 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:02:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 106 0 0 0 0 0 0 0 0 100 1 0 0 0 56 24 52 0 1 0 0 622 0 0 0 100 2 0 0 14 19 3 18 1 1 0 0 581 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 750 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 105 8 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:02:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 106 0 0 0 0 2 0 0 0 100 1 0 0 0 53 23 46 2 0 0 0 620 0 0 0 100 2 0 0 14 16 2 14 0 0 0 0 560 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 10 2 32 1 0 1 0 750 0 0 0 100 5 0 0 0 7 1 4 0 1 0 0 1 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:02:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 112 0 0 2 0 0 0 0 0 100 1 0 0 0 65 25 64 0 0 1 0 641 0 0 0 100 2 0 0 14 25 3 24 1 1 1 0 575 0 0 0 100 3 0 0 0 11 3 6 0 1 1 0 0 0 0 0 100 4 0 0 0 12 3 32 0 0 1 0 750 0 0 0 100 5 0 0 0 27 12 18 0 0 2 0 20 0 0 0 100 6 0 0 0 112 51 106 0 0 0 0 0 0 0 0 100 7 0 0 8 215 104 8 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:02:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 110 0 0 0 0 2 0 0 0 100 1 0 0 0 53 23 46 0 0 0 0 619 0 0 0 100 2 0 0 14 10 2 8 0 0 0 0 560 0 0 0 100 3 0 0 0 15 2 10 0 1 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 750 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:02:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 56 24 52 0 0 0 0 621 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 561 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 749 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:02:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 114 0 0 0 0 2 0 0 0 100 1 0 0 0 53 23 46 2 0 0 0 619 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 559 0 0 0 100 3 0 0 0 11 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 36 0 2 1 0 751 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 112 0 0 0 0 1 0 0 0 100 1 0 0 0 51 23 46 0 0 0 0 621 0 0 0 100 2 0 0 14 9 2 6 1 0 0 0 560 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 2 34 1 1 0 0 750 0 0 0 100 5 0 0 0 7 0 4 0 1 1 0 0 0 0 0 100 6 0 0 0 110 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 118 0 0 1 0 2 0 0 0 100 1 0 0 0 55 23 56 0 0 0 0 631 0 0 0 100 2 7 0 14 15 3 18 0 0 0 0 577 0 0 0 100 3 0 0 0 11 3 6 0 0 0 0 5 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 750 0 0 0 100 5 0 0 0 22 10 16 0 0 0 0 18 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 215 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 100 0 2 0 0 0 0 0 0 100 1 0 0 0 51 23 46 0 0 0 0 620 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 561 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 20 2 44 0 2 0 0 748 0 0 0 100 5 0 0 0 9 0 2 0 0 1 0 0 0 0 0 100 6 0 0 0 110 50 106 0 1 0 0 0 0 0 0 100 7 0 0 8 213 104 8 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:03:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 138 0 1 1 0 2 0 0 0 100 1 0 0 0 58 24 50 2 0 0 0 619 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 559 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 14 3 34 1 0 0 0 749 0 0 0 100 5 0 0 0 5 0 2 0 1 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 216 104 12 0 0 2 0 259 0 0 0 100 April 1, 2026 at 07:03:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2303 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 53 24 48 0 0 0 0 622 0 0 0 100 2 0 0 14 9 2 6 1 0 0 0 560 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 748 0 0 0 100 5 0 0 0 9 2 4 0 0 0 0 2 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 105 8 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:03:05 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 116 0 0 0 0 2 0 0 0 100 1 0 0 0 53 23 50 0 1 1 0 620 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 560 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 748 0 0 0 100 5 0 0 0 7 0 4 0 0 0 0 18 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 216 105 12 0 0 0 0 268 0 0 0 100 April 1, 2026 at 07:03:06 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 7 2303 201 116 0 0 1 0 0 0 0 0 100 1 0 0 0 65 25 64 0 0 2 0 633 0 0 0 100 2 0 0 14 20 3 24 1 1 1 0 572 0 0 0 100 3 0 0 0 12 3 4 0 0 1 0 0 0 0 0 100 4 0 0 0 12 3 32 1 0 2 0 748 0 0 0 100 5 0 0 0 20 8 12 0 0 1 0 17 0 0 0 100 6 0 0 0 113 51 104 0 0 1 0 0 0 0 0 100 7 0 0 14 216 104 10 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:03:07 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 202 114 0 0 1 0 2 0 0 0 100 1 0 0 0 53 23 46 2 0 0 0 621 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 561 0 0 0 100 3 0 0 0 11 3 8 0 1 0 0 5 0 0 0 100 4 0 0 0 9 2 34 0 1 0 0 760 0 0 0 100 5 0 0 0 8 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:08 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 43 18 36 1 0 0 0 635 0 0 0 100 2 0 0 14 28 10 26 1 2 0 0 568 0 0 0 100 3 0 0 0 10 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 10 2 36 1 1 0 0 747 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:09 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 112 0 0 0 0 2 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 599 0 0 0 100 2 0 0 14 48 22 46 0 0 0 0 581 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 2 34 1 0 0 0 747 0 0 0 100 5 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:10 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 112 0 0 0 0 1 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 601 0 0 0 100 2 0 0 14 48 22 46 1 0 0 0 579 0 0 0 100 3 0 0 0 9 2 6 0 1 0 0 0 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 749 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:11 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 116 0 0 0 0 2 0 0 0 100 1 0 0 0 23 5 22 2 0 0 0 611 0 0 0 100 2 1 0 14 52 22 54 0 0 0 0 618 0 0 0 100 3 0 0 0 10 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 34 1 1 0 0 748 0 0 0 100 5 0 0 0 19 5 14 0 0 1 0 18 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 215 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:12 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 114 0 0 0 0 0 0 0 0 100 1 0 0 0 13 3 8 0 1 0 0 599 0 0 0 100 2 0 0 14 49 22 46 1 0 0 0 580 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 747 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 110 50 106 0 1 1 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:13 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 202 112 0 0 0 0 2 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 601 0 0 0 100 2 0 0 14 49 22 46 1 0 0 0 581 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 3 34 1 0 0 0 750 0 0 0 100 5 0 0 0 7 2 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:14 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 110 0 0 0 0 0 0 0 0 100 1 0 0 0 13 4 8 0 0 0 0 601 0 0 0 100 2 0 0 14 50 23 48 0 0 0 0 600 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 32 0 0 1 0 748 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 111 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 215 105 10 0 1 0 0 260 0 0 0 100 April 1, 2026 at 07:03:15 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 0 0 3 0 2 0 0 0 100 1 0 0 0 13 3 8 2 1 0 0 599 0 0 0 100 2 0 0 14 48 22 46 0 0 0 0 580 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 747 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 216 104 12 0 0 2 0 259 0 0 0 100 April 1, 2026 at 07:03:16 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 116 0 0 1 0 0 0 0 0 100 1 0 0 0 27 8 26 0 0 1 0 625 0 0 0 100 2 0 0 14 56 23 54 2 0 1 0 591 0 0 0 100 3 0 0 0 11 3 4 0 0 1 0 0 0 0 0 100 4 0 0 0 11 3 32 1 0 1 0 749 0 0 0 100 5 0 0 0 19 8 12 0 1 0 0 8 0 0 0 100 6 0 0 0 112 51 104 0 0 1 0 0 0 0 0 100 7 0 0 8 215 104 10 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:03:17 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 116 0 0 3 0 2 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 601 0 0 0 100 2 0 0 14 49 22 46 1 0 0 0 580 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 8 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 216 104 10 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:03:18 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 114 0 1 0 0 0 0 0 0 100 1 0 0 0 14 4 10 0 0 0 0 600 0 0 0 100 2 0 0 14 48 22 46 0 0 0 0 581 0 0 0 100 3 0 0 0 10 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 2 36 1 1 2 0 749 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 1 0 0 0 0 0 0 100 7 0 0 8 216 104 12 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:19 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 203 112 0 0 0 0 2 0 0 0 100 1 0 0 0 14 3 6 2 0 0 0 600 0 0 0 100 2 0 0 14 48 22 46 0 0 0 0 580 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 9 2 34 1 1 1 0 747 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:20 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 0 0 2 0 1 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 600 0 0 0 100 2 0 0 14 49 22 46 1 0 0 0 579 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 12 2 38 0 1 1 0 747 0 0 0 100 5 0 0 0 8 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:21 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 118 0 0 0 0 2 0 0 0 100 1 0 0 0 16 3 16 0 0 0 0 612 0 0 0 100 2 0 0 14 52 22 54 1 0 0 0 592 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 2 36 1 1 2 0 749 0 0 0 100 5 0 0 0 22 8 18 0 1 0 0 18 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 215 104 8 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:22 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 112 0 0 0 0 0 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 601 0 0 0 100 2 0 0 14 48 22 46 0 0 0 0 580 0 0 0 100 3 1 0 0 11 3 6 0 0 0 0 5 0 0 0 100 4 0 0 0 10 2 34 1 1 1 0 759 0 0 0 100 5 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:23 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2309 203 114 0 0 0 0 2 0 0 0 100 1 0 0 0 16 4 10 2 0 0 0 599 0 0 0 100 2 0 0 14 46 21 44 0 0 0 0 579 0 0 0 100 3 0 0 0 9 2 4 0 0 0 0 0 0 0 0 100 4 0 0 0 11 3 36 0 0 0 0 748 0 0 0 100 5 0 0 0 9 0 4 0 0 2 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:24 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 13 4 8 0 0 0 0 601 0 0 0 100 2 0 0 14 11 3 8 1 1 0 0 560 0 0 0 100 3 0 0 0 48 21 44 0 1 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 749 0 0 0 100 5 0 0 0 12 2 6 0 0 1 0 2 0 0 0 100 6 0 0 0 112 50 108 0 1 1 0 0 0 0 0 100 7 0 0 8 214 105 8 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:03:25 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2305 202 112 0 0 0 0 2 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 600 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 560 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 0 0 0 0 748 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 1 0 0 0 0 0 0 100 7 0 0 9 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:26 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 116 0 0 1 0 0 0 0 0 100 1 0 0 0 21 5 20 0 0 1 0 613 0 0 0 100 2 1 0 14 14 3 14 0 0 1 0 570 0 0 0 100 3 0 0 0 51 23 44 0 0 1 0 20 0 0 0 100 4 0 0 0 11 3 32 1 0 2 0 748 0 0 0 100 5 0 0 0 19 8 12 0 0 1 0 17 0 0 0 100 6 0 0 0 114 51 108 0 0 1 0 0 0 0 0 100 7 0 0 8 217 104 14 0 1 1 0 259 0 0 0 100 April 1, 2026 at 07:03:27 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2305 202 114 0 0 0 0 2 0 0 0 100 1 0 0 0 13 3 6 2 0 0 0 599 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 561 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 10 2 34 1 0 0 0 748 0 0 0 100 5 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 9 219 104 16 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:28 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 110 0 0 0 0 0 0 0 0 100 1 0 0 0 16 5 12 0 0 0 0 602 0 0 0 100 2 0 0 14 10 2 6 1 0 0 0 559 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 34 0 1 0 0 748 0 0 0 100 5 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:29 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 134 0 1 1 0 2 0 0 0 100 1 0 0 0 11 3 6 0 0 0 0 600 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 561 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 8 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:03:30 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 202 114 0 0 0 0 1 0 0 0 100 1 0 0 0 12 3 8 0 1 0 0 599 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 559 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 8 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:03:31 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2306 202 118 0 0 0 0 2 0 0 0 100 1 0 0 0 21 5 20 2 0 0 0 618 0 0 0 100 2 1 0 14 12 2 14 0 0 0 0 572 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 0 0 1 0 747 0 0 0 100 5 0 0 0 17 6 12 0 0 1 0 13 0 0 0 100 6 0 0 0 109 50 104 0 1 0 0 0 0 0 0 100 7 0 0 9 215 104 8 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:32 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 203 116 0 0 0 0 0 0 0 0 100 1 0 0 0 19 4 12 0 1 2 0 600 0 0 0 100 2 0 0 14 11 3 8 1 0 1 0 561 0 0 0 100 3 0 0 0 51 23 48 0 1 0 0 20 0 0 0 100 4 0 0 0 12 3 34 1 0 1 0 749 0 0 0 100 5 0 0 0 9 2 6 0 1 0 0 1 0 0 0 100 6 0 0 0 111 51 104 0 0 1 0 0 0 0 0 100 7 0 0 8 215 105 10 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:03:33 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 200 112 0 0 0 0 2 0 0 0 100 1 0 0 0 18 5 14 0 0 1 0 599 0 0 0 100 2 0 0 14 10 2 10 1 1 1 0 559 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 10 3 34 0 0 0 0 749 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:34 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 15 5 10 0 0 0 0 602 0 0 0 100 2 0 0 14 10 3 8 0 0 0 0 580 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 10 2 34 2 1 1 0 747 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 9 214 105 8 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:03:35 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 2 0 0 0 100 1 0 0 0 15 4 8 2 0 0 0 599 0 0 0 100 2 0 0 14 10 2 8 0 0 0 0 561 0 0 0 100 3 0 0 0 50 22 46 0 1 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 749 0 0 0 100 5 0 0 0 7 0 4 0 0 0 0 18 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 216 105 12 0 0 0 0 268 0 0 0 100 April 1, 2026 at 07:03:36 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2304 201 118 0 1 0 0 0 0 0 0 100 1 0 0 0 24 6 24 0 0 1 0 618 0 0 0 100 2 0 0 14 15 3 14 1 0 1 0 570 0 0 0 100 3 0 0 0 55 23 48 0 0 1 0 20 0 0 0 100 4 0 0 0 11 3 32 1 0 1 0 748 0 0 0 100 5 0 0 0 22 8 12 0 0 1 0 17 0 0 0 100 6 0 0 0 112 51 104 0 0 1 0 0 0 0 0 100 7 0 0 9 215 104 10 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:03:37 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2306 202 110 0 0 0 0 2 0 0 0 100 1 0 0 0 13 4 8 0 0 0 0 601 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 560 0 0 0 100 3 0 0 0 51 23 46 0 0 0 0 21 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 9 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:38 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2308 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 16 5 14 0 1 0 0 599 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 559 0 0 0 100 3 0 0 0 51 22 46 0 0 1 0 20 0 0 0 100 4 0 0 0 11 2 34 1 1 0 0 748 0 0 0 100 5 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:39 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2302 201 112 0 0 1 0 2 0 0 0 100 1 0 0 0 15 4 8 2 0 0 0 600 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 560 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 1 0 748 0 0 0 100 5 0 0 0 8 0 4 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 9 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:40 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 110 0 0 0 0 1 0 0 0 100 1 0 0 0 15 5 10 0 0 0 0 601 0 0 0 100 2 0 0 14 9 2 6 1 0 0 0 561 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 7 1 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 1 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:41 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 118 0 0 0 0 2 0 0 0 100 1 0 0 0 23 6 26 0 0 0 0 630 0 0 0 100 2 0 0 14 12 2 14 1 0 0 0 569 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 748 0 0 0 100 5 0 0 0 20 6 12 0 0 1 0 4 0 0 0 100 6 0 0 0 110 50 108 0 1 0 0 0 0 0 0 100 7 0 0 8 215 104 8 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:03:42 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 110 0 0 0 0 2 0 0 0 100 1 0 0 0 17 4 10 0 1 0 0 600 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 560 0 0 0 100 3 0 0 0 49 22 46 0 1 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 747 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 111 50 104 0 0 1 0 0 0 0 0 100 7 0 0 8 213 104 8 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:03:43 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2310 203 114 0 0 0 0 8 0 0 0 100 1 0 0 0 18 5 12 2 0 0 0 600 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 560 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 12 3 36 1 0 0 0 751 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 215 104 12 0 0 0 0 261 0 0 0 100 April 1, 2026 at 07:03:44 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 20 5 16 0 0 0 0 601 0 0 0 100 2 0 0 14 9 2 6 1 0 0 0 560 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 748 0 0 0 100 5 0 0 0 13 4 6 0 0 0 0 3 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 105 8 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:03:45 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 112 0 0 0 0 2 0 0 0 100 1 0 0 0 15 4 10 0 0 1 0 599 0 0 0 100 2 0 0 14 13 2 16 1 1 1 0 560 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:46 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2304 201 112 0 0 1 0 0 0 0 0 100 1 1 0 0 24 6 24 0 0 1 0 615 0 0 0 100 2 0 0 14 14 3 14 0 0 1 0 572 0 0 0 100 3 0 0 0 52 23 46 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 32 1 0 1 0 748 0 0 0 100 5 0 0 0 23 11 12 0 0 1 0 17 0 0 0 100 6 0 0 0 112 51 104 0 0 1 0 0 0 0 0 100 7 0 0 9 215 104 10 0 0 1 0 259 0 0 0 100 April 1, 2026 at 07:03:47 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 110 0 0 0 0 2 0 0 0 100 1 0 0 0 15 4 8 2 0 0 0 600 0 0 0 100 2 0 0 14 10 2 8 0 0 1 0 560 0 0 0 100 3 0 0 0 50 22 46 0 1 0 0 20 0 0 0 100 4 0 0 0 9 2 34 0 1 0 0 748 0 0 0 100 5 0 0 0 7 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:48 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 16 5 12 0 0 0 0 600 0 0 0 100 2 0 0 14 9 2 6 1 0 0 0 561 0 0 0 100 3 0 0 0 50 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 11 2 34 1 1 0 0 747 0 0 0 100 5 0 0 0 6 0 2 0 1 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:49 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2306 202 112 0 0 0 0 2 0 0 0 100 1 0 0 0 15 5 10 0 0 0 0 602 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 559 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 749 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 9 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:50 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 202 114 0 1 0 0 1 0 0 0 100 1 0 0 0 13 4 8 0 0 0 0 599 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 560 0 0 0 100 3 0 0 0 50 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 748 0 0 0 100 5 0 0 0 7 0 2 0 0 0 0 0 0 0 0 100 6 0 0 0 110 50 104 0 1 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:51 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2305 201 116 0 0 0 0 0 0 0 0 100 1 0 0 0 26 6 27 2 2 0 0 620 0 0 0 100 2 0 0 14 12 2 14 0 0 0 0 573 0 0 0 100 3 0 0 0 50 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 11 2 32 1 0 0 0 747 0 0 0 100 5 1 0 0 30 14 18 1 0 1 0 20 0 0 0 100 6 0 0 0 111 50 106 0 0 0 0 0 0 0 0 100 7 0 0 8 217 104 12 0 1 0 0 259 0 0 0 100 April 1, 2026 at 07:03:52 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2304 201 108 0 0 0 0 0 0 0 0 100 1 0 0 0 13 4 8 0 0 0 0 599 0 0 0 100 2 0 0 14 9 2 6 1 0 0 0 559 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 749 0 0 0 100 5 0 0 0 7 0 3 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 9 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:53 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2306 201 124 0 1 1 0 0 0 0 0 100 1 0 0 0 20 7 16 0 0 0 0 627 0 0 0 100 2 0 0 14 8 2 6 1 0 0 0 561 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 11 3 34 1 0 1 0 749 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 216 104 12 0 0 2 0 259 0 0 0 100 April 1, 2026 at 07:03:54 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 16 5 12 0 1 0 0 601 0 0 0 100 2 0 0 14 10 3 8 0 0 0 0 580 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 7 1 2 0 0 0 0 1 0 0 0 100 6 0 0 0 109 50 104 0 1 0 0 0 0 0 0 100 7 0 0 8 214 105 8 0 0 0 0 260 0 0 0 100 April 1, 2026 at 07:03:55 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 17 5 10 2 0 0 0 602 0 0 0 100 2 0 0 14 8 2 6 0 0 0 0 560 0 0 0 100 3 0 0 0 49 22 44 0 0 0 0 20 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 748 0 0 0 100 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 100 6 0 0 0 109 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 212 104 6 0 0 0 0 259 0 0 0 100 April 1, 2026 at 07:03:56 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 8 2309 201 132 0 0 2 0 1 0 0 0 100 1 1299 0 1 35 6 42 1 0 2 0 652 0 0 0 100 2 0 0 14 21 3 26 1 1 1 0 586 0 0 0 100 3 0 0 0 38 16 30 0 0 1 0 19 0 0 0 100 4 0 0 0 13 3 32 1 0 1 0 746 0 0 0 100 5 7 0 0 73 53 27 0 0 5 0 141 0 0 0 100 6 0 0 0 113 51 104 0 0 1 0 0 0 0 0 100 7 0 0 14 222 104 20 0 1 4 0 259 0 0 0 100 April 1, 2026 at 07:03:57 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2317 201 2794 6 5 109 0 7 0 1 0 99 1 0 0 0 150 8 410 3 1 2653 0 2394 1 3 0 96 2 0 0 14 12 2 10 1 0 1 0 562 0 0 0 100 3 0 0 0 10 2 6 0 1 0 0 0 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 1281 0 0 6950 6930 218 60 5 6042 0 71 0 4 0 96 6 0 0 0 109 50 102 0 0 0 0 0 0 0 0 100 7 0 0 8 757 104 2149 3 2 1682 0 262 0 2 0 98 April 1, 2026 at 07:03:58 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2306 201 158 0 3 34 0 0 0 0 0 100 1 0 0 0 49 7 68 0 3 34 0 613 0 0 0 100 2 1 0 14 39 2 70 1 4 30 0 589 0 0 0 100 3 0 0 0 43 16 45 0 1 23 0 0 0 0 0 100 4 0 0 0 44 15 78 0 4 22 0 747 0 0 0 100 5 0 0 0 49 14 55 0 4 25 0 0 0 0 0 100 6 0 0 0 128 50 145 0 4 21 0 0 0 0 0 100 7 0 0 9 234 104 52 0 3 31 0 259 0 0 0 100 April 1, 2026 at 07:03:59 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 270 0 2 26 0 0 0 0 0 100 1 0 0 0 43 5 62 0 1 14 0 603 0 0 0 100 2 0 0 14 51 4 84 0 2 29 0 645 0 0 0 100 3 0 0 0 49 19 44 0 1 21 0 3 0 0 0 100 4 0 0 0 42 21 60 1 4 8 0 746 0 0 0 100 5 0 0 0 305 270 59 0 2 103 0 0 0 0 0 100 6 0 0 0 132 50 154 0 1 24 0 0 0 0 0 100 7 0 0 8 276 104 128 0 3 56 0 259 0 0 0 100 April 1, 2026 at 07:04:00 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 202 284 0 1 6 0 1 0 0 0 100 1 0 0 0 17 4 12 2 0 0 0 600 0 0 0 100 2 0 0 14 33 4 48 0 0 34 0 679 0 0 0 100 3 0 0 0 12 2 8 0 0 0 0 3 0 0 0 100 4 0 0 0 9 2 32 1 0 0 0 748 0 0 0 100 5 0 0 0 437 426 7 0 2 189 0 0 0 0 0 100 6 0 0 0 108 50 102 0 1 0 0 0 0 0 0 100 7 0 0 8 270 104 122 0 0 60 0 259 0 0 0 100 April 1, 2026 at 07:04:01 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2305 201 243 0 0 6 0 0 0 0 0 100 1 0 0 0 20 5 24 0 0 0 0 616 0 0 0 100 2 0 0 14 44 8 56 3 0 13 0 667 0 0 0 100 3 0 0 0 14 2 14 0 0 0 0 13 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 747 0 0 0 100 5 0 0 0 294 286 4 0 0 82 0 0 0 0 0 100 6 0 0 0 108 50 102 0 0 0 0 0 0 0 0 100 7 0 0 9 265 104 108 0 0 35 0 259 0 0 0 100 April 1, 2026 at 07:04:02 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2304 201 110 0 0 0 0 0 0 0 0 100 1 0 0 0 15 4 12 0 0 0 0 601 0 0 0 100 2 0 0 14 20 4 22 0 0 0 0 598 0 0 0 100 3 0 0 0 10 2 6 0 0 0 0 3 0 0 0 100 4 0 0 0 9 2 32 1 0 1 0 747 0 0 0 100 5 0 0 0 21 14 4 0 0 0 0 0 0 0 0 100 6 0 0 0 110 50 104 0 0 0 0 0 0 0 0 100 7 0 0 8 214 104 10 0 1 1 0 259 0 0 0 100 April 1, 2026 at 07:04:03 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 5 2307 201 206 0 0 4 0 0 0 0 0 100 1 0 0 0 16 5 12 0 0 0 0 602 0 0 0 100 2 0 0 14 28 4 38 0 0 21 0 642 0 0 0 100 3 0 0 0 13 3 10 0 0 1 0 3 0 0 0 100 4 0 0 0 12 3 36 1 0 0 0 748 0 0 0 100 5 0 0 0 243 238 0 0 0 72 0 0 0 0 0 100 6 0 0 0 108 50 104 0 0 3 0 0 0 0 0 100 7 0 0 8 261 104 98 0 0 27 0 259 0 0 0 100 April 1, 2026 at 07:04:04 PM UTC CPU minf mjf xcal intr ithr csw icsw migr smtx srw syscl usr sys wt idl 0 0 0 4 2307 201 146 0 0 2 0 0 0 0 0 100 1 0 0 0 20 5 16 2 0 0 0 603 0 0 0 100 2 1 0 14 25 4 32 0 0 3 0 622 0 0 0 100 3 0 0 0 11 2 8 0 0 0 0 6 0 0 0 100 4 0 0 0 8 2 32 0 0 0 0 747 0 0 0 100 5 0 0 0 96 88 6 0 0 20 0 1 0 0 0 100 6 0 0 0 108 50 102 0 1 0 0 0 0 0 0 100 7 0 0 9 226 105 30 0 0 11 0 260 0 0 0 100