+---------------------------------------------------------------------+
|  Log file: pa.results.log                                           |
|  Compiler version: 9.13.4                                           |
|  Created on: Tue May 19 02:01:26 2026                               |
|  Run ID: 7efab217e53a458e                                           |
+---------------------------------------------------------------------+

Allocation state: Final Allocation
------------------------------------------------------------------------------
|       PHV Group        | Containers Used |   Bits Used   | Bits Available |
| (container bit widths) |     (% used)    |    (% used)   |                |
------------------------------------------------------------------------------
|         0 (32)         |   18 (90.00%)   |  571 (89.22%) |      640       |
|         1 (32)         |   16 (80.00%)   |  465 (72.66%) |      640       |
|         2 (32)         |    7 (35.00%)   |  224 (35.00%) |      640       |
|         3 (32)         |    8 (40.00%)   |  256 (40.00%) |      640       |
|    Total for 32 bit    |   49 (61.25%)   | 1516 (59.22%) |      2560      |
|                        |                 |               |                |
|         4 (8)          |   16 (80.00%)   |  117 (73.12%) |      160       |
|         5 (8)          |   10 (50.00%)   |  80 (50.00%)  |      160       |
|         6 (8)          |    1 (5.00%)    |   1 (0.62%)   |      160       |
|         7 (8)          |    0 (0.00%)    |   0 (0.00%)   |      160       |
|    Total for 8 bit     |   27 (33.75%)   |  198 (30.94%) |      640       |
|                        |                 |               |                |
|         8 (16)         |   17 (85.00%)   |  230 (71.88%) |      320       |
|         9 (16)         |   16 (80.00%)   |  242 (75.62%) |      320       |
|        10 (16)         |    4 (20.00%)   |  64 (20.00%)  |      320       |
|        11 (16)         |    5 (25.00%)   |  80 (25.00%)  |      320       |
|        12 (16)         |    4 (20.00%)   |  64 (20.00%)  |      320       |
|        13 (16)         |    1 (5.00%)    |   16 (5.00%)  |      320       |
|    Total for 16 bit    |   47 (39.17%)   |  696 (36.25%) |      1920      |
|                        |                 |               |                |
|     Overall total      |   123 (43.93%)  | 2410 (47.07%) |      5120      |
------------------------------------------------------------------------------

--------------------------------------------
PHV Allocation
--------------------------------------------

Allocations in Group 0 32 bits
  32-bit PHV 0n (ingress): phv0[31:28] = hdr.tcp.data_offset[3:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[31:28] = hdr.inner_tcp.data_offset[3:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[27:24] = hdr.tcp.res[3:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[27:24] = hdr.inner_tcp.res[3:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[23:16] = hdr.tcp.flags[7:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[23:16] = hdr.inner_tcp.flags[7:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[15:0] = hdr.tcp.window[15:0] (deparsed)
  32-bit PHV 0n (ingress): phv0[15:0] = hdr.inner_tcp.window[15:0] (deparsed)
  32-bit PHV 1n (ingress): phv1[31:16] = hdr.geneve_opts.oxg_ext_tag.class[15:0] (deparsed)
  32-bit PHV 1n (ingress): phv1[15:15] = hdr.geneve_opts.oxg_ext_tag.crit[0:0] (deparsed)
  32-bit PHV 1n (ingress): phv1[14:8] = hdr.geneve_opts.oxg_ext_tag.type[6:0] (deparsed)
  32-bit PHV 1n (ingress): phv1[7:5] = hdr.geneve_opts.oxg_ext_tag.reserved[2:0] (deparsed)
  32-bit PHV 1n (ingress): phv1[4:0] = hdr.geneve_opts.oxg_ext_tag.opt_len[4:0] (deparsed)
  32-bit PHV 2n (ingress): phv2[31:0] = meta.orig_src_ipv4[31:0]
  32-bit PHV 2n (ingress): phv2[7:0] = l3_router_fwd.ecmp_hash[7:0]
  32-bit PHV 3n (ingress): phv3[31:0] = meta.nat_ingress_tgt[127:96]
  32-bit PHV 3n (ingress): phv3[7:0] = $tmp10[7:0]
  32-bit PHV 4n (ingress): phv4[31:30] = hdr.geneve.version[1:0] (deparsed)
  32-bit PHV 4n (ingress): phv4[29:24] = hdr.geneve.opt_len[5:0] (deparsed)
  32-bit PHV 4n (ingress): phv4[23:23] = hdr.geneve.ctrl[0:0] (deparsed)
  32-bit PHV 4n (ingress): phv4[22:22] = hdr.geneve.crit[0:0] (deparsed)
  32-bit PHV 4n (ingress): phv4[21:16] = hdr.geneve.reserved[5:0] (deparsed)
  32-bit PHV 4n (ingress): phv4[15:0] = hdr.geneve.protocol[15:0] (deparsed)
  32-bit PHV 5n (ingress): phv5[31:0] = meta.nexthop[31:0]
  32-bit PHV 5n (ingress): phv5[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed)
  32-bit PHV 5n (ingress): phv5[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed)
  32-bit PHV 6n (egress): phv6[31:0] = hdr.ipv6.dst_addr[127:96] (deparsed)
  32-bit PHV 7n (ingress): phv7[31:0] = meta.nat_inner_mac[31:0]
  32-bit PHV 7n (ingress): phv7[7:0] = $tmp11[7:0]
  32-bit PHV 8n (ingress): phv8[31:0] = meta.nexthop[63:32]
  32-bit PHV 8n (ingress): phv8[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed)
  32-bit PHV 8n (ingress): phv8[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed)
  32-bit PHV 9n (ingress): phv9[31:0] = hdr.sidecar.sc_payload[31:0] (deparsed)
  32-bit PHV 10n (ingress): phv10[31:0] = hdr.sidecar.sc_payload[63:32] (deparsed)
  32-bit PHV 11n (ingress): phv11[26:26] = meta.encap_needed[0:0]
  32-bit PHV 11n (ingress): phv11[25:16] = meta.pkt_type[9:0]
  32-bit PHV 11n (ingress): phv11[15:0] = meta.nat_ingress_csum[15:0] (deparsed)
  32-bit PHV 12m (ingress): phv12[31:0] = hdr.inner_ipv4.dst_addr[31:0] (deparsed)
  32-bit PHV 12m (ingress): phv12[31:0] = hdr.inner_ipv6.dst_addr[127:96] (deparsed)
  32-bit PHV 13m (ingress): phv13[31:0] = hdr.ipv4.dst_addr[31:0] (deparsed)
  32-bit PHV 13m (ingress): phv13[31:0] = hdr.ipv6.dst_addr[127:96] (deparsed)
  32-bit PHV 14m (ingress): phv14[31:0] = hdr.inner_ipv4.src_addr[31:0] (deparsed)
  32-bit PHV 14m (ingress): phv14[31:0] = hdr.inner_ipv6.src_addr[127:96] (deparsed)
  32-bit PHV 15m (ingress): phv15[31:0] = hdr.ipv4.src_addr[31:0] (deparsed)
  32-bit PHV 15m (ingress): phv15[31:0] = hdr.ipv6.src_addr[127:96] (deparsed)
  32-bit PHV 16d (ingress): phv16[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed)
  32-bit PHV 17d (ingress): phv17[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed)
  >> 17 in ingress and 1 in egress

Allocations in Group 1 32 bits
  32-bit PHV 20n (ingress): phv20[31:16] = hdr.ipv4.identification[15:0] (deparsed)
  32-bit PHV 20n (ingress): phv20[31:0] = hdr.ipv6.dst_addr[31:0] (deparsed)
  32-bit PHV 20n (ingress): phv20[15:13] = hdr.ipv4.flags[2:0] (deparsed)
  32-bit PHV 20n (ingress): phv20[12:0] = hdr.ipv4.frag_offset[12:0] (deparsed)
  32-bit PHV 21n (ingress): phv21[31:16] = hdr.inner_ipv4.identification[15:0] (deparsed)
  32-bit PHV 21n (ingress): phv21[31:28] = hdr.inner_ipv6.version[3:0] (deparsed)
  32-bit PHV 21n (ingress): phv21[27:20] = hdr.inner_ipv6.traffic_class[7:0] (deparsed)
  32-bit PHV 21n (ingress): phv21[19:0] = hdr.inner_ipv6.flow_label[19:0] (deparsed)
  32-bit PHV 21n (ingress): phv21[15:13] = hdr.inner_ipv4.flags[2:0] (deparsed)
  32-bit PHV 21n (ingress): phv21[12:0] = hdr.inner_ipv4.frag_offset[12:0] (deparsed)
  32-bit PHV 22n (ingress): phv22[31:0] = meta.nat_ingress_tgt[31:0]
  32-bit PHV 23n (ingress): phv23[15:0] = meta.l4_dst_port[15:0]
  32-bit PHV 24n (ingress): phv24[31:28] = hdr.ipv6.version[3:0] (deparsed)
  32-bit PHV 24n (ingress): phv24[27:20] = hdr.ipv6.traffic_class[7:0] (deparsed)
  32-bit PHV 24n (ingress): phv24[19:0] = hdr.ipv6.flow_label[19:0] (deparsed)
  32-bit PHV 25n (ingress): phv25[31:16] = hdr.udp.src_port[15:0] (deparsed)
  32-bit PHV 25n (ingress): phv25[15:0] = hdr.udp.dst_port[15:0] (deparsed)
  32-bit PHV 26n (egress): phv26[31:0] = hdr.ethernet.src_mac[31:0] (deparsed)
  32-bit PHV 27n (egress): phv27[31:0] = hdr.ipv6.dst_addr[31:0] (deparsed)
  32-bit PHV 28n (egress): phv28[31:0] = hdr.ipv6.dst_addr[63:32] (deparsed)
  32-bit PHV 29n (egress): phv29[31:0] = hdr.ipv6.dst_addr[95:64] (deparsed)
  32-bit PHV 30n (ingress): phv30[31:0] = meta.orig_dst_ipv4[31:0]
  32-bit PHV 31n (egress): phv31[17:17] = meta.bridge_hdr.nat_egress_hit[0:0]
  32-bit PHV 32m (ingress): phv32[31:0] = hdr.inner_ipv6.dst_addr[31:0] (deparsed)
  32-bit PHV 33m (ingress): phv33[31:0] = hdr.inner_ipv6.src_addr[31:0] (deparsed)
  32-bit PHV 34m (ingress): phv34[31:0] = hdr.ipv6.src_addr[31:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[31:0] = hdr.icmp.data[31:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[31:16] = hdr.tcp.checksum[15:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[31:16] = hdr.inner_tcp.checksum[15:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[31:16] = hdr.inner_udp.src_port[15:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[31:0] = hdr.inner_icmp.data[31:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[15:0] = hdr.tcp.urgent_ptr[15:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[15:0] = hdr.inner_tcp.urgent_ptr[15:0] (deparsed)
  32-bit PHV 35m (ingress): phv35[15:0] = hdr.inner_udp.dst_port[15:0] (deparsed)
  >> 11 in ingress and 5 in egress

Allocations in Group 2 32 bits
  32-bit PHV 40n (ingress): phv40[31:0] = hdr.ipv6.dst_addr[63:32] (deparsed)
  32-bit PHV 41n (ingress): phv41[31:0] = hdr.tcp.ack_no[31:0] (deparsed)
  32-bit PHV 41n (ingress): phv41[31:0] = hdr.inner_tcp.ack_no[31:0] (deparsed)
  32-bit PHV 42n (ingress): phv42[31:0] = meta.nat_ingress_tgt[63:32]
  32-bit PHV 52m (ingress): phv52[31:0] = hdr.inner_ipv6.dst_addr[63:32] (deparsed)
  32-bit PHV 53m (ingress): phv53[31:0] = hdr.inner_ipv6.src_addr[63:32] (deparsed)
  32-bit PHV 54m (ingress): phv54[31:0] = hdr.ipv6.src_addr[63:32] (deparsed)
  32-bit PHV 55m (ingress): phv55[31:16] = hdr.tcp.src_port[15:0] (deparsed)
  32-bit PHV 55m (ingress): phv55[31:16] = hdr.inner_tcp.src_port[15:0] (deparsed)
  32-bit PHV 55m (ingress): phv55[15:0] = hdr.tcp.dst_port[15:0] (deparsed)
  32-bit PHV 55m (ingress): phv55[15:0] = hdr.inner_tcp.dst_port[15:0] (deparsed)
  >> 7 in ingress and 0 in egress

Allocations in Group 3 32 bits
  32-bit PHV 60n (ingress): phv60[31:0] = hdr.ipv6.dst_addr[95:64] (deparsed)
  32-bit PHV 61n (ingress): phv61[31:0] = hdr.tcp.seq_no[31:0] (deparsed)
  32-bit PHV 61n (ingress): phv61[31:0] = hdr.inner_tcp.seq_no[31:0] (deparsed)
  32-bit PHV 62n (ingress): phv62[31:0] = meta.nat_ingress_tgt[95:64]
  32-bit PHV 63n (ingress): phv63[31:0] = meta.orig_src_mac[31:0]
  32-bit PHV 72m (ingress): phv72[31:0] = hdr.inner_ipv6.dst_addr[95:64] (deparsed)
  32-bit PHV 73m (ingress): phv73[31:0] = hdr.inner_ipv6.src_addr[95:64] (deparsed)
  32-bit PHV 74m (ingress): phv74[31:0] = hdr.ipv6.src_addr[95:64] (deparsed)
  32-bit PHV 75m (ingress): phv75[31:0] = hdr.ethernet.dst_mac[31:0] (deparsed)
  >> 8 in ingress and 0 in egress

Allocations in Group 4 8 bits
  8-bit PHV 80n (ingress): phv80[7:0] = $tmp7[7:0] (deparsed)
  8-bit PHV 81n (ingress): phv81[7:7] = hdr.arp.$valid[0:0] (deparsed)
  8-bit PHV 81n (ingress): phv81[6:6] = hdr.ipv6.$valid[0:0] (deparsed)
  8-bit PHV 81n (ingress): phv81[5:5] = hdr.geneve_opts.oxg_mss.$valid[0:0]
  8-bit PHV 81n (ingress): phv81[4:4] = hdr.geneve_opts.oxg_mss_tag.$valid[0:0] (deparsed)
  8-bit PHV 81n (ingress): phv81[3:3] = hdr.geneve_opts.oxg_mcast.$valid[0:0]
  8-bit PHV 81n (ingress): phv81[2:2] = hdr.geneve_opts.oxg_mcast_tag.$valid[0:0] (deparsed)
  8-bit PHV 81n (ingress): phv81[1:1] = hdr.geneve_opts.oxg_ext_tag.$valid[0:0] (deparsed)
  8-bit PHV 81n (ingress): phv81[0:0] = hdr.inner_ipv6.$valid[0:0] (deparsed)
  8-bit PHV 82n (ingress): phv82[7:7] = meta.nexthop_is_v6[0:0]
  8-bit PHV 82n (ingress): phv82[6:6] = meta.resolve_nexthop[0:0]
  8-bit PHV 82n (ingress): phv82[5:3] = ig_intr_md_for_dprsr.drop_ctl[2:0] (deparsed)
  8-bit PHV 82n (ingress): phv82[2:2] = hdr.icmp.hdr_checksum.$deparse_updated_csum_0[0:0] (deparsed)
  8-bit PHV 82n (ingress): phv82[1:1] = hdr.icmp.hdr_checksum.$deparse_original_csum[0:0] (deparsed)
  8-bit PHV 82n (ingress): phv82[0:0] = hdr.vlan.$valid[0:0] (deparsed)
  8-bit PHV 83n (ingress): phv83[7:7] = meta.is_mcast[0:0]
  8-bit PHV 83n (ingress): phv83[6:6] = meta.is_switch_address[0:0]
  8-bit PHV 83n (ingress): phv83[5:5] = meta.is_link_local_mcastv6[0:0]
  8-bit PHV 83n (ingress): phv83[4:4] = hdr.udp.checksum.$deparse_updated_csum_3[0:0] (deparsed)
  8-bit PHV 83n (ingress): phv83[3:3] = hdr.udp.checksum.$deparse_updated_csum_2[0:0] (deparsed)
  8-bit PHV 83n (ingress): phv83[2:2] = hdr.udp.checksum.$deparse_updated_csum_1[0:0] (deparsed)
  8-bit PHV 83n (ingress): phv83[1:1] = hdr.udp.checksum.$deparse_updated_csum_0[0:0] (deparsed)
  8-bit PHV 83n (ingress): phv83[0:0] = hdr.udp.checksum.$deparse_original_csum[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[7:7] = hdr.geneve.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[6:6] = hdr.udp.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[5:5] = hdr.ipv4.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[4:4] = hdr.vlan.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[3:3] = hdr.ethernet.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[2:2] = eg_intr_md_for_dprsr.drop_ctl.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[1:1] = eg_intr_md.egress_port.$valid[0:0] (deparsed)
  8-bit PHV 84n (egress): phv84[0:0] = eg_intr_md_for_dprsr.mirror_io_select.$valid[0:0] (deparsed)
  8-bit PHV 85n (ingress): phv85[7:0] = meta.route_ttl_is_1[7:0]
  8-bit PHV 85n (ingress): phv85[7:0] = meta.nat_geneve_vni[23:16]
  8-bit PHV 85n (ingress): phv85[0:0] = $tmp12[0:0]
  8-bit PHV 86n (ingress): phv86[0:0] = meta.skip_ttl_check[0:0]
  8-bit PHV 88n (ingress): phv88[7:0] = hdr.ipv4.ttl[7:0] (deparsed)
  8-bit PHV 88n (ingress): phv88[7:0] = hdr.ipv6.hop_limit[7:0] (deparsed)
  8-bit PHV 89n (ingress): phv89[7:7] = meta.nat_egress_hit[0:0]
  8-bit PHV 89n (ingress): phv89[7:7] = meta.bridge_hdr.__pad_0[0:0]
  8-bit PHV 89n (ingress): phv89[6:2] = meta.bridge_hdr.reserved[4:0] (deparsed)
  8-bit PHV 89n (ingress): phv89[1:1] = meta.uplink_ingress[0:0]
  8-bit PHV 89n (ingress): phv89[1:1] = meta.bridge_hdr.nat_egress_hit[0:0] (deparsed)
  8-bit PHV 89n (ingress): phv89[0:0] = meta.bridge_hdr.is_mcast_routed[0:0] (deparsed)
  8-bit PHV 90n (ingress): phv90[7:0] = meta.nexthop[87:80]
  8-bit PHV 90n (ingress): phv90[7:0] = hdr.geneve.vni[23:16] (deparsed)
  8-bit PHV 90n (ingress): phv90[7:0] = hdr.geneve.vni[23:16] (deparsed)
  8-bit PHV 91n (ingress): phv91[7:0] = hdr.sidecar.sc_payload[87:80] (deparsed)
  8-bit PHV 92m (ingress): phv92[7:0] = hdr.inner_ipv4.ttl[7:0] (deparsed)
  8-bit PHV 92m (ingress): phv92[7:0] = hdr.inner_ipv6.hop_limit[7:0] (deparsed)
  8-bit PHV 93m (ingress): phv93[3:0] = ig_intr_md_for_dprsr.mirror_type[3:0] (deparsed)
  8-bit PHV 94m (ingress): phv94[7:0] = hdr.inner_ipv4.protocol[7:0] (deparsed)
  8-bit PHV 94m (ingress): phv94[7:0] = hdr.inner_ipv6.next_hdr[7:0] (deparsed)
  8-bit PHV 95m (ingress): phv95[7:0] = hdr.ipv4.protocol[7:0] (deparsed)
  8-bit PHV 95m (ingress): phv95[7:0] = hdr.ipv6.next_hdr[7:0] (deparsed)
  8-bit PHV 96d (ingress): phv96[7:0] = hdr.geneve.vni[23:16] (deparsed)
  >> 15 in ingress and 1 in egress

Allocations in Group 5 8 bits
  8-bit PHV 100n (ingress): phv100[7:0] = hdr.sidecar.sc_payload[95:88] (deparsed)
  8-bit PHV 101n (ingress): phv101[7:4] = hdr.ipv4.version[3:0] (deparsed)
  8-bit PHV 101n (ingress): phv101[3:0] = hdr.ipv4.ihl[3:0] (deparsed)
  8-bit PHV 102n (egress): phv102[7:0] = meta.drop_reason[7:0]
  8-bit PHV 104n (ingress): phv104[7:0] = meta.nexthop[95:88]
  8-bit PHV 104n (ingress): phv104[7:4] = hdr.inner_ipv4.version[3:0] (deparsed)
  8-bit PHV 104n (ingress): phv104[7:4] = hdr.inner_ipv4.version[3:0] (deparsed)
  8-bit PHV 104n (ingress): phv104[3:0] = hdr.inner_ipv4.ihl[3:0] (deparsed)
  8-bit PHV 104n (ingress): phv104[3:0] = hdr.inner_ipv4.ihl[3:0] (deparsed)
  8-bit PHV 112m (ingress): phv112[7:0] = hdr.ethernet.src_mac[7:0] (deparsed)
  8-bit PHV 112m (ingress): phv112[7:0] = hdr.ethernet.src_mac[7:0] (deparsed)
  8-bit PHV 112m (ingress): phv112[7:0] = l3_router_fwd.slots[7:0]
  8-bit PHV 113m (ingress): phv113[7:0] = hdr.geneve.reserved2[7:0] (deparsed)
  8-bit PHV 114m (ingress): phv114[7:0] = hdr.inner_ipv4.diffserv[7:0] (deparsed)
  8-bit PHV 115m (ingress): phv115[7:0] = hdr.ipv4.diffserv[7:0] (deparsed)
  8-bit PHV 116d (ingress): phv116[7:4] = hdr.inner_ipv4.version[3:0] (deparsed)
  8-bit PHV 116d (ingress): phv116[3:0] = hdr.inner_ipv4.ihl[3:0] (deparsed)
  8-bit PHV 117d (ingress): phv117[7:0] = hdr.ethernet.src_mac[7:0] (deparsed)
  >> 9 in ingress and 1 in egress

Allocations in Group 6 8 bits
  8-bit PHV 132m (egress): phv132[0:0] = is_link_local_ipv6_mcast_0[0:0]
  >> 0 in ingress and 1 in egress

Allocations in Group 8 16 bits
  16-bit PHV 160n (ingress): phv160[15:0] = meta.icmp_csum[15:0] (deparsed)
  16-bit PHV 161n (ingress): phv161[15:0] = meta.body_checksum[15:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[15:15] = hdr.inner_icmp.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[14:14] = hdr.inner_udp.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[13:13] = hdr.inner_tcp.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[12:12] = hdr.inner_ipv4.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[11:11] = hdr.inner_eth.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[10:10] = hdr.geneve.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[9:9] = hdr.udp.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[8:8] = hdr.tcp.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[7:7] = hdr.icmp.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[6:6] = hdr.ipv4.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[5:5] = hdr.sidecar.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[4:4] = hdr.ethernet.$valid[0:0]
  16-bit PHV 162n (ingress): phv162[3:3] = meta.bridge_hdr.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[2:2] = ig_intr_md_for_dprsr.drop_ctl.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[1:1] = ig_intr_md_for_tm.ucast_egress_port.$valid[0:0] (deparsed)
  16-bit PHV 162n (ingress): phv162[0:0] = ig_intr_md_for_dprsr.mirror_type.$valid[0:0] (deparsed)
  16-bit PHV 163n (ingress): phv163[15:0] = hdr.inner_ipv4.total_len[15:0] (deparsed)
  16-bit PHV 163n (ingress): phv163[15:0] = hdr.inner_ipv6.payload_len[15:0] (deparsed)
  16-bit PHV 164n (ingress): phv164[13:13] = meta.nat_ingress_hit[0:0]
  16-bit PHV 164n (ingress): phv164[12:12] = meta.icmp_recalc[0:0]
  16-bit PHV 164n (ingress): phv164[11:11] = meta.service_routed[0:0]
  16-bit PHV 164n (ingress): phv164[10:10] = l3_router_fwd.is_hit[0:0]
  16-bit PHV 164n (ingress): phv164[9:9] = meta.dropped[0:0]
  16-bit PHV 164n (ingress): phv164[8:1] = meta.drop_reason[7:0]
  16-bit PHV 164n (ingress): phv164[0:0] = meta.ipv4_checksum_err[0:0]
  16-bit PHV 165n (ingress): phv165[15:0] = hdr.ipv4.total_len[15:0] (deparsed)
  16-bit PHV 165n (ingress): phv165[15:0] = hdr.ipv6.payload_len[15:0] (deparsed)
  16-bit PHV 166n (ingress): phv166[15:0] = meta.l4_length[15:0] (deparsed)
  16-bit PHV 167n (ingress): phv167[15:0] = meta.nexthop[127:112]
  16-bit PHV 167n (ingress): phv167[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed)
  16-bit PHV 167n (ingress): phv167[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed)
  16-bit PHV 168n (ingress): phv168[15:0] = hdr.udp.hdr_length[15:0] (deparsed)
  16-bit PHV 169n (ingress): phv169[15:13] = hdr.vlan.pcp[2:0] (deparsed)
  16-bit PHV 169n (ingress): phv169[12:12] = hdr.vlan.dei[0:0] (deparsed)
  16-bit PHV 169n (ingress): phv169[11:0] = hdr.vlan.vlan_id[11:0] (deparsed)
  16-bit PHV 170n (ingress): phv170[15:0] = hdr.sidecar.sc_payload[127:112] (deparsed)
  16-bit PHV 171n (ingress): phv171[15:8] = hdr.icmp.type[7:0] (deparsed)
  16-bit PHV 171n (ingress): phv171[15:8] = hdr.inner_icmp.type[7:0] (deparsed)
  16-bit PHV 171n (ingress): phv171[7:0] = hdr.icmp.code[7:0] (deparsed)
  16-bit PHV 171n (ingress): phv171[7:0] = hdr.inner_icmp.code[7:0] (deparsed)
  16-bit PHV 172m (egress): phv172[10:10] = hdr.ipv6.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[9:9] = hdr.geneve_opts.oxg_mss.$valid[0:0]
  16-bit PHV 172m (egress): phv172[8:8] = hdr.geneve_opts.oxg_mss_tag.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[7:7] = hdr.geneve_opts.oxg_mcast.$valid[0:0]
  16-bit PHV 172m (egress): phv172[6:6] = hdr.geneve_opts.oxg_mcast_tag.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[5:5] = hdr.geneve_opts.oxg_ext_tag.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[4:4] = hdr.inner_ipv6.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[3:3] = hdr.inner_udp.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[2:2] = hdr.inner_tcp.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[1:1] = hdr.inner_ipv4.$valid[0:0] (deparsed)
  16-bit PHV 172m (egress): phv172[0:0] = hdr.inner_eth.$valid[0:0] (deparsed)
  16-bit PHV 173m (egress): phv173[8:0] = eg_intr_md.egress_port[8:0] (deparsed)
  16-bit PHV 174m (egress): phv174[2:0] = eg_intr_md_for_dprsr.drop_ctl[2:0] (deparsed)
  16-bit PHV 175m (egress): phv175[0:0] = eg_intr_md_for_dprsr.mirror_io_select[0:0] (deparsed)
  16-bit PHV 176d (ingress): phv176[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed)
  >> 13 in ingress and 4 in egress

Allocations in Group 9 16 bits
  16-bit PHV 180n (ingress): phv180[15:0] = l3_router_fwd.idx[15:0]
  16-bit PHV 181n (ingress): phv181[15:0] = hdr.sidecar.sc_egress[15:0] (deparsed)
  16-bit PHV 182n (ingress): phv182[15:0] = hdr.sidecar.sc_ingress[15:0] (deparsed)
  16-bit PHV 183n (ingress): phv183[15:0] = meta.nexthop[79:64]
  16-bit PHV 183n (ingress): phv183[15:0] = hdr.geneve.vni[15:0] (deparsed)
  16-bit PHV 183n (ingress): phv183[15:0] = hdr.geneve.vni[15:0] (deparsed)
  16-bit PHV 184n (ingress): phv184[15:0] = meta.nat_geneve_vni[15:0]
  16-bit PHV 185n (ingress): phv185[15:0] = hdr.sidecar.sc_payload[79:64] (deparsed)
  16-bit PHV 186n (ingress): phv186[15:0] = meta.nexthop[111:96]
  16-bit PHV 186n (ingress): phv186[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed)
  16-bit PHV 186n (ingress): phv186[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed)
  16-bit PHV 187n (ingress): phv187[15:0] = hdr.sidecar.sc_payload[111:96] (deparsed)
  16-bit PHV 188n (ingress): phv188[15:0] = meta.nat_inner_mac[47:32]
  16-bit PHV 189n (ingress): phv189[15:0] = meta.l4_src_port[15:0]
  16-bit PHV 192m (ingress): phv192[15:0] = l3_router_fwd.slot[15:0]
  16-bit PHV 193m (ingress): phv193[8:0] = ig_intr_md.ingress_port[8:0]
  16-bit PHV 194m (ingress): phv194[8:0] = ig_intr_md_for_tm.ucast_egress_port[8:0] (deparsed)
  16-bit PHV 195m (ingress): phv195[15:0] = hdr.inner_eth.src_mac[15:0] (deparsed)
  16-bit PHV 196d (ingress): phv196[15:0] = hdr.geneve.vni[15:0] (deparsed)
  16-bit PHV 197d (ingress): phv197[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed)
  >> 16 in ingress and 0 in egress

Allocations in Group 10 16 bits
  16-bit PHV 212m (ingress): phv212[15:0] = hdr.sidecar.sc_ether_type[15:0] (deparsed)
  16-bit PHV 213m (ingress): phv213[15:0] = hdr.ethernet.ether_type[15:0] (deparsed)
  16-bit PHV 214m (ingress): phv214[15:0] = hdr.vlan.ether_type[15:0] (deparsed)
  16-bit PHV 215m (ingress): phv215[15:0] = hdr.inner_eth.ether_type[15:0] (deparsed)
  >> 4 in ingress and 0 in egress

Allocations in Group 11 16 bits
  16-bit PHV 220n (ingress): phv220[15:0] = meta.orig_src_mac[47:32]
  16-bit PHV 232m (ingress): phv232[15:0] = hdr.ethernet.src_mac[47:32] (deparsed)
  16-bit PHV 233m (ingress): phv233[15:0] = hdr.ethernet.dst_mac[47:32] (deparsed)
  16-bit PHV 234m (ingress): phv234[15:0] = hdr.icmp.hdr_checksum[15:0] (deparsed)
  16-bit PHV 234m (ingress): phv234[15:0] = hdr.inner_udp.checksum[15:0] (deparsed)
  16-bit PHV 234m (ingress): phv234[15:0] = hdr.inner_icmp.hdr_checksum[15:0] (deparsed)
  16-bit PHV 235m (ingress): phv235[15:0] = hdr.udp.checksum[15:0] (deparsed)
  >> 5 in ingress and 0 in egress

Allocations in Group 12 16 bits
  16-bit PHV 252m (ingress): phv252[15:0] = hdr.inner_ipv4.hdr_checksum[15:0] (deparsed)
  16-bit PHV 253m (ingress): phv253[15:0] = hdr.ipv4.hdr_checksum[15:0] (deparsed)
  16-bit PHV 254m (ingress): phv254[15:9] = meta.bridge_hdr.__pad_1[6:0]
  16-bit PHV 254m (ingress): phv254[8:0] = meta.bridge_hdr.ingress_port[8:0] (deparsed)
  16-bit PHV 255m (ingress): phv255[15:8] = hdr.sidecar.sc_code[7:0] (deparsed)
  16-bit PHV 255m (ingress): phv255[7:0] = hdr.sidecar.sc_pad[7:0] (deparsed)
  >> 4 in ingress and 0 in egress

Allocations in Group 13 16 bits
  16-bit PHV 272m (egress): phv272[15:0] = hdr.ethernet.src_mac[47:32] (tagalong capable) (deparsed)
  >> 0 in ingress and 1 in egress


Final POV layout (ingress):

Final POV layout (egress):