| 1 | +---------------------------------------------------------------------+ | ||
| 2 | | Log file: pa.results.log | | ||
| 3 | | Compiler version: 9.13.4 | | ||
| 4 | | Created on: Tue May 19 02:01:26 2026 | | ||
| 5 | | Run ID: 7efab217e53a458e | | ||
| 6 | +---------------------------------------------------------------------+ | ||
| 7 | |||
| 8 | Allocation state: Final Allocation | ||
| 9 | ------------------------------------------------------------------------------ | ||
| 10 | | PHV Group | Containers Used | Bits Used | Bits Available | | ||
| 11 | | (container bit widths) | (% used) | (% used) | | | ||
| 12 | ------------------------------------------------------------------------------ | ||
| 13 | | 0 (32) | 18 (90.00%) | 571 (89.22%) | 640 | | ||
| 14 | | 1 (32) | 16 (80.00%) | 465 (72.66%) | 640 | | ||
| 15 | | 2 (32) | 7 (35.00%) | 224 (35.00%) | 640 | | ||
| 16 | | 3 (32) | 8 (40.00%) | 256 (40.00%) | 640 | | ||
| 17 | | Total for 32 bit | 49 (61.25%) | 1516 (59.22%) | 2560 | | ||
| 18 | | | | | | | ||
| 19 | | 4 (8) | 16 (80.00%) | 117 (73.12%) | 160 | | ||
| 20 | | 5 (8) | 10 (50.00%) | 80 (50.00%) | 160 | | ||
| 21 | | 6 (8) | 1 (5.00%) | 1 (0.62%) | 160 | | ||
| 22 | | 7 (8) | 0 (0.00%) | 0 (0.00%) | 160 | | ||
| 23 | | Total for 8 bit | 27 (33.75%) | 198 (30.94%) | 640 | | ||
| 24 | | | | | | | ||
| 25 | | 8 (16) | 17 (85.00%) | 230 (71.88%) | 320 | | ||
| 26 | | 9 (16) | 16 (80.00%) | 242 (75.62%) | 320 | | ||
| 27 | | 10 (16) | 4 (20.00%) | 64 (20.00%) | 320 | | ||
| 28 | | 11 (16) | 5 (25.00%) | 80 (25.00%) | 320 | | ||
| 29 | | 12 (16) | 4 (20.00%) | 64 (20.00%) | 320 | | ||
| 30 | | 13 (16) | 1 (5.00%) | 16 (5.00%) | 320 | | ||
| 31 | | Total for 16 bit | 47 (39.17%) | 696 (36.25%) | 1920 | | ||
| 32 | | | | | | | ||
| 33 | | Overall total | 123 (43.93%) | 2410 (47.07%) | 5120 | | ||
| 34 | ------------------------------------------------------------------------------ | ||
| 35 | |||
| 36 | -------------------------------------------- | ||
| 37 | PHV Allocation | ||
| 38 | -------------------------------------------- | ||
| 39 | |||
| 40 | Allocations in Group 0 32 bits | ||
| 41 | 32-bit PHV 0n (ingress): phv0[31:28] = hdr.tcp.data_offset[3:0] (deparsed) | ||
| 42 | 32-bit PHV 0n (ingress): phv0[31:28] = hdr.inner_tcp.data_offset[3:0] (deparsed) | ||
| 43 | 32-bit PHV 0n (ingress): phv0[27:24] = hdr.tcp.res[3:0] (deparsed) | ||
| 44 | 32-bit PHV 0n (ingress): phv0[27:24] = hdr.inner_tcp.res[3:0] (deparsed) | ||
| 45 | 32-bit PHV 0n (ingress): phv0[23:16] = hdr.tcp.flags[7:0] (deparsed) | ||
| 46 | 32-bit PHV 0n (ingress): phv0[23:16] = hdr.inner_tcp.flags[7:0] (deparsed) | ||
| 47 | 32-bit PHV 0n (ingress): phv0[15:0] = hdr.tcp.window[15:0] (deparsed) | ||
| 48 | 32-bit PHV 0n (ingress): phv0[15:0] = hdr.inner_tcp.window[15:0] (deparsed) | ||
| 49 | 32-bit PHV 1n (ingress): phv1[31:16] = hdr.geneve_opts.oxg_ext_tag.class[15:0] (deparsed) | ||
| 50 | 32-bit PHV 1n (ingress): phv1[15:15] = hdr.geneve_opts.oxg_ext_tag.crit[0:0] (deparsed) | ||
| 51 | 32-bit PHV 1n (ingress): phv1[14:8] = hdr.geneve_opts.oxg_ext_tag.type[6:0] (deparsed) | ||
| 52 | 32-bit PHV 1n (ingress): phv1[7:5] = hdr.geneve_opts.oxg_ext_tag.reserved[2:0] (deparsed) | ||
| 53 | 32-bit PHV 1n (ingress): phv1[4:0] = hdr.geneve_opts.oxg_ext_tag.opt_len[4:0] (deparsed) | ||
| 54 | 32-bit PHV 2n (ingress): phv2[31:0] = meta.orig_src_ipv4[31:0] | ||
| 55 | 32-bit PHV 2n (ingress): phv2[7:0] = l3_router_fwd.ecmp_hash[7:0] | ||
| 56 | 32-bit PHV 3n (ingress): phv3[31:0] = meta.nat_ingress_tgt[127:96] | ||
| 57 | 32-bit PHV 3n (ingress): phv3[7:0] = $tmp10[7:0] | ||
| 58 | 32-bit PHV 4n (ingress): phv4[31:30] = hdr.geneve.version[1:0] (deparsed) | ||
| 59 | 32-bit PHV 4n (ingress): phv4[29:24] = hdr.geneve.opt_len[5:0] (deparsed) | ||
| 60 | 32-bit PHV 4n (ingress): phv4[23:23] = hdr.geneve.ctrl[0:0] (deparsed) | ||
| 61 | 32-bit PHV 4n (ingress): phv4[22:22] = hdr.geneve.crit[0:0] (deparsed) | ||
| 62 | 32-bit PHV 4n (ingress): phv4[21:16] = hdr.geneve.reserved[5:0] (deparsed) | ||
| 63 | 32-bit PHV 4n (ingress): phv4[15:0] = hdr.geneve.protocol[15:0] (deparsed) | ||
| 64 | 32-bit PHV 5n (ingress): phv5[31:0] = meta.nexthop[31:0] | ||
| 65 | 32-bit PHV 5n (ingress): phv5[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed) | ||
| 66 | 32-bit PHV 5n (ingress): phv5[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed) | ||
| 67 | 32-bit PHV 6n (egress): phv6[31:0] = hdr.ipv6.dst_addr[127:96] (deparsed) | ||
| 68 | 32-bit PHV 7n (ingress): phv7[31:0] = meta.nat_inner_mac[31:0] | ||
| 69 | 32-bit PHV 7n (ingress): phv7[7:0] = $tmp11[7:0] | ||
| 70 | 32-bit PHV 8n (ingress): phv8[31:0] = meta.nexthop[63:32] | ||
| 71 | 32-bit PHV 8n (ingress): phv8[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed) | ||
| 72 | 32-bit PHV 8n (ingress): phv8[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed) | ||
| 73 | 32-bit PHV 9n (ingress): phv9[31:0] = hdr.sidecar.sc_payload[31:0] (deparsed) | ||
| 74 | 32-bit PHV 10n (ingress): phv10[31:0] = hdr.sidecar.sc_payload[63:32] (deparsed) | ||
| 75 | 32-bit PHV 11n (ingress): phv11[26:26] = meta.encap_needed[0:0] | ||
| 76 | 32-bit PHV 11n (ingress): phv11[25:16] = meta.pkt_type[9:0] | ||
| 77 | 32-bit PHV 11n (ingress): phv11[15:0] = meta.nat_ingress_csum[15:0] (deparsed) | ||
| 78 | 32-bit PHV 12m (ingress): phv12[31:0] = hdr.inner_ipv4.dst_addr[31:0] (deparsed) | ||
| 79 | 32-bit PHV 12m (ingress): phv12[31:0] = hdr.inner_ipv6.dst_addr[127:96] (deparsed) | ||
| 80 | 32-bit PHV 13m (ingress): phv13[31:0] = hdr.ipv4.dst_addr[31:0] (deparsed) | ||
| 81 | 32-bit PHV 13m (ingress): phv13[31:0] = hdr.ipv6.dst_addr[127:96] (deparsed) | ||
| 82 | 32-bit PHV 14m (ingress): phv14[31:0] = hdr.inner_ipv4.src_addr[31:0] (deparsed) | ||
| 83 | 32-bit PHV 14m (ingress): phv14[31:0] = hdr.inner_ipv6.src_addr[127:96] (deparsed) | ||
| 84 | 32-bit PHV 15m (ingress): phv15[31:0] = hdr.ipv4.src_addr[31:0] (deparsed) | ||
| 85 | 32-bit PHV 15m (ingress): phv15[31:0] = hdr.ipv6.src_addr[127:96] (deparsed) | ||
| 86 | 32-bit PHV 16d (ingress): phv16[31:0] = hdr.inner_eth.src_mac[47:16] (deparsed) | ||
| 87 | 32-bit PHV 17d (ingress): phv17[31:0] = hdr.inner_eth.dst_mac[31:0] (deparsed) | ||
| 88 | >> 17 in ingress and 1 in egress | ||
| 89 | |||
| 90 | Allocations in Group 1 32 bits | ||
| 91 | 32-bit PHV 20n (ingress): phv20[31:16] = hdr.ipv4.identification[15:0] (deparsed) | ||
| 92 | 32-bit PHV 20n (ingress): phv20[31:0] = hdr.ipv6.dst_addr[31:0] (deparsed) | ||
| 93 | 32-bit PHV 20n (ingress): phv20[15:13] = hdr.ipv4.flags[2:0] (deparsed) | ||
| 94 | 32-bit PHV 20n (ingress): phv20[12:0] = hdr.ipv4.frag_offset[12:0] (deparsed) | ||
| 95 | 32-bit PHV 21n (ingress): phv21[31:16] = hdr.inner_ipv4.identification[15:0] (deparsed) | ||
| 96 | 32-bit PHV 21n (ingress): phv21[31:28] = hdr.inner_ipv6.version[3:0] (deparsed) | ||
| 97 | 32-bit PHV 21n (ingress): phv21[27:20] = hdr.inner_ipv6.traffic_class[7:0] (deparsed) | ||
| 98 | 32-bit PHV 21n (ingress): phv21[19:0] = hdr.inner_ipv6.flow_label[19:0] (deparsed) | ||
| 99 | 32-bit PHV 21n (ingress): phv21[15:13] = hdr.inner_ipv4.flags[2:0] (deparsed) | ||
| 100 | 32-bit PHV 21n (ingress): phv21[12:0] = hdr.inner_ipv4.frag_offset[12:0] (deparsed) | ||
| 101 | 32-bit PHV 22n (ingress): phv22[31:0] = meta.nat_ingress_tgt[31:0] | ||
| 102 | 32-bit PHV 23n (ingress): phv23[15:0] = meta.l4_dst_port[15:0] | ||
| 103 | 32-bit PHV 24n (ingress): phv24[31:28] = hdr.ipv6.version[3:0] (deparsed) | ||
| 104 | 32-bit PHV 24n (ingress): phv24[27:20] = hdr.ipv6.traffic_class[7:0] (deparsed) | ||
| 105 | 32-bit PHV 24n (ingress): phv24[19:0] = hdr.ipv6.flow_label[19:0] (deparsed) | ||
| 106 | 32-bit PHV 25n (ingress): phv25[31:16] = hdr.udp.src_port[15:0] (deparsed) | ||
| 107 | 32-bit PHV 25n (ingress): phv25[15:0] = hdr.udp.dst_port[15:0] (deparsed) | ||
| 108 | 32-bit PHV 26n (egress): phv26[31:0] = hdr.ethernet.src_mac[31:0] (deparsed) | ||
| 109 | 32-bit PHV 27n (egress): phv27[31:0] = hdr.ipv6.dst_addr[31:0] (deparsed) | ||
| 110 | 32-bit PHV 28n (egress): phv28[31:0] = hdr.ipv6.dst_addr[63:32] (deparsed) | ||
| 111 | 32-bit PHV 29n (egress): phv29[31:0] = hdr.ipv6.dst_addr[95:64] (deparsed) | ||
| 112 | 32-bit PHV 30n (ingress): phv30[31:0] = meta.orig_dst_ipv4[31:0] | ||
| 113 | 32-bit PHV 31n (egress): phv31[17:17] = meta.bridge_hdr.nat_egress_hit[0:0] | ||
| 114 | 32-bit PHV 32m (ingress): phv32[31:0] = hdr.inner_ipv6.dst_addr[31:0] (deparsed) | ||
| 115 | 32-bit PHV 33m (ingress): phv33[31:0] = hdr.inner_ipv6.src_addr[31:0] (deparsed) | ||
| 116 | 32-bit PHV 34m (ingress): phv34[31:0] = hdr.ipv6.src_addr[31:0] (deparsed) | ||
| 117 | 32-bit PHV 35m (ingress): phv35[31:0] = hdr.icmp.data[31:0] (deparsed) | ||
| 118 | 32-bit PHV 35m (ingress): phv35[31:16] = hdr.tcp.checksum[15:0] (deparsed) | ||
| 119 | 32-bit PHV 35m (ingress): phv35[31:16] = hdr.inner_tcp.checksum[15:0] (deparsed) | ||
| 120 | 32-bit PHV 35m (ingress): phv35[31:16] = hdr.inner_udp.src_port[15:0] (deparsed) | ||
| 121 | 32-bit PHV 35m (ingress): phv35[31:0] = hdr.inner_icmp.data[31:0] (deparsed) | ||
| 122 | 32-bit PHV 35m (ingress): phv35[15:0] = hdr.tcp.urgent_ptr[15:0] (deparsed) | ||
| 123 | 32-bit PHV 35m (ingress): phv35[15:0] = hdr.inner_tcp.urgent_ptr[15:0] (deparsed) | ||
| 124 | 32-bit PHV 35m (ingress): phv35[15:0] = hdr.inner_udp.dst_port[15:0] (deparsed) | ||
| 125 | >> 11 in ingress and 5 in egress | ||
| 126 | |||
| 127 | Allocations in Group 2 32 bits | ||
| 128 | 32-bit PHV 40n (ingress): phv40[31:0] = hdr.ipv6.dst_addr[63:32] (deparsed) | ||
| 129 | 32-bit PHV 41n (ingress): phv41[31:0] = hdr.tcp.ack_no[31:0] (deparsed) | ||
| 130 | 32-bit PHV 41n (ingress): phv41[31:0] = hdr.inner_tcp.ack_no[31:0] (deparsed) | ||
| 131 | 32-bit PHV 42n (ingress): phv42[31:0] = meta.nat_ingress_tgt[63:32] | ||
| 132 | 32-bit PHV 52m (ingress): phv52[31:0] = hdr.inner_ipv6.dst_addr[63:32] (deparsed) | ||
| 133 | 32-bit PHV 53m (ingress): phv53[31:0] = hdr.inner_ipv6.src_addr[63:32] (deparsed) | ||
| 134 | 32-bit PHV 54m (ingress): phv54[31:0] = hdr.ipv6.src_addr[63:32] (deparsed) | ||
| 135 | 32-bit PHV 55m (ingress): phv55[31:16] = hdr.tcp.src_port[15:0] (deparsed) | ||
| 136 | 32-bit PHV 55m (ingress): phv55[31:16] = hdr.inner_tcp.src_port[15:0] (deparsed) | ||
| 137 | 32-bit PHV 55m (ingress): phv55[15:0] = hdr.tcp.dst_port[15:0] (deparsed) | ||
| 138 | 32-bit PHV 55m (ingress): phv55[15:0] = hdr.inner_tcp.dst_port[15:0] (deparsed) | ||
| 139 | >> 7 in ingress and 0 in egress | ||
| 140 | |||
| 141 | Allocations in Group 3 32 bits | ||
| 142 | 32-bit PHV 60n (ingress): phv60[31:0] = hdr.ipv6.dst_addr[95:64] (deparsed) | ||
| 143 | 32-bit PHV 61n (ingress): phv61[31:0] = hdr.tcp.seq_no[31:0] (deparsed) | ||
| 144 | 32-bit PHV 61n (ingress): phv61[31:0] = hdr.inner_tcp.seq_no[31:0] (deparsed) | ||
| 145 | 32-bit PHV 62n (ingress): phv62[31:0] = meta.nat_ingress_tgt[95:64] | ||
| 146 | 32-bit PHV 63n (ingress): phv63[31:0] = meta.orig_src_mac[31:0] | ||
| 147 | 32-bit PHV 72m (ingress): phv72[31:0] = hdr.inner_ipv6.dst_addr[95:64] (deparsed) | ||
| 148 | 32-bit PHV 73m (ingress): phv73[31:0] = hdr.inner_ipv6.src_addr[95:64] (deparsed) | ||
| 149 | 32-bit PHV 74m (ingress): phv74[31:0] = hdr.ipv6.src_addr[95:64] (deparsed) | ||
| 150 | 32-bit PHV 75m (ingress): phv75[31:0] = hdr.ethernet.dst_mac[31:0] (deparsed) | ||
| 151 | >> 8 in ingress and 0 in egress | ||
| 152 | |||
| 153 | Allocations in Group 4 8 bits | ||
| 154 | 8-bit PHV 80n (ingress): phv80[7:0] = $tmp7[7:0] (deparsed) | ||
| 155 | 8-bit PHV 81n (ingress): phv81[7:7] = hdr.arp.$valid[0:0] (deparsed) | ||
| 156 | 8-bit PHV 81n (ingress): phv81[6:6] = hdr.ipv6.$valid[0:0] (deparsed) | ||
| 157 | 8-bit PHV 81n (ingress): phv81[5:5] = hdr.geneve_opts.oxg_mss.$valid[0:0] | ||
| 158 | 8-bit PHV 81n (ingress): phv81[4:4] = hdr.geneve_opts.oxg_mss_tag.$valid[0:0] (deparsed) | ||
| 159 | 8-bit PHV 81n (ingress): phv81[3:3] = hdr.geneve_opts.oxg_mcast.$valid[0:0] | ||
| 160 | 8-bit PHV 81n (ingress): phv81[2:2] = hdr.geneve_opts.oxg_mcast_tag.$valid[0:0] (deparsed) | ||
| 161 | 8-bit PHV 81n (ingress): phv81[1:1] = hdr.geneve_opts.oxg_ext_tag.$valid[0:0] (deparsed) | ||
| 162 | 8-bit PHV 81n (ingress): phv81[0:0] = hdr.inner_ipv6.$valid[0:0] (deparsed) | ||
| 163 | 8-bit PHV 82n (ingress): phv82[7:7] = meta.nexthop_is_v6[0:0] | ||
| 164 | 8-bit PHV 82n (ingress): phv82[6:6] = meta.resolve_nexthop[0:0] | ||
| 165 | 8-bit PHV 82n (ingress): phv82[5:3] = ig_intr_md_for_dprsr.drop_ctl[2:0] (deparsed) | ||
| 166 | 8-bit PHV 82n (ingress): phv82[2:2] = hdr.icmp.hdr_checksum.$deparse_updated_csum_0[0:0] (deparsed) | ||
| 167 | 8-bit PHV 82n (ingress): phv82[1:1] = hdr.icmp.hdr_checksum.$deparse_original_csum[0:0] (deparsed) | ||
| 168 | 8-bit PHV 82n (ingress): phv82[0:0] = hdr.vlan.$valid[0:0] (deparsed) | ||
| 169 | 8-bit PHV 83n (ingress): phv83[7:7] = meta.is_mcast[0:0] | ||
| 170 | 8-bit PHV 83n (ingress): phv83[6:6] = meta.is_switch_address[0:0] | ||
| 171 | 8-bit PHV 83n (ingress): phv83[5:5] = meta.is_link_local_mcastv6[0:0] | ||
| 172 | 8-bit PHV 83n (ingress): phv83[4:4] = hdr.udp.checksum.$deparse_updated_csum_3[0:0] (deparsed) | ||
| 173 | 8-bit PHV 83n (ingress): phv83[3:3] = hdr.udp.checksum.$deparse_updated_csum_2[0:0] (deparsed) | ||
| 174 | 8-bit PHV 83n (ingress): phv83[2:2] = hdr.udp.checksum.$deparse_updated_csum_1[0:0] (deparsed) | ||
| 175 | 8-bit PHV 83n (ingress): phv83[1:1] = hdr.udp.checksum.$deparse_updated_csum_0[0:0] (deparsed) | ||
| 176 | 8-bit PHV 83n (ingress): phv83[0:0] = hdr.udp.checksum.$deparse_original_csum[0:0] (deparsed) | ||
| 177 | 8-bit PHV 84n (egress): phv84[7:7] = hdr.geneve.$valid[0:0] (deparsed) | ||
| 178 | 8-bit PHV 84n (egress): phv84[6:6] = hdr.udp.$valid[0:0] (deparsed) | ||
| 179 | 8-bit PHV 84n (egress): phv84[5:5] = hdr.ipv4.$valid[0:0] (deparsed) | ||
| 180 | 8-bit PHV 84n (egress): phv84[4:4] = hdr.vlan.$valid[0:0] (deparsed) | ||
| 181 | 8-bit PHV 84n (egress): phv84[3:3] = hdr.ethernet.$valid[0:0] (deparsed) | ||
| 182 | 8-bit PHV 84n (egress): phv84[2:2] = eg_intr_md_for_dprsr.drop_ctl.$valid[0:0] (deparsed) | ||
| 183 | 8-bit PHV 84n (egress): phv84[1:1] = eg_intr_md.egress_port.$valid[0:0] (deparsed) | ||
| 184 | 8-bit PHV 84n (egress): phv84[0:0] = eg_intr_md_for_dprsr.mirror_io_select.$valid[0:0] (deparsed) | ||
| 185 | 8-bit PHV 85n (ingress): phv85[7:0] = meta.route_ttl_is_1[7:0] | ||
| 186 | 8-bit PHV 85n (ingress): phv85[7:0] = meta.nat_geneve_vni[23:16] | ||
| 187 | 8-bit PHV 85n (ingress): phv85[0:0] = $tmp12[0:0] | ||
| 188 | 8-bit PHV 86n (ingress): phv86[0:0] = meta.skip_ttl_check[0:0] | ||
| 189 | 8-bit PHV 88n (ingress): phv88[7:0] = hdr.ipv4.ttl[7:0] (deparsed) | ||
| 190 | 8-bit PHV 88n (ingress): phv88[7:0] = hdr.ipv6.hop_limit[7:0] (deparsed) | ||
| 191 | 8-bit PHV 89n (ingress): phv89[7:7] = meta.nat_egress_hit[0:0] | ||
| 192 | 8-bit PHV 89n (ingress): phv89[7:7] = meta.bridge_hdr.__pad_0[0:0] | ||
| 193 | 8-bit PHV 89n (ingress): phv89[6:2] = meta.bridge_hdr.reserved[4:0] (deparsed) | ||
| 194 | 8-bit PHV 89n (ingress): phv89[1:1] = meta.uplink_ingress[0:0] | ||
| 195 | 8-bit PHV 89n (ingress): phv89[1:1] = meta.bridge_hdr.nat_egress_hit[0:0] (deparsed) | ||
| 196 | 8-bit PHV 89n (ingress): phv89[0:0] = meta.bridge_hdr.is_mcast_routed[0:0] (deparsed) | ||
| 197 | 8-bit PHV 90n (ingress): phv90[7:0] = meta.nexthop[87:80] | ||
| 198 | 8-bit PHV 90n (ingress): phv90[7:0] = hdr.geneve.vni[23:16] (deparsed) | ||
| 199 | 8-bit PHV 90n (ingress): phv90[7:0] = hdr.geneve.vni[23:16] (deparsed) | ||
| 200 | 8-bit PHV 91n (ingress): phv91[7:0] = hdr.sidecar.sc_payload[87:80] (deparsed) | ||
| 201 | 8-bit PHV 92m (ingress): phv92[7:0] = hdr.inner_ipv4.ttl[7:0] (deparsed) | ||
| 202 | 8-bit PHV 92m (ingress): phv92[7:0] = hdr.inner_ipv6.hop_limit[7:0] (deparsed) | ||
| 203 | 8-bit PHV 93m (ingress): phv93[3:0] = ig_intr_md_for_dprsr.mirror_type[3:0] (deparsed) | ||
| 204 | 8-bit PHV 94m (ingress): phv94[7:0] = hdr.inner_ipv4.protocol[7:0] (deparsed) | ||
| 205 | 8-bit PHV 94m (ingress): phv94[7:0] = hdr.inner_ipv6.next_hdr[7:0] (deparsed) | ||
| 206 | 8-bit PHV 95m (ingress): phv95[7:0] = hdr.ipv4.protocol[7:0] (deparsed) | ||
| 207 | 8-bit PHV 95m (ingress): phv95[7:0] = hdr.ipv6.next_hdr[7:0] (deparsed) | ||
| 208 | 8-bit PHV 96d (ingress): phv96[7:0] = hdr.geneve.vni[23:16] (deparsed) | ||
| 209 | >> 15 in ingress and 1 in egress | ||
| 210 | |||
| 211 | Allocations in Group 5 8 bits | ||
| 212 | 8-bit PHV 100n (ingress): phv100[7:0] = hdr.sidecar.sc_payload[95:88] (deparsed) | ||
| 213 | 8-bit PHV 101n (ingress): phv101[7:4] = hdr.ipv4.version[3:0] (deparsed) | ||
| 214 | 8-bit PHV 101n (ingress): phv101[3:0] = hdr.ipv4.ihl[3:0] (deparsed) | ||
| 215 | 8-bit PHV 102n (egress): phv102[7:0] = meta.drop_reason[7:0] | ||
| 216 | 8-bit PHV 104n (ingress): phv104[7:0] = meta.nexthop[95:88] | ||
| 217 | 8-bit PHV 104n (ingress): phv104[7:4] = hdr.inner_ipv4.version[3:0] (deparsed) | ||
| 218 | 8-bit PHV 104n (ingress): phv104[7:4] = hdr.inner_ipv4.version[3:0] (deparsed) | ||
| 219 | 8-bit PHV 104n (ingress): phv104[3:0] = hdr.inner_ipv4.ihl[3:0] (deparsed) | ||
| 220 | 8-bit PHV 104n (ingress): phv104[3:0] = hdr.inner_ipv4.ihl[3:0] (deparsed) | ||
| 221 | 8-bit PHV 112m (ingress): phv112[7:0] = hdr.ethernet.src_mac[7:0] (deparsed) | ||
| 222 | 8-bit PHV 112m (ingress): phv112[7:0] = hdr.ethernet.src_mac[7:0] (deparsed) | ||
| 223 | 8-bit PHV 112m (ingress): phv112[7:0] = l3_router_fwd.slots[7:0] | ||
| 224 | 8-bit PHV 113m (ingress): phv113[7:0] = hdr.geneve.reserved2[7:0] (deparsed) | ||
| 225 | 8-bit PHV 114m (ingress): phv114[7:0] = hdr.inner_ipv4.diffserv[7:0] (deparsed) | ||
| 226 | 8-bit PHV 115m (ingress): phv115[7:0] = hdr.ipv4.diffserv[7:0] (deparsed) | ||
| 227 | 8-bit PHV 116d (ingress): phv116[7:4] = hdr.inner_ipv4.version[3:0] (deparsed) | ||
| 228 | 8-bit PHV 116d (ingress): phv116[3:0] = hdr.inner_ipv4.ihl[3:0] (deparsed) | ||
| 229 | 8-bit PHV 117d (ingress): phv117[7:0] = hdr.ethernet.src_mac[7:0] (deparsed) | ||
| 230 | >> 9 in ingress and 1 in egress | ||
| 231 | |||
| 232 | Allocations in Group 6 8 bits | ||
| 233 | 8-bit PHV 132m (egress): phv132[0:0] = is_link_local_ipv6_mcast_0[0:0] | ||
| 234 | >> 0 in ingress and 1 in egress | ||
| 235 | |||
| 236 | Allocations in Group 8 16 bits | ||
| 237 | 16-bit PHV 160n (ingress): phv160[15:0] = meta.icmp_csum[15:0] (deparsed) | ||
| 238 | 16-bit PHV 161n (ingress): phv161[15:0] = meta.body_checksum[15:0] (deparsed) | ||
| 239 | 16-bit PHV 162n (ingress): phv162[15:15] = hdr.inner_icmp.$valid[0:0] (deparsed) | ||
| 240 | 16-bit PHV 162n (ingress): phv162[14:14] = hdr.inner_udp.$valid[0:0] (deparsed) | ||
| 241 | 16-bit PHV 162n (ingress): phv162[13:13] = hdr.inner_tcp.$valid[0:0] (deparsed) | ||
| 242 | 16-bit PHV 162n (ingress): phv162[12:12] = hdr.inner_ipv4.$valid[0:0] (deparsed) | ||
| 243 | 16-bit PHV 162n (ingress): phv162[11:11] = hdr.inner_eth.$valid[0:0] (deparsed) | ||
| 244 | 16-bit PHV 162n (ingress): phv162[10:10] = hdr.geneve.$valid[0:0] (deparsed) | ||
| 245 | 16-bit PHV 162n (ingress): phv162[9:9] = hdr.udp.$valid[0:0] (deparsed) | ||
| 246 | 16-bit PHV 162n (ingress): phv162[8:8] = hdr.tcp.$valid[0:0] (deparsed) | ||
| 247 | 16-bit PHV 162n (ingress): phv162[7:7] = hdr.icmp.$valid[0:0] (deparsed) | ||
| 248 | 16-bit PHV 162n (ingress): phv162[6:6] = hdr.ipv4.$valid[0:0] (deparsed) | ||
| 249 | 16-bit PHV 162n (ingress): phv162[5:5] = hdr.sidecar.$valid[0:0] (deparsed) | ||
| 250 | 16-bit PHV 162n (ingress): phv162[4:4] = hdr.ethernet.$valid[0:0] | ||
| 251 | 16-bit PHV 162n (ingress): phv162[3:3] = meta.bridge_hdr.$valid[0:0] (deparsed) | ||
| 252 | 16-bit PHV 162n (ingress): phv162[2:2] = ig_intr_md_for_dprsr.drop_ctl.$valid[0:0] (deparsed) | ||
| 253 | 16-bit PHV 162n (ingress): phv162[1:1] = ig_intr_md_for_tm.ucast_egress_port.$valid[0:0] (deparsed) | ||
| 254 | 16-bit PHV 162n (ingress): phv162[0:0] = ig_intr_md_for_dprsr.mirror_type.$valid[0:0] (deparsed) | ||
| 255 | 16-bit PHV 163n (ingress): phv163[15:0] = hdr.inner_ipv4.total_len[15:0] (deparsed) | ||
| 256 | 16-bit PHV 163n (ingress): phv163[15:0] = hdr.inner_ipv6.payload_len[15:0] (deparsed) | ||
| 257 | 16-bit PHV 164n (ingress): phv164[13:13] = meta.nat_ingress_hit[0:0] | ||
| 258 | 16-bit PHV 164n (ingress): phv164[12:12] = meta.icmp_recalc[0:0] | ||
| 259 | 16-bit PHV 164n (ingress): phv164[11:11] = meta.service_routed[0:0] | ||
| 260 | 16-bit PHV 164n (ingress): phv164[10:10] = l3_router_fwd.is_hit[0:0] | ||
| 261 | 16-bit PHV 164n (ingress): phv164[9:9] = meta.dropped[0:0] | ||
| 262 | 16-bit PHV 164n (ingress): phv164[8:1] = meta.drop_reason[7:0] | ||
| 263 | 16-bit PHV 164n (ingress): phv164[0:0] = meta.ipv4_checksum_err[0:0] | ||
| 264 | 16-bit PHV 165n (ingress): phv165[15:0] = hdr.ipv4.total_len[15:0] (deparsed) | ||
| 265 | 16-bit PHV 165n (ingress): phv165[15:0] = hdr.ipv6.payload_len[15:0] (deparsed) | ||
| 266 | 16-bit PHV 166n (ingress): phv166[15:0] = meta.l4_length[15:0] (deparsed) | ||
| 267 | 16-bit PHV 167n (ingress): phv167[15:0] = meta.nexthop[127:112] | ||
| 268 | 16-bit PHV 167n (ingress): phv167[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed) | ||
| 269 | 16-bit PHV 167n (ingress): phv167[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed) | ||
| 270 | 16-bit PHV 168n (ingress): phv168[15:0] = hdr.udp.hdr_length[15:0] (deparsed) | ||
| 271 | 16-bit PHV 169n (ingress): phv169[15:13] = hdr.vlan.pcp[2:0] (deparsed) | ||
| 272 | 16-bit PHV 169n (ingress): phv169[12:12] = hdr.vlan.dei[0:0] (deparsed) | ||
| 273 | 16-bit PHV 169n (ingress): phv169[11:0] = hdr.vlan.vlan_id[11:0] (deparsed) | ||
| 274 | 16-bit PHV 170n (ingress): phv170[15:0] = hdr.sidecar.sc_payload[127:112] (deparsed) | ||
| 275 | 16-bit PHV 171n (ingress): phv171[15:8] = hdr.icmp.type[7:0] (deparsed) | ||
| 276 | 16-bit PHV 171n (ingress): phv171[15:8] = hdr.inner_icmp.type[7:0] (deparsed) | ||
| 277 | 16-bit PHV 171n (ingress): phv171[7:0] = hdr.icmp.code[7:0] (deparsed) | ||
| 278 | 16-bit PHV 171n (ingress): phv171[7:0] = hdr.inner_icmp.code[7:0] (deparsed) | ||
| 279 | 16-bit PHV 172m (egress): phv172[10:10] = hdr.ipv6.$valid[0:0] (deparsed) | ||
| 280 | 16-bit PHV 172m (egress): phv172[9:9] = hdr.geneve_opts.oxg_mss.$valid[0:0] | ||
| 281 | 16-bit PHV 172m (egress): phv172[8:8] = hdr.geneve_opts.oxg_mss_tag.$valid[0:0] (deparsed) | ||
| 282 | 16-bit PHV 172m (egress): phv172[7:7] = hdr.geneve_opts.oxg_mcast.$valid[0:0] | ||
| 283 | 16-bit PHV 172m (egress): phv172[6:6] = hdr.geneve_opts.oxg_mcast_tag.$valid[0:0] (deparsed) | ||
| 284 | 16-bit PHV 172m (egress): phv172[5:5] = hdr.geneve_opts.oxg_ext_tag.$valid[0:0] (deparsed) | ||
| 285 | 16-bit PHV 172m (egress): phv172[4:4] = hdr.inner_ipv6.$valid[0:0] (deparsed) | ||
| 286 | 16-bit PHV 172m (egress): phv172[3:3] = hdr.inner_udp.$valid[0:0] (deparsed) | ||
| 287 | 16-bit PHV 172m (egress): phv172[2:2] = hdr.inner_tcp.$valid[0:0] (deparsed) | ||
| 288 | 16-bit PHV 172m (egress): phv172[1:1] = hdr.inner_ipv4.$valid[0:0] (deparsed) | ||
| 289 | 16-bit PHV 172m (egress): phv172[0:0] = hdr.inner_eth.$valid[0:0] (deparsed) | ||
| 290 | 16-bit PHV 173m (egress): phv173[8:0] = eg_intr_md.egress_port[8:0] (deparsed) | ||
| 291 | 16-bit PHV 174m (egress): phv174[2:0] = eg_intr_md_for_dprsr.drop_ctl[2:0] (deparsed) | ||
| 292 | 16-bit PHV 175m (egress): phv175[0:0] = eg_intr_md_for_dprsr.mirror_io_select[0:0] (deparsed) | ||
| 293 | 16-bit PHV 176d (ingress): phv176[15:0] = hdr.inner_udp.hdr_length[15:0] (deparsed) | ||
| 294 | >> 13 in ingress and 4 in egress | ||
| 295 | |||
| 296 | Allocations in Group 9 16 bits | ||
| 297 | 16-bit PHV 180n (ingress): phv180[15:0] = l3_router_fwd.idx[15:0] | ||
| 298 | 16-bit PHV 181n (ingress): phv181[15:0] = hdr.sidecar.sc_egress[15:0] (deparsed) | ||
| 299 | 16-bit PHV 182n (ingress): phv182[15:0] = hdr.sidecar.sc_ingress[15:0] (deparsed) | ||
| 300 | 16-bit PHV 183n (ingress): phv183[15:0] = meta.nexthop[79:64] | ||
| 301 | 16-bit PHV 183n (ingress): phv183[15:0] = hdr.geneve.vni[15:0] (deparsed) | ||
| 302 | 16-bit PHV 183n (ingress): phv183[15:0] = hdr.geneve.vni[15:0] (deparsed) | ||
| 303 | 16-bit PHV 184n (ingress): phv184[15:0] = meta.nat_geneve_vni[15:0] | ||
| 304 | 16-bit PHV 185n (ingress): phv185[15:0] = hdr.sidecar.sc_payload[79:64] (deparsed) | ||
| 305 | 16-bit PHV 186n (ingress): phv186[15:0] = meta.nexthop[111:96] | ||
| 306 | 16-bit PHV 186n (ingress): phv186[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed) | ||
| 307 | 16-bit PHV 186n (ingress): phv186[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed) | ||
| 308 | 16-bit PHV 187n (ingress): phv187[15:0] = hdr.sidecar.sc_payload[111:96] (deparsed) | ||
| 309 | 16-bit PHV 188n (ingress): phv188[15:0] = meta.nat_inner_mac[47:32] | ||
| 310 | 16-bit PHV 189n (ingress): phv189[15:0] = meta.l4_src_port[15:0] | ||
| 311 | 16-bit PHV 192m (ingress): phv192[15:0] = l3_router_fwd.slot[15:0] | ||
| 312 | 16-bit PHV 193m (ingress): phv193[8:0] = ig_intr_md.ingress_port[8:0] | ||
| 313 | 16-bit PHV 194m (ingress): phv194[8:0] = ig_intr_md_for_tm.ucast_egress_port[8:0] (deparsed) | ||
| 314 | 16-bit PHV 195m (ingress): phv195[15:0] = hdr.inner_eth.src_mac[15:0] (deparsed) | ||
| 315 | 16-bit PHV 196d (ingress): phv196[15:0] = hdr.geneve.vni[15:0] (deparsed) | ||
| 316 | 16-bit PHV 197d (ingress): phv197[15:0] = hdr.inner_eth.dst_mac[47:32] (deparsed) | ||
| 317 | >> 16 in ingress and 0 in egress | ||
| 318 | |||
| 319 | Allocations in Group 10 16 bits | ||
| 320 | 16-bit PHV 212m (ingress): phv212[15:0] = hdr.sidecar.sc_ether_type[15:0] (deparsed) | ||
| 321 | 16-bit PHV 213m (ingress): phv213[15:0] = hdr.ethernet.ether_type[15:0] (deparsed) | ||
| 322 | 16-bit PHV 214m (ingress): phv214[15:0] = hdr.vlan.ether_type[15:0] (deparsed) | ||
| 323 | 16-bit PHV 215m (ingress): phv215[15:0] = hdr.inner_eth.ether_type[15:0] (deparsed) | ||
| 324 | >> 4 in ingress and 0 in egress | ||
| 325 | |||
| 326 | Allocations in Group 11 16 bits | ||
| 327 | 16-bit PHV 220n (ingress): phv220[15:0] = meta.orig_src_mac[47:32] | ||
| 328 | 16-bit PHV 232m (ingress): phv232[15:0] = hdr.ethernet.src_mac[47:32] (deparsed) | ||
| 329 | 16-bit PHV 233m (ingress): phv233[15:0] = hdr.ethernet.dst_mac[47:32] (deparsed) | ||
| 330 | 16-bit PHV 234m (ingress): phv234[15:0] = hdr.icmp.hdr_checksum[15:0] (deparsed) | ||
| 331 | 16-bit PHV 234m (ingress): phv234[15:0] = hdr.inner_udp.checksum[15:0] (deparsed) | ||
| 332 | 16-bit PHV 234m (ingress): phv234[15:0] = hdr.inner_icmp.hdr_checksum[15:0] (deparsed) | ||
| 333 | 16-bit PHV 235m (ingress): phv235[15:0] = hdr.udp.checksum[15:0] (deparsed) | ||
| 334 | >> 5 in ingress and 0 in egress | ||
| 335 | |||
| 336 | Allocations in Group 12 16 bits | ||
| 337 | 16-bit PHV 252m (ingress): phv252[15:0] = hdr.inner_ipv4.hdr_checksum[15:0] (deparsed) | ||
| 338 | 16-bit PHV 253m (ingress): phv253[15:0] = hdr.ipv4.hdr_checksum[15:0] (deparsed) | ||
| 339 | 16-bit PHV 254m (ingress): phv254[15:9] = meta.bridge_hdr.__pad_1[6:0] | ||
| 340 | 16-bit PHV 254m (ingress): phv254[8:0] = meta.bridge_hdr.ingress_port[8:0] (deparsed) | ||
| 341 | 16-bit PHV 255m (ingress): phv255[15:8] = hdr.sidecar.sc_code[7:0] (deparsed) | ||
| 342 | 16-bit PHV 255m (ingress): phv255[7:0] = hdr.sidecar.sc_pad[7:0] (deparsed) | ||
| 343 | >> 4 in ingress and 0 in egress | ||
| 344 | |||
| 345 | Allocations in Group 13 16 bits | ||
| 346 | 16-bit PHV 272m (egress): phv272[15:0] = hdr.ethernet.src_mac[47:32] (tagalong capable) (deparsed) | ||
| 347 | >> 0 in ingress and 1 in egress | ||
| 348 | |||
| 349 | |||
| 350 | Final POV layout (ingress): | ||
| 351 | |||
| 352 | Final POV layout (egress): | ||