+---------------------------------------------------------------------+ | Log file: mau.resources.log | | Compiler version: 9.13.4 | | Created on: Tue Oct 20 02:05:00 2026 | | Run ID: e20eef7aef6c4569 | +---------------------------------------------------------------------+ --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 20 | 6 | 29 | 2 | 15 | 8 | 6 | 2 | 6 | 0 | 3 | 0 | 13 | 5 | 5 | 4 | 0 | 0 | 0 | 16 | | 1 | 16 | 41 | 69 | 1 | 9 | 30 | 8 | 16 | 5 | 0 | 4 | 0 | 9 | 4 | 6 | 87 | 0 | 0 | 0 | 12 | | 2 | 32 | 2 | 90 | 0 | 5 | 36 | 6 | 1 | 8 | 0 | 2 | 0 | 7 | 3 | 3 | 56 | 0 | 0 | 0 | 6 | | 3 | 7 | 24 | 0 | 0 | 4 | 14 | 5 | 24 | 2 | 0 | 2 | 0 | 4 | 0 | 4 | 52 | 0 | 0 | 0 | 6 | | 4 | 8 | 11 | 27 | 2 | 4 | 15 | 8 | 7 | 4 | 0 | 4 | 0 | 4 | 4 | 3 | 35 | 0 | 0 | 0 | 6 | | 5 | 15 | 0 | 38 | 2 | 12 | 7 | 4 | 0 | 5 | 0 | 2 | 0 | 11 | 4 | 10 | 15 | 0 | 0 | 0 | 16 | | 6 | 6 | 0 | 9 | 1 | 7 | 12 | 8 | 0 | 2 | 0 | 4 | 0 | 6 | 4 | 7 | 55 | 0 | 0 | 0 | 12 | | 7 | 9 | 43 | 1 | 0 | 8 | 10 | 6 | 18 | 10 | 0 | 3 | 0 | 8 | 0 | 9 | 24 | 0 | 0 | 0 | 11 | | 8 | 60 | 0 | 66 | 2 | 1 | 15 | 3 | 0 | 2 | 0 | 1 | 0 | 2 | 1 | 1 | 15 | 0 | 0 | 0 | 1 | | 9 | 3 | 7 | 0 | 0 | 2 | 1 | 0 | 2 | 4 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 3 | | 10 | 2 | 0 | 10 | 0 | 1 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | 1 | 1 | 0 | 12 | 0 | 0 | 0 | 1 | | 11 | 47 | 16 | 26 | 2 | 10 | 12 | 7 | 22 | 6 | 0 | 2 | 0 | 10 | 4 | 7 | 16 | 0 | 0 | 0 | 15 | | 12 | 23 | 16 | 80 | 0 | 4 | 22 | 9 | 24 | 9 | 0 | 3 | 0 | 5 | 2 | 11 | 21 | 0 | 0 | 0 | 13 | | 13 | 3 | 16 | 40 | 0 | 1 | 8 | 3 | 21 | 2 | 0 | 1 | 0 | 1 | 1 | 1 | 8 | 0 | 0 | 0 | 2 | | 14 | 3 | 0 | 40 | 0 | 2 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 1 | 2 | 3 | 0 | 0 | 0 | 3 | | 15 | 4 | 0 | 80 | 0 | 0 | 29 | 5 | 0 | 5 | 0 | 1 | 0 | 1 | 1 | 1 | 24 | 0 | 0 | 0 | 2 | | 16 | 7 | 0 | 80 | 0 | 1 | 31 | 5 | 0 | 5 | 0 | 1 | 0 | 2 | 1 | 4 | 55 | 0 | 0 | 0 | 5 | | 17 | 3 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 4 | 33 | 0 | 0 | 0 | 4 | | 18 | 21 | 0 | 80 | 0 | 2 | 24 | 6 | 0 | 4 | 0 | 2 | 0 | 3 | 2 | 1 | 33 | 0 | 0 | 0 | 3 | | 19 | 8 | 0 | 27 | 2 | 6 | 8 | 6 | 0 | 3 | 0 | 3 | 0 | 6 | 3 | 4 | 8 | 0 | 0 | 0 | 6 | | | | | | | | | | | | | | | | | | | | | | | | Totals | 297 | 182 | 792 | 14 | 95 | 290 | 95 | 137 | 93 | 0 | 38 | 0 | 98 | 41 | 84 | 556 | 0 | 0 | 0 | 143 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | 0 | 15.62% | 9.09% | 6.97% | 33.33% | 93.75% | 10.00% | 12.50% | 8.33% | 18.75% | 0.00% | 75.00% | 0.00% | 81.25% | 31.25% | 31.25% | 3.12% | 0.00% | 0.00% | 0.00% | 100.00% | | 1 | 12.50% | 62.12% | 16.59% | 16.67% | 56.25% | 37.50% | 16.67% | 66.67% | 15.62% | 0.00% | 100.00% | 0.00% | 56.25% | 25.00% | 37.50% | 67.97% | 0.00% | 0.00% | 0.00% | 75.00% | | 2 | 25.00% | 3.03% | 21.63% | 0.00% | 31.25% | 45.00% | 12.50% | 4.17% | 25.00% | 0.00% | 50.00% | 0.00% | 43.75% | 18.75% | 18.75% | 43.75% | 0.00% | 0.00% | 0.00% | 37.50% | | 3 | 5.47% | 36.36% | 0.00% | 0.00% | 25.00% | 17.50% | 10.42% | 100.00% | 6.25% | 0.00% | 50.00% | 0.00% | 25.00% | 0.00% | 25.00% | 40.62% | 0.00% | 0.00% | 0.00% | 37.50% | | 4 | 6.25% | 16.67% | 6.49% | 33.33% | 25.00% | 18.75% | 16.67% | 29.17% | 12.50% | 0.00% | 100.00% | 0.00% | 25.00% | 25.00% | 18.75% | 27.34% | 0.00% | 0.00% | 0.00% | 37.50% | | 5 | 11.72% | 0.00% | 9.13% | 33.33% | 75.00% | 8.75% | 8.33% | 0.00% | 15.62% | 0.00% | 50.00% | 0.00% | 68.75% | 25.00% | 62.50% | 11.72% | 0.00% | 0.00% | 0.00% | 100.00% | | 6 | 4.69% | 0.00% | 2.16% | 16.67% | 43.75% | 15.00% | 16.67% | 0.00% | 6.25% | 0.00% | 100.00% | 0.00% | 37.50% | 25.00% | 43.75% | 42.97% | 0.00% | 0.00% | 0.00% | 75.00% | | 7 | 7.03% | 65.15% | 0.24% | 0.00% | 50.00% | 12.50% | 12.50% | 75.00% | 31.25% | 0.00% | 75.00% | 0.00% | 50.00% | 0.00% | 56.25% | 18.75% | 0.00% | 0.00% | 0.00% | 68.75% | | 8 | 46.88% | 0.00% | 15.87% | 33.33% | 6.25% | 18.75% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 12.50% | 6.25% | 6.25% | 11.72% | 0.00% | 0.00% | 0.00% | 6.25% | | 9 | 2.34% | 10.61% | 0.00% | 0.00% | 12.50% | 1.25% | 0.00% | 8.33% | 12.50% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 18.75% | | 10 | 1.56% | 0.00% | 2.40% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | | 11 | 36.72% | 24.24% | 6.25% | 33.33% | 62.50% | 15.00% | 14.58% | 91.67% | 18.75% | 0.00% | 50.00% | 0.00% | 62.50% | 25.00% | 43.75% | 12.50% | 0.00% | 0.00% | 0.00% | 93.75% | | 12 | 17.97% | 24.24% | 19.23% | 0.00% | 25.00% | 27.50% | 18.75% | 100.00% | 28.12% | 0.00% | 75.00% | 0.00% | 31.25% | 12.50% | 68.75% | 16.41% | 0.00% | 0.00% | 0.00% | 81.25% | | 13 | 2.34% | 24.24% | 9.62% | 0.00% | 6.25% | 10.00% | 6.25% | 87.50% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 6.25% | 6.25% | 0.00% | 0.00% | 0.00% | 12.50% | | 14 | 2.34% | 0.00% | 9.62% | 0.00% | 12.50% | 5.00% | 0.00% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 12.50% | 6.25% | 12.50% | 2.34% | 0.00% | 0.00% | 0.00% | 18.75% | | 15 | 3.12% | 0.00% | 19.23% | 0.00% | 0.00% | 36.25% | 10.42% | 0.00% | 15.62% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 6.25% | 18.75% | 0.00% | 0.00% | 0.00% | 12.50% | | 16 | 5.47% | 0.00% | 19.23% | 0.00% | 6.25% | 38.75% | 10.42% | 0.00% | 15.62% | 0.00% | 25.00% | 0.00% | 12.50% | 6.25% | 25.00% | 42.97% | 0.00% | 0.00% | 0.00% | 31.25% | | 17 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 25.00% | 25.78% | 0.00% | 0.00% | 0.00% | 25.00% | | 18 | 16.41% | 0.00% | 19.23% | 0.00% | 12.50% | 30.00% | 12.50% | 0.00% | 12.50% | 0.00% | 50.00% | 0.00% | 18.75% | 12.50% | 6.25% | 25.78% | 0.00% | 0.00% | 0.00% | 18.75% | | 19 | 6.25% | 0.00% | 6.49% | 33.33% | 37.50% | 10.00% | 12.50% | 0.00% | 9.38% | 0.00% | 75.00% | 0.00% | 37.50% | 18.75% | 25.00% | 6.25% | 0.00% | 0.00% | 0.00% | 37.50% | | | | | | | | | | | | | | | | | | | | | | | | Average | 11.60% | 13.79% | 9.52% | 11.67% | 29.69% | 18.12% | 9.90% | 28.54% | 14.53% | 0.00% | 47.50% | 0.00% | 30.63% | 12.81% | 26.25% | 21.72% | 0.00% | 0.00% | 0.00% | 44.69% | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Allocated Resource Usage -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind | | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result | | | | | | | | | | Bus | | Bus | Bus | Bus | | | | | | | | | | Bytes | | | | | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.drop_mcast_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 | | Ingress.filter.uplink_ports | 0 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 | | Ingress.packet_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-84 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-85 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-86 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-87 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-88 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-89 | 0 | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-90 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-91 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-92 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-93 | 0 | 8 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-96 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_filter_drop_bad_mac | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_filter_drop_bad_mac_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_filter_drop_bad_mac_1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar203 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar203-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2111 | 0 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2111-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2114 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar224 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar224-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar238 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar238-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Egress.egress_filter.egress_filter | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 | | Egress.mcast_egress.asic_id_to_port | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | Egress.mcast_egress.mcast_tag_check | 1 | 19 | 0 | 0 | 1 | 4 | 0 | 0 | 1 | 0 | 0 | 1 | | Egress.mcast_egress.tbl_decap_ports | 1 | 2 | 40 | 0 | 4 | 0 | 0 | 34 | 3 | 1 | 1 | 0 | | Egress.mcast_egress.tbl_decap_ports$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v4 | 1 | 4 | 0 | 0 | 1 | 2 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.attached_subnet_ingress.attached_subnets_v4$action | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v4_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v6 | 1 | 16 | 0 | 0 | 1 | 6 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.attached_subnet_ingress.attached_subnets_v6$action | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.attached_subnet_ingress.attached_subnets_v6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.ipv6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.filter.switch_ipv6_addr | 1 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 | | Ingress.ingress_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-151 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-152 | 1 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-161 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-162 | 1 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-94 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-95 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-97 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-98 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar2110 | 1 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2110-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2358 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2370 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Egress.mcast_egress.port_bitmap_check | 2 | 1 | 10 | 0 | 1 | 0 | 0 | 4 | 9 | 1 | 1 | 0 | | Ingress.nat_ingress.icmp_dst_port | 2 | 2 | 0 | 0 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4_mcast | 2 | 7 | 40 | 0 | 4 | 0 | 0 | 26 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_ipv4_mcast$action | 2 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6_mcast | 2 | 19 | 40 | 0 | 8 | 0 | 0 | 26 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_ipv6_mcast$action | 2 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.mcast_ipv4_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.mcast_ipv6_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | cond-100 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-101 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-103 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-104 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-99 | 2 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4 | 3 | 8 | 0 | 0 | 1 | 4 | 0 | 26 | 2 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4$action | 3 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6 | 3 | 20 | 0 | 0 | 0 | 20 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv6$action | 3 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv6_ingress_ctr | 3 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | cond-102 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-153 | 3 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-154 | 3 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-155 | 3 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2073 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2076 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2078 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Egress.drop_reason_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.forwarded_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.mac_rewrite.ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.mac_rewrite.mac_rewrite | 4 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 | | Egress.mac_rewrite.mac_rewrite$action | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Egress.mcast_egress.modify_hdr | 4 | 3 | 0 | 0 | 1 | 1 | 0 | 2 | 5 | 0 | 0 | 1 | | Ingress.nat_ingress.ingress_ipv4 | 4 | 8 | 0 | 0 | 0 | 6 | 0 | 26 | 2 | 0 | 0 | 0 | | Ingress.nat_ingress.ingress_ipv4$action | 4 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.ipv4_ingress_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-156 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-163 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5-gateway | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5_egress | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | | tbl_sidecar2376 | 4 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2379 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2379-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Egress.drop_port_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.nat_ingress.CalculateIPv4Len.ipv4_set_len | 5 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_hit | 5 | 3 | 10 | 0 | 1 | 0 | 0 | 8 | 4 | 1 | 1 | 0 | | Ingress.nat_ingress.ingress_hit$action | 5 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-105 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-106 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-107 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-108 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-110 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-150 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-157 | 5 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-158 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-159 | 5 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-160 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-164 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_sidecar1607 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1609 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1612 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1622_0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1624_0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2199 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2375 | 5 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2375-gateway | 5 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2382 | 5 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar730 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar738 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar764 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | Egress.external_mcast_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.link_local_mcast_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.underlay_mcast_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Egress.unicast_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-111 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-112 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-114 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-165 | 6 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-166 | 6 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | tbl_nat_ingress_CalculateIPv4Len_invert | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv4$action | 6 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_nat_ingress_encap_ipv6 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 1 | 0 | 0 | 1 | | tbl_nat_ingress_encap_ipv6$action | 6 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1612_0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1627 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar2409 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2411 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2413 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2413-gateway | 6 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2416 | 6 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2416-gateway | 6 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.mcast_ingress.mcast_ipv4_ssm_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_ipv6_ssm_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_source_filter_ipv4 | 7 | 8 | 0 | 0 | 1 | 4 | 0 | 1 | 2 | 0 | 0 | 1 | | Ingress.mcast_ingress.mcast_source_filter_ipv6 | 7 | 32 | 0 | 0 | 1 | 12 | 0 | 1 | 2 | 0 | 0 | 1 | | Ingress.services.service | 7 | 8 | 0 | 0 | 1 | 2 | 0 | 20 | 7 | 0 | 0 | 1 | | Ingress.services.service$action | 7 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.services.service_ctr | 7 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | cond-109 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-113 | 7 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-115 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-116 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-117 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-118 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-119 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-120 | 7 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_mcast_ingress_drop_mcastv4_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_mcast_ingress_drop_mcastv6_no_group | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1832 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1841 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar413 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar750 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.mcast_ingress.mcast_ipv6_ctr | 8 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_replication_ipv6 | 8 | 58 | 66 | 0 | 8 | 0 | 0 | 15 | 2 | 1 | 1 | 0 | | Ingress.mcast_ingress.mcast_replication_ipv6$action | 8 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-121 | 8 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | mcast_ingress_mcast_replication_ipv6 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.mcast_ingress.mcast_tag_check | 9 | 7 | 0 | 0 | 1 | 2 | 0 | 0 | 5 | 0 | 0 | 1 | | cond-122 | 9 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-123 | 9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.nat_egress.nat_egress | 10 | 1 | 10 | 0 | 1 | 0 | 0 | 12 | 7 | 1 | 1 | 0 | | Ingress.nat_egress.nat_egress$action | 10 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-124 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.lookup | 11 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.lookup$action | 11 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 11 | 16 | 0 | 0 | 1 | 6 | 0 | 6 | 2 | 0 | 0 | 1 | | cond-125 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-126 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-127 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-128 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-131 | 11 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-135 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-136 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-137 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-139 | 11 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_4-gateway | 11 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | ingresshdr.icmp.hdr_checksum_encode_update_condition_4_ingress | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 | | ingresshdr.udp.checksum_encode_update_condition_3_ingress | 11 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 | | tbl_sidecar1265 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1272$precompute | 11 | 12 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | | tbl_sidecar1356 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1405 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1421$precompute | 11 | 36 | 8 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | | tbl_sidecar1491 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.MulticastRouter4.ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.MulticastRouter4.tbl | 12 | 4 | 40 | 0 | 4 | 0 | 0 | 4 | 3 | 1 | 1 | 0 | | Ingress.l3_router.MulticastRouter6.ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.MulticastRouter6.tbl | 12 | 16 | 40 | 0 | 8 | 0 | 0 | 4 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 12 | 16 | 0 | 0 | 1 | 24 | 0 | 6 | 2 | 0 | 0 | 1 | | cond-129 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-130 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-133 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-138 | 12 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1272 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1296 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1363 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1367 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1371 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1373 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1421 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1500 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1504 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1508 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.select_route | 13 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.index_ctr | 13 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.lookup | 13 | 16 | 0 | 0 | 1 | 21 | 0 | 6 | 2 | 0 | 0 | 1 | | cond-132 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.select_route | 14 | 2 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 | | cond-140 | 14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-141 | 14 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar1137 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar1432 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router4.lookup_idx.forward_ctr | 15 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router4.lookup_idx.route | 15 | 4 | 80 | 0 | 8 | 0 | 0 | 24 | 5 | 1 | 1 | 0 | | Ingress.l3_router.Router4.lookup_idx.route$action | 15 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1009 | 15 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Router6.lookup_idx.forward_ctr | 16 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Router6.lookup_idx.route | 16 | 4 | 80 | 0 | 8 | 0 | 0 | 22 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Router6.lookup_idx.route$action | 16 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-134 | 16 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_Router4_icmp_error | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router4_icmp_error_0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router4_icmp_error_0$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1301 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1303 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | cond-142 | 17 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_l3_router_Router6_icmp_error | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error$action | 17 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_l3_router_Router6_icmp_error_0 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 | | tbl_l3_router_Router6_icmp_error_0$action | 17 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | tbl_sidecar1437 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | | tbl_sidecar1441 | 17 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | Ingress.l3_router.Arp.ctr | 18 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Arp.tbl | 18 | 4 | 40 | 0 | 4 | 0 | 0 | 18 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Arp.tbl$action | 18 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Ndp.ctr | 18 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | | Ingress.l3_router.Ndp.tbl | 18 | 16 | 40 | 0 | 8 | 0 | 0 | 15 | 3 | 1 | 1 | 0 | | Ingress.l3_router.Ndp.tbl$action | 18 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-143 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-144 | 18 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | Ingress.drop_port_ctr | 19 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.drop_reason_ctr | 19 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.ctr | 19 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | | Ingress.mac_rewrite.mac_rewrite | 19 | 2 | 10 | 0 | 1 | 0 | 0 | 8 | 2 | 1 | 1 | 0 | | Ingress.mac_rewrite.mac_rewrite$action | 19 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | cond-145 | 19 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-146 | 19 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-147 | 19 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | cond-148 | 19 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | | cond-149 | 19 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2153 | 19 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2153-gateway | 19 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | | tbl_sidecar2155 | 19 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | | tbl_sidecar2161 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | | tbl_sidecar2164 | 19 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------