PHV ALLOCATION SUCCESSFUL PHV Allocation +-----------+-------+-----------------+--------------------------------------------------------+ |Container |Gress |Container Slice |Field Slice | +-----------+-------+-----------------+--------------------------------------------------------+ |B0 |I | |ingress::$tmp3 | | | | | | |MB0 |E |[0] |egress::hdr.geneve_opts.oxg_mss_tag.$valid | | | |[1] |egress::hdr.geneve_opts.oxg_mss.$valid | | | |[2] |egress::hdr.ipv6.$valid | | | |[3] |egress::eg_intr_md_for_dprsr.mirror_io_select | | | | | | |DB0 |I | |ingress::hdr.geneve.vni[23:16] ARA | | | | | | |B1 |I |[0] |ingress::hdr.vlan.$valid | | | |[1] |ingress::hdr.icmp.hdr_checksum.$deparse_original_csum | | | |[2] |ingress::hdr.icmp.hdr_checksum.$deparse_updated_csum_0 | | | |[3] |ingress::ig_intr_md_for_tm.bypass_egress | | | |[6:4] |ingress::ig_intr_md_for_dprsr.drop_ctl | | | |[7] |ingress::meta.encap_needed | | | | | | |MB1 |I | |ingress::meta.nat_geneve_vni[23:16] | | | | | | |... | | | | | | | | | |B2 |I |[0] |ingress::hdr.udp.checksum.$deparse_original_csum | | | |[1] |ingress::hdr.udp.checksum.$deparse_updated_csum_0 | | | |[2] |ingress::hdr.udp.checksum.$deparse_updated_csum_1 | | | |[3] |ingress::hdr.udp.checksum.$deparse_updated_csum_2 | | | |[4] |ingress::hdr.udp.checksum.$deparse_updated_csum_3 | | | |[5] |ingress::meta.dropped | | | |[6] |ingress::meta.service_routed | | | |[7] |ingress::meta.nat_egress_hit | | | | | | |MB2 |I | |ingress::l3_router_Router4_fwd.nexthop6[31:24] | | | | |ingress::l3_router_Router6_fwd.nexthop[31:24] | | | | | | |... | | | | | | | | | |B3 |I | |ingress::hdr.geneve.vni[23:16] | | | | |ingress::hdr.geneve.vni[23:16] ARA | | | | |ingress::meta.nexthop_ipv6[31:24] ARA | | | | | | |MB3 |I | |ingress::l3_router_Router4_fwd.nexthop[31:24] | | | | |ingress::l3_router_Router6_fwd.slots | | | | | | |... | | | | | | | | | |B4 |I | |ingress::hdr.sidecar.sc_payload[31:24] | | | | | | |... | | | | | | | | | |B8 |I | |ingress::meta.nexthop_ipv4[31:24] | | | | | | |... | | | | | | | | | |MB4 |I | |ingress::hdr.inner_ipv4.ttl | | | | |ingress::hdr.inner_ipv6.hop_limit | | | | | | |... | | | | | | | | | |MB5 |I |[3:0] |ingress::ig_intr_md_for_dprsr.mirror_type | | | | | | |... | | | | | | | | | |MB6 |I | |ingress::hdr.inner_ipv4.protocol | | | | |ingress::hdr.inner_ipv6.next_hdr | | | | | | |... | | | | | | | | | |MB7 |I | |ingress::hdr.ipv4.protocol | | | | |ingress::hdr.ipv6.next_hdr | | | | | | |... | | | | | | | | | |B12 |I | |ingress::hdr.ipv4.ttl | | | | |ingress::hdr.ipv6.hop_limit | | | | | | |... | | | | | | | | | |MB8 |I | |ingress::hdr.geneve.reserved2 | | | | |ingress::hdr.geneve.reserved2 ARA | | | | |ingress::l3_router_Router4_fwd.nexthop6[7:0] ARA | | | | | | |DB8 |I | |ingress::hdr.geneve.reserved2 ARA | | | | | | |MB9 |I | |ingress::hdr.sidecar.sc_payload[7:0] | | | | | | |... | | | | | | | | | |MB10 |I | |ingress::meta.nexthop_ipv6[7:0] | | | | | | |... | | | | | | | | | |MB11 |I | |ingress::l3_router_Router6_fwd.nexthop[7:0] | | | | |ingress::l3_router_Router4_fwd.nexthop[7:0] | | | | | | |... | | | | | | | | | |B24 |I | |ingress::meta.nexthop_ipv4[7:0] | | | | | | |... | | | | | | | | | |MB12 |I | |ingress::meta.drop_reason | | | | | | |... | | | | | | | | | |H0 |I |[7:0] |ingress::hdr.inner_tcp.flags | | | |[11:8] |ingress::hdr.inner_tcp.res | | | |[15:12] |ingress::hdr.inner_tcp.data_offset | | | |[7:0] |ingress::hdr.tcp.flags | | | |[11:8] |ingress::hdr.tcp.res | | | |[15:12] |ingress::hdr.tcp.data_offset | | | |[7:0] |ingress::hdr.inner_icmp.code | | | |[15:8] |ingress::hdr.inner_icmp.type | | | |[7:0] |ingress::hdr.icmp.code | | | |[15:8] |ingress::hdr.icmp.type | | | | | | |MH0 |I | |ingress::meta.icmp_csum | | | | | | |DH0 |I |[8:0] |ingress::meta.bridge_hdr.ingress_port ARA | | | | | | |H1 |I |[7:0] |ingress::hdr.inner_ipv4.diffserv | | | |[11:8] |ingress::hdr.inner_ipv4.ihl | | | |[15:12] |ingress::hdr.inner_ipv4.version | | | | | | |MH1 |I | |ingress::meta.body_checksum | | | | | | |... | | | | | | | | | |H2 |I |[7:0] |ingress::hdr.ipv4.diffserv | | | |[11:8] |ingress::hdr.ipv4.ihl | | | |[15:12] |ingress::hdr.ipv4.version | | | | | | |MH2 |I | |ingress::hdr.ethernet.src_mac[15:0] | | | | | | |... | | | | | | | | | |H3 |I | |ingress::hdr.udp.checksum | | | | | | |MH3 |I | |ingress::hdr.inner_tcp.checksum | | | | |ingress::hdr.tcp.checksum | | | | |ingress::hdr.inner_icmp.data[15:0] | | | | |ingress::hdr.icmp.data[15:0] | | | | |ingress::hdr.inner_udp.checksum | | | | | | |... | | | | | | | | | |H4 |I |[15:9] |ingress::meta.bridge_hdr.__pad_0 | | | |[8:0] |ingress::meta.bridge_hdr.ingress_port | | | |[8:0] |ingress::meta.bridge_hdr.ingress_port ARA | | | |[7:0] |ingress::l3_router_Router4_fwd.slots ARA | | | | | | |H5 |I |[7:0] |ingress::hdr.sidecar.sc_pad | | | |[15:8] |ingress::hdr.sidecar.sc_code | | | | | | |H6 |I | |ingress::meta.nat_ingress_csum | | | | | | |... | | | | | | | | | |H8 |I | |ingress::meta.l4_src_port | | | | | | |... | | | | | | | | | |MH4 |I |[0] |ingress::meta.ipv4_checksum_err | | | | | | |DH4 |I | |ingress::hdr.inner_udp.hdr_length ARA | | | | | | |MH5 |E |[0] |egress::eg_intr_md_for_dprsr.mirror_io_select.$valid | | | |[1] |egress::eg_intr_md.egress_port.$valid | | | |[2] |egress::hdr.ethernet.$valid | | | |[3] |egress::hdr.vlan.$valid | | | |[4] |egress::hdr.ipv4.$valid | | | |[5] |egress::hdr.icmp.$valid | | | |[6] |egress::hdr.udp.$valid | | | |[7] |egress::hdr.geneve.$valid | | | |[8] |egress::hdr.inner_eth.$valid | | | |[9] |egress::hdr.inner_ipv4.$valid | | | |[10] |egress::hdr.inner_tcp.$valid | | | |[11] |egress::hdr.inner_udp.$valid | | | |[12] |egress::hdr.inner_ipv6.$valid | | | |[13] |egress::hdr.geneve_opts.oxg_ext_tag.$valid | | | |[14] |egress::hdr.geneve_opts.oxg_mcast_tag.$valid | | | |[15] |egress::hdr.geneve_opts.oxg_mcast.$valid | | | | | | |DH5 |I | |ingress::hdr.inner_eth.src_mac[15:0] ARA | | | | | | |MH6 |I |[7:0] |ingress::l3_router_Router4_fwd.slot[7:0] | | | |[15:8] |ingress::l3_router_Router4_fwd.slot[15:8] | | | |[7:0] |ingress::l3_router_Router6_fwd.slot[7:0] | | | |[15:8] |ingress::l3_router_Router6_fwd.slot[15:8] | | | | | | |... | | | | | | | | | |MH7 |I | |ingress::meta.l4_dst_port | | | | | | |... | | | | | | | | | |H12 |I | |ingress::hdr.inner_ipv4.total_len | | | | |ingress::hdr.inner_ipv6.payload_len | | | | | | |H13 |I | |ingress::hdr.ipv4.total_len | | | | |ingress::hdr.ipv6.payload_len | | | | | | |H14 |I | |ingress::meta.l4_length | | | | | | |H15 |I | |ingress::hdr.inner_udp.hdr_length | | | | |ingress::hdr.inner_udp.hdr_length ARA | | | |[8:0] |ingress::l3_router_Router4_fwd.port ARA | | | | | | |H16 |I | |ingress::hdr.udp.hdr_length | | | | | | |H17 |I |[8:0] |ingress::ig_intr_md_for_tm.ucast_egress_port | | | |[9] |ingress::l3_router_Router4_fwd.is_hit | | | |[9] |ingress::l3_router_Router6_fwd.is_hit | | | | | | |H18 |I |[8:0] |ingress::hdr.sidecar.sc_egress[8:0] | | | |[15:9] |ingress::hdr.sidecar.sc_egress[15:9] | | | | | | |H19 |I |[8:0] |ingress::hdr.sidecar.sc_ingress[8:0] | | | |[15:9] |ingress::hdr.sidecar.sc_ingress[15:9] | | | | | | |H20 |I |[7:0] |ingress::l3_router_Router4_fwd.idx[7:0] | | | |[15:8] |ingress::l3_router_Router4_fwd.idx[15:8] | | | |[7:0] |ingress::l3_router_Router6_fwd.idx[7:0] | | | |[15:8] |ingress::l3_router_Router6_fwd.idx[15:8] | | | | | | |H21 |I |[8:0] |ingress::ig_intr_md.ingress_port | | | | | | |H22 |I |[8:0] |ingress::l3_router_Router6_fwd.port ARA | | | | |ingress::hdr.inner_eth.src_mac[15:0] | | | | |ingress::hdr.inner_eth.src_mac[15:0] ARA | | | | | | |H23 |I |[11:0] |ingress::hdr.vlan.vlan_id | | | |[12] |ingress::hdr.vlan.dei | | | |[15:13] |ingress::hdr.vlan.pcp | | | | | | |MH8 |E |[8:0] |egress::eg_intr_md.egress_port | | | | | | |DH8 |I | |ingress::hdr.inner_eth.dst_mac[31:16] ARA | | | | | | |MH9 |I | |ingress::meta.nat_inner_mac[31:16] | | | | | | |DH9 |I | |ingress::hdr.inner_ipv4.hdr_checksum ARA | | | | | | |MH10 |I |[7:0] |ingress::meta.orig_src_mac[39:32] | | | |[15:8] |ingress::meta.orig_src_mac[47:40] | | | | | | |DH10 |I | |ingress::hdr.ipv4.hdr_checksum ARA | | | | | | |MH11 |I | |ingress::meta.nat_inner_mac[47:32] | | | | | | |DH11 |I | |ingress::hdr.inner_eth.dst_mac[47:32] ARA | | | | | | |H24 |I | |ingress::hdr.inner_eth.dst_mac[31:16] | | | | |ingress::hdr.inner_eth.dst_mac[31:16] ARA | | | | |ingress::meta.nexthop_ipv6[111:96] ARA | | | | | | |H25 |I |[7:0] |ingress::hdr.ethernet.dst_mac[39:32] | | | |[15:8] |ingress::hdr.ethernet.dst_mac[47:40] | | | | | | |H26 |I | |ingress::hdr.inner_ipv4.hdr_checksum | | | | |ingress::hdr.inner_ipv4.hdr_checksum ARA | | | | |ingress::l3_router_Router4_fwd.nexthop6[111:96] ARA | | | | | | |H27 |I | |ingress::hdr.ipv4.hdr_checksum | | | | |ingress::hdr.ipv4.hdr_checksum ARA | | | | |ingress::l3_router_Router6_fwd.nexthop[111:96] ARA | | | | | | |H28 |I | |ingress::hdr.inner_eth.dst_mac[47:32] | | | | |ingress::hdr.inner_eth.dst_mac[47:32] ARA | | | |[1:0] |ingress::l3_router_Router4_fwd.ecmp_hash[7:6] ARA | | | | | | |H29 |I | |ingress::hdr.sidecar.sc_payload[111:96] | | | | | | |... | | | | | | | | | |MH12 |I | |ingress::hdr.sidecar.sc_payload[127:112] | | | | | | |... | | | | | | | | | |MH13 |I | |ingress::meta.nexthop_ipv6[127:112] | | | | | | |... | | | | | | | | | |MH14 |I | |ingress::l3_router_Router4_fwd.nexthop6[127:112] | | | | |ingress::l3_router_Router6_fwd.nexthop[127:112] | | | | | | |... | | | | | | | | | |MH15 |I | |ingress::hdr.inner_eth.src_mac[47:32] | | | | | | |... | | | | | | | | | |MH16 |I | |ingress::hdr.sidecar.sc_ether_type | | | | | | |... | | | | | | | | | |MH17 |I | |ingress::hdr.ethernet.ether_type | | | | | | |... | | | | | | | | | |MH18 |I | |ingress::hdr.vlan.ether_type | | | | | | |... | | | | | | | | | |MH19 |I | |ingress::hdr.inner_eth.ether_type | | | | | | |... | | | | | | | | | |MH20 |I | |ingress::hdr.inner_udp.dst_port | | | | |ingress::hdr.inner_tcp.window | | | | |ingress::hdr.tcp.window | | | | |ingress::hdr.inner_icmp.data[31:16] | | | | |ingress::hdr.icmp.data[31:16] | | | | | | |DH20 |I | |ingress::hdr.geneve.vni[15:0] ARA | | | | | | |MH21 |I | |ingress::hdr.udp.dst_port | | | | | | |DH21 |I | |ingress::hdr.inner_eth.src_mac[31:16] ARA | | | | | | |MH22 |I |[5:0] |ingress::hdr.inner_udp.src_port[5:0] | | | |[15:6] |ingress::hdr.inner_udp.src_port[15:6] | | | | |ingress::hdr.inner_tcp.urgent_ptr | | | | |ingress::hdr.tcp.urgent_ptr | | | | |ingress::hdr.inner_icmp.hdr_checksum | | | | |ingress::hdr.icmp.hdr_checksum | | | | | | |DH22 |I | |ingress::hdr.inner_eth.dst_mac[15:0] ARA | | | | | | |MH23 |I |[5:0] |ingress::hdr.udp.src_port[5:0] | | | |[15:6] |ingress::hdr.udp.src_port[15:6] | | | | | | |... | | | | | | | | | |H60 |I |[5:0] |ingress::meta.flow_hash[5:0] | | | |[15:6] |ingress::meta.flow_hash[15:6] | | | | | | |H61 |I |[5:0] |ingress::l3_router_Router4_fwd.ecmp_hash[5:0] | | | |[5:0] |ingress::l3_router_Router6_fwd.ecmp_hash[5:0] | | | | |ingress::meta.nat_geneve_vni[15:0] | | | | | | |H62 |I | |ingress::hdr.geneve.vni[15:0] | | | | |ingress::hdr.geneve.vni[15:0] ARA | | | | |ingress::meta.nexthop_ipv6[23:8] ARA | | | | | | |H63 |I | |ingress::hdr.sidecar.sc_payload[23:8] | | | | | | |H64 |I | |ingress::l3_router_Router4_fwd.nexthop6[23:8] | | | | |ingress::l3_router_Router6_fwd.nexthop[23:8] | | | | |ingress::meta.nat_inner_mac[15:0] | | | | | | |H65 |I | |ingress::meta.nexthop_ipv4[23:8] | | | | | | |H66 |I | |ingress::l3_router_Router4_fwd.nexthop[23:8] ARA | | | | |ingress::hdr.inner_eth.src_mac[31:16] | | | | |ingress::hdr.inner_eth.src_mac[31:16] ARA | | | | | | |H67 |I | |ingress::hdr.inner_eth.dst_mac[15:0] | | | | |ingress::hdr.inner_eth.dst_mac[15:0] ARA | | | |[1:0] |ingress::l3_router_Router6_fwd.ecmp_hash[7:6] ARA | | | | | | |... | | | | | | | | | |W0 |I |[0] |ingress::ig_intr_md_for_dprsr.mirror_type.$valid | | | |[1] |ingress::ig_intr_md_for_tm.ucast_egress_port.$valid | | | |[2] |ingress::ig_intr_md_for_dprsr.drop_ctl.$valid | | | |[3] |ingress::ig_intr_md_for_tm.bypass_egress.$valid | | | |[4] |ingress::meta.bridge_hdr.$valid | | | |[5] |ingress::hdr.ethernet.$valid | | | |[6] |ingress::hdr.sidecar.$valid | | | |[7] |ingress::hdr.ipv4.$valid | | | |[8] |ingress::hdr.icmp.$valid | | | |[9] |ingress::hdr.tcp.$valid | | | |[10] |ingress::hdr.udp.$valid | | | |[11] |ingress::hdr.geneve.$valid | | | |[12] |ingress::hdr.inner_eth.$valid | | | |[13] |ingress::hdr.inner_ipv4.$valid | | | |[14] |ingress::hdr.inner_tcp.$valid | | | |[15] |ingress::hdr.inner_udp.$valid | | | |[16] |ingress::hdr.inner_icmp.$valid | | | |[17] |ingress::hdr.inner_ipv6.$valid | | | |[18] |ingress::hdr.geneve_opts.oxg_ext_tag.$valid | | | |[19] |ingress::hdr.geneve_opts.oxg_mcast_tag.$valid | | | |[20] |ingress::hdr.geneve_opts.oxg_mcast.$valid | | | |[21] |ingress::hdr.geneve_opts.oxg_mss_tag.$valid | | | |[22] |ingress::hdr.geneve_opts.oxg_mss.$valid | | | |[23] |ingress::hdr.ipv6.$valid | | | |[24] |ingress::hdr.arp.$valid | | | |[25] |ingress::meta.is_mcast | | | |[26] |ingress::meta.icmp_recalc | | | |[27] |ingress::meta.resolve_nexthop | | | | | | |MW0 |I | |ingress::meta.orig_src_ipv4 | | | | | | |... | | | | | | | | | |W1 |I |[4:0] |ingress::hdr.geneve_opts.oxg_ext_tag.opt_len | | | |[7:5] |ingress::hdr.geneve_opts.oxg_ext_tag.reserved | | | |[14:8] |ingress::hdr.geneve_opts.oxg_ext_tag.type | | | |[15] |ingress::hdr.geneve_opts.oxg_ext_tag.crit | | | |[31:16] |ingress::hdr.geneve_opts.oxg_ext_tag.class | | | | | | |MW1 |I | |ingress::hdr.inner_ipv4.dst_addr | | | | |ingress::hdr.inner_ipv6.dst_addr[31:0] | | | | | | |... | | | | | | | | | |W2 |I | |ingress::hdr.ipv4.src_addr | | | | |ingress::hdr.ipv6.dst_addr[31:0] | | | | | | |MW2 |I | |ingress::hdr.ipv4.dst_addr | | | | |ingress::hdr.ipv6.src_addr[31:0] | | | | | | |... | | | | | | | | | |W3 |I |[15:0] |ingress::hdr.inner_tcp.dst_port | | | |[31:16] |ingress::hdr.inner_tcp.src_port | | | |[15:0] |ingress::hdr.tcp.dst_port | | | |[31:16] |ingress::hdr.tcp.src_port | | | | | | |MW3 |I | |ingress::hdr.inner_ipv4.src_addr | | | | |ingress::hdr.inner_ipv6.src_addr[31:0] | | | | | | |... | | | | | | | | | |W4 |I | |ingress::meta.nat_ingress_tgt[31:0] | | | | | | |W5 |I |[15:0] |ingress::hdr.geneve.protocol | | | |[21:16] |ingress::hdr.geneve.reserved | | | |[22] |ingress::hdr.geneve.crit | | | |[23] |ingress::hdr.geneve.ctrl | | | |[29:24] |ingress::hdr.geneve.opt_len | | | |[31:30] |ingress::hdr.geneve.version | | | | | | |W6 |I | |ingress::hdr.ethernet.src_mac[47:16] | | | | | | |... | | | | | | | | | |W8 |I | |ingress::meta.orig_dst_ipv4 | | | | | | |... | | | | | | | | | |MW4 |I | |ingress::hdr.inner_ipv6.dst_addr[63:32] | | | | | | |... | | | | | | | | | |MW5 |I | |ingress::hdr.inner_ipv6.src_addr[63:32] | | | | | | |... | | | | | | | | | |MW6 |I | |ingress::hdr.ipv6.src_addr[63:32] | | | | | | |... | | | | | | | | | |MW7 |I | |ingress::meta.nat_ingress_tgt[63:32] | | | | | | |... | | | | | | | | | |W12 |I | |ingress::hdr.ipv6.dst_addr[63:32] | | | |[12:0] |ingress::hdr.ipv4.frag_offset | | | |[15:13] |ingress::hdr.ipv4.flags | | | |[31:16] |ingress::hdr.ipv4.identification | | | | | | |W13 |I |[12:0] |ingress::hdr.inner_ipv4.frag_offset | | | |[15:13] |ingress::hdr.inner_ipv4.flags | | | |[31:16] |ingress::hdr.inner_ipv4.identification | | | |[19:0] |ingress::hdr.inner_ipv6.flow_label | | | |[27:20] |ingress::hdr.inner_ipv6.traffic_class | | | |[31:28] |ingress::hdr.inner_ipv6.version | | | | | | |W14 |I |[19:0] |ingress::hdr.ipv6.flow_label | | | |[27:20] |ingress::hdr.ipv6.traffic_class | | | |[31:28] |ingress::hdr.ipv6.version | | | | | | |W15 |I |[23:0] |ingress::hdr.ethernet.dst_mac[23:0] | | | |[31:24] |ingress::hdr.ethernet.dst_mac[31:24] | | | | | | |W16 |I |[23:0] |ingress::meta.orig_src_mac[23:0] | | | |[31:24] |ingress::meta.orig_src_mac[31:24] | | | | | | |... | | | | | | | | | |MW8 |I | |ingress::hdr.inner_ipv6.dst_addr[95:64] | | | | | | |DW8 |I | |ingress::hdr.ipv6.dst_addr[95:64] ARA | | | | | | |MW9 |I | |ingress::hdr.inner_ipv6.src_addr[95:64] | | | | | | |... | | | | | | | | | |MW10 |I | |ingress::hdr.ipv6.src_addr[95:64] | | | | | | |... | | | | | | | | | |MW11 |I | |ingress::meta.nat_ingress_tgt[95:64] | | | | | | |... | | | | | | | | | |W24 |I | |ingress::hdr.ipv6.dst_addr[95:64] | | | | |ingress::hdr.ipv6.dst_addr[95:64] ARA | | | | |ingress::meta.nexthop_ipv6[63:32] ARA | | | | | | |W25 |I | |ingress::hdr.inner_tcp.ack_no | | | | |ingress::hdr.tcp.ack_no | | | | | | |W26 |I | |ingress::hdr.sidecar.sc_payload[63:32] | | | | | | |... | | | | | | | | | |W28 |I | |ingress::l3_router_Router4_fwd.nexthop6[63:32] | | | | |ingress::l3_router_Router6_fwd.nexthop[63:32] | | | |[0] |ingress::meta.uplink_ingress | | | | | | |... | | | | | | | | | |MW12 |I | |ingress::hdr.inner_ipv6.dst_addr[127:96] | | | | | | |DW12 |I | |ingress::hdr.ipv6.dst_addr[127:96] ARA | | | | | | |MW13 |I | |ingress::hdr.inner_ipv6.src_addr[127:96] | | | | | | |... | | | | | | | | | |MW14 |I | |ingress::hdr.ipv6.src_addr[127:96] | | | | | | |... | | | | | | | | | |MW15 |I | |ingress::meta.nat_ingress_tgt[127:96] | | | | | | |... | | | | | | | | | |W36 |I | |ingress::hdr.ipv6.dst_addr[127:96] | | | | |ingress::hdr.ipv6.dst_addr[127:96] ARA | | | | |ingress::meta.nexthop_ipv6[95:64] ARA | | | | | | |W37 |I | |ingress::hdr.inner_tcp.seq_no | | | | |ingress::hdr.tcp.seq_no | | | | | | |W38 |I | |ingress::hdr.sidecar.sc_payload[95:64] | | | | | | |... | | | | | | | | | |W40 |I | |ingress::l3_router_Router4_fwd.nexthop6[95:64] | | | | |ingress::l3_router_Router6_fwd.nexthop[95:64] | | | |[0] |ingress::meta.is_switch_address | | | |[10:1] |ingress::meta.pkt_type | | | |[11] |ingress::meta.is_link_local_mcastv6 | | | |[12] |ingress::meta.nat_ingress_hit | | | | | | |... | | | | | | | | | +-----------+-------+-----------------+--------------------------------------------------------+ POV Allocation (ingress): +-----------+-----------------+--------------------------------------------------------+ |Container |Container Slice |Field Slice | +-----------+-----------------+--------------------------------------------------------+ |B1 |[0] |ingress::hdr.vlan.$valid | | |[1] |ingress::hdr.icmp.hdr_checksum.$deparse_original_csum | | |[2] |ingress::hdr.icmp.hdr_checksum.$deparse_updated_csum_0 | +-----------+-----------------+--------------------------------------------------------+ |B2 |[0] |ingress::hdr.udp.checksum.$deparse_original_csum | | |[1] |ingress::hdr.udp.checksum.$deparse_updated_csum_0 | | |[2] |ingress::hdr.udp.checksum.$deparse_updated_csum_1 | | |[3] |ingress::hdr.udp.checksum.$deparse_updated_csum_2 | | |[4] |ingress::hdr.udp.checksum.$deparse_updated_csum_3 | +-----------+-----------------+--------------------------------------------------------+ |W0 |[0] |ingress::ig_intr_md_for_dprsr.mirror_type.$valid | | |[1] |ingress::ig_intr_md_for_tm.ucast_egress_port.$valid | | |[2] |ingress::ig_intr_md_for_dprsr.drop_ctl.$valid | | |[3] |ingress::ig_intr_md_for_tm.bypass_egress.$valid | | |[4] |ingress::meta.bridge_hdr.$valid | | |[5] |ingress::hdr.ethernet.$valid | | |[6] |ingress::hdr.sidecar.$valid | | |[7] |ingress::hdr.ipv4.$valid | | |[8] |ingress::hdr.icmp.$valid | | |[9] |ingress::hdr.tcp.$valid | | |[10] |ingress::hdr.udp.$valid | | |[11] |ingress::hdr.geneve.$valid | | |[12] |ingress::hdr.inner_eth.$valid | | |[13] |ingress::hdr.inner_ipv4.$valid | | |[14] |ingress::hdr.inner_tcp.$valid | | |[15] |ingress::hdr.inner_udp.$valid | | |[16] |ingress::hdr.inner_icmp.$valid | | |[17] |ingress::hdr.inner_ipv6.$valid | | |[18] |ingress::hdr.geneve_opts.oxg_ext_tag.$valid | | |[19] |ingress::hdr.geneve_opts.oxg_mcast_tag.$valid | | |[20] |ingress::hdr.geneve_opts.oxg_mcast.$valid | | |[21] |ingress::hdr.geneve_opts.oxg_mss_tag.$valid | | |[22] |ingress::hdr.geneve_opts.oxg_mss.$valid | | |[23] |ingress::hdr.ipv6.$valid | | |[24] |ingress::hdr.arp.$valid | +-----------+-----------------+--------------------------------------------------------+ | |Total Bits Used |33 / 128 ( 25.8 %) | | |Pack Density |33 / 48 ( 68.8 %) | +-----------+-----------------+--------------------------------------------------------+ POV Allocation (egress): +-----------+-----------------+------------------------------------------------------+ |Container |Container Slice |Field Slice | +-----------+-----------------+------------------------------------------------------+ |MB0 |[0] |egress::hdr.geneve_opts.oxg_mss_tag.$valid | | |[1] |egress::hdr.geneve_opts.oxg_mss.$valid | | |[2] |egress::hdr.ipv6.$valid | +-----------+-----------------+------------------------------------------------------+ |MH5 |[0] |egress::eg_intr_md_for_dprsr.mirror_io_select.$valid | | |[1] |egress::eg_intr_md.egress_port.$valid | | |[2] |egress::hdr.ethernet.$valid | | |[3] |egress::hdr.vlan.$valid | | |[4] |egress::hdr.ipv4.$valid | | |[5] |egress::hdr.icmp.$valid | | |[6] |egress::hdr.udp.$valid | | |[7] |egress::hdr.geneve.$valid | | |[8] |egress::hdr.inner_eth.$valid | | |[9] |egress::hdr.inner_ipv4.$valid | | |[10] |egress::hdr.inner_tcp.$valid | | |[11] |egress::hdr.inner_udp.$valid | | |[12] |egress::hdr.inner_ipv6.$valid | | |[13] |egress::hdr.geneve_opts.oxg_ext_tag.$valid | | |[14] |egress::hdr.geneve_opts.oxg_mcast_tag.$valid | | |[15] |egress::hdr.geneve_opts.oxg_mcast.$valid | +-----------+-----------------+------------------------------------------------------+ | |Total Bits Used |19 / 128 ( 14.8 %) | | |Pack Density |19 / 24 ( 79.2 %) | +-----------+-----------------+------------------------------------------------------+ +--------------------------------------------------------+------------+-----------+----------------+-----------------+ |Field Slice |Live Range |Container |Container Type |Container Slice | +--------------------------------------------------------+------------+-----------+----------------+-----------------+ |ingress::ig_intr_md_for_dprsr.mirror_type.$valid |[-1r, 14w] |W0 |W |[0] | |ingress::ig_intr_md.ingress_port |[-1r, 14w] |H21 |H |[8:0] | |ingress::meta.bridge_hdr.__pad_0 |[-1r, 14w] |H4 |H |[15:9] | |ingress::meta.bridge_hdr.ingress_port |[0w, 7r] |DH0 |DH |[8:0] | |ingress::meta.bridge_hdr.ingress_port |[-1w, 0r] |H4 |H |[8:0] | |ingress::meta.bridge_hdr.ingress_port |[7w, 14r] |H4 |H |[8:0] | |ingress::hdr.ethernet.dst_mac[39:32] |[-1r, 14w] |H25 |H |[7:0] | |ingress::hdr.ethernet.dst_mac[47:40] |[-1r, 14w] |H25 |H |[15:8] | |ingress::hdr.ethernet.dst_mac[23:0] |[-1r, 14w] |W15 |W |[23:0] | |ingress::hdr.ethernet.dst_mac[31:24] |[-1r, 14w] |W15 |W |[31:24] | |ingress::hdr.ethernet.src_mac[15:0] |[-1r, 14w] |MH2 |MH | | |ingress::hdr.ethernet.src_mac[47:16] |[-1r, 14w] |W6 |W | | |ingress::hdr.ethernet.ether_type |[-1r, 14w] |MH17 |MH | | |ingress::meta.dropped |[-1r, 14w] |B2 |B |[5] | |ingress::meta.ipv4_checksum_err |[-1r, 14w] |MH4 |MH |[0] | |ingress::meta.is_switch_address |[-1r, 14w] |W40 |W |[0] | |ingress::meta.is_mcast |[-1r, 14w] |W0 |W |[25] | |ingress::meta.is_link_local_mcastv6 |[-1r, 14w] |W40 |W |[11] | |ingress::meta.service_routed |[-1r, 14w] |B2 |B |[6] | |ingress::meta.nat_egress_hit |[-1r, 14w] |B2 |B |[7] | |ingress::meta.nat_ingress_hit |[-1r, 14w] |W40 |W |[12] | |ingress::meta.uplink_ingress |[-1r, 14w] |W28 |W |[0] | |ingress::meta.encap_needed |[-1r, 14w] |B1 |B |[7] | |ingress::meta.resolve_nexthop |[-1r, 14w] |W0 |W |[27] | |ingress::meta.nexthop_ipv4[31:24] |[-1r, 14w] |B8 |B | | |ingress::meta.nexthop_ipv4[7:0] |[-1r, 14w] |B24 |B | | |ingress::meta.nexthop_ipv4[23:8] |[-1r, 14w] |H65 |H | | |ingress::meta.nexthop_ipv6[7:0] |[-1r, 14w] |MB10 |MB | | |ingress::meta.nexthop_ipv6[127:112] |[-1r, 14w] |MH13 |MH | | |ingress::meta.nexthop_ipv6[31:24] |[4w, 11r] |B3 |B | | |ingress::meta.nexthop_ipv6[111:96] |[4w, 11r] |H24 |H | | |ingress::meta.nexthop_ipv6[23:8] |[4w, 11r] |H62 |H | | |ingress::meta.nexthop_ipv6[63:32] |[6w, 11r] |W24 |W | | |ingress::meta.nexthop_ipv6[95:64] |[6w, 11r] |W36 |W | | |ingress::meta.pkt_type |[-1r, 14w] |W40 |W |[10:1] | |ingress::meta.drop_reason |[-1r, 14w] |MB12 |MB | | |ingress::meta.l4_src_port |[-1r, 14w] |H8 |H | | |ingress::meta.l4_dst_port |[-1r, 14w] |MH7 |MH | | |ingress::meta.flow_hash[5:0] |[-1r, 14w] |H60 |H |[5:0] | |ingress::meta.flow_hash[15:6] |[-1r, 14w] |H60 |H |[15:6] | |ingress::meta.nat_ingress_tgt[63:32] |[-1r, 14w] |MW7 |MW | | |ingress::meta.nat_ingress_tgt[95:64] |[-1r, 14w] |MW11 |MW | | |ingress::meta.nat_ingress_tgt[127:96] |[-1r, 14w] |MW15 |MW | | |ingress::meta.nat_ingress_tgt[31:0] |[-1r, 14w] |W4 |W | | |ingress::meta.nat_inner_mac[31:16] |[-1r, 14w] |MH9 |MH | | |ingress::meta.nat_inner_mac[47:32] |[-1r, 14w] |MH11 |MH | | |ingress::meta.nat_inner_mac[15:0] |[-1r, 14w] |H64 |H | | |ingress::meta.nat_geneve_vni[23:16] |[-1r, 14w] |MB1 |MB | | |ingress::meta.nat_geneve_vni[15:0] |[-1r, 14w] |H61 |H | | |ingress::meta.icmp_recalc |[-1r, 14w] |W0 |W |[26] | |ingress::meta.icmp_csum |[-1r, 14w] |MH0 |MH | | |ingress::meta.body_checksum |[-1r, 14w] |MH1 |MH | | |ingress::meta.l4_length |[-1r, 14w] |H14 |H | | |ingress::meta.orig_src_mac[39:32] |[-1r, 14w] |MH10 |MH |[7:0] | |ingress::meta.orig_src_mac[47:40] |[-1r, 14w] |MH10 |MH |[15:8] | |ingress::meta.orig_src_mac[23:0] |[-1r, 14w] |W16 |W |[23:0] | |ingress::meta.orig_src_mac[31:24] |[-1r, 14w] |W16 |W |[31:24] | |ingress::meta.orig_src_ipv4 |[-1r, 14w] |MW0 |MW | | |ingress::meta.orig_dst_ipv4 |[-1r, 14w] |W8 |W | | |ingress::meta.nat_ingress_csum |[-1r, 14w] |H6 |H | | |ingress::hdr.sidecar.sc_code |[-1r, 14w] |H5 |H |[15:8] | |ingress::hdr.sidecar.sc_pad |[-1r, 14w] |H5 |H |[7:0] | |ingress::hdr.sidecar.sc_ingress[8:0] |[-1r, 14w] |H19 |H |[8:0] | |ingress::hdr.sidecar.sc_ingress[15:9] |[-1r, 14w] |H19 |H |[15:9] | |ingress::hdr.sidecar.sc_egress[8:0] |[-1r, 14w] |H18 |H |[8:0] | |ingress::hdr.sidecar.sc_egress[15:9] |[-1r, 14w] |H18 |H |[15:9] | |ingress::hdr.sidecar.sc_ether_type |[-1r, 14w] |MH16 |MH | | |ingress::hdr.sidecar.sc_payload[7:0] |[-1r, 14w] |MB9 |MB | | |ingress::hdr.sidecar.sc_payload[127:112] |[-1r, 14w] |MH12 |MH | | |ingress::hdr.sidecar.sc_payload[31:24] |[-1r, 14w] |B4 |B | | |ingress::hdr.sidecar.sc_payload[111:96] |[-1r, 14w] |H29 |H | | |ingress::hdr.sidecar.sc_payload[23:8] |[-1r, 14w] |H63 |H | | |ingress::hdr.sidecar.sc_payload[63:32] |[-1r, 14w] |W26 |W | | |ingress::hdr.sidecar.sc_payload[95:64] |[-1r, 14w] |W38 |W | | |ingress::hdr.vlan.pcp |[-1r, 14w] |H23 |H |[15:13] | |ingress::hdr.vlan.dei |[-1r, 14w] |H23 |H |[12] | |ingress::hdr.vlan.vlan_id |[-1r, 14w] |H23 |H |[11:0] | |ingress::hdr.vlan.ether_type |[-1r, 14w] |MH18 |MH | | |ingress::hdr.ipv4.version |[-1r, 14w] |H2 |H |[15:12] | |ingress::hdr.ipv4.ihl |[-1r, 14w] |H2 |H |[11:8] | |ingress::hdr.ipv4.diffserv |[-1r, 14w] |H2 |H |[7:0] | |ingress::hdr.ipv4.total_len |[-1r, 14w] |H13 |H | | |ingress::hdr.ipv4.identification |[-1r, 14w] |W12 |W |[31:16] | |ingress::hdr.ipv4.flags |[-1r, 14w] |W12 |W |[15:13] | |ingress::hdr.ipv4.frag_offset |[-1r, 14w] |W12 |W |[12:0] | |ingress::hdr.ipv4.ttl |[-1r, 14w] |B12 |B | | |ingress::hdr.ipv4.protocol |[-1r, 14w] |MB7 |MB | | |ingress::hdr.ipv4.hdr_checksum |[6w, 10r] |DH10 |DH | | |ingress::hdr.ipv4.hdr_checksum |[-1w, 6r] |H27 |H | | |ingress::hdr.ipv4.hdr_checksum |[10w, 14r] |H27 |H | | |ingress::hdr.ipv4.src_addr |[-1r, 14w] |W2 |W | | |ingress::hdr.ipv4.dst_addr |[-1r, 14w] |MW2 |MW | | |ingress::hdr.icmp.type |[-1r, 14w] |H0 |H |[15:8] | |ingress::hdr.icmp.code |[-1r, 14w] |H0 |H |[7:0] | |ingress::hdr.icmp.hdr_checksum |[-1r, 14w] |MH22 |MH | | |ingress::hdr.icmp.data[15:0] |[-1r, 14w] |MH3 |MH | | |ingress::hdr.icmp.data[31:16] |[-1r, 14w] |MH20 |MH | | |ingress::hdr.tcp.src_port |[-1r, 14w] |W3 |W |[31:16] | |ingress::hdr.tcp.dst_port |[-1r, 14w] |W3 |W |[15:0] | |ingress::hdr.tcp.seq_no |[-1r, 14w] |W37 |W | | |ingress::hdr.tcp.ack_no |[-1r, 14w] |W25 |W | | |ingress::hdr.tcp.data_offset |[-1r, 14w] |H0 |H |[15:12] | |ingress::hdr.tcp.res |[-1r, 14w] |H0 |H |[11:8] | |ingress::hdr.tcp.flags |[-1r, 14w] |H0 |H |[7:0] | |ingress::hdr.tcp.window |[-1r, 14w] |MH20 |MH | | |ingress::hdr.tcp.checksum |[-1r, 14w] |MH3 |MH | | |ingress::hdr.tcp.urgent_ptr |[-1r, 14w] |MH22 |MH | | |ingress::hdr.udp.src_port[5:0] |[-1r, 14w] |MH23 |MH |[5:0] | |ingress::hdr.udp.src_port[15:6] |[-1r, 14w] |MH23 |MH |[15:6] | |ingress::hdr.udp.dst_port |[-1r, 14w] |MH21 |MH | | |ingress::hdr.udp.hdr_length |[-1r, 14w] |H16 |H | | |ingress::hdr.udp.checksum |[-1r, 14w] |H3 |H | | |ingress::hdr.geneve.version |[-1r, 14w] |W5 |W |[31:30] | |ingress::hdr.geneve.opt_len |[-1r, 14w] |W5 |W |[29:24] | |ingress::hdr.geneve.ctrl |[-1r, 14w] |W5 |W |[23] | |ingress::hdr.geneve.crit |[-1r, 14w] |W5 |W |[22] | |ingress::hdr.geneve.reserved |[-1r, 14w] |W5 |W |[21:16] | |ingress::hdr.geneve.protocol |[-1r, 14w] |W5 |W |[15:0] | |ingress::hdr.geneve.vni[23:16] |[4w, 11r] |DB0 |DB | | |ingress::hdr.geneve.vni[15:0] |[4w, 11r] |DH20 |DH | | |ingress::hdr.geneve.vni[23:16] |[-1w, 4r] |B3 |B | | |ingress::hdr.geneve.vni[23:16] |[11w, 14r] |B3 |B | | |ingress::hdr.geneve.vni[15:0] |[-1w, 4r] |H62 |H | | |ingress::hdr.geneve.vni[15:0] |[11w, 14r] |H62 |H | | |ingress::hdr.geneve.reserved2 |[4w, 10r] |DB8 |DB | | |ingress::hdr.geneve.reserved2 |[-1w, 4r] |MB8 |MB | | |ingress::hdr.geneve.reserved2 |[10w, 14r] |MB8 |MB | | |ingress::hdr.inner_eth.dst_mac[31:16] |[4w, 11r] |DH8 |DH | | |ingress::hdr.inner_eth.dst_mac[47:32] |[4w, 7r] |DH11 |DH | | |ingress::hdr.inner_eth.dst_mac[15:0] |[4w, 7r] |DH22 |DH | | |ingress::hdr.inner_eth.dst_mac[31:16] |[-1w, 4r] |H24 |H | | |ingress::hdr.inner_eth.dst_mac[31:16] |[11w, 14r] |H24 |H | | |ingress::hdr.inner_eth.dst_mac[47:32] |[-1w, 4r] |H28 |H | | |ingress::hdr.inner_eth.dst_mac[47:32] |[7w, 14r] |H28 |H | | |ingress::hdr.inner_eth.dst_mac[15:0] |[-1w, 4r] |H67 |H | | |ingress::hdr.inner_eth.dst_mac[15:0] |[7w, 14r] |H67 |H | | |ingress::hdr.inner_eth.src_mac[15:0] |[4w, 10r] |DH5 |DH | | |ingress::hdr.inner_eth.src_mac[31:16] |[4w, 10r] |DH21 |DH | | |ingress::hdr.inner_eth.src_mac[47:32] |[-1r, 14w] |MH15 |MH | | |ingress::hdr.inner_eth.src_mac[15:0] |[-1w, 4r] |H22 |H | | |ingress::hdr.inner_eth.src_mac[15:0] |[10w, 14r] |H22 |H | | |ingress::hdr.inner_eth.src_mac[31:16] |[-1w, 4r] |H66 |H | | |ingress::hdr.inner_eth.src_mac[31:16] |[10w, 14r] |H66 |H | | |ingress::hdr.inner_eth.ether_type |[-1r, 14w] |MH19 |MH | | |ingress::hdr.inner_ipv4.version |[-1r, 14w] |H1 |H |[15:12] | |ingress::hdr.inner_ipv4.ihl |[-1r, 14w] |H1 |H |[11:8] | |ingress::hdr.inner_ipv4.diffserv |[-1r, 14w] |H1 |H |[7:0] | |ingress::hdr.inner_ipv4.total_len |[-1r, 14w] |H12 |H | | |ingress::hdr.inner_ipv4.identification |[-1r, 14w] |W13 |W |[31:16] | |ingress::hdr.inner_ipv4.flags |[-1r, 14w] |W13 |W |[15:13] | |ingress::hdr.inner_ipv4.frag_offset |[-1r, 14w] |W13 |W |[12:0] | |ingress::hdr.inner_ipv4.ttl |[-1r, 14w] |MB4 |MB | | |ingress::hdr.inner_ipv4.protocol |[-1r, 14w] |MB6 |MB | | |ingress::hdr.inner_ipv4.hdr_checksum |[5w, 10r] |DH9 |DH | | |ingress::hdr.inner_ipv4.hdr_checksum |[-1w, 5r] |H26 |H | | |ingress::hdr.inner_ipv4.hdr_checksum |[10w, 14r] |H26 |H | | |ingress::hdr.inner_ipv4.src_addr |[-1r, 14w] |MW3 |MW | | |ingress::hdr.inner_ipv4.dst_addr |[-1r, 14w] |MW1 |MW | | |ingress::hdr.inner_tcp.src_port |[-1r, 14w] |W3 |W |[31:16] | |ingress::hdr.inner_tcp.dst_port |[-1r, 14w] |W3 |W |[15:0] | |ingress::hdr.inner_tcp.seq_no |[-1r, 14w] |W37 |W | | |ingress::hdr.inner_tcp.ack_no |[-1r, 14w] |W25 |W | | |ingress::hdr.inner_tcp.data_offset |[-1r, 14w] |H0 |H |[15:12] | |ingress::hdr.inner_tcp.res |[-1r, 14w] |H0 |H |[11:8] | |ingress::hdr.inner_tcp.flags |[-1r, 14w] |H0 |H |[7:0] | |ingress::hdr.inner_tcp.window |[-1r, 14w] |MH20 |MH | | |ingress::hdr.inner_tcp.checksum |[-1r, 14w] |MH3 |MH | | |ingress::hdr.inner_tcp.urgent_ptr |[-1r, 14w] |MH22 |MH | | |ingress::hdr.inner_udp.src_port[5:0] |[-1r, 14w] |MH22 |MH |[5:0] | |ingress::hdr.inner_udp.src_port[15:6] |[-1r, 14w] |MH22 |MH |[15:6] | |ingress::hdr.inner_udp.dst_port |[-1r, 14w] |MH20 |MH | | |ingress::hdr.inner_udp.hdr_length |[5w, 10r] |DH4 |DH | | |ingress::hdr.inner_udp.hdr_length |[-1w, 5r] |H15 |H | | |ingress::hdr.inner_udp.hdr_length |[10w, 14r] |H15 |H | | |ingress::hdr.inner_udp.checksum |[-1r, 14w] |MH3 |MH | | |ingress::hdr.inner_icmp.type |[-1r, 14w] |H0 |H |[15:8] | |ingress::hdr.inner_icmp.code |[-1r, 14w] |H0 |H |[7:0] | |ingress::hdr.inner_icmp.hdr_checksum |[-1r, 14w] |MH22 |MH | | |ingress::hdr.inner_icmp.data[15:0] |[-1r, 14w] |MH3 |MH | | |ingress::hdr.inner_icmp.data[31:16] |[-1r, 14w] |MH20 |MH | | |ingress::hdr.inner_ipv6.version |[-1r, 14w] |W13 |W |[31:28] | |ingress::hdr.inner_ipv6.traffic_class |[-1r, 14w] |W13 |W |[27:20] | |ingress::hdr.inner_ipv6.flow_label |[-1r, 14w] |W13 |W |[19:0] | |ingress::hdr.inner_ipv6.payload_len |[-1r, 14w] |H12 |H | | |ingress::hdr.inner_ipv6.next_hdr |[-1r, 14w] |MB6 |MB | | |ingress::hdr.inner_ipv6.hop_limit |[-1r, 14w] |MB4 |MB | | |ingress::hdr.inner_ipv6.src_addr[31:0] |[-1r, 14w] |MW3 |MW | | |ingress::hdr.inner_ipv6.src_addr[63:32] |[-1r, 14w] |MW5 |MW | | |ingress::hdr.inner_ipv6.src_addr[95:64] |[-1r, 14w] |MW9 |MW | | |ingress::hdr.inner_ipv6.src_addr[127:96] |[-1r, 14w] |MW13 |MW | | |ingress::hdr.inner_ipv6.dst_addr[31:0] |[-1r, 14w] |MW1 |MW | | |ingress::hdr.inner_ipv6.dst_addr[63:32] |[-1r, 14w] |MW4 |MW | | |ingress::hdr.inner_ipv6.dst_addr[95:64] |[-1r, 14w] |MW8 |MW | | |ingress::hdr.inner_ipv6.dst_addr[127:96] |[-1r, 14w] |MW12 |MW | | |ingress::hdr.geneve_opts.oxg_ext_tag.class |[-1r, 14w] |W1 |W |[31:16] | |ingress::hdr.geneve_opts.oxg_ext_tag.crit |[-1r, 14w] |W1 |W |[15] | |ingress::hdr.geneve_opts.oxg_ext_tag.type |[-1r, 14w] |W1 |W |[14:8] | |ingress::hdr.geneve_opts.oxg_ext_tag.reserved |[-1r, 14w] |W1 |W |[7:5] | |ingress::hdr.geneve_opts.oxg_ext_tag.opt_len |[-1r, 14w] |W1 |W |[4:0] | |ingress::hdr.ipv6.version |[-1r, 14w] |W14 |W |[31:28] | |ingress::hdr.ipv6.traffic_class |[-1r, 14w] |W14 |W |[27:20] | |ingress::hdr.ipv6.flow_label |[-1r, 14w] |W14 |W |[19:0] | |ingress::hdr.ipv6.payload_len |[-1r, 14w] |H13 |H | | |ingress::hdr.ipv6.next_hdr |[-1r, 14w] |MB7 |MB | | |ingress::hdr.ipv6.hop_limit |[-1r, 14w] |B12 |B | | |ingress::hdr.ipv6.src_addr[31:0] |[-1r, 14w] |MW2 |MW | | |ingress::hdr.ipv6.src_addr[63:32] |[-1r, 14w] |MW6 |MW | | |ingress::hdr.ipv6.src_addr[95:64] |[-1r, 14w] |MW10 |MW | | |ingress::hdr.ipv6.src_addr[127:96] |[-1r, 14w] |MW14 |MW | | |ingress::hdr.ipv6.dst_addr[95:64] |[6w, 11r] |DW8 |DW | | |ingress::hdr.ipv6.dst_addr[127:96] |[6w, 11r] |DW12 |DW | | |ingress::hdr.ipv6.dst_addr[31:0] |[-1r, 14w] |W2 |W | | |ingress::hdr.ipv6.dst_addr[63:32] |[-1r, 14w] |W12 |W | | |ingress::hdr.ipv6.dst_addr[95:64] |[-1w, 6r] |W24 |W | | |ingress::hdr.ipv6.dst_addr[95:64] |[11w, 14r] |W24 |W | | |ingress::hdr.ipv6.dst_addr[127:96] |[-1w, 6r] |W36 |W | | |ingress::hdr.ipv6.dst_addr[127:96] |[11w, 14r] |W36 |W | | |ingress::ig_intr_md_for_tm.ucast_egress_port |[-1r, 14w] |H17 |H |[8:0] | |ingress::ig_intr_md_for_tm.bypass_egress |[-1r, 14w] |B1 |B |[3] | |ingress::ig_intr_md_for_tm.ucast_egress_port.$valid |[-1r, 14w] |W0 |W |[1] | |ingress::l3_router_Router4_fwd.nexthop[31:24] |[-1r, 14w] |MB3 |MB | | |ingress::l3_router_Router4_fwd.nexthop[7:0] |[-1r, 14w] |MB11 |MB | | |ingress::l3_router_Router4_fwd.nexthop[23:8] |[4w, 10r] |H66 |H | | |ingress::l3_router_Router4_fwd.nexthop6[31:24] |[-1r, 14w] |MB2 |MB | | |ingress::l3_router_Router4_fwd.nexthop6[7:0] |[4w, 10r] |MB8 |MB | | |ingress::l3_router_Router4_fwd.nexthop6[127:112] |[-1r, 14w] |MH14 |MH | | |ingress::l3_router_Router4_fwd.nexthop6[111:96] |[5w, 10r] |H26 |H | | |ingress::l3_router_Router4_fwd.nexthop6[23:8] |[-1r, 14w] |H64 |H | | |ingress::l3_router_Router4_fwd.nexthop6[63:32] |[-1r, 14w] |W28 |W | | |ingress::l3_router_Router4_fwd.nexthop6[95:64] |[-1r, 14w] |W40 |W | | |ingress::l3_router_Router4_fwd.port |[5w, 10r] |H15 |H |[8:0] | |ingress::l3_router_Router4_fwd.is_hit |[-1r, 14w] |H17 |H |[9] | |ingress::l3_router_Router4_fwd.ecmp_hash[7:6] |[4w, 7r] |H28 |H |[1:0] | |ingress::l3_router_Router4_fwd.ecmp_hash[5:0] |[-1r, 14w] |H61 |H |[5:0] | |ingress::l3_router_Router4_fwd.idx[7:0] |[-1r, 14w] |H20 |H |[7:0] | |ingress::l3_router_Router4_fwd.idx[15:8] |[-1r, 14w] |H20 |H |[15:8] | |ingress::l3_router_Router4_fwd.slots |[0w, 7r] |H4 |H |[7:0] | |ingress::l3_router_Router4_fwd.slot[7:0] |[-1r, 14w] |MH6 |MH |[7:0] | |ingress::l3_router_Router4_fwd.slot[15:8] |[-1r, 14w] |MH6 |MH |[15:8] | |ingress::l3_router_Router6_fwd.nexthop[31:24] |[-1r, 14w] |MB2 |MB | | |ingress::l3_router_Router6_fwd.nexthop[7:0] |[-1r, 14w] |MB11 |MB | | |ingress::l3_router_Router6_fwd.nexthop[127:112] |[-1r, 14w] |MH14 |MH | | |ingress::l3_router_Router6_fwd.nexthop[111:96] |[6w, 10r] |H27 |H | | |ingress::l3_router_Router6_fwd.nexthop[23:8] |[-1r, 14w] |H64 |H | | |ingress::l3_router_Router6_fwd.nexthop[63:32] |[-1r, 14w] |W28 |W | | |ingress::l3_router_Router6_fwd.nexthop[95:64] |[-1r, 14w] |W40 |W | | |ingress::l3_router_Router6_fwd.port |[4w, 10r] |H22 |H |[8:0] | |ingress::l3_router_Router6_fwd.is_hit |[-1r, 14w] |H17 |H |[9] | |ingress::l3_router_Router6_fwd.ecmp_hash[5:0] |[-1r, 14w] |H61 |H |[5:0] | |ingress::l3_router_Router6_fwd.ecmp_hash[7:6] |[4w, 7r] |H67 |H |[1:0] | |ingress::l3_router_Router6_fwd.idx[7:0] |[-1r, 14w] |H20 |H |[7:0] | |ingress::l3_router_Router6_fwd.idx[15:8] |[-1r, 14w] |H20 |H |[15:8] | |ingress::l3_router_Router6_fwd.slots |[-1r, 14w] |MB3 |MB | | |ingress::l3_router_Router6_fwd.slot[7:0] |[-1r, 14w] |MH6 |MH |[7:0] | |ingress::l3_router_Router6_fwd.slot[15:8] |[-1r, 14w] |MH6 |MH |[15:8] | |ingress::ig_intr_md_for_dprsr.drop_ctl |[-1r, 14w] |B1 |B |[6:4] | |ingress::ig_intr_md_for_dprsr.mirror_type |[-1r, 14w] |MB5 |MB |[3:0] | |ingress::ig_intr_md_for_dprsr.drop_ctl.$valid |[-1r, 14w] |W0 |W |[2] | |ingress::ig_intr_md_for_tm.bypass_egress.$valid |[-1r, 14w] |W0 |W |[3] | |ingress::hdr.udp.checksum.$deparse_original_csum |[-1r, 14w] |B2 |B |[0] | |ingress::hdr.udp.checksum.$deparse_updated_csum_0 |[-1r, 14w] |B2 |B |[1] | |ingress::hdr.udp.checksum.$deparse_updated_csum_1 |[-1r, 14w] |B2 |B |[2] | |ingress::hdr.udp.checksum.$deparse_updated_csum_2 |[-1r, 14w] |B2 |B |[3] | |ingress::hdr.udp.checksum.$deparse_updated_csum_3 |[-1r, 14w] |B2 |B |[4] | |ingress::hdr.icmp.hdr_checksum.$deparse_original_csum |[-1r, 14w] |B1 |B |[1] | |ingress::hdr.icmp.hdr_checksum.$deparse_updated_csum_0 |[-1r, 14w] |B1 |B |[2] | |ingress::$tmp3 |[-1r, 14w] |B0 |B | | |egress::eg_intr_md_for_dprsr.mirror_io_select |[-1r, 14w] |MB0 |MB |[3] | |egress::eg_intr_md_for_dprsr.mirror_io_select.$valid |[-1r, 14w] |MH5 |MH |[0] | |egress::eg_intr_md.egress_port |[-1r, 14w] |MH8 |MH |[8:0] | |egress::eg_intr_md.egress_port.$valid |[-1r, 14w] |MH5 |MH |[1] | |ingress::meta.bridge_hdr.$valid |[-1r, 14w] |W0 |W |[4] | |ingress::hdr.ethernet.$valid |[-1r, 14w] |W0 |W |[5] | |ingress::hdr.sidecar.$valid |[-1r, 14w] |W0 |W |[6] | |ingress::hdr.vlan.$valid |[-1r, 14w] |B1 |B |[0] | |ingress::hdr.ipv4.$valid |[-1r, 14w] |W0 |W |[7] | |ingress::hdr.icmp.$valid |[-1r, 14w] |W0 |W |[8] | |ingress::hdr.tcp.$valid |[-1r, 14w] |W0 |W |[9] | |ingress::hdr.udp.$valid |[-1r, 14w] |W0 |W |[10] | |ingress::hdr.geneve.$valid |[-1r, 14w] |W0 |W |[11] | |ingress::hdr.inner_eth.$valid |[-1r, 14w] |W0 |W |[12] | |ingress::hdr.inner_ipv4.$valid |[-1r, 14w] |W0 |W |[13] | |ingress::hdr.inner_tcp.$valid |[-1r, 14w] |W0 |W |[14] | |ingress::hdr.inner_udp.$valid |[-1r, 14w] |W0 |W |[15] | |ingress::hdr.inner_icmp.$valid |[-1r, 14w] |W0 |W |[16] | |ingress::hdr.inner_ipv6.$valid |[-1r, 14w] |W0 |W |[17] | |ingress::hdr.geneve_opts.oxg_ext_tag.$valid |[-1r, 14w] |W0 |W |[18] | |ingress::hdr.geneve_opts.oxg_mcast_tag.$valid |[-1r, 14w] |W0 |W |[19] | |ingress::hdr.geneve_opts.oxg_mcast.$valid |[-1r, 14w] |W0 |W |[20] | |ingress::hdr.geneve_opts.oxg_mss_tag.$valid |[-1r, 14w] |W0 |W |[21] | |ingress::hdr.geneve_opts.oxg_mss.$valid |[-1r, 14w] |W0 |W |[22] | |ingress::hdr.ipv6.$valid |[-1r, 14w] |W0 |W |[23] | |ingress::hdr.arp.$valid |[-1r, 14w] |W0 |W |[24] | |egress::hdr.ethernet.$valid |[-1r, 14w] |MH5 |MH |[2] | |egress::hdr.vlan.$valid |[-1r, 14w] |MH5 |MH |[3] | |egress::hdr.ipv4.$valid |[-1r, 14w] |MH5 |MH |[4] | |egress::hdr.icmp.$valid |[-1r, 14w] |MH5 |MH |[5] | |egress::hdr.udp.$valid |[-1r, 14w] |MH5 |MH |[6] | |egress::hdr.geneve.$valid |[-1r, 14w] |MH5 |MH |[7] | |egress::hdr.inner_eth.$valid |[-1r, 14w] |MH5 |MH |[8] | |egress::hdr.inner_ipv4.$valid |[-1r, 14w] |MH5 |MH |[9] | |egress::hdr.inner_tcp.$valid |[-1r, 14w] |MH5 |MH |[10] | |egress::hdr.inner_udp.$valid |[-1r, 14w] |MH5 |MH |[11] | |egress::hdr.inner_ipv6.$valid |[-1r, 14w] |MH5 |MH |[12] | |egress::hdr.geneve_opts.oxg_ext_tag.$valid |[-1r, 14w] |MH5 |MH |[13] | |egress::hdr.geneve_opts.oxg_mcast_tag.$valid |[-1r, 14w] |MH5 |MH |[14] | |egress::hdr.geneve_opts.oxg_mcast.$valid |[-1r, 14w] |MH5 |MH |[15] | |egress::hdr.geneve_opts.oxg_mss_tag.$valid |[-1r, 14w] |MB0 |MB |[0] | |egress::hdr.geneve_opts.oxg_mss.$valid |[-1r, 14w] |MB0 |MB |[1] | |egress::hdr.ipv6.$valid |[-1r, 14w] |MB0 |MB |[2] | +--------------------------------------------------------+------------+-----------+----------------+-----------------+ PHV Allocation State MAU Groups: +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | Container Set | Containers Used | Bits Used | Bits Used on Ingress | Bits Used on Egress | Bits Allocated | Bits Allocated on Ingress | Bits Allocated on Egress | Available Bits | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | B0-11 | 6 ( 50 %) | 48 ( 50 %) | 48 ( 50 %) | 0 ( 0 %) | 64 ( 66.7 %) | 64 ( 66.7 %) | 0 ( 0 %) | 96 | | MB0-3 | 4 ( 100 %) | 28 ( 87.5 %) | 24 ( 75 %) | 4 ( 12.5 %) | 44 ( 138 %) | 40 ( 125 %) | 4 ( 12.5 %) | 32 | | DB0-3 | 1 ( 25 %) | 8 ( 25 %) | 8 ( 25 %) | 0 ( 0 %) | 8 ( 25 %) | 8 ( 25 %) | 0 ( 0 %) | 32 | | | | | | | | | | | | Usage for Group 1 | 11 ( 55 %) | 84 ( 52.5 %) | 80 ( 50 %) | 4 ( 2.5 %) | 116 ( 72.5 %) | 112 ( 70 %) | 4 ( 2.5 %) | 160 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | B12-23 | 1 ( 8.33 %) | 8 ( 8.33 %) | 8 ( 8.33 %) | 0 ( 0 %) | 16 ( 16.7 %) | 16 ( 16.7 %) | 0 ( 0 %) | 96 | | MB4-7 | 4 ( 100 %) | 28 ( 87.5 %) | 28 ( 87.5 %) | 0 ( 0 %) | 52 ( 162 %) | 52 ( 162 %) | 0 ( 0 %) | 32 | | DB4-7 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 | | | | | | | | | | | | Usage for Group 2 | 5 ( 25 %) | 36 ( 22.5 %) | 36 ( 22.5 %) | 0 ( 0 %) | 68 ( 42.5 %) | 68 ( 42.5 %) | 0 ( 0 %) | 160 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | B24-35 | 1 ( 8.33 %) | 8 ( 8.33 %) | 8 ( 8.33 %) | 0 ( 0 %) | 8 ( 8.33 %) | 8 ( 8.33 %) | 0 ( 0 %) | 96 | | MB8-11 | 4 ( 100 %) | 32 ( 100 %) | 32 ( 100 %) | 0 ( 0 %) | 56 ( 175 %) | 56 ( 175 %) | 0 ( 0 %) | 32 | | DB8-11 | 1 ( 25 %) | 8 ( 25 %) | 8 ( 25 %) | 0 ( 0 %) | 8 ( 25 %) | 8 ( 25 %) | 0 ( 0 %) | 32 | | | | | | | | | | | | Usage for Group 3 | 6 ( 30 %) | 48 ( 30 %) | 48 ( 30 %) | 0 ( 0 %) | 72 ( 45 %) | 72 ( 45 %) | 0 ( 0 %) | 160 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | B36-47 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 96 | | MB12-15 | 1 ( 25 %) | 8 ( 25 %) | 8 ( 25 %) | 0 ( 0 %) | 8 ( 25 %) | 8 ( 25 %) | 0 ( 0 %) | 32 | | DB12-15 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 32 | | | | | | | | | | | | Usage for Group 4 | 1 ( 5 %) | 8 ( 5 %) | 8 ( 5 %) | 0 ( 0 %) | 8 ( 5 %) | 8 ( 5 %) | 0 ( 0 %) | 160 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | H0-11 | 8 ( 66.7 %) | 128 ( 66.7 %) | 128 ( 66.7 %) | 0 ( 0 %) | 193 ( 101 %) | 193 ( 101 %) | 0 ( 0 %) | 192 | | MH0-3 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 128 ( 200 %) | 128 ( 200 %) | 0 ( 0 %) | 64 | | DH0-3 | 1 ( 25 %) | 9 ( 14.1 %) | 9 ( 14.1 %) | 0 ( 0 %) | 9 ( 14.1 %) | 9 ( 14.1 %) | 0 ( 0 %) | 64 | | | | | | | | | | | | Usage for Group 5 | 13 ( 65 %) | 201 ( 62.8 %) | 201 ( 62.8 %) | 0 ( 0 %) | 330 ( 103 %) | 330 ( 103 %) | 0 ( 0 %) | 320 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | H12-23 | 12 ( 100 %) | 179 ( 93.2 %) | 179 ( 93.2 %) | 0 ( 0 %) | 278 ( 145 %) | 278 ( 145 %) | 0 ( 0 %) | 192 | | MH4-7 | 4 ( 100 %) | 49 ( 76.6 %) | 33 ( 51.6 %) | 16 ( 25 %) | 65 ( 102 %) | 49 ( 76.6 %) | 16 ( 25 %) | 64 | | DH4-7 | 2 ( 50 %) | 32 ( 50 %) | 32 ( 50 %) | 0 ( 0 %) | 32 ( 50 %) | 32 ( 50 %) | 0 ( 0 %) | 64 | | | | | | | | | | | | Usage for Group 6 | 18 ( 90 %) | 260 ( 81.2 %) | 244 ( 76.2 %) | 16 ( 5 %) | 375 ( 117 %) | 359 ( 112 %) | 16 ( 5 %) | 320 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | H24-35 | 6 ( 50 %) | 96 ( 50 %) | 96 ( 50 %) | 0 ( 0 %) | 210 ( 109 %) | 210 ( 109 %) | 0 ( 0 %) | 192 | | MH8-11 | 4 ( 100 %) | 57 ( 89.1 %) | 48 ( 75 %) | 9 ( 14.1 %) | 57 ( 89.1 %) | 48 ( 75 %) | 9 ( 14.1 %) | 64 | | DH8-11 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 | | | | | | | | | | | | Usage for Group 7 | 14 ( 70 %) | 217 ( 67.8 %) | 208 ( 65 %) | 9 ( 2.81 %) | 331 ( 103 %) | 322 ( 101 %) | 9 ( 2.81 %) | 320 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | H36-47 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 192 | | MH12-15 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 80 ( 125 %) | 80 ( 125 %) | 0 ( 0 %) | 64 | | DH12-15 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 64 | | | | | | | | | | | | Usage for Group 8 | 4 ( 20 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 80 ( 25 %) | 80 ( 25 %) | 0 ( 0 %) | 320 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | H48-59 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 192 | | MH16-19 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 64 | | DH16-19 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 64 | | | | | | | | | | | | Usage for Group 9 | 4 ( 20 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 64 ( 20 %) | 64 ( 20 %) | 0 ( 0 %) | 320 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | H60-71 | 8 ( 66.7 %) | 128 ( 66.7 %) | 128 ( 66.7 %) | 0 ( 0 %) | 254 ( 132 %) | 254 ( 132 %) | 0 ( 0 %) | 192 | | MH20-23 | 4 ( 100 %) | 64 ( 100 %) | 64 ( 100 %) | 0 ( 0 %) | 192 ( 300 %) | 192 ( 300 %) | 0 ( 0 %) | 64 | | DH20-23 | 3 ( 75 %) | 48 ( 75 %) | 48 ( 75 %) | 0 ( 0 %) | 48 ( 75 %) | 48 ( 75 %) | 0 ( 0 %) | 64 | | | | | | | | | | | | Usage for Group 10 | 15 ( 75 %) | 240 ( 75 %) | 240 ( 75 %) | 0 ( 0 %) | 494 ( 154 %) | 494 ( 154 %) | 0 ( 0 %) | 320 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | W0-11 | 8 ( 66.7 %) | 252 ( 65.6 %) | 252 ( 65.6 %) | 0 ( 0 %) | 316 ( 82.3 %) | 316 ( 82.3 %) | 0 ( 0 %) | 384 | | MW0-3 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 224 ( 175 %) | 224 ( 175 %) | 0 ( 0 %) | 128 | | DW0-3 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 128 | | | | | | | | | | | | Usage for Group 11 | 12 ( 60 %) | 380 ( 59.4 %) | 380 ( 59.4 %) | 0 ( 0 %) | 540 ( 84.4 %) | 540 ( 84.4 %) | 0 ( 0 %) | 640 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | W12-23 | 5 ( 41.7 %) | 160 ( 41.7 %) | 160 ( 41.7 %) | 0 ( 0 %) | 224 ( 58.3 %) | 224 ( 58.3 %) | 0 ( 0 %) | 384 | | MW4-7 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 | | DW4-7 | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 0 ( 0 %) | 128 | | | | | | | | | | | | Usage for Group 12 | 9 ( 45 %) | 288 ( 45 %) | 288 ( 45 %) | 0 ( 0 %) | 352 ( 55 %) | 352 ( 55 %) | 0 ( 0 %) | 640 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | W24-35 | 4 ( 33.3 %) | 128 ( 33.3 %) | 128 ( 33.3 %) | 0 ( 0 %) | 257 ( 66.9 %) | 257 ( 66.9 %) | 0 ( 0 %) | 384 | | MW8-11 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 | | DW8-11 | 1 ( 25 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 128 | | | | | | | | | | | | Usage for Group 13 | 9 ( 45 %) | 288 ( 45 %) | 288 ( 45 %) | 0 ( 0 %) | 417 ( 65.2 %) | 417 ( 65.2 %) | 0 ( 0 %) | 640 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | W36-47 | 4 ( 33.3 %) | 128 ( 33.3 %) | 128 ( 33.3 %) | 0 ( 0 %) | 269 ( 70.1 %) | 269 ( 70.1 %) | 0 ( 0 %) | 384 | | MW12-15 | 4 ( 100 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 ( 100 %) | 128 ( 100 %) | 0 ( 0 %) | 128 | | DW12-15 | 1 ( 25 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 32 ( 25 %) | 32 ( 25 %) | 0 ( 0 %) | 128 | | | | | | | | | | | | Usage for Group 14 | 9 ( 45 %) | 288 ( 45 %) | 288 ( 45 %) | 0 ( 0 %) | 429 ( 67 %) | 429 ( 67 %) | 0 ( 0 %) | 640 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | Usage for 8b | 23 ( 28.8 %) | 176 ( 27.5 %) | 172 ( 26.9 %) | 4 ( 0.625%) | 264 ( 41.2 %) | 260 ( 40.6 %) | 4 ( 0.625%) | 640 | | Usage for 16b | 68 ( 56.7 %) | 1046 ( 54.5 %) | 1021 ( 53.2 %) | 25 ( 1.3 %) | 1674 ( 87.2 %) | 1649 ( 85.9 %) | 25 ( 1.3 %) | 1920 | | Usage for 32b | 39 ( 48.8 %) | 1244 ( 48.6 %) | 1244 ( 48.6 %) | 0 ( 0 %) | 1738 ( 67.9 %) | 1738 ( 67.9 %) | 0 ( 0 %) | 2560 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | Usage for dark | 14 ( 25 %) | 233 ( 22.8 %) | 233 ( 22.8 %) | 0 ( 0 %) | 233 ( 22.8 %) | 233 ( 22.8 %) | 0 ( 0 %) | 1024 | | Usage for mocha | 53 ( 94.6 %) | 970 ( 94.7 %) | 941 ( 91.9 %) | 29 ( 2.83 %) | 1354 ( 132 %) | 1325 ( 129 %) | 29 ( 2.83 %) | 1024 | | Usage for normal | 63 ( 37.5 %) | 1263 ( 41.1 %) | 1263 ( 41.1 %) | 0 ( 0 %) | 2089 ( 68 %) | 2089 ( 68 %) | 0 ( 0 %) | 3072 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+ | Overall PHV Usage | 130 ( 46.4 %) | 2466 ( 48.2 %) | 2437 ( 47.6 %) | 29 ( 0.566%) | 3676 ( 71.8 %) | 3647 ( 71.2 %) | 29 ( 0.566%) | 5120 | +--------------------+-----------------+----------------+----------------------+---------------------+----------------+---------------------------+--------------------------+----------------+