Max level shown:
1 +---------------------------------------------------------------------+
2 | Log file: mau.resources.log |
3 | Compiler version: 9.13.4 |
4 | Created on: Thu Oct 22 16:22:13 2026 |
5 | Run ID: 10fe22fc054f48d1 |
6 +---------------------------------------------------------------------+
7 
8 
9 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
10 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
11 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
12 | 0 | 35 | 6 | 35 | 2 | 15 | 6 | 4 | 2 | 7 | 0 | 2 | 0 | 14 | 4 | 6 | 2 | 0 | 0 | 0 | 16 |
13 | 1 | 55 | 56 | 85 | 2 | 11 | 30 | 8 | 16 | 5 | 0 | 4 | 0 | 10 | 6 | 6 | 87 | 0 | 0 | 0 | 14 |
14 | 2 | 27 | 20 | 100 | 0 | 5 | 48 | 11 | 20 | 8 | 0 | 4 | 0 | 6 | 4 | 2 | 85 | 0 | 0 | 0 | 8 |
15 | 3 | 11 | 11 | 27 | 3 | 5 | 17 | 9 | 11 | 4 | 0 | 4 | 0 | 4 | 3 | 3 | 27 | 0 | 0 | 0 | 6 |
16 | 4 | 16 | 0 | 38 | 2 | 12 | 11 | 8 | 0 | 5 | 0 | 4 | 0 | 10 | 7 | 9 | 21 | 0 | 0 | 0 | 15 |
17 | 5 | 7 | 0 | 9 | 1 | 7 | 10 | 6 | 0 | 2 | 0 | 3 | 0 | 7 | 3 | 7 | 56 | 0 | 0 | 0 | 11 |
18 | 6 | 9 | 43 | 1 | 0 | 8 | 10 | 6 | 18 | 14 | 0 | 3 | 0 | 8 | 0 | 9 | 38 | 0 | 0 | 0 | 11 |
19 | 7 | 22 | 0 | 53 | 1 | 1 | 15 | 3 | 0 | 2 | 0 | 1 | 0 | 2 | 1 | 1 | 12 | 0 | 0 | 0 | 1 |
20 | 8 | 2 | 7 | 0 | 0 | 2 | 1 | 0 | 2 | 4 | 0 | 0 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 3 |
21 | 9 | 2 | 0 | 10 | 0 | 1 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | 1 | 1 | 0 | 12 | 0 | 0 | 0 | 1 |
22 | 10 | 4 | 20 | 0 | 0 | 8 | 11 | 7 | 22 | 4 | 0 | 2 | 0 | 8 | 1 | 6 | 11 | 0 | 0 | 0 | 10 |
23 | 11 | 29 | 16 | 130 | 0 | 5 | 27 | 9 | 24 | 8 | 0 | 3 | 0 | 7 | 4 | 9 | 29 | 0 | 0 | 0 | 13 |
24 | 12 | 0 | 16 | 0 | 0 | 0 | 8 | 3 | 21 | 5 | 0 | 1 | 0 | 0 | 0 | 6 | 70 | 0 | 0 | 0 | 6 |
25 | 13 | 7 | 0 | 120 | 0 | 2 | 33 | 5 | 0 | 6 | 0 | 1 | 0 | 4 | 2 | 1 | 26 | 0 | 0 | 0 | 3 |
26 | 14 | 3 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | 1 | 0 | 5 | 32 | 0 | 0 | 0 | 5 |
27 | 15 | 4 | 0 | 80 | 0 | 0 | 29 | 5 | 0 | 2 | 0 | 1 | 0 | 1 | 1 | 0 | 24 | 0 | 0 | 0 | 1 |
28 | 16 | 3 | 0 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | 1 | 0 | 4 | 32 | 0 | 0 | 0 | 4 |
29 | 17 | 21 | 0 | 80 | 0 | 2 | 24 | 6 | 0 | 4 | 0 | 2 | 0 | 3 | 2 | 1 | 32 | 0 | 0 | 0 | 3 |
30 | 18 | 7 | 0 | 27 | 2 | 6 | 8 | 6 | 0 | 3 | 0 | 3 | 0 | 6 | 3 | 4 | 8 | 0 | 0 | 0 | 6 |
31 | | | | | | | | | | | | | | | | | | | | | |
32 | Totals | 264 | 195 | 795 | 13 | 92 | 294 | 96 | 136 | 96 | 0 | 38 | 0 | 95 | 42 | 80 | 604 | 0 | 0 | 0 | 137 |
33 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
34 
35 
36 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
37 | Stage Number | Exact Match Input xbar | Ternary Match Input xbar | Hash Bit | Hash Dist Unit | Gateway | SRAM | Map RAM | TCAM | VLIW Instr | Meter ALU | Stats ALU | Stash | Exact Match Search Bus | Exact Match Result Bus | Tind Result Bus | Action Data Bus Bytes | 8-bit Action Slots | 16-bit Action Slots | 32-bit Action Slots | Logical TableID |
38 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
39 | 0 | 27.34% | 9.09% | 8.41% | 33.33% | 93.75% | 7.50% | 8.33% | 8.33% | 21.88% | 0.00% | 50.00% | 0.00% | 87.50% | 25.00% | 37.50% | 1.56% | 0.00% | 0.00% | 0.00% | 100.00% |
40 | 1 | 42.97% | 84.85% | 20.43% | 33.33% | 68.75% | 37.50% | 16.67% | 66.67% | 15.62% | 0.00% | 100.00% | 0.00% | 62.50% | 37.50% | 37.50% | 67.97% | 0.00% | 0.00% | 0.00% | 87.50% |
41 | 2 | 21.09% | 30.30% | 24.04% | 0.00% | 31.25% | 60.00% | 22.92% | 83.33% | 25.00% | 0.00% | 100.00% | 0.00% | 37.50% | 25.00% | 12.50% | 66.41% | 0.00% | 0.00% | 0.00% | 50.00% |
42 | 3 | 8.59% | 16.67% | 6.49% | 50.00% | 31.25% | 21.25% | 18.75% | 45.83% | 12.50% | 0.00% | 100.00% | 0.00% | 25.00% | 18.75% | 18.75% | 21.09% | 0.00% | 0.00% | 0.00% | 37.50% |
43 | 4 | 12.50% | 0.00% | 9.13% | 33.33% | 75.00% | 13.75% | 16.67% | 0.00% | 15.62% | 0.00% | 100.00% | 0.00% | 62.50% | 43.75% | 56.25% | 16.41% | 0.00% | 0.00% | 0.00% | 93.75% |
44 | 5 | 5.47% | 0.00% | 2.16% | 16.67% | 43.75% | 12.50% | 12.50% | 0.00% | 6.25% | 0.00% | 75.00% | 0.00% | 43.75% | 18.75% | 43.75% | 43.75% | 0.00% | 0.00% | 0.00% | 68.75% |
45 | 6 | 7.03% | 65.15% | 0.24% | 0.00% | 50.00% | 12.50% | 12.50% | 75.00% | 43.75% | 0.00% | 75.00% | 0.00% | 50.00% | 0.00% | 56.25% | 29.69% | 0.00% | 0.00% | 0.00% | 68.75% |
46 | 7 | 17.19% | 0.00% | 12.74% | 16.67% | 6.25% | 18.75% | 6.25% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 12.50% | 6.25% | 6.25% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% |
47 | 8 | 1.56% | 10.61% | 0.00% | 0.00% | 12.50% | 1.25% | 0.00% | 8.33% | 12.50% | 0.00% | 0.00% | 0.00% | 12.50% | 0.00% | 6.25% | 0.00% | 0.00% | 0.00% | 0.00% | 18.75% |
48 | 9 | 1.56% | 0.00% | 2.40% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 6.25% | 6.25% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% |
49 | 10 | 3.12% | 30.30% | 0.00% | 0.00% | 50.00% | 13.75% | 14.58% | 91.67% | 12.50% | 0.00% | 50.00% | 0.00% | 50.00% | 6.25% | 37.50% | 8.59% | 0.00% | 0.00% | 0.00% | 62.50% |
50 | 11 | 22.66% | 24.24% | 31.25% | 0.00% | 31.25% | 33.75% | 18.75% | 100.00% | 25.00% | 0.00% | 75.00% | 0.00% | 43.75% | 25.00% | 56.25% | 22.66% | 0.00% | 0.00% | 0.00% | 81.25% |
51 | 12 | 0.00% | 24.24% | 0.00% | 0.00% | 0.00% | 10.00% | 6.25% | 87.50% | 15.62% | 0.00% | 25.00% | 0.00% | 0.00% | 0.00% | 37.50% | 54.69% | 0.00% | 0.00% | 0.00% | 37.50% |
52 | 13 | 5.47% | 0.00% | 28.85% | 0.00% | 12.50% | 41.25% | 10.42% | 0.00% | 18.75% | 0.00% | 25.00% | 0.00% | 25.00% | 12.50% | 6.25% | 20.31% | 0.00% | 0.00% | 0.00% | 18.75% |
53 | 14 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 12.50% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 31.25% | 25.00% | 0.00% | 0.00% | 0.00% | 31.25% |
54 | 15 | 3.12% | 0.00% | 19.23% | 0.00% | 0.00% | 36.25% | 10.42% | 0.00% | 6.25% | 0.00% | 25.00% | 0.00% | 6.25% | 6.25% | 0.00% | 18.75% | 0.00% | 0.00% | 0.00% | 6.25% |
55 | 16 | 2.34% | 0.00% | 0.00% | 0.00% | 6.25% | 2.50% | 0.00% | 0.00% | 9.38% | 0.00% | 0.00% | 0.00% | 6.25% | 0.00% | 25.00% | 25.00% | 0.00% | 0.00% | 0.00% | 25.00% |
56 | 17 | 16.41% | 0.00% | 19.23% | 0.00% | 12.50% | 30.00% | 12.50% | 0.00% | 12.50% | 0.00% | 50.00% | 0.00% | 18.75% | 12.50% | 6.25% | 25.00% | 0.00% | 0.00% | 0.00% | 18.75% |
57 | 18 | 5.47% | 0.00% | 6.49% | 33.33% | 37.50% | 10.00% | 12.50% | 0.00% | 9.38% | 0.00% | 75.00% | 0.00% | 37.50% | 18.75% | 25.00% | 6.25% | 0.00% | 0.00% | 0.00% | 37.50% |
58 | | | | | | | | | | | | | | | | | | | | | |
59 | Average | 10.86% | 15.55% | 10.06% | 11.40% | 30.26% | 19.34% | 10.53% | 29.82% | 15.79% | 0.00% | 50.00% | 0.00% | 31.25% | 13.82% | 26.32% | 24.84% | 0.00% | 0.00% | 0.00% | 45.07% |
60 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
61 
62 
63 Allocated Resource Usage
64 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
65 | Table | Stage | Crossbar | Hash | Gateways | RAMs | TCAMs | Map | Action | VLIW | Exm | Exm | Tind |
66 | Name | Number | Bytes | Bits | | | | RAMs | Data | Slots | Search | Result | Result |
67 | | | | | | | | | Bus | | Bus | Bus | Bus |
68 | | | | | | | | | Bytes | | | | |
69 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
70 | IngressParser.$PORT_METADATA | -1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
71 | Ingress.filter.drop_mcast_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
72 | Ingress.filter.ipv4_ctr | 0 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
73 | Ingress.filter.switch_ipv4_addr | 0 | 6 | 0 | 0 | 1 | 2 | 0 | 0 | 3 | 0 | 0 | 1 |
74 | Ingress.filter.uplink_ports | 0 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 |
75 | cond-80 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
76 | cond-81 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
77 | cond-82 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
78 | cond-83 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
79 | cond-84 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
80 | cond-85 | 0 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
81 | cond-86 | 0 | 6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
82 | cond-87 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
83 | cond-88 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
84 | cond-89 | 0 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
85 | cond-90 | 0 | 8 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
86 | cond-93 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
87 | cond-95 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
88 | tbl_filter_drop_bad_mac | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
89 | tbl_filter_drop_bad_mac_0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
90 | tbl_filter_drop_bad_mac_1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
91 | tbl_filter_drop_bad_mac_2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
92 | tbl_sidecar2094 | 0 | 13 | 16 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 0 |
93 | tbl_sidecar2141 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
94 | tbl_sidecar255 | 0 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
95 | tbl_sidecar255-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
96 | tbl_sidecar269 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
97 | tbl_sidecar269-gateway | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
98 | Egress.egress_filter.egress_filter | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 0 | 2 | 1 | 1 | 0 |
99 | Egress.mcast_egress.asic_id_to_port | 1 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
100 | Egress.mcast_egress.mcast_tag_check | 1 | 19 | 0 | 0 | 1 | 4 | 0 | 0 | 1 | 0 | 0 | 1 |
101 | Egress.mcast_egress.tbl_decap_ports | 1 | 2 | 40 | 0 | 4 | 0 | 0 | 34 | 3 | 1 | 1 | 0 |
102 | Egress.mcast_egress.tbl_decap_ports$action | 1 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
103 | Ingress.attached_subnet_ingress.attached_subnets_v4 | 1 | 4 | 0 | 0 | 1 | 2 | 0 | 25 | 2 | 0 | 0 | 1 |
104 | Ingress.attached_subnet_ingress.attached_subnets_v4$action | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
105 | Ingress.attached_subnet_ingress.attached_subnets_v4_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
106 | Ingress.attached_subnet_ingress.attached_subnets_v6 | 1 | 16 | 0 | 0 | 1 | 6 | 0 | 25 | 2 | 0 | 0 | 1 |
107 | Ingress.attached_subnet_ingress.attached_subnets_v6$action | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
108 | Ingress.attached_subnet_ingress.attached_subnets_v6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
109 | Ingress.filter.drop_mcast_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
110 | Ingress.filter.ipv6_ctr | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
111 | Ingress.filter.switch_ipv6_addr | 1 | 18 | 0 | 0 | 1 | 4 | 0 | 0 | 3 | 0 | 0 | 1 |
112 | cond-146 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
113 | cond-147 | 1 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
114 | cond-153 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
115 | cond-154 | 1 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
116 | cond-91 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
117 | cond-92 | 1 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
118 | cond-94 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
119 | cond-96 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
120 | cond-97 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
121 | tbl_sidecar209 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
122 | tbl_sidecar209-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
123 | tbl_sidecar2102 | 1 | 37 | 16 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 1 | 0 |
124 | tbl_sidecar234 | 1 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
125 | tbl_sidecar234-gateway | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
126 | tbl_sidecar2387 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
127 | tbl_sidecar2397 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
128 | Egress.mac_rewrite.ctr | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
129 | Egress.mac_rewrite.mac_rewrite | 2 | 2 | 10 | 0 | 1 | 0 | 0 | 6 | 2 | 1 | 1 | 0 |
130 | Egress.mac_rewrite.mac_rewrite$action | 2 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
131 | Egress.mcast_egress.port_bitmap_check | 2 | 1 | 10 | 0 | 1 | 0 | 0 | 4 | 9 | 1 | 1 | 0 |
132 | Ingress.nat_ingress.ingress_ipv4_mcast | 2 | 4 | 40 | 0 | 4 | 0 | 0 | 25 | 2 | 1 | 1 | 0 |
133 | Ingress.nat_ingress.ingress_ipv4_mcast$action | 2 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
134 | Ingress.nat_ingress.ingress_ipv6 | 2 | 20 | 0 | 0 | 0 | 20 | 0 | 25 | 2 | 0 | 0 | 0 |
135 | Ingress.nat_ingress.ingress_ipv6$action | 2 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
136 | Ingress.nat_ingress.ingress_ipv6_mcast | 2 | 16 | 40 | 0 | 8 | 0 | 0 | 25 | 2 | 1 | 1 | 0 |
137 | Ingress.nat_ingress.ingress_ipv6_mcast$action | 2 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
138 | Ingress.nat_ingress.ipv6_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
139 | Ingress.nat_ingress.mcast_ipv4_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
140 | Ingress.nat_ingress.mcast_ipv6_ingress_ctr | 2 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
141 | cond-100 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
142 | cond-102 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
143 | cond-103 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
144 | cond-98 | 2 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
145 | cond-99 | 2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
146 | Egress.drop_reason_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
147 | Egress.mcast_egress.modify_hdr | 3 | 3 | 0 | 0 | 1 | 1 | 0 | 2 | 5 | 0 | 0 | 1 |
148 | Ingress.ingress_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
149 | Ingress.nat_ingress.ingress_ipv4 | 3 | 8 | 0 | 0 | 1 | 10 | 0 | 25 | 2 | 0 | 0 | 1 |
150 | Ingress.nat_ingress.ingress_ipv4$action | 3 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
151 | Ingress.nat_ingress.ipv4_ingress_ctr | 3 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
152 | Ingress.packet_ctr | 3 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
153 | cond-101 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
154 | cond-148 | 3 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
155 | cond-155 | 3 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
156 | tbl_sidecar2061 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
157 | tbl_sidecar2137 | 3 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
158 | tbl_sidecar2137-gateway | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
159 | tbl_sidecar2138 | 3 | 2 | 10 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
160 | tbl_sidecar2138-gateway | 3 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
161 | tbl_sidecar2403 | 3 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
162 | Egress.drop_port_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
163 | Egress.forwarded_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
164 | Egress.mcast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
165 | Egress.unicast_ctr | 4 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
166 | Ingress.nat_ingress.CalculateIPv4Len.ipv4_set_len | 4 | 1 | 10 | 0 | 1 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
167 | Ingress.nat_ingress.ingress_hit | 4 | 3 | 10 | 0 | 1 | 0 | 0 | 8 | 4 | 1 | 1 | 0 |
168 | Ingress.nat_ingress.ingress_hit$action | 4 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
169 | cond-104 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
170 | cond-107 | 4 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
171 | cond-145 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
172 | cond-149 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
173 | cond-150 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
174 | cond-151 | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
175 | cond-152 | 4 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
176 | cond-156 | 4 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
177 | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5-gateway | 4 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
178 | egresshdr.inner_ipv4.hdr_checksum_encode_update_condition_5_egress | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
179 | tbl_sidecar1594 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
180 | tbl_sidecar1596 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 |
181 | tbl_sidecar1599 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
182 | tbl_sidecar1609_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
183 | tbl_sidecar1611_0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
184 | tbl_sidecar2228 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
185 | tbl_sidecar2402 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
186 | tbl_sidecar2402-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
187 | tbl_sidecar2406 | 4 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
188 | tbl_sidecar2406-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
189 | tbl_sidecar2409 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
190 | tbl_sidecar2443 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
191 | tbl_sidecar2443-gateway | 4 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
192 | tbl_sidecar751 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
193 | Egress.external_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
194 | Egress.link_local_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
195 | Egress.underlay_mcast_ctr | 5 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
196 | cond-105 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
197 | cond-108 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
198 | cond-109 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
199 | cond-111 | 5 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
200 | cond-157 | 5 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
201 | cond-158 | 5 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
202 | tbl_nat_ingress_CalculateIPv4Len_invert | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
203 | tbl_nat_ingress_encap_ipv4 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 1 | 0 | 0 | 1 |
204 | tbl_nat_ingress_encap_ipv4$action | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
205 | tbl_nat_ingress_encap_ipv6 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 27 | 1 | 0 | 0 | 1 |
206 | tbl_nat_ingress_encap_ipv6$action | 5 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
207 | tbl_sidecar1599_0 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
208 | tbl_sidecar1614 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | 0 | 0 | 1 |
209 | tbl_sidecar2436 | 5 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
210 | tbl_sidecar2438 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
211 | tbl_sidecar2440 | 5 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
212 | tbl_sidecar2440-gateway | 5 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
213 | Ingress.mcast_ingress.mcast_ipv4_ssm_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
214 | Ingress.mcast_ingress.mcast_ipv6_ssm_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
215 | Ingress.mcast_ingress.mcast_source_filter_ipv4 | 6 | 8 | 0 | 0 | 1 | 4 | 0 | 4 | 2 | 0 | 0 | 1 |
216 | Ingress.mcast_ingress.mcast_source_filter_ipv6 | 6 | 32 | 0 | 0 | 1 | 12 | 0 | 4 | 2 | 0 | 0 | 1 |
217 | Ingress.services.service | 6 | 8 | 0 | 0 | 1 | 2 | 0 | 22 | 7 | 0 | 0 | 1 |
218 | Ingress.services.service$action | 6 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
219 | Ingress.services.service_ctr | 6 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
220 | cond-106 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
221 | cond-110 | 6 | 5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
222 | cond-112 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
223 | cond-113 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
224 | cond-114 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
225 | cond-115 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
226 | cond-116 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
227 | cond-117 | 6 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
228 | tbl_mcast_ingress_drop_mcastv4_no_group | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
229 | tbl_mcast_ingress_drop_mcastv6_no_group | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
230 | tbl_sidecar1830 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
231 | tbl_sidecar1839 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
232 | tbl_sidecar441 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
233 | tbl_sidecar737 | 6 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
234 | Ingress.mcast_ingress.mcast_ipv6_ctr | 7 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
235 | Ingress.mcast_ingress.mcast_replication_ipv6 | 7 | 20 | 53 | 0 | 8 | 0 | 0 | 12 | 2 | 1 | 1 | 0 |
236 | Ingress.mcast_ingress.mcast_replication_ipv6$action | 7 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
237 | cond-118 | 7 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
238 | mcast_ingress_mcast_replication_ipv6 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
239 | Ingress.mcast_ingress.mcast_tag_check | 8 | 7 | 0 | 0 | 1 | 2 | 0 | 0 | 5 | 0 | 0 | 1 |
240 | cond-119 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
241 | cond-120 | 8 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
242 | Ingress.nat_egress.nat_egress | 9 | 1 | 10 | 0 | 1 | 0 | 0 | 12 | 7 | 1 | 1 | 0 |
243 | Ingress.nat_egress.nat_egress$action | 9 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
244 | cond-121 | 9 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
245 | Ingress.l3_router.Router4.lookup_idx.index_ctr | 10 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
246 | Ingress.l3_router.Router4.lookup_idx.lookup | 10 | 4 | 0 | 0 | 1 | 16 | 0 | 4 | 2 | 0 | 0 | 1 |
247 | Ingress.l3_router.Router4.lookup_idx.lookup$action | 10 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
248 | Ingress.l3_router.Router6.lookup_idx.index_ctr | 10 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
249 | Ingress.l3_router.Router6.lookup_idx.lookup | 10 | 16 | 0 | 0 | 1 | 6 | 0 | 6 | 2 | 0 | 0 | 1 |
250 | cond-122 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
251 | cond-123 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
252 | cond-124 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
253 | cond-125 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
254 | cond-131 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
255 | cond-132 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
256 | cond-133 | 10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
257 | ingresshdr.icmp.hdr_checksum_encode_update_condition_4-gateway | 10 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
258 | ingresshdr.icmp.hdr_checksum_encode_update_condition_4_ingress | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 2 | 0 | 1 | 0 |
259 | tbl_sidecar1260 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
260 | tbl_sidecar1343 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
261 | tbl_sidecar1399_0 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
262 | tbl_sidecar1479 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
263 | Ingress.l3_router.MulticastRouter4.ctr | 11 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
264 | Ingress.l3_router.MulticastRouter4.tbl | 11 | 4 | 40 | 0 | 4 | 0 | 0 | 4 | 3 | 1 | 1 | 0 |
265 | Ingress.l3_router.MulticastRouter6.ctr | 11 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
266 | Ingress.l3_router.MulticastRouter6.tbl | 11 | 16 | 40 | 0 | 8 | 0 | 0 | 4 | 3 | 1 | 1 | 0 |
267 | Ingress.l3_router.Router4.lookup_idx.select_route | 11 | 3 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
268 | Ingress.l3_router.Router6.lookup_idx.index_ctr | 11 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
269 | Ingress.l3_router.Router6.lookup_idx.lookup | 11 | 16 | 0 | 0 | 1 | 24 | 0 | 6 | 2 | 0 | 0 | 1 |
270 | cond-126 | 11 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
271 | cond-127 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
272 | cond-128 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
273 | cond-129 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
274 | cond-134 | 11 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
275 | ingresshdr.udp.checksum_encode_update_condition_3_ingress | 11 | 2 | 10 | 0 | 1 | 0 | 0 | 1 | 2 | 1 | 1 | 0 |
276 | tbl_sidecar1268 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
277 | tbl_sidecar1349 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
278 | tbl_sidecar1354 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | 0 | 0 | 1 |
279 | tbl_sidecar1359 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
280 | tbl_sidecar1361 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
281 | tbl_sidecar1485 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
282 | tbl_sidecar1490 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
283 | tbl_sidecar1495 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
284 | Ingress.l3_router.Router6.lookup_idx.index_ctr | 12 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
285 | Ingress.l3_router.Router6.lookup_idx.lookup | 12 | 16 | 0 | 0 | 1 | 21 | 0 | 6 | 2 | 0 | 0 | 1 |
286 | tbl_l3_router_MulticastRouter4_icmp_error | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
287 | tbl_l3_router_MulticastRouter4_icmp_error$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
288 | tbl_l3_router_MulticastRouter4_icmp_error_0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
289 | tbl_l3_router_MulticastRouter4_icmp_error_0$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
290 | tbl_l3_router_MulticastRouter6_icmp_error | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
291 | tbl_l3_router_MulticastRouter6_icmp_error$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
292 | tbl_l3_router_MulticastRouter6_icmp_error_0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
293 | tbl_l3_router_MulticastRouter6_icmp_error_0$action | 12 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
294 | tbl_sidecar1124 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
295 | Ingress.l3_router.Router4.lookup_idx.forward_ctr | 13 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
296 | Ingress.l3_router.Router4.lookup_idx.route | 13 | 4 | 80 | 0 | 8 | 0 | 0 | 24 | 5 | 1 | 1 | 0 |
297 | Ingress.l3_router.Router4.lookup_idx.route$action | 13 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
298 | Ingress.l3_router.Router6.lookup_idx.select_route | 13 | 3 | 40 | 0 | 4 | 0 | 0 | 2 | 2 | 1 | 1 | 0 |
299 | cond-135 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
300 | cond-136 | 13 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
301 | tbl_sidecar1405 | 13 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
302 | cond-130 | 14 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
303 | tbl_l3_router_Router4_icmp_error | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
304 | tbl_l3_router_Router4_icmp_error$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
305 | tbl_l3_router_Router4_icmp_error_0 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
306 | tbl_l3_router_Router4_icmp_error_0$action | 14 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
307 | tbl_sidecar1273 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
308 | tbl_sidecar1275 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
309 | tbl_sidecar996 | 14 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
310 | Ingress.l3_router.Router6.lookup_idx.forward_ctr | 15 | 0 | 0 | 0 | 5 | 0 | 5 | 0 | 0 | 0 | 0 | 0 |
311 | Ingress.l3_router.Router6.lookup_idx.route | 15 | 4 | 80 | 0 | 8 | 0 | 0 | 24 | 3 | 1 | 1 | 0 |
312 | Ingress.l3_router.Router6.lookup_idx.route$action | 15 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
313 | cond-137 | 16 | 3 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
314 | tbl_l3_router_Router6_icmp_error | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
315 | tbl_l3_router_Router6_icmp_error$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
316 | tbl_l3_router_Router6_icmp_error_0 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 16 | 1 | 0 | 0 | 1 |
317 | tbl_l3_router_Router6_icmp_error_0$action | 16 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
318 | tbl_sidecar1410 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
319 | tbl_sidecar1414 | 16 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
320 | Ingress.l3_router.Arp.ctr | 17 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
321 | Ingress.l3_router.Arp.tbl | 17 | 4 | 40 | 0 | 4 | 0 | 0 | 18 | 3 | 1 | 1 | 0 |
322 | Ingress.l3_router.Arp.tbl$action | 17 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
323 | Ingress.l3_router.Ndp.ctr | 17 | 0 | 0 | 0 | 3 | 0 | 3 | 0 | 0 | 0 | 0 | 0 |
324 | Ingress.l3_router.Ndp.tbl | 17 | 16 | 40 | 0 | 8 | 0 | 0 | 14 | 3 | 1 | 1 | 0 |
325 | Ingress.l3_router.Ndp.tbl$action | 17 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
326 | cond-138 | 17 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
327 | cond-139 | 17 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
328 | Ingress.drop_port_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
329 | Ingress.drop_reason_ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
330 | Ingress.mac_rewrite.ctr | 18 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 0 | 0 | 0 | 0 |
331 | Ingress.mac_rewrite.mac_rewrite | 18 | 2 | 10 | 0 | 1 | 0 | 0 | 8 | 2 | 1 | 1 | 0 |
332 | Ingress.mac_rewrite.mac_rewrite$action | 18 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
333 | cond-140 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
334 | cond-141 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
335 | cond-142 | 18 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
336 | cond-143 | 18 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 |
337 | cond-144 | 18 | 2 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
338 | tbl_sidecar2182 | 18 | 2 | 9 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
339 | tbl_sidecar2182-gateway | 18 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
340 | tbl_sidecar2184 | 18 | 1 | 8 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 |
341 | tbl_sidecar2190 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
342 | tbl_sidecar2193 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
343 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
344